2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
40 #include <video/omapdss.h>
43 #include "dss_features.h"
47 #define DISPC_SZ_REGS SZ_4K
49 enum omap_burst_size {
55 #define REG_GET(idx, start, end) \
56 FLD_GET(dispc_read_reg(idx), start, end)
58 #define REG_FLD_MOD(idx, val, start, end) \
59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
61 struct dispc_features {
72 unsigned long max_lcd_pclk;
73 unsigned long max_tv_pclk;
74 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
75 const struct omap_video_timings *mgr_timings,
76 u16 width, u16 height, u16 out_width, u16 out_height,
77 enum omap_color_mode color_mode, bool *five_taps,
78 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
79 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
80 unsigned long (*calc_core_clk) (unsigned long pclk,
81 u16 width, u16 height, u16 out_width, u16 out_height,
85 /* swap GFX & WB fifos */
86 bool gfx_fifo_workaround:1;
88 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
89 bool no_framedone_tv:1;
91 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
92 bool mstandby_workaround:1;
94 bool set_max_preload:1;
97 #define DISPC_MAX_NR_FIFOS 5
100 struct platform_device *pdev;
104 irq_handler_t user_handler;
107 unsigned long core_clk_rate;
108 unsigned long tv_pclk_rate;
110 u32 fifo_size[DISPC_MAX_NR_FIFOS];
111 /* maps which plane is using a fifo. fifo-id -> plane-id */
112 int fifo_assignment[DISPC_MAX_NR_FIFOS];
115 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
117 const struct dispc_features *feat;
122 enum omap_color_component {
123 /* used for all color formats for OMAP3 and earlier
124 * and for RGB and Y color component on OMAP4
126 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
127 /* used for UV component for
128 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
129 * color formats on OMAP4
131 DISPC_COLOR_COMPONENT_UV = 1 << 1,
134 enum mgr_reg_fields {
135 DISPC_MGR_FLD_ENABLE,
136 DISPC_MGR_FLD_STNTFT,
138 DISPC_MGR_FLD_TFTDATALINES,
139 DISPC_MGR_FLD_STALLMODE,
140 DISPC_MGR_FLD_TCKENABLE,
141 DISPC_MGR_FLD_TCKSELECTION,
143 DISPC_MGR_FLD_FIFOHANDCHECK,
144 /* used to maintain a count of the above fields */
148 struct dispc_reg_field {
154 static const struct {
159 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
161 [OMAP_DSS_CHANNEL_LCD] = {
163 .vsync_irq = DISPC_IRQ_VSYNC,
164 .framedone_irq = DISPC_IRQ_FRAMEDONE,
165 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
167 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
168 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
169 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
170 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
171 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
172 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
173 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
174 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
175 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
178 [OMAP_DSS_CHANNEL_DIGIT] = {
180 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
181 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
182 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
184 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
185 [DISPC_MGR_FLD_STNTFT] = { },
186 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
187 [DISPC_MGR_FLD_TFTDATALINES] = { },
188 [DISPC_MGR_FLD_STALLMODE] = { },
189 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
190 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
191 [DISPC_MGR_FLD_CPR] = { },
192 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
195 [OMAP_DSS_CHANNEL_LCD2] = {
197 .vsync_irq = DISPC_IRQ_VSYNC2,
198 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
199 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
201 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
202 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
203 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
204 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
205 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
206 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
207 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
208 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
209 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
212 [OMAP_DSS_CHANNEL_LCD3] = {
214 .vsync_irq = DISPC_IRQ_VSYNC3,
215 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
216 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
218 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
219 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
220 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
221 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
222 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
223 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
224 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
225 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
226 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
231 struct color_conv_coef {
232 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
236 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
237 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
239 static inline void dispc_write_reg(const u16 idx, u32 val)
241 __raw_writel(val, dispc.base + idx);
244 static inline u32 dispc_read_reg(const u16 idx)
246 return __raw_readl(dispc.base + idx);
249 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
251 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
252 return REG_GET(rfld.reg, rfld.high, rfld.low);
255 static void mgr_fld_write(enum omap_channel channel,
256 enum mgr_reg_fields regfld, int val) {
257 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
258 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
262 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
264 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
266 static void dispc_save_context(void)
270 DSSDBG("dispc_save_context\n");
276 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
277 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
279 if (dss_has_feature(FEAT_MGR_LCD2)) {
283 if (dss_has_feature(FEAT_MGR_LCD3)) {
288 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
289 SR(DEFAULT_COLOR(i));
292 if (i == OMAP_DSS_CHANNEL_DIGIT)
303 if (dss_has_feature(FEAT_CPR)) {
310 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
315 SR(OVL_ATTRIBUTES(i));
316 SR(OVL_FIFO_THRESHOLD(i));
318 SR(OVL_PIXEL_INC(i));
319 if (dss_has_feature(FEAT_PRELOAD))
321 if (i == OMAP_DSS_GFX) {
322 SR(OVL_WINDOW_SKIP(i));
327 SR(OVL_PICTURE_SIZE(i));
331 for (j = 0; j < 8; j++)
332 SR(OVL_FIR_COEF_H(i, j));
334 for (j = 0; j < 8; j++)
335 SR(OVL_FIR_COEF_HV(i, j));
337 for (j = 0; j < 5; j++)
338 SR(OVL_CONV_COEF(i, j));
340 if (dss_has_feature(FEAT_FIR_COEF_V)) {
341 for (j = 0; j < 8; j++)
342 SR(OVL_FIR_COEF_V(i, j));
345 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_H2(i, j));
355 for (j = 0; j < 8; j++)
356 SR(OVL_FIR_COEF_HV2(i, j));
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_V2(i, j));
361 if (dss_has_feature(FEAT_ATTR2))
362 SR(OVL_ATTRIBUTES2(i));
365 if (dss_has_feature(FEAT_CORE_CLK_DIV))
368 dispc.ctx_valid = true;
370 DSSDBG("context saved\n");
373 static void dispc_restore_context(void)
377 DSSDBG("dispc_restore_context\n");
379 if (!dispc.ctx_valid)
386 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
387 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
389 if (dss_has_feature(FEAT_MGR_LCD2))
391 if (dss_has_feature(FEAT_MGR_LCD3))
394 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
395 RR(DEFAULT_COLOR(i));
398 if (i == OMAP_DSS_CHANNEL_DIGIT)
409 if (dss_has_feature(FEAT_CPR)) {
416 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
421 RR(OVL_ATTRIBUTES(i));
422 RR(OVL_FIFO_THRESHOLD(i));
424 RR(OVL_PIXEL_INC(i));
425 if (dss_has_feature(FEAT_PRELOAD))
427 if (i == OMAP_DSS_GFX) {
428 RR(OVL_WINDOW_SKIP(i));
433 RR(OVL_PICTURE_SIZE(i));
437 for (j = 0; j < 8; j++)
438 RR(OVL_FIR_COEF_H(i, j));
440 for (j = 0; j < 8; j++)
441 RR(OVL_FIR_COEF_HV(i, j));
443 for (j = 0; j < 5; j++)
444 RR(OVL_CONV_COEF(i, j));
446 if (dss_has_feature(FEAT_FIR_COEF_V)) {
447 for (j = 0; j < 8; j++)
448 RR(OVL_FIR_COEF_V(i, j));
451 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_H2(i, j));
461 for (j = 0; j < 8; j++)
462 RR(OVL_FIR_COEF_HV2(i, j));
464 for (j = 0; j < 8; j++)
465 RR(OVL_FIR_COEF_V2(i, j));
467 if (dss_has_feature(FEAT_ATTR2))
468 RR(OVL_ATTRIBUTES2(i));
471 if (dss_has_feature(FEAT_CORE_CLK_DIV))
474 /* enable last, because LCD & DIGIT enable are here */
476 if (dss_has_feature(FEAT_MGR_LCD2))
478 if (dss_has_feature(FEAT_MGR_LCD3))
480 /* clear spurious SYNC_LOST_DIGIT interrupts */
481 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
484 * enable last so IRQs won't trigger before
485 * the context is fully restored
489 DSSDBG("context restored\n");
495 int dispc_runtime_get(void)
499 DSSDBG("dispc_runtime_get\n");
501 r = pm_runtime_get_sync(&dispc.pdev->dev);
503 return r < 0 ? r : 0;
505 EXPORT_SYMBOL(dispc_runtime_get);
507 void dispc_runtime_put(void)
511 DSSDBG("dispc_runtime_put\n");
513 r = pm_runtime_put_sync(&dispc.pdev->dev);
514 WARN_ON(r < 0 && r != -ENOSYS);
516 EXPORT_SYMBOL(dispc_runtime_put);
518 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
520 return mgr_desc[channel].vsync_irq;
522 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
524 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
526 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
529 return mgr_desc[channel].framedone_irq;
531 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
533 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
535 return mgr_desc[channel].sync_lost_irq;
537 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
539 u32 dispc_wb_get_framedone_irq(void)
541 return DISPC_IRQ_FRAMEDONEWB;
544 bool dispc_mgr_go_busy(enum omap_channel channel)
546 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
548 EXPORT_SYMBOL(dispc_mgr_go_busy);
550 void dispc_mgr_go(enum omap_channel channel)
552 WARN_ON(dispc_mgr_is_enabled(channel) == false);
553 WARN_ON(dispc_mgr_go_busy(channel));
555 DSSDBG("GO %s\n", mgr_desc[channel].name);
557 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
559 EXPORT_SYMBOL(dispc_mgr_go);
561 bool dispc_wb_go_busy(void)
563 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
566 void dispc_wb_go(void)
568 enum omap_plane plane = OMAP_DSS_WB;
571 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
576 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
578 DSSERR("GO bit not down for WB\n");
582 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
585 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
587 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
590 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
592 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
595 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
597 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
600 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
602 BUG_ON(plane == OMAP_DSS_GFX);
604 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
607 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
610 BUG_ON(plane == OMAP_DSS_GFX);
612 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
615 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
617 BUG_ON(plane == OMAP_DSS_GFX);
619 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
622 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
623 int fir_vinc, int five_taps,
624 enum omap_color_component color_comp)
626 const struct dispc_coef *h_coef, *v_coef;
629 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
630 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
632 for (i = 0; i < 8; i++) {
635 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
636 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
637 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
638 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
639 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
640 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
641 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
642 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
644 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
645 dispc_ovl_write_firh_reg(plane, i, h);
646 dispc_ovl_write_firhv_reg(plane, i, hv);
648 dispc_ovl_write_firh2_reg(plane, i, h);
649 dispc_ovl_write_firhv2_reg(plane, i, hv);
655 for (i = 0; i < 8; i++) {
657 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
658 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
659 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
660 dispc_ovl_write_firv_reg(plane, i, v);
662 dispc_ovl_write_firv2_reg(plane, i, v);
668 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
669 const struct color_conv_coef *ct)
671 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
673 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
674 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
675 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
676 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
677 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
684 static void dispc_setup_color_conv_coef(void)
687 int num_ovl = dss_feat_get_num_ovls();
688 int num_wb = dss_feat_get_num_wbs();
689 const struct color_conv_coef ctbl_bt601_5_ovl = {
690 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
692 const struct color_conv_coef ctbl_bt601_5_wb = {
693 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
696 for (i = 1; i < num_ovl; i++)
697 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
699 for (; i < num_wb; i++)
700 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
703 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
705 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
708 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
710 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
713 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
715 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
718 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
720 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
723 static void dispc_ovl_set_pos(enum omap_plane plane,
724 enum omap_overlay_caps caps, int x, int y)
728 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
731 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
733 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
736 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
739 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
741 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
742 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
744 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
747 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
752 BUG_ON(plane == OMAP_DSS_GFX);
754 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
756 if (plane == OMAP_DSS_WB)
757 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
759 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
762 static void dispc_ovl_set_zorder(enum omap_plane plane,
763 enum omap_overlay_caps caps, u8 zorder)
765 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
768 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
771 static void dispc_ovl_enable_zorder_planes(void)
775 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
778 for (i = 0; i < dss_feat_get_num_ovls(); i++)
779 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
782 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
783 enum omap_overlay_caps caps, bool enable)
785 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
788 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
791 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
792 enum omap_overlay_caps caps, u8 global_alpha)
794 static const unsigned shifts[] = { 0, 8, 16, 24, };
797 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
800 shift = shifts[plane];
801 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
804 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
806 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
809 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
811 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
814 static void dispc_ovl_set_color_mode(enum omap_plane plane,
815 enum omap_color_mode color_mode)
818 if (plane != OMAP_DSS_GFX) {
819 switch (color_mode) {
820 case OMAP_DSS_COLOR_NV12:
822 case OMAP_DSS_COLOR_RGBX16:
824 case OMAP_DSS_COLOR_RGBA16:
826 case OMAP_DSS_COLOR_RGB12U:
828 case OMAP_DSS_COLOR_ARGB16:
830 case OMAP_DSS_COLOR_RGB16:
832 case OMAP_DSS_COLOR_ARGB16_1555:
834 case OMAP_DSS_COLOR_RGB24U:
836 case OMAP_DSS_COLOR_RGB24P:
838 case OMAP_DSS_COLOR_YUV2:
840 case OMAP_DSS_COLOR_UYVY:
842 case OMAP_DSS_COLOR_ARGB32:
844 case OMAP_DSS_COLOR_RGBA32:
846 case OMAP_DSS_COLOR_RGBX32:
848 case OMAP_DSS_COLOR_XRGB16_1555:
854 switch (color_mode) {
855 case OMAP_DSS_COLOR_CLUT1:
857 case OMAP_DSS_COLOR_CLUT2:
859 case OMAP_DSS_COLOR_CLUT4:
861 case OMAP_DSS_COLOR_CLUT8:
863 case OMAP_DSS_COLOR_RGB12U:
865 case OMAP_DSS_COLOR_ARGB16:
867 case OMAP_DSS_COLOR_RGB16:
869 case OMAP_DSS_COLOR_ARGB16_1555:
871 case OMAP_DSS_COLOR_RGB24U:
873 case OMAP_DSS_COLOR_RGB24P:
875 case OMAP_DSS_COLOR_RGBX16:
877 case OMAP_DSS_COLOR_RGBA16:
879 case OMAP_DSS_COLOR_ARGB32:
881 case OMAP_DSS_COLOR_RGBA32:
883 case OMAP_DSS_COLOR_RGBX32:
885 case OMAP_DSS_COLOR_XRGB16_1555:
892 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
895 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
896 enum omap_dss_rotation_type rotation_type)
898 if (dss_has_feature(FEAT_BURST_2D) == 0)
901 if (rotation_type == OMAP_DSS_ROT_TILER)
902 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
904 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
907 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
911 int chan = 0, chan2 = 0;
917 case OMAP_DSS_VIDEO1:
918 case OMAP_DSS_VIDEO2:
919 case OMAP_DSS_VIDEO3:
927 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
928 if (dss_has_feature(FEAT_MGR_LCD2)) {
930 case OMAP_DSS_CHANNEL_LCD:
934 case OMAP_DSS_CHANNEL_DIGIT:
938 case OMAP_DSS_CHANNEL_LCD2:
942 case OMAP_DSS_CHANNEL_LCD3:
943 if (dss_has_feature(FEAT_MGR_LCD3)) {
956 val = FLD_MOD(val, chan, shift, shift);
957 val = FLD_MOD(val, chan2, 31, 30);
959 val = FLD_MOD(val, channel, shift, shift);
961 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
963 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
965 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
969 enum omap_channel channel;
975 case OMAP_DSS_VIDEO1:
976 case OMAP_DSS_VIDEO2:
977 case OMAP_DSS_VIDEO3:
985 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
987 if (dss_has_feature(FEAT_MGR_LCD3)) {
988 if (FLD_GET(val, 31, 30) == 0)
989 channel = FLD_GET(val, shift, shift);
990 else if (FLD_GET(val, 31, 30) == 1)
991 channel = OMAP_DSS_CHANNEL_LCD2;
993 channel = OMAP_DSS_CHANNEL_LCD3;
994 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
995 if (FLD_GET(val, 31, 30) == 0)
996 channel = FLD_GET(val, shift, shift);
998 channel = OMAP_DSS_CHANNEL_LCD2;
1000 channel = FLD_GET(val, shift, shift);
1006 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1008 enum omap_plane plane = OMAP_DSS_WB;
1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1013 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1014 enum omap_burst_size burst_size)
1016 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1019 shift = shifts[plane];
1020 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1023 static void dispc_configure_burst_sizes(void)
1026 const int burst_size = BURST_SIZE_X8;
1028 /* Configure burst size always to maximum size */
1029 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1030 dispc_ovl_set_burst_size(i, burst_size);
1033 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1035 unsigned unit = dss_feat_get_burst_size_unit();
1036 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1040 void dispc_enable_gamma_table(bool enable)
1043 * This is partially implemented to support only disabling of
1047 DSSWARN("Gamma table enabling for TV not yet supported");
1051 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1054 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1056 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1059 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1062 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1063 const struct omap_dss_cpr_coefs *coefs)
1065 u32 coef_r, coef_g, coef_b;
1067 if (!dss_mgr_is_lcd(channel))
1070 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1071 FLD_VAL(coefs->rb, 9, 0);
1072 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1073 FLD_VAL(coefs->gb, 9, 0);
1074 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1075 FLD_VAL(coefs->bb, 9, 0);
1077 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1078 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1079 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1082 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1086 BUG_ON(plane == OMAP_DSS_GFX);
1088 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1089 val = FLD_MOD(val, enable, 9, 9);
1090 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1093 static void dispc_ovl_enable_replication(enum omap_plane plane,
1094 enum omap_overlay_caps caps, bool enable)
1096 static const unsigned shifts[] = { 5, 10, 10, 10 };
1099 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1102 shift = shifts[plane];
1103 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1106 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1111 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1112 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1114 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1117 static void dispc_init_fifos(void)
1124 unit = dss_feat_get_buffer_size_unit();
1126 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1128 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1129 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1131 dispc.fifo_size[fifo] = size;
1134 * By default fifos are mapped directly to overlays, fifo 0 to
1135 * ovl 0, fifo 1 to ovl 1, etc.
1137 dispc.fifo_assignment[fifo] = fifo;
1141 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1142 * causes problems with certain use cases, like using the tiler in 2D
1143 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1144 * giving GFX plane a larger fifo. WB but should work fine with a
1147 if (dispc.feat->gfx_fifo_workaround) {
1150 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1152 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1153 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1154 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1155 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1157 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1159 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1160 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1164 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1169 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1170 if (dispc.fifo_assignment[fifo] == plane)
1171 size += dispc.fifo_size[fifo];
1177 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1179 u8 hi_start, hi_end, lo_start, lo_end;
1182 unit = dss_feat_get_buffer_size_unit();
1184 WARN_ON(low % unit != 0);
1185 WARN_ON(high % unit != 0);
1190 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1191 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1193 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1195 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1196 lo_start, lo_end) * unit,
1197 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1198 hi_start, hi_end) * unit,
1199 low * unit, high * unit);
1201 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1202 FLD_VAL(high, hi_start, hi_end) |
1203 FLD_VAL(low, lo_start, lo_end));
1206 * configure the preload to the pipeline's high threhold, if HT it's too
1207 * large for the preload field, set the threshold to the maximum value
1208 * that can be held by the preload register
1210 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1211 plane != OMAP_DSS_WB)
1212 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1214 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1216 void dispc_enable_fifomerge(bool enable)
1218 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1223 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1224 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1227 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1228 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1232 * All sizes are in bytes. Both the buffer and burst are made of
1233 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1236 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1237 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1240 burst_size = dispc_ovl_get_burst_size(plane);
1241 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1243 if (use_fifomerge) {
1244 total_fifo_size = 0;
1245 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1246 total_fifo_size += dispc_ovl_get_fifo_size(i);
1248 total_fifo_size = ovl_fifo_size;
1252 * We use the same low threshold for both fifomerge and non-fifomerge
1253 * cases, but for fifomerge we calculate the high threshold using the
1254 * combined fifo size
1257 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1258 *fifo_low = ovl_fifo_size - burst_size * 2;
1259 *fifo_high = total_fifo_size - burst_size;
1260 } else if (plane == OMAP_DSS_WB) {
1262 * Most optimal configuration for writeback is to push out data
1263 * to the interconnect the moment writeback pushes enough pixels
1264 * in the FIFO to form a burst
1267 *fifo_high = burst_size;
1269 *fifo_low = ovl_fifo_size - burst_size;
1270 *fifo_high = total_fifo_size - buf_unit;
1273 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1275 static void dispc_ovl_set_fir(enum omap_plane plane,
1277 enum omap_color_component color_comp)
1281 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1282 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1284 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1285 &hinc_start, &hinc_end);
1286 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1287 &vinc_start, &vinc_end);
1288 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1289 FLD_VAL(hinc, hinc_start, hinc_end);
1291 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1293 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1294 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1298 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1301 u8 hor_start, hor_end, vert_start, vert_end;
1303 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1304 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1306 val = FLD_VAL(vaccu, vert_start, vert_end) |
1307 FLD_VAL(haccu, hor_start, hor_end);
1309 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1312 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1315 u8 hor_start, hor_end, vert_start, vert_end;
1317 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1318 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1320 val = FLD_VAL(vaccu, vert_start, vert_end) |
1321 FLD_VAL(haccu, hor_start, hor_end);
1323 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1326 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1331 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1332 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1335 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1340 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1341 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1344 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1345 u16 orig_width, u16 orig_height,
1346 u16 out_width, u16 out_height,
1347 bool five_taps, u8 rotation,
1348 enum omap_color_component color_comp)
1350 int fir_hinc, fir_vinc;
1352 fir_hinc = 1024 * orig_width / out_width;
1353 fir_vinc = 1024 * orig_height / out_height;
1355 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1357 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1360 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1361 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1362 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1364 int h_accu2_0, h_accu2_1;
1365 int v_accu2_0, v_accu2_1;
1366 int chroma_hinc, chroma_vinc;
1376 const struct accu *accu_table;
1377 const struct accu *accu_val;
1379 static const struct accu accu_nv12[4] = {
1380 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1381 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1382 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1383 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1386 static const struct accu accu_nv12_ilace[4] = {
1387 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1388 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1389 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1390 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1393 static const struct accu accu_yuv[4] = {
1394 { 0, 1, 0, 1, 0, 1, 0, 1 },
1395 { 0, 1, 0, 1, 0, 1, 0, 1 },
1396 { -1, 1, 0, 1, 0, 1, 0, 1 },
1397 { 0, 1, 0, 1, -1, 1, 0, 1 },
1401 case OMAP_DSS_ROT_0:
1404 case OMAP_DSS_ROT_90:
1407 case OMAP_DSS_ROT_180:
1410 case OMAP_DSS_ROT_270:
1418 switch (color_mode) {
1419 case OMAP_DSS_COLOR_NV12:
1421 accu_table = accu_nv12_ilace;
1423 accu_table = accu_nv12;
1425 case OMAP_DSS_COLOR_YUV2:
1426 case OMAP_DSS_COLOR_UYVY:
1427 accu_table = accu_yuv;
1434 accu_val = &accu_table[idx];
1436 chroma_hinc = 1024 * orig_width / out_width;
1437 chroma_vinc = 1024 * orig_height / out_height;
1439 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1440 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1441 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1442 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1444 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1445 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1448 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1449 u16 orig_width, u16 orig_height,
1450 u16 out_width, u16 out_height,
1451 bool ilace, bool five_taps,
1452 bool fieldmode, enum omap_color_mode color_mode,
1459 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1460 out_width, out_height, five_taps,
1461 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1462 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1464 /* RESIZEENABLE and VERTICALTAPS */
1465 l &= ~((0x3 << 5) | (0x1 << 21));
1466 l |= (orig_width != out_width) ? (1 << 5) : 0;
1467 l |= (orig_height != out_height) ? (1 << 6) : 0;
1468 l |= five_taps ? (1 << 21) : 0;
1470 /* VRESIZECONF and HRESIZECONF */
1471 if (dss_has_feature(FEAT_RESIZECONF)) {
1473 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1474 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1477 /* LINEBUFFERSPLIT */
1478 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1480 l |= five_taps ? (1 << 22) : 0;
1483 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1486 * field 0 = even field = bottom field
1487 * field 1 = odd field = top field
1489 if (ilace && !fieldmode) {
1491 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1492 if (accu0 >= 1024/2) {
1498 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1499 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1502 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1503 u16 orig_width, u16 orig_height,
1504 u16 out_width, u16 out_height,
1505 bool ilace, bool five_taps,
1506 bool fieldmode, enum omap_color_mode color_mode,
1509 int scale_x = out_width != orig_width;
1510 int scale_y = out_height != orig_height;
1511 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1513 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1515 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1516 color_mode != OMAP_DSS_COLOR_UYVY &&
1517 color_mode != OMAP_DSS_COLOR_NV12)) {
1518 /* reset chroma resampling for RGB formats */
1519 if (plane != OMAP_DSS_WB)
1520 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1524 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1525 out_height, ilace, color_mode, rotation);
1527 switch (color_mode) {
1528 case OMAP_DSS_COLOR_NV12:
1529 if (chroma_upscale) {
1530 /* UV is subsampled by 2 horizontally and vertically */
1534 /* UV is downsampled by 2 horizontally and vertically */
1540 case OMAP_DSS_COLOR_YUV2:
1541 case OMAP_DSS_COLOR_UYVY:
1542 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1543 if (rotation == OMAP_DSS_ROT_0 ||
1544 rotation == OMAP_DSS_ROT_180) {
1546 /* UV is subsampled by 2 horizontally */
1549 /* UV is downsampled by 2 horizontally */
1553 /* must use FIR for YUV422 if rotated */
1554 if (rotation != OMAP_DSS_ROT_0)
1555 scale_x = scale_y = true;
1563 if (out_width != orig_width)
1565 if (out_height != orig_height)
1568 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1569 out_width, out_height, five_taps,
1570 rotation, DISPC_COLOR_COMPONENT_UV);
1572 if (plane != OMAP_DSS_WB)
1573 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1574 (scale_x || scale_y) ? 1 : 0, 8, 8);
1577 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1579 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1582 static void dispc_ovl_set_scaling(enum omap_plane plane,
1583 u16 orig_width, u16 orig_height,
1584 u16 out_width, u16 out_height,
1585 bool ilace, bool five_taps,
1586 bool fieldmode, enum omap_color_mode color_mode,
1589 BUG_ON(plane == OMAP_DSS_GFX);
1591 dispc_ovl_set_scaling_common(plane,
1592 orig_width, orig_height,
1593 out_width, out_height,
1595 fieldmode, color_mode,
1598 dispc_ovl_set_scaling_uv(plane,
1599 orig_width, orig_height,
1600 out_width, out_height,
1602 fieldmode, color_mode,
1606 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1607 enum omap_dss_rotation_type rotation_type,
1608 bool mirroring, enum omap_color_mode color_mode)
1610 bool row_repeat = false;
1613 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1614 color_mode == OMAP_DSS_COLOR_UYVY) {
1618 case OMAP_DSS_ROT_0:
1621 case OMAP_DSS_ROT_90:
1624 case OMAP_DSS_ROT_180:
1627 case OMAP_DSS_ROT_270:
1633 case OMAP_DSS_ROT_0:
1636 case OMAP_DSS_ROT_90:
1639 case OMAP_DSS_ROT_180:
1642 case OMAP_DSS_ROT_270:
1648 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1655 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1656 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1657 row_repeat ? 1 : 0, 18, 18);
1659 if (color_mode == OMAP_DSS_COLOR_NV12) {
1660 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1661 (rotation == OMAP_DSS_ROT_0 ||
1662 rotation == OMAP_DSS_ROT_180);
1664 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1669 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1671 switch (color_mode) {
1672 case OMAP_DSS_COLOR_CLUT1:
1674 case OMAP_DSS_COLOR_CLUT2:
1676 case OMAP_DSS_COLOR_CLUT4:
1678 case OMAP_DSS_COLOR_CLUT8:
1679 case OMAP_DSS_COLOR_NV12:
1681 case OMAP_DSS_COLOR_RGB12U:
1682 case OMAP_DSS_COLOR_RGB16:
1683 case OMAP_DSS_COLOR_ARGB16:
1684 case OMAP_DSS_COLOR_YUV2:
1685 case OMAP_DSS_COLOR_UYVY:
1686 case OMAP_DSS_COLOR_RGBA16:
1687 case OMAP_DSS_COLOR_RGBX16:
1688 case OMAP_DSS_COLOR_ARGB16_1555:
1689 case OMAP_DSS_COLOR_XRGB16_1555:
1691 case OMAP_DSS_COLOR_RGB24P:
1693 case OMAP_DSS_COLOR_RGB24U:
1694 case OMAP_DSS_COLOR_ARGB32:
1695 case OMAP_DSS_COLOR_RGBA32:
1696 case OMAP_DSS_COLOR_RGBX32:
1704 static s32 pixinc(int pixels, u8 ps)
1708 else if (pixels > 1)
1709 return 1 + (pixels - 1) * ps;
1710 else if (pixels < 0)
1711 return 1 - (-pixels + 1) * ps;
1717 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1719 u16 width, u16 height,
1720 enum omap_color_mode color_mode, bool fieldmode,
1721 unsigned int field_offset,
1722 unsigned *offset0, unsigned *offset1,
1723 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1727 /* FIXME CLUT formats */
1728 switch (color_mode) {
1729 case OMAP_DSS_COLOR_CLUT1:
1730 case OMAP_DSS_COLOR_CLUT2:
1731 case OMAP_DSS_COLOR_CLUT4:
1732 case OMAP_DSS_COLOR_CLUT8:
1735 case OMAP_DSS_COLOR_YUV2:
1736 case OMAP_DSS_COLOR_UYVY:
1740 ps = color_mode_to_bpp(color_mode) / 8;
1744 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1748 * field 0 = even field = bottom field
1749 * field 1 = odd field = top field
1751 switch (rotation + mirror * 4) {
1752 case OMAP_DSS_ROT_0:
1753 case OMAP_DSS_ROT_180:
1755 * If the pixel format is YUV or UYVY divide the width
1756 * of the image by 2 for 0 and 180 degree rotation.
1758 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1759 color_mode == OMAP_DSS_COLOR_UYVY)
1761 case OMAP_DSS_ROT_90:
1762 case OMAP_DSS_ROT_270:
1765 *offset0 = field_offset * screen_width * ps;
1769 *row_inc = pixinc(1 +
1770 (y_predecim * screen_width - x_predecim * width) +
1771 (fieldmode ? screen_width : 0), ps);
1772 *pix_inc = pixinc(x_predecim, ps);
1775 case OMAP_DSS_ROT_0 + 4:
1776 case OMAP_DSS_ROT_180 + 4:
1777 /* If the pixel format is YUV or UYVY divide the width
1778 * of the image by 2 for 0 degree and 180 degree
1780 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1781 color_mode == OMAP_DSS_COLOR_UYVY)
1783 case OMAP_DSS_ROT_90 + 4:
1784 case OMAP_DSS_ROT_270 + 4:
1787 *offset0 = field_offset * screen_width * ps;
1790 *row_inc = pixinc(1 -
1791 (y_predecim * screen_width + x_predecim * width) -
1792 (fieldmode ? screen_width : 0), ps);
1793 *pix_inc = pixinc(x_predecim, ps);
1802 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1804 u16 width, u16 height,
1805 enum omap_color_mode color_mode, bool fieldmode,
1806 unsigned int field_offset,
1807 unsigned *offset0, unsigned *offset1,
1808 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1813 /* FIXME CLUT formats */
1814 switch (color_mode) {
1815 case OMAP_DSS_COLOR_CLUT1:
1816 case OMAP_DSS_COLOR_CLUT2:
1817 case OMAP_DSS_COLOR_CLUT4:
1818 case OMAP_DSS_COLOR_CLUT8:
1822 ps = color_mode_to_bpp(color_mode) / 8;
1826 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1829 /* width & height are overlay sizes, convert to fb sizes */
1831 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1840 * field 0 = even field = bottom field
1841 * field 1 = odd field = top field
1843 switch (rotation + mirror * 4) {
1844 case OMAP_DSS_ROT_0:
1847 *offset0 = *offset1 + field_offset * screen_width * ps;
1849 *offset0 = *offset1;
1850 *row_inc = pixinc(1 +
1851 (y_predecim * screen_width - fbw * x_predecim) +
1852 (fieldmode ? screen_width : 0), ps);
1853 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1854 color_mode == OMAP_DSS_COLOR_UYVY)
1855 *pix_inc = pixinc(x_predecim, 2 * ps);
1857 *pix_inc = pixinc(x_predecim, ps);
1859 case OMAP_DSS_ROT_90:
1860 *offset1 = screen_width * (fbh - 1) * ps;
1862 *offset0 = *offset1 + field_offset * ps;
1864 *offset0 = *offset1;
1865 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1866 y_predecim + (fieldmode ? 1 : 0), ps);
1867 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1869 case OMAP_DSS_ROT_180:
1870 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1872 *offset0 = *offset1 - field_offset * screen_width * ps;
1874 *offset0 = *offset1;
1875 *row_inc = pixinc(-1 -
1876 (y_predecim * screen_width - fbw * x_predecim) -
1877 (fieldmode ? screen_width : 0), ps);
1878 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1879 color_mode == OMAP_DSS_COLOR_UYVY)
1880 *pix_inc = pixinc(-x_predecim, 2 * ps);
1882 *pix_inc = pixinc(-x_predecim, ps);
1884 case OMAP_DSS_ROT_270:
1885 *offset1 = (fbw - 1) * ps;
1887 *offset0 = *offset1 - field_offset * ps;
1889 *offset0 = *offset1;
1890 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1891 y_predecim - (fieldmode ? 1 : 0), ps);
1892 *pix_inc = pixinc(x_predecim * screen_width, ps);
1896 case OMAP_DSS_ROT_0 + 4:
1897 *offset1 = (fbw - 1) * ps;
1899 *offset0 = *offset1 + field_offset * screen_width * ps;
1901 *offset0 = *offset1;
1902 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1903 (fieldmode ? screen_width : 0),
1905 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1906 color_mode == OMAP_DSS_COLOR_UYVY)
1907 *pix_inc = pixinc(-x_predecim, 2 * ps);
1909 *pix_inc = pixinc(-x_predecim, ps);
1912 case OMAP_DSS_ROT_90 + 4:
1915 *offset0 = *offset1 + field_offset * ps;
1917 *offset0 = *offset1;
1918 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1919 y_predecim + (fieldmode ? 1 : 0),
1921 *pix_inc = pixinc(x_predecim * screen_width, ps);
1924 case OMAP_DSS_ROT_180 + 4:
1925 *offset1 = screen_width * (fbh - 1) * ps;
1927 *offset0 = *offset1 - field_offset * screen_width * ps;
1929 *offset0 = *offset1;
1930 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1931 (fieldmode ? screen_width : 0),
1933 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1934 color_mode == OMAP_DSS_COLOR_UYVY)
1935 *pix_inc = pixinc(x_predecim, 2 * ps);
1937 *pix_inc = pixinc(x_predecim, ps);
1940 case OMAP_DSS_ROT_270 + 4:
1941 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1943 *offset0 = *offset1 - field_offset * ps;
1945 *offset0 = *offset1;
1946 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1947 y_predecim - (fieldmode ? 1 : 0),
1949 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1958 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1959 enum omap_color_mode color_mode, bool fieldmode,
1960 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1961 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1965 switch (color_mode) {
1966 case OMAP_DSS_COLOR_CLUT1:
1967 case OMAP_DSS_COLOR_CLUT2:
1968 case OMAP_DSS_COLOR_CLUT4:
1969 case OMAP_DSS_COLOR_CLUT8:
1973 ps = color_mode_to_bpp(color_mode) / 8;
1977 DSSDBG("scrw %d, width %d\n", screen_width, width);
1980 * field 0 = even field = bottom field
1981 * field 1 = odd field = top field
1985 *offset0 = *offset1 + field_offset * screen_width * ps;
1987 *offset0 = *offset1;
1988 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1989 (fieldmode ? screen_width : 0), ps);
1990 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1991 color_mode == OMAP_DSS_COLOR_UYVY)
1992 *pix_inc = pixinc(x_predecim, 2 * ps);
1994 *pix_inc = pixinc(x_predecim, ps);
1998 * This function is used to avoid synclosts in OMAP3, because of some
1999 * undocumented horizontal position and timing related limitations.
2001 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2002 const struct omap_video_timings *t, u16 pos_x,
2003 u16 width, u16 height, u16 out_width, u16 out_height,
2006 const int ds = DIV_ROUND_UP(height, out_height);
2007 unsigned long nonactive;
2008 static const u8 limits[3] = { 8, 10, 20 };
2012 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2015 if (out_height < height)
2017 if (out_width < width)
2019 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2020 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2021 if (blank <= limits[i])
2024 /* FIXME add checks for 3-tap filter once the limitations are known */
2029 * Pixel data should be prepared before visible display point starts.
2030 * So, atleast DS-2 lines must have already been fetched by DISPC
2031 * during nonactive - pos_x period.
2033 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2034 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2035 val, max(0, ds - 2) * width);
2036 if (val < max(0, ds - 2) * width)
2040 * All lines need to be refilled during the nonactive period of which
2041 * only one line can be loaded during the active period. So, atleast
2042 * DS - 1 lines should be loaded during nonactive period.
2044 val = div_u64((u64)nonactive * lclk, pclk);
2045 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2046 val, max(0, ds - 1) * width);
2047 if (val < max(0, ds - 1) * width)
2053 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2054 const struct omap_video_timings *mgr_timings, u16 width,
2055 u16 height, u16 out_width, u16 out_height,
2056 enum omap_color_mode color_mode)
2061 if (height <= out_height && width <= out_width)
2062 return (unsigned long) pclk;
2064 if (height > out_height) {
2065 unsigned int ppl = mgr_timings->x_res;
2067 tmp = pclk * height * out_width;
2068 do_div(tmp, 2 * out_height * ppl);
2071 if (height > 2 * out_height) {
2072 if (ppl == out_width)
2075 tmp = pclk * (height - 2 * out_height) * out_width;
2076 do_div(tmp, 2 * out_height * (ppl - out_width));
2077 core_clk = max_t(u32, core_clk, tmp);
2081 if (width > out_width) {
2083 do_div(tmp, out_width);
2084 core_clk = max_t(u32, core_clk, tmp);
2086 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2093 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2094 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2096 if (height > out_height && width > out_width)
2102 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2103 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2105 unsigned int hf, vf;
2108 * FIXME how to determine the 'A' factor
2109 * for the no downscaling case ?
2112 if (width > 3 * out_width)
2114 else if (width > 2 * out_width)
2116 else if (width > out_width)
2120 if (height > out_height)
2125 return pclk * vf * hf;
2128 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2129 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2132 * If the overlay/writeback is in mem to mem mode, there are no
2133 * downscaling limitations with respect to pixel clock, return 1 as
2134 * required core clock to represent that we have sufficient enough
2135 * core clock to do maximum downscaling
2140 if (width > out_width)
2141 return DIV_ROUND_UP(pclk, out_width) * width;
2146 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2147 const struct omap_video_timings *mgr_timings,
2148 u16 width, u16 height, u16 out_width, u16 out_height,
2149 enum omap_color_mode color_mode, bool *five_taps,
2150 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2151 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2154 u16 in_width, in_height;
2155 int min_factor = min(*decim_x, *decim_y);
2156 const int maxsinglelinewidth =
2157 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2162 in_height = height / *decim_y;
2163 in_width = width / *decim_x;
2164 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2165 in_height, out_width, out_height, mem_to_mem);
2166 error = (in_width > maxsinglelinewidth || !*core_clk ||
2167 *core_clk > dispc_core_clk_rate());
2169 if (*decim_x == *decim_y) {
2170 *decim_x = min_factor;
2173 swap(*decim_x, *decim_y);
2174 if (*decim_x < *decim_y)
2178 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2180 if (in_width > maxsinglelinewidth) {
2181 DSSERR("Cannot scale max input width exceeded");
2187 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2188 const struct omap_video_timings *mgr_timings,
2189 u16 width, u16 height, u16 out_width, u16 out_height,
2190 enum omap_color_mode color_mode, bool *five_taps,
2191 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2192 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2195 u16 in_width, in_height;
2196 int min_factor = min(*decim_x, *decim_y);
2197 const int maxsinglelinewidth =
2198 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2201 in_height = height / *decim_y;
2202 in_width = width / *decim_x;
2203 *five_taps = in_height > out_height;
2205 if (in_width > maxsinglelinewidth)
2206 if (in_height > out_height &&
2207 in_height < out_height * 2)
2211 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2212 in_width, in_height, out_width,
2213 out_height, color_mode);
2215 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2216 in_height, out_width, out_height,
2219 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2220 pos_x, in_width, in_height, out_width,
2221 out_height, *five_taps);
2222 if (error && *five_taps) {
2227 error = (error || in_width > maxsinglelinewidth * 2 ||
2228 (in_width > maxsinglelinewidth && *five_taps) ||
2229 !*core_clk || *core_clk > dispc_core_clk_rate());
2231 if (*decim_x == *decim_y) {
2232 *decim_x = min_factor;
2235 swap(*decim_x, *decim_y);
2236 if (*decim_x < *decim_y)
2240 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2242 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2243 height, out_width, out_height, *five_taps)) {
2244 DSSERR("horizontal timing too tight\n");
2248 if (in_width > (maxsinglelinewidth * 2)) {
2249 DSSERR("Cannot setup scaling");
2250 DSSERR("width exceeds maximum width possible");
2254 if (in_width > maxsinglelinewidth && *five_taps) {
2255 DSSERR("cannot setup scaling with five taps");
2261 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2262 const struct omap_video_timings *mgr_timings,
2263 u16 width, u16 height, u16 out_width, u16 out_height,
2264 enum omap_color_mode color_mode, bool *five_taps,
2265 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2266 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2268 u16 in_width, in_width_max;
2269 int decim_x_min = *decim_x;
2270 u16 in_height = height / *decim_y;
2271 const int maxsinglelinewidth =
2272 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2273 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2276 in_width_max = out_width * maxdownscale;
2278 in_width_max = dispc_core_clk_rate() /
2279 DIV_ROUND_UP(pclk, out_width);
2282 *decim_x = DIV_ROUND_UP(width, in_width_max);
2284 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2285 if (*decim_x > *x_predecim)
2289 in_width = width / *decim_x;
2290 } while (*decim_x <= *x_predecim &&
2291 in_width > maxsinglelinewidth && ++*decim_x);
2293 if (in_width > maxsinglelinewidth) {
2294 DSSERR("Cannot scale width exceeds max line width");
2298 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2299 out_width, out_height, mem_to_mem);
2303 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2304 enum omap_overlay_caps caps,
2305 const struct omap_video_timings *mgr_timings,
2306 u16 width, u16 height, u16 out_width, u16 out_height,
2307 enum omap_color_mode color_mode, bool *five_taps,
2308 int *x_predecim, int *y_predecim, u16 pos_x,
2309 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2311 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2312 const int max_decim_limit = 16;
2313 unsigned long core_clk = 0;
2314 int decim_x, decim_y, ret;
2316 if (width == out_width && height == out_height)
2319 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2323 *x_predecim = *y_predecim = 1;
2325 *x_predecim = max_decim_limit;
2326 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2327 dss_has_feature(FEAT_BURST_2D)) ?
2328 2 : max_decim_limit;
2331 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2332 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2333 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2334 color_mode == OMAP_DSS_COLOR_CLUT8) {
2341 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2342 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2344 if (decim_x > *x_predecim || out_width > width * 8)
2347 if (decim_y > *y_predecim || out_height > height * 8)
2350 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2351 out_width, out_height, color_mode, five_taps,
2352 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2357 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2358 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2360 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2361 DSSERR("failed to set up scaling, "
2362 "required core clk rate = %lu Hz, "
2363 "current core clk rate = %lu Hz\n",
2364 core_clk, dispc_core_clk_rate());
2368 *x_predecim = decim_x;
2369 *y_predecim = decim_y;
2373 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2374 const struct omap_overlay_info *oi,
2375 const struct omap_video_timings *timings,
2376 int *x_predecim, int *y_predecim)
2378 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2379 bool five_taps = true;
2380 bool fieldmode = false;
2381 u16 in_height = oi->height;
2382 u16 in_width = oi->width;
2383 bool ilace = timings->interlace;
2384 u16 out_width, out_height;
2385 int pos_x = oi->pos_x;
2386 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2387 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2389 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2390 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2392 if (ilace && oi->height == out_height)
2400 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2401 in_height, out_height);
2404 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2407 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2408 in_height, out_width, out_height, oi->color_mode,
2409 &five_taps, x_predecim, y_predecim, pos_x,
2410 oi->rotation_type, false);
2412 EXPORT_SYMBOL(dispc_ovl_check);
2414 static int dispc_ovl_setup_common(enum omap_plane plane,
2415 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2416 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2417 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2418 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2419 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2420 bool replication, const struct omap_video_timings *mgr_timings,
2423 bool five_taps = true;
2424 bool fieldmode = false;
2426 unsigned offset0, offset1;
2429 u16 frame_width, frame_height;
2430 unsigned int field_offset = 0;
2431 u16 in_height = height;
2432 u16 in_width = width;
2433 int x_predecim = 1, y_predecim = 1;
2434 bool ilace = mgr_timings->interlace;
2435 unsigned long pclk = dispc_plane_pclk_rate(plane);
2436 unsigned long lclk = dispc_plane_lclk_rate(plane);
2441 out_width = out_width == 0 ? width : out_width;
2442 out_height = out_height == 0 ? height : out_height;
2444 if (ilace && height == out_height)
2453 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2454 "out_height %d\n", in_height, pos_y,
2458 if (!dss_feat_color_mode_supported(plane, color_mode))
2461 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2462 in_height, out_width, out_height, color_mode,
2463 &five_taps, &x_predecim, &y_predecim, pos_x,
2464 rotation_type, mem_to_mem);
2468 in_width = in_width / x_predecim;
2469 in_height = in_height / y_predecim;
2471 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2472 color_mode == OMAP_DSS_COLOR_UYVY ||
2473 color_mode == OMAP_DSS_COLOR_NV12)
2476 if (ilace && !fieldmode) {
2478 * when downscaling the bottom field may have to start several
2479 * source lines below the top field. Unfortunately ACCUI
2480 * registers will only hold the fractional part of the offset
2481 * so the integer part must be added to the base address of the
2484 if (!in_height || in_height == out_height)
2487 field_offset = in_height / out_height / 2;
2490 /* Fields are independent but interleaved in memory. */
2499 if (plane == OMAP_DSS_WB) {
2500 frame_width = out_width;
2501 frame_height = out_height;
2503 frame_width = in_width;
2504 frame_height = height;
2507 if (rotation_type == OMAP_DSS_ROT_TILER)
2508 calc_tiler_rotation_offset(screen_width, frame_width,
2509 color_mode, fieldmode, field_offset,
2510 &offset0, &offset1, &row_inc, &pix_inc,
2511 x_predecim, y_predecim);
2512 else if (rotation_type == OMAP_DSS_ROT_DMA)
2513 calc_dma_rotation_offset(rotation, mirror, screen_width,
2514 frame_width, frame_height,
2515 color_mode, fieldmode, field_offset,
2516 &offset0, &offset1, &row_inc, &pix_inc,
2517 x_predecim, y_predecim);
2519 calc_vrfb_rotation_offset(rotation, mirror,
2520 screen_width, frame_width, frame_height,
2521 color_mode, fieldmode, field_offset,
2522 &offset0, &offset1, &row_inc, &pix_inc,
2523 x_predecim, y_predecim);
2525 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2526 offset0, offset1, row_inc, pix_inc);
2528 dispc_ovl_set_color_mode(plane, color_mode);
2530 dispc_ovl_configure_burst_type(plane, rotation_type);
2532 dispc_ovl_set_ba0(plane, paddr + offset0);
2533 dispc_ovl_set_ba1(plane, paddr + offset1);
2535 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2536 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2537 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2540 dispc_ovl_set_row_inc(plane, row_inc);
2541 dispc_ovl_set_pix_inc(plane, pix_inc);
2543 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2544 in_height, out_width, out_height);
2546 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2548 dispc_ovl_set_input_size(plane, in_width, in_height);
2550 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2551 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2552 out_height, ilace, five_taps, fieldmode,
2553 color_mode, rotation);
2554 dispc_ovl_set_output_size(plane, out_width, out_height);
2555 dispc_ovl_set_vid_color_conv(plane, cconv);
2558 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2561 dispc_ovl_set_zorder(plane, caps, zorder);
2562 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2563 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2565 dispc_ovl_enable_replication(plane, caps, replication);
2570 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2571 bool replication, const struct omap_video_timings *mgr_timings,
2575 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2576 enum omap_channel channel;
2578 channel = dispc_ovl_get_channel_out(plane);
2580 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2581 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2582 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2583 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2584 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2586 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2587 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2588 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2589 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2590 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2594 EXPORT_SYMBOL(dispc_ovl_setup);
2596 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2597 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2601 enum omap_plane plane = OMAP_DSS_WB;
2602 const int pos_x = 0, pos_y = 0;
2603 const u8 zorder = 0, global_alpha = 0;
2604 const bool replication = false;
2606 int in_width = mgr_timings->x_res;
2607 int in_height = mgr_timings->y_res;
2608 enum omap_overlay_caps caps =
2609 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2611 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2612 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2613 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2616 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2617 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2618 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2619 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2620 replication, mgr_timings, mem_to_mem);
2622 switch (wi->color_mode) {
2623 case OMAP_DSS_COLOR_RGB16:
2624 case OMAP_DSS_COLOR_RGB24P:
2625 case OMAP_DSS_COLOR_ARGB16:
2626 case OMAP_DSS_COLOR_RGBA16:
2627 case OMAP_DSS_COLOR_RGB12U:
2628 case OMAP_DSS_COLOR_ARGB16_1555:
2629 case OMAP_DSS_COLOR_XRGB16_1555:
2630 case OMAP_DSS_COLOR_RGBX16:
2638 /* setup extra DISPC_WB_ATTRIBUTES */
2639 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2640 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2641 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2642 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2647 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2649 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2651 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2655 EXPORT_SYMBOL(dispc_ovl_enable);
2657 bool dispc_ovl_enabled(enum omap_plane plane)
2659 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2661 EXPORT_SYMBOL(dispc_ovl_enabled);
2663 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2665 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2666 /* flush posted write */
2667 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2669 EXPORT_SYMBOL(dispc_mgr_enable);
2671 bool dispc_mgr_is_enabled(enum omap_channel channel)
2673 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2675 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2677 void dispc_wb_enable(bool enable)
2679 dispc_ovl_enable(OMAP_DSS_WB, enable);
2682 bool dispc_wb_is_enabled(void)
2684 return dispc_ovl_enabled(OMAP_DSS_WB);
2687 static void dispc_lcd_enable_signal_polarity(bool act_high)
2689 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2692 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2695 void dispc_lcd_enable_signal(bool enable)
2697 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2700 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2703 void dispc_pck_free_enable(bool enable)
2705 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2708 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2711 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2713 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2717 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2719 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2722 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2724 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2728 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2730 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2733 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2734 enum omap_dss_trans_key_type type,
2737 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2739 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2742 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2744 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2747 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2750 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2753 if (ch == OMAP_DSS_CHANNEL_LCD)
2754 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2755 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2756 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2759 void dispc_mgr_setup(enum omap_channel channel,
2760 const struct omap_overlay_manager_info *info)
2762 dispc_mgr_set_default_color(channel, info->default_color);
2763 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2764 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2765 dispc_mgr_enable_alpha_fixed_zorder(channel,
2766 info->partial_alpha_enabled);
2767 if (dss_has_feature(FEAT_CPR)) {
2768 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2769 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2772 EXPORT_SYMBOL(dispc_mgr_setup);
2774 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2778 switch (data_lines) {
2796 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2799 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2805 case DSS_IO_PAD_MODE_RESET:
2809 case DSS_IO_PAD_MODE_RFBI:
2813 case DSS_IO_PAD_MODE_BYPASS:
2822 l = dispc_read_reg(DISPC_CONTROL);
2823 l = FLD_MOD(l, gpout0, 15, 15);
2824 l = FLD_MOD(l, gpout1, 16, 16);
2825 dispc_write_reg(DISPC_CONTROL, l);
2828 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2830 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2833 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2834 const struct dss_lcd_mgr_config *config)
2836 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2838 dispc_mgr_enable_stallmode(channel, config->stallmode);
2839 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2841 dispc_mgr_set_clock_div(channel, &config->clock_info);
2843 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2845 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2847 dispc_mgr_set_lcd_type_tft(channel);
2849 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2851 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2853 return width <= dispc.feat->mgr_width_max &&
2854 height <= dispc.feat->mgr_height_max;
2857 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2858 int vsw, int vfp, int vbp)
2860 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2861 hfp < 1 || hfp > dispc.feat->hp_max ||
2862 hbp < 1 || hbp > dispc.feat->hp_max ||
2863 vsw < 1 || vsw > dispc.feat->sw_max ||
2864 vfp < 0 || vfp > dispc.feat->vp_max ||
2865 vbp < 0 || vbp > dispc.feat->vp_max)
2870 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2873 if (dss_mgr_is_lcd(channel))
2874 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2876 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2879 bool dispc_mgr_timings_ok(enum omap_channel channel,
2880 const struct omap_video_timings *timings)
2882 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2885 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2888 if (dss_mgr_is_lcd(channel)) {
2889 /* TODO: OMAP4+ supports interlace for LCD outputs */
2890 if (timings->interlace)
2893 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2894 timings->hbp, timings->vsw, timings->vfp,
2902 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2903 int hfp, int hbp, int vsw, int vfp, int vbp,
2904 enum omap_dss_signal_level vsync_level,
2905 enum omap_dss_signal_level hsync_level,
2906 enum omap_dss_signal_edge data_pclk_edge,
2907 enum omap_dss_signal_level de_level,
2908 enum omap_dss_signal_edge sync_pclk_edge)
2911 u32 timing_h, timing_v, l;
2912 bool onoff, rf, ipc;
2914 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2915 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2916 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2917 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2918 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2919 FLD_VAL(vbp, dispc.feat->bp_start, 20);
2921 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2922 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2924 switch (data_pclk_edge) {
2925 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2928 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2931 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2936 switch (sync_pclk_edge) {
2937 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2941 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2945 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2953 l = FLD_VAL(onoff, 17, 17) |
2954 FLD_VAL(rf, 16, 16) |
2955 FLD_VAL(de_level, 15, 15) |
2956 FLD_VAL(ipc, 14, 14) |
2957 FLD_VAL(hsync_level, 13, 13) |
2958 FLD_VAL(vsync_level, 12, 12);
2960 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2963 /* change name to mode? */
2964 void dispc_mgr_set_timings(enum omap_channel channel,
2965 const struct omap_video_timings *timings)
2967 unsigned xtot, ytot;
2968 unsigned long ht, vt;
2969 struct omap_video_timings t = *timings;
2971 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2973 if (!dispc_mgr_timings_ok(channel, &t)) {
2978 if (dss_mgr_is_lcd(channel)) {
2979 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2980 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2981 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2983 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2984 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2986 ht = timings->pixelclock / xtot;
2987 vt = timings->pixelclock / xtot / ytot;
2989 DSSDBG("pck %u\n", timings->pixelclock);
2990 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2991 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2992 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2993 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2994 t.de_level, t.sync_pclk_edge);
2996 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2998 if (t.interlace == true)
3002 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3004 EXPORT_SYMBOL(dispc_mgr_set_timings);
3006 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3009 BUG_ON(lck_div < 1);
3010 BUG_ON(pck_div < 1);
3012 dispc_write_reg(DISPC_DIVISORo(channel),
3013 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3015 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3016 channel == OMAP_DSS_CHANNEL_LCD)
3017 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3020 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3024 l = dispc_read_reg(DISPC_DIVISORo(channel));
3025 *lck_div = FLD_GET(l, 23, 16);
3026 *pck_div = FLD_GET(l, 7, 0);
3029 unsigned long dispc_fclk_rate(void)
3031 struct platform_device *dsidev;
3032 unsigned long r = 0;
3034 switch (dss_get_dispc_clk_source()) {
3035 case OMAP_DSS_CLK_SRC_FCK:
3036 r = dss_get_dispc_clk_rate();
3038 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3039 dsidev = dsi_get_dsidev_from_id(0);
3040 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3042 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3043 dsidev = dsi_get_dsidev_from_id(1);
3044 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3054 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3056 struct platform_device *dsidev;
3061 if (dss_mgr_is_lcd(channel)) {
3062 l = dispc_read_reg(DISPC_DIVISORo(channel));
3064 lcd = FLD_GET(l, 23, 16);
3066 switch (dss_get_lcd_clk_source(channel)) {
3067 case OMAP_DSS_CLK_SRC_FCK:
3068 r = dss_get_dispc_clk_rate();
3070 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3071 dsidev = dsi_get_dsidev_from_id(0);
3072 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3074 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3075 dsidev = dsi_get_dsidev_from_id(1);
3076 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3085 return dispc_fclk_rate();
3089 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3093 if (dss_mgr_is_lcd(channel)) {
3097 l = dispc_read_reg(DISPC_DIVISORo(channel));
3099 pcd = FLD_GET(l, 7, 0);
3101 r = dispc_mgr_lclk_rate(channel);
3105 return dispc.tv_pclk_rate;
3109 void dispc_set_tv_pclk(unsigned long pclk)
3111 dispc.tv_pclk_rate = pclk;
3114 unsigned long dispc_core_clk_rate(void)
3116 return dispc.core_clk_rate;
3119 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3121 enum omap_channel channel;
3123 if (plane == OMAP_DSS_WB)
3126 channel = dispc_ovl_get_channel_out(plane);
3128 return dispc_mgr_pclk_rate(channel);
3131 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3133 enum omap_channel channel;
3135 if (plane == OMAP_DSS_WB)
3138 channel = dispc_ovl_get_channel_out(plane);
3140 return dispc_mgr_lclk_rate(channel);
3143 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3146 enum omap_dss_clk_source lcd_clk_src;
3148 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3150 lcd_clk_src = dss_get_lcd_clk_source(channel);
3152 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3153 dss_get_generic_clk_source_name(lcd_clk_src),
3154 dss_feat_get_clk_source_name(lcd_clk_src));
3156 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3158 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3159 dispc_mgr_lclk_rate(channel), lcd);
3160 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3161 dispc_mgr_pclk_rate(channel), pcd);
3164 void dispc_dump_clocks(struct seq_file *s)
3168 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3170 if (dispc_runtime_get())
3173 seq_printf(s, "- DISPC -\n");
3175 seq_printf(s, "dispc fclk source = %s (%s)\n",
3176 dss_get_generic_clk_source_name(dispc_clk_src),
3177 dss_feat_get_clk_source_name(dispc_clk_src));
3179 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3181 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3182 seq_printf(s, "- DISPC-CORE-CLK -\n");
3183 l = dispc_read_reg(DISPC_DIVISOR);
3184 lcd = FLD_GET(l, 23, 16);
3186 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3187 (dispc_fclk_rate()/lcd), lcd);
3190 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3192 if (dss_has_feature(FEAT_MGR_LCD2))
3193 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3194 if (dss_has_feature(FEAT_MGR_LCD3))
3195 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3197 dispc_runtime_put();
3200 static void dispc_dump_regs(struct seq_file *s)
3203 const char *mgr_names[] = {
3204 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3205 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3206 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3207 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3209 const char *ovl_names[] = {
3210 [OMAP_DSS_GFX] = "GFX",
3211 [OMAP_DSS_VIDEO1] = "VID1",
3212 [OMAP_DSS_VIDEO2] = "VID2",
3213 [OMAP_DSS_VIDEO3] = "VID3",
3215 const char **p_names;
3217 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3219 if (dispc_runtime_get())
3222 /* DISPC common registers */
3223 DUMPREG(DISPC_REVISION);
3224 DUMPREG(DISPC_SYSCONFIG);
3225 DUMPREG(DISPC_SYSSTATUS);
3226 DUMPREG(DISPC_IRQSTATUS);
3227 DUMPREG(DISPC_IRQENABLE);
3228 DUMPREG(DISPC_CONTROL);
3229 DUMPREG(DISPC_CONFIG);
3230 DUMPREG(DISPC_CAPABLE);
3231 DUMPREG(DISPC_LINE_STATUS);
3232 DUMPREG(DISPC_LINE_NUMBER);
3233 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3234 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3235 DUMPREG(DISPC_GLOBAL_ALPHA);
3236 if (dss_has_feature(FEAT_MGR_LCD2)) {
3237 DUMPREG(DISPC_CONTROL2);
3238 DUMPREG(DISPC_CONFIG2);
3240 if (dss_has_feature(FEAT_MGR_LCD3)) {
3241 DUMPREG(DISPC_CONTROL3);
3242 DUMPREG(DISPC_CONFIG3);
3244 if (dss_has_feature(FEAT_MFLAG))
3245 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3249 #define DISPC_REG(i, name) name(i)
3250 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3251 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3252 dispc_read_reg(DISPC_REG(i, r)))
3254 p_names = mgr_names;
3256 /* DISPC channel specific registers */
3257 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3258 DUMPREG(i, DISPC_DEFAULT_COLOR);
3259 DUMPREG(i, DISPC_TRANS_COLOR);
3260 DUMPREG(i, DISPC_SIZE_MGR);
3262 if (i == OMAP_DSS_CHANNEL_DIGIT)
3265 DUMPREG(i, DISPC_TIMING_H);
3266 DUMPREG(i, DISPC_TIMING_V);
3267 DUMPREG(i, DISPC_POL_FREQ);
3268 DUMPREG(i, DISPC_DIVISORo);
3270 DUMPREG(i, DISPC_DATA_CYCLE1);
3271 DUMPREG(i, DISPC_DATA_CYCLE2);
3272 DUMPREG(i, DISPC_DATA_CYCLE3);
3274 if (dss_has_feature(FEAT_CPR)) {
3275 DUMPREG(i, DISPC_CPR_COEF_R);
3276 DUMPREG(i, DISPC_CPR_COEF_G);
3277 DUMPREG(i, DISPC_CPR_COEF_B);
3281 p_names = ovl_names;
3283 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3284 DUMPREG(i, DISPC_OVL_BA0);
3285 DUMPREG(i, DISPC_OVL_BA1);
3286 DUMPREG(i, DISPC_OVL_POSITION);
3287 DUMPREG(i, DISPC_OVL_SIZE);
3288 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3289 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3290 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3291 DUMPREG(i, DISPC_OVL_ROW_INC);
3292 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3293 if (dss_has_feature(FEAT_PRELOAD))
3294 DUMPREG(i, DISPC_OVL_PRELOAD);
3296 if (i == OMAP_DSS_GFX) {
3297 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3298 DUMPREG(i, DISPC_OVL_TABLE_BA);
3302 DUMPREG(i, DISPC_OVL_FIR);
3303 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3304 DUMPREG(i, DISPC_OVL_ACCU0);
3305 DUMPREG(i, DISPC_OVL_ACCU1);
3306 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3307 DUMPREG(i, DISPC_OVL_BA0_UV);
3308 DUMPREG(i, DISPC_OVL_BA1_UV);
3309 DUMPREG(i, DISPC_OVL_FIR2);
3310 DUMPREG(i, DISPC_OVL_ACCU2_0);
3311 DUMPREG(i, DISPC_OVL_ACCU2_1);
3313 if (dss_has_feature(FEAT_ATTR2))
3314 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3315 if (dss_has_feature(FEAT_PRELOAD))
3316 DUMPREG(i, DISPC_OVL_PRELOAD);
3317 if (dss_has_feature(FEAT_MFLAG))
3318 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3324 #define DISPC_REG(plane, name, i) name(plane, i)
3325 #define DUMPREG(plane, name, i) \
3326 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3327 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3328 dispc_read_reg(DISPC_REG(plane, name, i)))
3330 /* Video pipeline coefficient registers */
3332 /* start from OMAP_DSS_VIDEO1 */
3333 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3334 for (j = 0; j < 8; j++)
3335 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3337 for (j = 0; j < 8; j++)
3338 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3340 for (j = 0; j < 5; j++)
3341 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3343 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3344 for (j = 0; j < 8; j++)
3345 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3348 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3349 for (j = 0; j < 8; j++)
3350 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3352 for (j = 0; j < 8; j++)
3353 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3355 for (j = 0; j < 8; j++)
3356 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3360 dispc_runtime_put();
3366 /* calculate clock rates using dividers in cinfo */
3367 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3368 struct dispc_clock_info *cinfo)
3370 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3372 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3375 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3376 cinfo->pck = cinfo->lck / cinfo->pck_div;
3381 bool dispc_div_calc(unsigned long dispc,
3382 unsigned long pck_min, unsigned long pck_max,
3383 dispc_div_calc_func func, void *data)
3385 int lckd, lckd_start, lckd_stop;
3386 int pckd, pckd_start, pckd_stop;
3387 unsigned long pck, lck;
3388 unsigned long lck_max;
3389 unsigned long pckd_hw_min, pckd_hw_max;
3390 unsigned min_fck_per_pck;
3393 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3394 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3396 min_fck_per_pck = 0;
3399 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3400 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3402 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3404 pck_min = pck_min ? pck_min : 1;
3405 pck_max = pck_max ? pck_max : ULONG_MAX;
3407 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3408 lckd_stop = min(dispc / pck_min, 255ul);
3410 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3413 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3414 pckd_stop = min(lck / pck_min, pckd_hw_max);
3416 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3420 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3421 * clock, which means we're configuring DISPC fclk here
3422 * also. Thus we need to use the calculated lck. For
3423 * OMAP4+ the DISPC fclk is a separate clock.
3425 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3426 fck = dispc_core_clk_rate();
3430 if (fck < pck * min_fck_per_pck)
3433 if (func(lckd, pckd, lck, pck, data))
3441 void dispc_mgr_set_clock_div(enum omap_channel channel,
3442 const struct dispc_clock_info *cinfo)
3444 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3445 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3447 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3450 int dispc_mgr_get_clock_div(enum omap_channel channel,
3451 struct dispc_clock_info *cinfo)
3455 fck = dispc_fclk_rate();
3457 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3458 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3460 cinfo->lck = fck / cinfo->lck_div;
3461 cinfo->pck = cinfo->lck / cinfo->pck_div;
3466 u32 dispc_read_irqstatus(void)
3468 return dispc_read_reg(DISPC_IRQSTATUS);
3470 EXPORT_SYMBOL(dispc_read_irqstatus);
3472 void dispc_clear_irqstatus(u32 mask)
3474 dispc_write_reg(DISPC_IRQSTATUS, mask);
3476 EXPORT_SYMBOL(dispc_clear_irqstatus);
3478 u32 dispc_read_irqenable(void)
3480 return dispc_read_reg(DISPC_IRQENABLE);
3482 EXPORT_SYMBOL(dispc_read_irqenable);
3484 void dispc_write_irqenable(u32 mask)
3486 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3488 /* clear the irqstatus for newly enabled irqs */
3489 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3491 dispc_write_reg(DISPC_IRQENABLE, mask);
3493 EXPORT_SYMBOL(dispc_write_irqenable);
3495 void dispc_enable_sidle(void)
3497 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3500 void dispc_disable_sidle(void)
3502 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3505 static void _omap_dispc_initial_config(void)
3509 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3510 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3511 l = dispc_read_reg(DISPC_DIVISOR);
3512 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3513 l = FLD_MOD(l, 1, 0, 0);
3514 l = FLD_MOD(l, 1, 23, 16);
3515 dispc_write_reg(DISPC_DIVISOR, l);
3517 dispc.core_clk_rate = dispc_fclk_rate();
3521 if (dss_has_feature(FEAT_FUNCGATED))
3522 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3524 dispc_setup_color_conv_coef();
3526 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3530 dispc_configure_burst_sizes();
3532 dispc_ovl_enable_zorder_planes();
3534 if (dispc.feat->mstandby_workaround)
3535 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3538 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3545 .mgr_width_start = 10,
3546 .mgr_height_start = 26,
3547 .mgr_width_max = 2048,
3548 .mgr_height_max = 2048,
3549 .max_lcd_pclk = 66500000,
3550 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3551 .calc_core_clk = calc_core_clk_24xx,
3553 .no_framedone_tv = true,
3554 .set_max_preload = false,
3557 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3564 .mgr_width_start = 10,
3565 .mgr_height_start = 26,
3566 .mgr_width_max = 2048,
3567 .mgr_height_max = 2048,
3568 .max_lcd_pclk = 173000000,
3569 .max_tv_pclk = 59000000,
3570 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3571 .calc_core_clk = calc_core_clk_34xx,
3573 .no_framedone_tv = true,
3574 .set_max_preload = false,
3577 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3584 .mgr_width_start = 10,
3585 .mgr_height_start = 26,
3586 .mgr_width_max = 2048,
3587 .mgr_height_max = 2048,
3588 .max_lcd_pclk = 173000000,
3589 .max_tv_pclk = 59000000,
3590 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3591 .calc_core_clk = calc_core_clk_34xx,
3593 .no_framedone_tv = true,
3594 .set_max_preload = false,
3597 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3604 .mgr_width_start = 10,
3605 .mgr_height_start = 26,
3606 .mgr_width_max = 2048,
3607 .mgr_height_max = 2048,
3608 .max_lcd_pclk = 170000000,
3609 .max_tv_pclk = 185625000,
3610 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3611 .calc_core_clk = calc_core_clk_44xx,
3613 .gfx_fifo_workaround = true,
3614 .set_max_preload = true,
3617 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3624 .mgr_width_start = 11,
3625 .mgr_height_start = 27,
3626 .mgr_width_max = 4096,
3627 .mgr_height_max = 4096,
3628 .max_lcd_pclk = 170000000,
3629 .max_tv_pclk = 186000000,
3630 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3631 .calc_core_clk = calc_core_clk_44xx,
3633 .gfx_fifo_workaround = true,
3634 .mstandby_workaround = true,
3635 .set_max_preload = true,
3638 static int __init dispc_init_features(struct platform_device *pdev)
3640 const struct dispc_features *src;
3641 struct dispc_features *dst;
3643 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3645 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3649 switch (omapdss_get_version()) {
3650 case OMAPDSS_VER_OMAP24xx:
3651 src = &omap24xx_dispc_feats;
3654 case OMAPDSS_VER_OMAP34xx_ES1:
3655 src = &omap34xx_rev1_0_dispc_feats;
3658 case OMAPDSS_VER_OMAP34xx_ES3:
3659 case OMAPDSS_VER_OMAP3630:
3660 case OMAPDSS_VER_AM35xx:
3661 case OMAPDSS_VER_AM43xx:
3662 src = &omap34xx_rev3_0_dispc_feats;
3665 case OMAPDSS_VER_OMAP4430_ES1:
3666 case OMAPDSS_VER_OMAP4430_ES2:
3667 case OMAPDSS_VER_OMAP4:
3668 src = &omap44xx_dispc_feats;
3671 case OMAPDSS_VER_OMAP5:
3672 src = &omap54xx_dispc_feats;
3679 memcpy(dst, src, sizeof(*dst));
3685 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3687 if (!dispc.is_enabled)
3690 return dispc.user_handler(irq, dispc.user_data);
3693 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3697 if (dispc.user_handler != NULL)
3700 dispc.user_handler = handler;
3701 dispc.user_data = dev_id;
3703 /* ensure the dispc_irq_handler sees the values above */
3706 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3707 IRQF_SHARED, "OMAP DISPC", &dispc);
3709 dispc.user_handler = NULL;
3710 dispc.user_data = NULL;
3715 EXPORT_SYMBOL(dispc_request_irq);
3717 void dispc_free_irq(void *dev_id)
3719 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3721 dispc.user_handler = NULL;
3722 dispc.user_data = NULL;
3724 EXPORT_SYMBOL(dispc_free_irq);
3726 /* DISPC HW IP initialisation */
3727 static int __init omap_dispchw_probe(struct platform_device *pdev)
3731 struct resource *dispc_mem;
3735 r = dispc_init_features(dispc.pdev);
3739 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3741 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3745 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3746 resource_size(dispc_mem));
3748 DSSERR("can't ioremap DISPC\n");
3752 dispc.irq = platform_get_irq(dispc.pdev, 0);
3753 if (dispc.irq < 0) {
3754 DSSERR("platform_get_irq failed\n");
3758 pm_runtime_enable(&pdev->dev);
3760 r = dispc_runtime_get();
3762 goto err_runtime_get;
3764 _omap_dispc_initial_config();
3766 rev = dispc_read_reg(DISPC_REVISION);
3767 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3768 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3770 dispc_runtime_put();
3772 dss_init_overlay_managers();
3774 dss_debugfs_create_file("dispc", dispc_dump_regs);
3779 pm_runtime_disable(&pdev->dev);
3783 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3785 pm_runtime_disable(&pdev->dev);
3787 dss_uninit_overlay_managers();
3792 static int dispc_runtime_suspend(struct device *dev)
3794 dispc.is_enabled = false;
3795 /* ensure the dispc_irq_handler sees the is_enabled value */
3797 /* wait for current handler to finish before turning the DISPC off */
3798 synchronize_irq(dispc.irq);
3800 dispc_save_context();
3805 static int dispc_runtime_resume(struct device *dev)
3808 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3809 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3810 * _omap_dispc_initial_config(). We can thus use it to detect if
3811 * we have lost register context.
3813 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
3814 _omap_dispc_initial_config();
3816 dispc_restore_context();
3819 dispc.is_enabled = true;
3820 /* ensure the dispc_irq_handler sees the is_enabled value */
3826 static const struct dev_pm_ops dispc_pm_ops = {
3827 .runtime_suspend = dispc_runtime_suspend,
3828 .runtime_resume = dispc_runtime_resume,
3831 static const struct of_device_id dispc_of_match[] = {
3832 { .compatible = "ti,omap2-dispc", },
3833 { .compatible = "ti,omap3-dispc", },
3834 { .compatible = "ti,omap4-dispc", },
3835 { .compatible = "ti,omap5-dispc", },
3839 static struct platform_driver omap_dispchw_driver = {
3840 .remove = __exit_p(omap_dispchw_remove),
3842 .name = "omapdss_dispc",
3843 .owner = THIS_MODULE,
3844 .pm = &dispc_pm_ops,
3845 .of_match_table = dispc_of_match,
3849 int __init dispc_init_platform_driver(void)
3851 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3854 void __exit dispc_uninit_platform_driver(void)
3856 platform_driver_unregister(&omap_dispchw_driver);