2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <video/da8xx-fb.h>
35 #define DRIVER_NAME "da8xx_lcdc"
37 /* LCD Status Register */
38 #define LCD_END_OF_FRAME0 BIT(8)
39 #define LCD_FIFO_UNDERFLOW BIT(5)
40 #define LCD_SYNC_LOST BIT(2)
42 /* LCD DMA Control Register */
43 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
44 #define LCD_DMA_BURST_1 0x0
45 #define LCD_DMA_BURST_2 0x1
46 #define LCD_DMA_BURST_4 0x2
47 #define LCD_DMA_BURST_8 0x3
48 #define LCD_DMA_BURST_16 0x4
49 #define LCD_END_OF_FRAME_INT_ENA BIT(2)
50 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
52 /* LCD Control Register */
53 #define LCD_CLK_DIVISOR(x) ((x) << 8)
54 #define LCD_RASTER_MODE 0x01
56 /* LCD Raster Control Register */
57 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
58 #define PALETTE_AND_DATA 0x00
59 #define PALETTE_ONLY 0x01
61 #define LCD_MONO_8BIT_MODE BIT(9)
62 #define LCD_RASTER_ORDER BIT(8)
63 #define LCD_TFT_MODE BIT(7)
64 #define LCD_UNDERFLOW_INT_ENA BIT(6)
65 #define LCD_MONOCHROME_MODE BIT(1)
66 #define LCD_RASTER_ENABLE BIT(0)
67 #define LCD_TFT_ALT_ENABLE BIT(23)
68 #define LCD_STN_565_ENABLE BIT(24)
70 /* LCD Raster Timing 2 Register */
71 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
72 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
73 #define LCD_SYNC_CTRL BIT(25)
74 #define LCD_SYNC_EDGE BIT(24)
75 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
76 #define LCD_INVERT_LINE_CLOCK BIT(21)
77 #define LCD_INVERT_FRAME_CLOCK BIT(20)
80 #define LCD_CTRL_REG 0x4
81 #define LCD_STAT_REG 0x8
82 #define LCD_RASTER_CTRL_REG 0x28
83 #define LCD_RASTER_TIMING_0_REG 0x2C
84 #define LCD_RASTER_TIMING_1_REG 0x30
85 #define LCD_RASTER_TIMING_2_REG 0x34
86 #define LCD_DMA_CTRL_REG 0x40
87 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
88 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
90 #define WSI_TIMEOUT 50
91 #define PALETTE_SIZE 256
92 #define LEFT_MARGIN 64
93 #define RIGHT_MARGIN 64
94 #define UPPER_MARGIN 32
95 #define LOWER_MARGIN 32
97 static resource_size_t da8xx_fb_reg_base;
98 static struct resource *lcdc_regs;
100 static inline unsigned int lcdc_read(unsigned int addr)
102 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
105 static inline void lcdc_write(unsigned int val, unsigned int addr)
107 __raw_writel(val, da8xx_fb_reg_base + (addr));
110 struct da8xx_fb_par {
111 resource_size_t p_palette_base;
112 unsigned char *v_palette_base;
113 struct clk *lcdc_clk;
115 unsigned short pseudo_palette[16];
116 unsigned int databuf_sz;
117 unsigned int palette_sz;
118 unsigned int pxl_clk;
120 #ifdef CONFIG_CPU_FREQ
121 struct notifier_block freq_transition;
123 void (*panel_power_ctrl)(int);
126 /* Variable Screen Information */
127 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
135 .pixclock = 46666, /* 46us - AUO display */
137 .left_margin = LEFT_MARGIN,
138 .right_margin = RIGHT_MARGIN,
139 .upper_margin = UPPER_MARGIN,
140 .lower_margin = LOWER_MARGIN,
142 .vmode = FB_VMODE_NONINTERLACED
145 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
146 .id = "DA8xx FB Drv",
147 .type = FB_TYPE_PACKED_PIXELS,
149 .visual = FB_VISUAL_PSEUDOCOLOR,
153 .accel = FB_ACCEL_NONE
157 const char name[25]; /* Full name <vendor>_<model> */
158 unsigned short width;
159 unsigned short height;
160 int hfp; /* Horizontal front porch */
161 int hbp; /* Horizontal back porch */
162 int hsw; /* Horizontal Sync Pulse Width */
163 int vfp; /* Vertical front porch */
164 int vbp; /* Vertical back porch */
165 int vsw; /* Vertical Sync Pulse Width */
166 unsigned int pxl_clk; /* Pixel clock */
167 unsigned char invert_pxl_clk; /* Invert Pixel clock */
170 static struct da8xx_panel known_lcd_panels[] = {
171 /* Sharp LCD035Q3DG01 */
173 .name = "Sharp_LCD035Q3DG01",
185 /* Sharp LK043T1DG01 */
187 .name = "Sharp_LK043T1DG01",
201 /* Enable the Raster Engine of the LCD Controller */
202 static inline void lcd_enable_raster(void)
206 reg = lcdc_read(LCD_RASTER_CTRL_REG);
207 if (!(reg & LCD_RASTER_ENABLE))
208 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
211 /* Disable the Raster Engine of the LCD Controller */
212 static inline void lcd_disable_raster(void)
216 reg = lcdc_read(LCD_RASTER_CTRL_REG);
217 if (reg & LCD_RASTER_ENABLE)
218 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
221 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
223 u32 tmp = par->p_palette_base + par->databuf_sz - 4;
226 /* Update the databuf in the hw. */
227 lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
228 lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
231 reg = lcdc_read(LCD_RASTER_CTRL_REG);
233 if (load_mode == LOAD_DATA)
234 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
235 else if (load_mode == LOAD_PALETTE)
236 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
238 lcdc_write(reg, LCD_RASTER_CTRL_REG);
241 /* Configure the Burst Size of DMA */
242 static int lcd_cfg_dma(int burst_size)
246 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
247 switch (burst_size) {
249 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
252 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
255 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
258 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
261 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
266 lcdc_write(reg, LCD_DMA_CTRL_REG);
271 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
275 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
276 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
277 reg |= LCD_AC_BIAS_FREQUENCY(period) |
278 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
279 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
282 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
287 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
288 reg |= ((back_porch & 0xff) << 24)
289 | ((front_porch & 0xff) << 16)
290 | ((pulse_width & 0x3f) << 10);
291 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
294 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
299 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
300 reg |= ((back_porch & 0xff) << 24)
301 | ((front_porch & 0xff) << 16)
302 | ((pulse_width & 0x3f) << 10);
303 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
306 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
310 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
312 LCD_MONOCHROME_MODE);
314 switch (cfg->p_disp_panel->panel_shade) {
316 reg |= LCD_MONOCHROME_MODE;
317 if (cfg->mono_8bit_mode)
318 reg |= LCD_MONO_8BIT_MODE;
322 if (cfg->tft_alt_mode)
323 reg |= LCD_TFT_ALT_ENABLE;
327 if (cfg->stn_565_mode)
328 reg |= LCD_STN_565_ENABLE;
335 /* enable additional interrupts here */
336 reg |= LCD_UNDERFLOW_INT_ENA;
338 lcdc_write(reg, LCD_RASTER_CTRL_REG);
340 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
343 reg |= LCD_SYNC_CTRL;
345 reg &= ~LCD_SYNC_CTRL;
348 reg |= LCD_SYNC_EDGE;
350 reg &= ~LCD_SYNC_EDGE;
352 if (cfg->invert_line_clock)
353 reg |= LCD_INVERT_LINE_CLOCK;
355 reg &= ~LCD_INVERT_LINE_CLOCK;
357 if (cfg->invert_frm_clock)
358 reg |= LCD_INVERT_FRAME_CLOCK;
360 reg &= ~LCD_INVERT_FRAME_CLOCK;
362 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
367 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
368 u32 bpp, u32 raster_order)
372 /* Disable Dual Frame Buffer. */
373 reg = lcdc_read(LCD_DMA_CTRL_REG);
374 lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
376 /* Set the Panel Width */
377 /* Pixels per line = (PPL + 1)*16 */
378 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
380 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
382 reg |= ((width >> 4) - 1) << 4;
383 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
385 /* Set the Panel Height */
386 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
387 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
388 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
390 /* Set the Raster Order of the Frame Buffer */
391 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
393 reg |= LCD_RASTER_ORDER;
394 lcdc_write(reg, LCD_RASTER_CTRL_REG);
401 par->palette_sz = 16 * 2;
405 par->palette_sz = 256 * 2;
412 bpl = width * bpp / 8;
413 par->databuf_sz = height * bpl + par->palette_sz;
418 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
419 unsigned blue, unsigned transp,
420 struct fb_info *info)
422 struct da8xx_fb_par *par = info->par;
423 unsigned short *palette = (unsigned short *)par->v_palette_base;
429 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
432 if (info->var.bits_per_pixel == 8) {
437 pal = (red & 0x0f00);
438 pal |= (green & 0x00f0);
439 pal |= (blue & 0x000f);
441 palette[regno] = pal;
443 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
444 red >>= (16 - info->var.red.length);
445 red <<= info->var.red.offset;
447 green >>= (16 - info->var.green.length);
448 green <<= info->var.green.offset;
450 blue >>= (16 - info->var.blue.length);
451 blue <<= info->var.blue.offset;
453 par->pseudo_palette[regno] = red | green | blue;
461 static void lcd_reset(struct da8xx_fb_par *par)
463 /* Disable the Raster if previously Enabled */
464 lcd_disable_raster();
466 /* DMA has to be disabled */
467 lcdc_write(0, LCD_DMA_CTRL_REG);
468 lcdc_write(0, LCD_RASTER_CTRL_REG);
471 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
473 unsigned int lcd_clk, div;
475 lcd_clk = clk_get_rate(par->lcdc_clk);
476 div = lcd_clk / par->pxl_clk;
478 /* Configure the LCD clock divisor. */
479 lcdc_write(LCD_CLK_DIVISOR(div) |
480 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
483 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
484 struct da8xx_panel *panel)
491 /* Calculate the divider */
492 lcd_calc_clk_divider(par);
494 if (panel->invert_pxl_clk)
495 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
496 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
498 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
499 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
501 /* Configure the DMA burst size. */
502 ret = lcd_cfg_dma(cfg->dma_burst_sz);
506 /* Configure the AC bias properties. */
507 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
509 /* Configure the vertical and horizontal sync properties. */
510 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
511 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
513 /* Configure for disply */
514 ret = lcd_cfg_display(cfg);
518 if (QVGA != cfg->p_disp_panel->panel_type)
521 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
522 cfg->bpp >= cfg->p_disp_panel->min_bpp)
525 bpp = cfg->p_disp_panel->max_bpp;
528 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
529 (unsigned int)panel->height, bpp,
535 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
536 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
541 static irqreturn_t lcdc_irq_handler(int irq, void *arg)
543 u32 stat = lcdc_read(LCD_STAT_REG);
545 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
546 lcd_disable_raster();
547 lcdc_write(stat, LCD_STAT_REG);
550 lcdc_write(stat, LCD_STAT_REG);
555 static int fb_check_var(struct fb_var_screeninfo *var,
556 struct fb_info *info)
560 switch (var->bits_per_pixel) {
565 var->green.offset = 0;
566 var->green.length = 8;
567 var->blue.offset = 0;
568 var->blue.length = 8;
569 var->transp.offset = 0;
570 var->transp.length = 0;
575 var->green.offset = 0;
576 var->green.length = 4;
577 var->blue.offset = 0;
578 var->blue.length = 4;
579 var->transp.offset = 0;
580 var->transp.length = 0;
582 case 16: /* RGB 565 */
583 var->red.offset = 11;
585 var->green.offset = 5;
586 var->green.length = 6;
587 var->blue.offset = 0;
588 var->blue.length = 5;
589 var->transp.offset = 0;
590 var->transp.length = 0;
596 var->red.msb_right = 0;
597 var->green.msb_right = 0;
598 var->blue.msb_right = 0;
599 var->transp.msb_right = 0;
603 #ifdef CONFIG_CPU_FREQ
604 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
605 unsigned long val, void *data)
607 struct da8xx_fb_par *par;
609 par = container_of(nb, struct da8xx_fb_par, freq_transition);
610 if (val == CPUFREQ_PRECHANGE) {
611 lcd_disable_raster();
612 } else if (val == CPUFREQ_POSTCHANGE) {
613 lcd_calc_clk_divider(par);
620 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
622 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
624 return cpufreq_register_notifier(&par->freq_transition,
625 CPUFREQ_TRANSITION_NOTIFIER);
628 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
630 cpufreq_unregister_notifier(&par->freq_transition,
631 CPUFREQ_TRANSITION_NOTIFIER);
635 static int __devexit fb_remove(struct platform_device *dev)
637 struct fb_info *info = dev_get_drvdata(&dev->dev);
640 struct da8xx_fb_par *par = info->par;
642 #ifdef CONFIG_CPU_FREQ
643 lcd_da8xx_cpufreq_deregister(par);
645 if (par->panel_power_ctrl)
646 par->panel_power_ctrl(0);
648 lcd_disable_raster();
649 lcdc_write(0, LCD_RASTER_CTRL_REG);
652 lcdc_write(0, LCD_DMA_CTRL_REG);
654 unregister_framebuffer(info);
655 fb_dealloc_cmap(&info->cmap);
656 dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
657 info->screen_base - PAGE_SIZE,
658 info->fix.smem_start);
659 free_irq(par->irq, par);
660 clk_disable(par->lcdc_clk);
661 clk_put(par->lcdc_clk);
662 framebuffer_release(info);
663 iounmap((void __iomem *)da8xx_fb_reg_base);
664 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
670 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
673 struct lcd_sync_arg sync_arg;
676 case FBIOGET_CONTRAST:
677 case FBIOPUT_CONTRAST:
678 case FBIGET_BRIGHTNESS:
679 case FBIPUT_BRIGHTNESS:
684 if (copy_from_user(&sync_arg, (char *)arg,
685 sizeof(struct lcd_sync_arg)))
687 lcd_cfg_horizontal_sync(sync_arg.back_porch,
688 sync_arg.pulse_width,
689 sync_arg.front_porch);
692 if (copy_from_user(&sync_arg, (char *)arg,
693 sizeof(struct lcd_sync_arg)))
695 lcd_cfg_vertical_sync(sync_arg.back_porch,
696 sync_arg.pulse_width,
697 sync_arg.front_porch);
705 static int cfb_blank(int blank, struct fb_info *info)
707 struct da8xx_fb_par *par = info->par;
710 if (par->blank == blank)
715 case FB_BLANK_UNBLANK:
716 if (par->panel_power_ctrl)
717 par->panel_power_ctrl(1);
721 case FB_BLANK_POWERDOWN:
722 if (par->panel_power_ctrl)
723 par->panel_power_ctrl(0);
725 lcd_disable_raster();
734 static struct fb_ops da8xx_fb_ops = {
735 .owner = THIS_MODULE,
736 .fb_check_var = fb_check_var,
737 .fb_setcolreg = fb_setcolreg,
738 .fb_ioctl = fb_ioctl,
739 .fb_fillrect = cfb_fillrect,
740 .fb_copyarea = cfb_copyarea,
741 .fb_imageblit = cfb_imageblit,
742 .fb_blank = cfb_blank,
745 static int __init fb_probe(struct platform_device *device)
747 struct da8xx_lcdc_platform_data *fb_pdata =
748 device->dev.platform_data;
749 struct lcd_ctrl_config *lcd_cfg;
750 struct da8xx_panel *lcdc_info;
751 struct fb_info *da8xx_fb_info;
752 struct clk *fb_clk = NULL;
753 struct da8xx_fb_par *par;
757 if (fb_pdata == NULL) {
758 dev_err(&device->dev, "Can not get platform data\n");
762 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
764 dev_err(&device->dev,
765 "Can not get memory resource for LCD controller\n");
769 len = resource_size(lcdc_regs);
771 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
775 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
776 if (!da8xx_fb_reg_base) {
778 goto err_request_mem;
781 fb_clk = clk_get(&device->dev, NULL);
782 if (IS_ERR(fb_clk)) {
783 dev_err(&device->dev, "Can not get device clock\n");
787 ret = clk_enable(fb_clk);
791 for (i = 0, lcdc_info = known_lcd_panels;
792 i < ARRAY_SIZE(known_lcd_panels);
794 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
798 if (i == ARRAY_SIZE(known_lcd_panels)) {
799 dev_err(&device->dev, "GLCD: No valid panel found\n");
801 goto err_clk_disable;
803 dev_info(&device->dev, "GLCD: Found %s panel\n",
806 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
808 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
810 if (!da8xx_fb_info) {
811 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
813 goto err_clk_disable;
816 par = da8xx_fb_info->par;
817 par->lcdc_clk = fb_clk;
818 par->pxl_clk = lcdc_info->pxl_clk;
819 if (fb_pdata->panel_power_ctrl) {
820 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
821 par->panel_power_ctrl(1);
824 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
825 dev_err(&device->dev, "lcd_init failed\n");
830 /* allocate frame buffer */
831 da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
832 par->databuf_sz + PAGE_SIZE,
834 &da8xx_fb_info->fix.smem_start,
835 GFP_KERNEL | GFP_DMA);
837 if (!da8xx_fb_info->screen_base) {
838 dev_err(&device->dev,
839 "GLCD: kmalloc for frame buffer failed\n");
844 /* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
845 par->v_palette_base = da8xx_fb_info->screen_base +
846 (PAGE_SIZE - par->palette_sz);
847 par->p_palette_base = da8xx_fb_info->fix.smem_start +
848 (PAGE_SIZE - par->palette_sz);
850 /* the rest of the frame buffer is pixel data */
851 da8xx_fb_info->screen_base = par->v_palette_base + par->palette_sz;
852 da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
853 da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
854 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
856 par->irq = platform_get_irq(device, 0);
859 goto err_release_fb_mem;
862 ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
864 goto err_release_fb_mem;
867 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
869 da8xx_fb_var.xres = lcdc_info->width;
870 da8xx_fb_var.xres_virtual = lcdc_info->width;
872 da8xx_fb_var.yres = lcdc_info->height;
873 da8xx_fb_var.yres_virtual = lcdc_info->height;
875 da8xx_fb_var.grayscale =
876 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
877 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
879 da8xx_fb_var.hsync_len = lcdc_info->hsw;
880 da8xx_fb_var.vsync_len = lcdc_info->vsw;
882 /* Initialize fbinfo */
883 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
884 da8xx_fb_info->fix = da8xx_fb_fix;
885 da8xx_fb_info->var = da8xx_fb_var;
886 da8xx_fb_info->fbops = &da8xx_fb_ops;
887 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
888 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
889 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
891 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
895 /* First palette_sz byte of the frame buffer is the palette */
896 da8xx_fb_info->cmap.len = par->palette_sz;
898 /* Flush the buffer to the screen. */
899 lcd_blit(LOAD_DATA, par);
901 /* initialize var_screeninfo */
902 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
903 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
905 dev_set_drvdata(&device->dev, da8xx_fb_info);
906 /* Register the Frame Buffer */
907 if (register_framebuffer(da8xx_fb_info) < 0) {
908 dev_err(&device->dev,
909 "GLCD: Frame Buffer Registration Failed!\n");
911 goto err_dealloc_cmap;
914 #ifdef CONFIG_CPU_FREQ
915 ret = lcd_da8xx_cpufreq_register(par);
917 dev_err(&device->dev, "failed to register cpufreq\n");
922 /* enable raster engine */
927 #ifdef CONFIG_CPU_FREQ
929 unregister_framebuffer(da8xx_fb_info);
933 fb_dealloc_cmap(&da8xx_fb_info->cmap);
936 free_irq(par->irq, par);
939 dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
940 da8xx_fb_info->screen_base - PAGE_SIZE,
941 da8xx_fb_info->fix.smem_start);
944 framebuffer_release(da8xx_fb_info);
953 iounmap((void __iomem *)da8xx_fb_reg_base);
956 release_mem_region(lcdc_regs->start, len);
962 static int fb_suspend(struct platform_device *dev, pm_message_t state)
964 struct fb_info *info = platform_get_drvdata(dev);
965 struct da8xx_fb_par *par = info->par;
967 acquire_console_sem();
968 if (par->panel_power_ctrl)
969 par->panel_power_ctrl(0);
971 fb_set_suspend(info, 1);
972 lcd_disable_raster();
973 clk_disable(par->lcdc_clk);
974 release_console_sem();
978 static int fb_resume(struct platform_device *dev)
980 struct fb_info *info = platform_get_drvdata(dev);
981 struct da8xx_fb_par *par = info->par;
983 acquire_console_sem();
984 if (par->panel_power_ctrl)
985 par->panel_power_ctrl(1);
987 clk_enable(par->lcdc_clk);
989 fb_set_suspend(info, 0);
990 release_console_sem();
995 #define fb_suspend NULL
996 #define fb_resume NULL
999 static struct platform_driver da8xx_fb_driver = {
1001 .remove = fb_remove,
1002 .suspend = fb_suspend,
1003 .resume = fb_resume,
1005 .name = DRIVER_NAME,
1006 .owner = THIS_MODULE,
1010 static int __init da8xx_fb_init(void)
1012 return platform_driver_register(&da8xx_fb_driver);
1015 static void __exit da8xx_fb_cleanup(void)
1017 platform_driver_unregister(&da8xx_fb_driver);
1020 module_init(da8xx_fb_init);
1021 module_exit(da8xx_fb_cleanup);
1023 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1024 MODULE_AUTHOR("Texas Instruments");
1025 MODULE_LICENSE("GPL");