2 * drivers/video/chipsfb.c -- frame buffer device for
3 * Chips & Technologies 65550 chip.
5 * Copyright (C) 1998-2002 Paul Mackerras
7 * This file is derived from the Powermac "chips" driver:
8 * Copyright (C) 1997 Fabio Riccardi.
9 * And from the frame buffer device for Open Firmware-initialized devices:
10 * Copyright (C) 1997 Geert Uytterhoeven.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/vmalloc.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/console.h>
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
37 * Since we access the display with inb/outb to fixed port numbers,
38 * we can only handle one 6555x chip. -- paulus
40 #define write_ind(num, val, ap, dp) do { \
41 outb((num), (ap)); outb((val), (dp)); \
43 #define read_ind(num, var, ap, dp) do { \
44 outb((num), (ap)); var = inb((dp)); \
47 /* extension registers */
48 #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
49 #define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
50 /* flat panel registers */
51 #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
52 #define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
54 #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
55 #define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
56 /* graphics registers */
57 #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
58 #define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
59 /* sequencer registers */
60 #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
61 #define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
62 /* attribute registers - slightly strange */
63 #define write_ar(num, val) do { \
64 inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
66 #define read_ar(num, var) do { \
67 inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
75 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
76 static int chipsfb_check_var(struct fb_var_screeninfo *var,
77 struct fb_info *info);
78 static int chipsfb_set_par(struct fb_info *info);
79 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
80 u_int transp, struct fb_info *info);
81 static int chipsfb_blank(int blank, struct fb_info *info);
83 static struct fb_ops chipsfb_ops = {
85 .fb_check_var = chipsfb_check_var,
86 .fb_set_par = chipsfb_set_par,
87 .fb_setcolreg = chipsfb_setcolreg,
88 .fb_blank = chipsfb_blank,
89 .fb_fillrect = cfb_fillrect,
90 .fb_copyarea = cfb_copyarea,
91 .fb_imageblit = cfb_imageblit,
94 static int chipsfb_check_var(struct fb_var_screeninfo *var,
97 if (var->xres > 800 || var->yres > 600
98 || var->xres_virtual > 800 || var->yres_virtual > 600
99 || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
101 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
104 var->xres = var->xres_virtual = 800;
105 var->yres = var->yres_virtual = 600;
110 static int chipsfb_set_par(struct fb_info *info)
112 if (info->var.bits_per_pixel == 16) {
113 write_cr(0x13, 200); // Set line length (doublewords)
114 write_xr(0x81, 0x14); // 15 bit (555) color mode
115 write_xr(0x82, 0x00); // Disable palettes
116 write_xr(0x20, 0x10); // 16 bit blitter mode
118 info->fix.line_length = 800*2;
119 info->fix.visual = FB_VISUAL_TRUECOLOR;
121 info->var.red.offset = 10;
122 info->var.green.offset = 5;
123 info->var.blue.offset = 0;
124 info->var.red.length = info->var.green.length =
125 info->var.blue.length = 5;
128 /* p->var.bits_per_pixel == 8 */
129 write_cr(0x13, 100); // Set line length (doublewords)
130 write_xr(0x81, 0x12); // 8 bit color mode
131 write_xr(0x82, 0x08); // Graphics gamma enable
132 write_xr(0x20, 0x00); // 8 bit blitter mode
134 info->fix.line_length = 800;
135 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
137 info->var.red.offset = info->var.green.offset =
138 info->var.blue.offset = 0;
139 info->var.red.length = info->var.green.length =
140 info->var.blue.length = 8;
146 static int chipsfb_blank(int blank, struct fb_info *info)
148 return 1; /* get fb_blank to set the colormap to all black */
151 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
152 u_int transp, struct fb_info *info)
168 struct chips_init_reg {
173 static struct chips_init_reg chips_init_sr[] = {
180 static struct chips_init_reg chips_init_gr[] = {
186 static struct chips_init_reg chips_init_ar[] = {
192 static struct chips_init_reg chips_init_cr[] = {
223 static struct chips_init_reg chips_init_fr[] = {
233 /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
251 static struct chips_init_reg chips_init_xr[] = {
252 { 0xce, 0x00 }, /* set default memory clock */
253 { 0xcc, 0x43 }, /* memory clock ratio */
276 static void __init chips_hw_init(void)
280 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
281 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
282 outb(0x29, 0x3c2); /* set misc output reg */
283 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
284 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
285 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
286 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
287 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
288 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
289 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
290 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
291 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
292 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
295 static struct fb_fix_screeninfo chipsfb_fix = {
297 .type = FB_TYPE_PACKED_PIXELS,
298 .visual = FB_VISUAL_PSEUDOCOLOR,
299 .accel = FB_ACCEL_NONE,
302 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
303 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
304 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
305 // Motherboard actually supports 2MB -- there are two blank locations
306 // for a second pair of DRAMs. (Thanks, Apple!)
307 // * 3400 has 1MB (I think). Don't know if it's expandable.
309 .smem_len = 0x100000, /* 1MB */
312 static struct fb_var_screeninfo chipsfb_var = {
318 .red = { .length = 8 },
319 .green = { .length = 8 },
320 .blue = { .length = 8 },
323 .vmode = FB_VMODE_NONINTERLACED,
333 static void init_chips(struct fb_info *p, unsigned long addr)
335 memset(p->screen_base, 0, 0x100000);
337 p->fix = chipsfb_fix;
338 p->fix.smem_start = addr;
340 p->var = chipsfb_var;
342 p->fbops = &chipsfb_ops;
343 p->flags = FBINFO_DEFAULT;
345 fb_alloc_cmap(&p->cmap, 256, 0);
350 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
353 unsigned long addr, size;
357 if (pci_enable_device(dp) < 0) {
358 dev_err(&dp->dev, "Cannot enable PCI device\n");
362 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
364 addr = pci_resource_start(dp, 0);
365 size = pci_resource_len(dp, 0);
369 p = framebuffer_alloc(0, &dp->dev);
371 dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
376 if (pci_request_region(dp, 0, "chipsfb") != 0) {
377 dev_err(&dp->dev, "Cannot request framebuffer\n");
383 addr += 0x800000; // Use big-endian aperture
386 /* we should use pci_enable_device here, but,
387 the device doesn't declare its I/O ports in its BARs
388 so pci_enable_device won't turn on I/O responses */
389 pci_read_config_word(dp, PCI_COMMAND, &cmd);
390 cmd |= 3; /* enable memory and IO space */
391 pci_write_config_word(dp, PCI_COMMAND, cmd);
393 #ifdef CONFIG_PMAC_BACKLIGHT
394 /* turn on the backlight */
395 mutex_lock(&pmac_backlight_mutex);
396 if (pmac_backlight) {
397 pmac_backlight->props.power = FB_BLANK_UNBLANK;
398 backlight_update_status(pmac_backlight);
400 mutex_unlock(&pmac_backlight_mutex);
401 #endif /* CONFIG_PMAC_BACKLIGHT */
404 p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
406 p->screen_base = ioremap(addr, 0x200000);
408 if (p->screen_base == NULL) {
409 dev_err(&dp->dev, "Cannot map framebuffer\n");
411 goto err_release_pci;
414 pci_set_drvdata(dp, p);
418 if (register_framebuffer(p) < 0) {
419 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
423 dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
424 " (%dK RAM detected)\n",
425 p->node, p->fix.smem_len / 1024);
430 iounmap(p->screen_base);
432 pci_release_region(dp, 0);
434 framebuffer_release(p);
440 static void chipsfb_remove(struct pci_dev *dp)
442 struct fb_info *p = pci_get_drvdata(dp);
444 if (p->screen_base == NULL)
446 unregister_framebuffer(p);
447 iounmap(p->screen_base);
448 p->screen_base = NULL;
449 pci_release_region(dp, 0);
453 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
455 struct fb_info *p = pci_get_drvdata(pdev);
457 if (state.event == pdev->dev.power.power_state.event)
459 if (!(state.event & PM_EVENT_SLEEP))
464 fb_set_suspend(p, 1);
467 pdev->dev.power.power_state = state;
471 static int chipsfb_pci_resume(struct pci_dev *pdev)
473 struct fb_info *p = pci_get_drvdata(pdev);
476 fb_set_suspend(p, 0);
480 pdev->dev.power.power_state = PMSG_ON;
483 #endif /* CONFIG_PM */
486 static struct pci_device_id chipsfb_pci_tbl[] = {
487 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
491 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
493 static struct pci_driver chipsfb_driver = {
495 .id_table = chipsfb_pci_tbl,
496 .probe = chipsfb_pci_init,
497 .remove = chipsfb_remove,
499 .suspend = chipsfb_pci_suspend,
500 .resume = chipsfb_pci_resume,
504 int __init chips_init(void)
506 if (fb_get_options("chipsfb", NULL))
509 return pci_register_driver(&chipsfb_driver);
512 module_init(chips_init);
514 static void __exit chipsfb_exit(void)
516 pci_unregister_driver(&chipsfb_driver);
519 MODULE_LICENSE("GPL");