2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/memblock.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clk.h>
30 #include <linux/hardirq.h>
32 #include <asm/sizes.h>
34 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
37 #define clcdfb_dma_alloc dma_alloc_writecombine
38 #define clcdfb_dma_free dma_free_writecombine
39 #define clcdfb_dma_mmap dma_mmap_writecombine
41 #define clcdfb_dma_alloc dma_alloc_coherent
42 #define clcdfb_dma_free dma_free_coherent
43 #define clcdfb_dma_mmap dma_mmap_coherent
46 /* This is limited to 16 characters when displayed by X startup */
47 static const char *clcd_name = "CLCD FB";
50 * Unfortunately, the enable/disable functions may be called either from
51 * process or IRQ context, and we _need_ to delay. This is _not_ good.
53 static inline void clcdfb_sleep(unsigned int ms)
62 static inline void clcdfb_set_start(struct clcd_fb *fb)
64 unsigned long ustart = fb->fb.fix.smem_start;
67 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
68 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
70 writel(ustart, fb->regs + CLCD_UBAS);
71 writel(lstart, fb->regs + CLCD_LBAS);
74 static void clcdfb_disable(struct clcd_fb *fb)
78 if (fb->board->disable)
79 fb->board->disable(fb);
81 val = readl(fb->regs + fb->off_cntl);
82 if (val & CNTL_LCDPWR) {
84 writel(val, fb->regs + fb->off_cntl);
88 if (val & CNTL_LCDEN) {
90 writel(val, fb->regs + fb->off_cntl);
94 * Disable CLCD clock source.
96 if (fb->clk_enabled) {
97 fb->clk_enabled = false;
102 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
105 * Enable the CLCD clock source.
107 if (!fb->clk_enabled) {
108 fb->clk_enabled = true;
113 * Bring up by first enabling..
116 writel(cntl, fb->regs + fb->off_cntl);
121 * and now apply power.
124 writel(cntl, fb->regs + fb->off_cntl);
127 * finally, enable the interface.
129 if (fb->board->enable)
130 fb->board->enable(fb);
134 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
139 if (fb->panel->caps && fb->board->caps)
140 caps = fb->panel->caps & fb->board->caps;
142 /* Old way of specifying what can be used */
143 caps = fb->panel->cntl & CNTL_BGR ?
144 CLCD_CAP_BGR : CLCD_CAP_RGB;
145 /* But mask out 444 modes as they weren't supported */
146 caps &= ~CLCD_CAP_444;
149 /* Only TFT panels can do RGB888/BGR888 */
150 if (!(fb->panel->cntl & CNTL_LCDTFT))
151 caps &= ~CLCD_CAP_888;
153 memset(&var->transp, 0, sizeof(var->transp));
155 var->red.msb_right = 0;
156 var->green.msb_right = 0;
157 var->blue.msb_right = 0;
159 switch (var->bits_per_pixel) {
164 /* If we can't do 5551, reject */
165 caps &= CLCD_CAP_5551;
171 var->red.length = var->bits_per_pixel;
173 var->green.length = var->bits_per_pixel;
174 var->green.offset = 0;
175 var->blue.length = var->bits_per_pixel;
176 var->blue.offset = 0;
180 /* If we can't do 444, 5551 or 565, reject */
181 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
187 * Green length can be 4, 5 or 6 depending whether
188 * we're operating in 444, 5551 or 565 mode.
190 if (var->green.length == 4 && caps & CLCD_CAP_444)
191 caps &= CLCD_CAP_444;
192 if (var->green.length == 5 && caps & CLCD_CAP_5551)
193 caps &= CLCD_CAP_5551;
194 else if (var->green.length == 6 && caps & CLCD_CAP_565)
195 caps &= CLCD_CAP_565;
198 * PL110 officially only supports RGB555,
199 * but may be wired up to allow RGB565.
201 if (caps & CLCD_CAP_565) {
202 var->green.length = 6;
203 caps &= CLCD_CAP_565;
204 } else if (caps & CLCD_CAP_5551) {
205 var->green.length = 5;
206 caps &= CLCD_CAP_5551;
208 var->green.length = 4;
209 caps &= CLCD_CAP_444;
213 if (var->green.length >= 5) {
215 var->blue.length = 5;
218 var->blue.length = 4;
222 /* If we can't do 888, reject */
223 caps &= CLCD_CAP_888;
230 var->green.length = 8;
231 var->blue.length = 8;
239 * >= 16bpp displays have separate colour component bitfields
240 * encoded in the pixel data. Calculate their position from
241 * the bitfield length defined above.
243 if (ret == 0 && var->bits_per_pixel >= 16) {
246 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
247 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
251 * The requested format was not possible, try just
252 * our capabilities. One of BGR or RGB must be
255 bgr = caps & CLCD_CAP_BGR;
258 var->blue.offset = 0;
259 var->green.offset = var->blue.offset + var->blue.length;
260 var->red.offset = var->green.offset + var->green.length;
263 var->green.offset = var->red.offset + var->red.length;
264 var->blue.offset = var->green.offset + var->green.length;
271 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
273 struct clcd_fb *fb = to_clcd(info);
276 if (fb->board->check)
277 ret = fb->board->check(fb, var);
280 var->xres_virtual * var->bits_per_pixel / 8 *
281 var->yres_virtual > fb->fb.fix.smem_len)
285 ret = clcdfb_set_bitfields(fb, var);
290 static int clcdfb_set_par(struct fb_info *info)
292 struct clcd_fb *fb = to_clcd(info);
293 struct clcd_regs regs;
295 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
296 fb->fb.var.bits_per_pixel / 8;
298 if (fb->fb.var.bits_per_pixel <= 8)
299 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
301 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
303 fb->board->decode(fb, ®s);
307 writel(regs.tim0, fb->regs + CLCD_TIM0);
308 writel(regs.tim1, fb->regs + CLCD_TIM1);
309 writel(regs.tim2, fb->regs + CLCD_TIM2);
310 writel(regs.tim3, fb->regs + CLCD_TIM3);
312 clcdfb_set_start(fb);
314 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
316 fb->clcd_cntl = regs.cntl;
318 clcdfb_enable(fb, regs.cntl);
322 "CLCD: Registers set to\n"
323 " %08x %08x %08x %08x\n"
324 " %08x %08x %08x %08x\n",
325 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
326 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
327 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
328 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
334 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
336 unsigned int mask = (1 << bf->length) - 1;
338 return (val >> (16 - bf->length) & mask) << bf->offset;
342 * Set a single color register. The values supplied have a 16 bit
343 * magnitude. Return != 0 for invalid regno.
346 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
347 unsigned int blue, unsigned int transp, struct fb_info *info)
349 struct clcd_fb *fb = to_clcd(info);
352 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
353 convert_bitfield(blue, &fb->fb.var.blue) |
354 convert_bitfield(green, &fb->fb.var.green) |
355 convert_bitfield(red, &fb->fb.var.red);
357 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
358 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
359 u32 val, mask, newval;
361 newval = (red >> 11) & 0x001f;
362 newval |= (green >> 6) & 0x03e0;
363 newval |= (blue >> 1) & 0x7c00;
366 * 3.2.11: if we're configured for big endian
367 * byte order, the palette entries are swapped.
369 if (fb->clcd_cntl & CNTL_BEBO)
379 val = readl(fb->regs + hw_reg) & mask;
380 writel(val | newval, fb->regs + hw_reg);
387 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
388 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
389 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
390 * to e.g. a video mode which doesn't support it. Implements VESA suspend
391 * and powerdown modes on hardware that supports disabling hsync/vsync:
392 * blank_mode == 2: suspend vsync
393 * blank_mode == 3: suspend hsync
394 * blank_mode == 4: powerdown
396 static int clcdfb_blank(int blank_mode, struct fb_info *info)
398 struct clcd_fb *fb = to_clcd(info);
400 if (blank_mode != 0) {
403 clcdfb_enable(fb, fb->clcd_cntl);
408 int clcdfb_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma)
410 return clcdfb_dma_mmap(&fb->dev->dev, vma,
412 fb->fb.fix.smem_start,
413 fb->fb.fix.smem_len);
416 int clcdfb_mmap_io(struct clcd_fb *fb, struct vm_area_struct *vma)
418 unsigned long user_count, count, pfn, off;
420 user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
421 count = PAGE_ALIGN(fb->fb.fix.smem_len) >> PAGE_SHIFT;
422 pfn = fb->fb.fix.smem_start >> PAGE_SHIFT;
425 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
427 if (off < count && user_count <= (count - off))
428 return remap_pfn_range(vma, vma->vm_start, pfn + off,
429 user_count << PAGE_SHIFT,
435 void clcdfb_remove_dma(struct clcd_fb *fb)
437 clcdfb_dma_free(&fb->dev->dev, fb->fb.fix.smem_len,
438 fb->fb.screen_base, fb->fb.fix.smem_start);
441 void clcdfb_remove_io(struct clcd_fb *fb)
443 iounmap(fb->fb.screen_base);
446 static int clcdfb_mmap(struct fb_info *info,
447 struct vm_area_struct *vma)
449 struct clcd_fb *fb = to_clcd(info);
450 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
453 len = info->fix.smem_len;
455 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
457 ret = fb->board->mmap(fb, vma);
462 static struct fb_ops clcdfb_ops = {
463 .owner = THIS_MODULE,
464 .fb_check_var = clcdfb_check_var,
465 .fb_set_par = clcdfb_set_par,
466 .fb_setcolreg = clcdfb_setcolreg,
467 .fb_blank = clcdfb_blank,
468 .fb_fillrect = cfb_fillrect,
469 .fb_copyarea = cfb_copyarea,
470 .fb_imageblit = cfb_imageblit,
471 .fb_mmap = clcdfb_mmap,
474 static int clcdfb_register(struct clcd_fb *fb)
479 * ARM PL111 always has IENB at 0x1c; it's only PL110
480 * which is reversed on some platforms.
482 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
483 fb->off_ienb = CLCD_PL111_IENB;
484 fb->off_cntl = CLCD_PL111_CNTL;
486 #ifdef CONFIG_ARCH_VERSATILE
487 fb->off_ienb = CLCD_PL111_IENB;
488 fb->off_cntl = CLCD_PL111_CNTL;
490 fb->off_ienb = CLCD_PL110_IENB;
491 fb->off_cntl = CLCD_PL110_CNTL;
495 fb->clk = clk_get(&fb->dev->dev, NULL);
496 if (IS_ERR(fb->clk)) {
497 ret = PTR_ERR(fb->clk);
501 ret = clk_prepare(fb->clk);
505 fb->fb.device = &fb->dev->dev;
507 fb->fb.fix.mmio_start = fb->dev->res.start;
508 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
510 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
512 printk(KERN_ERR "CLCD: unable to remap registers\n");
517 fb->fb.fbops = &clcdfb_ops;
518 fb->fb.flags = FBINFO_FLAG_DEFAULT;
519 fb->fb.pseudo_palette = fb->cmap;
521 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
522 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
523 fb->fb.fix.type_aux = 0;
524 fb->fb.fix.xpanstep = 0;
525 fb->fb.fix.ypanstep = 0;
526 fb->fb.fix.ywrapstep = 0;
527 fb->fb.fix.accel = FB_ACCEL_NONE;
529 fb->fb.var.xres = fb->panel->mode.xres;
530 fb->fb.var.yres = fb->panel->mode.yres;
531 fb->fb.var.xres_virtual = fb->panel->mode.xres;
532 fb->fb.var.yres_virtual = fb->panel->mode.yres;
533 fb->fb.var.bits_per_pixel = fb->panel->bpp;
534 fb->fb.var.grayscale = fb->panel->grayscale;
535 fb->fb.var.pixclock = fb->panel->mode.pixclock;
536 fb->fb.var.left_margin = fb->panel->mode.left_margin;
537 fb->fb.var.right_margin = fb->panel->mode.right_margin;
538 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
539 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
540 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
541 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
542 fb->fb.var.sync = fb->panel->mode.sync;
543 fb->fb.var.vmode = fb->panel->mode.vmode;
544 fb->fb.var.activate = FB_ACTIVATE_NOW;
545 fb->fb.var.nonstd = 0;
546 fb->fb.var.height = fb->panel->height;
547 fb->fb.var.width = fb->panel->width;
548 fb->fb.var.accel_flags = 0;
550 fb->fb.monspecs.hfmin = 0;
551 fb->fb.monspecs.hfmax = 100000;
552 fb->fb.monspecs.vfmin = 0;
553 fb->fb.monspecs.vfmax = 400;
554 fb->fb.monspecs.dclkmin = 1000000;
555 fb->fb.monspecs.dclkmax = 100000000;
558 * Make sure that the bitfields are set appropriately.
560 clcdfb_set_bitfields(fb, &fb->fb.var);
563 * Allocate colourmap.
565 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
570 * Ensure interrupts are disabled.
572 writel(0, fb->regs + fb->off_ienb);
574 fb_set_var(&fb->fb, &fb->fb.var);
576 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
577 fb->board->name, fb->panel->mode.name);
579 ret = register_framebuffer(&fb->fb);
583 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
585 fb_dealloc_cmap(&fb->fb.cmap);
589 clk_unprepare(fb->clk);
596 struct string_lookup {
601 static struct string_lookup vmode_lookups[] = {
602 { "FB_VMODE_NONINTERLACED", FB_VMODE_NONINTERLACED},
603 { "FB_VMODE_INTERLACED", FB_VMODE_INTERLACED},
604 { "FB_VMODE_DOUBLE", FB_VMODE_DOUBLE},
605 { "FB_VMODE_ODD_FLD_FIRST", FB_VMODE_ODD_FLD_FIRST},
609 static struct string_lookup tim2_lookups[] = {
610 { "TIM2_CLKSEL", TIM2_CLKSEL},
611 { "TIM2_IVS", TIM2_IVS},
612 { "TIM2_IHS", TIM2_IHS},
613 { "TIM2_IPC", TIM2_IPC},
614 { "TIM2_IOE", TIM2_IOE},
615 { "TIM2_BCD", TIM2_BCD},
618 static struct string_lookup cntl_lookups[] = {
619 {"CNTL_LCDEN", CNTL_LCDEN},
620 {"CNTL_LCDBPP1", CNTL_LCDBPP1},
621 {"CNTL_LCDBPP2", CNTL_LCDBPP2},
622 {"CNTL_LCDBPP4", CNTL_LCDBPP4},
623 {"CNTL_LCDBPP8", CNTL_LCDBPP8},
624 {"CNTL_LCDBPP16", CNTL_LCDBPP16},
625 {"CNTL_LCDBPP16_565", CNTL_LCDBPP16_565},
626 {"CNTL_LCDBPP16_444", CNTL_LCDBPP16_444},
627 {"CNTL_LCDBPP24", CNTL_LCDBPP24},
628 {"CNTL_LCDBW", CNTL_LCDBW},
629 {"CNTL_LCDTFT", CNTL_LCDTFT},
630 {"CNTL_LCDMONO8", CNTL_LCDMONO8},
631 {"CNTL_LCDDUAL", CNTL_LCDDUAL},
632 {"CNTL_BGR", CNTL_BGR},
633 {"CNTL_BEBO", CNTL_BEBO},
634 {"CNTL_BEPO", CNTL_BEPO},
635 {"CNTL_LCDPWR", CNTL_LCDPWR},
636 {"CNTL_LCDVCOMP(1)", CNTL_LCDVCOMP(1)},
637 {"CNTL_LCDVCOMP(2)", CNTL_LCDVCOMP(2)},
638 {"CNTL_LCDVCOMP(3)", CNTL_LCDVCOMP(3)},
639 {"CNTL_LCDVCOMP(4)", CNTL_LCDVCOMP(4)},
640 {"CNTL_LCDVCOMP(5)", CNTL_LCDVCOMP(5)},
641 {"CNTL_LCDVCOMP(6)", CNTL_LCDVCOMP(6)},
642 {"CNTL_LCDVCOMP(7)", CNTL_LCDVCOMP(7)},
643 {"CNTL_LDMAFIFOTIME", CNTL_LDMAFIFOTIME},
644 {"CNTL_WATERMARK", CNTL_WATERMARK},
647 static struct string_lookup caps_lookups[] = {
648 {"CLCD_CAP_RGB444", CLCD_CAP_RGB444},
649 {"CLCD_CAP_RGB5551", CLCD_CAP_RGB5551},
650 {"CLCD_CAP_RGB565", CLCD_CAP_RGB565},
651 {"CLCD_CAP_RGB888", CLCD_CAP_RGB888},
652 {"CLCD_CAP_BGR444", CLCD_CAP_BGR444},
653 {"CLCD_CAP_BGR5551", CLCD_CAP_BGR5551},
654 {"CLCD_CAP_BGR565", CLCD_CAP_BGR565},
655 {"CLCD_CAP_BGR888", CLCD_CAP_BGR888},
656 {"CLCD_CAP_444", CLCD_CAP_444},
657 {"CLCD_CAP_5551", CLCD_CAP_5551},
658 {"CLCD_CAP_565", CLCD_CAP_565},
659 {"CLCD_CAP_888", CLCD_CAP_888},
660 {"CLCD_CAP_RGB", CLCD_CAP_RGB},
661 {"CLCD_CAP_BGR", CLCD_CAP_BGR},
662 {"CLCD_CAP_ALL", CLCD_CAP_ALL},
666 u32 parse_setting(struct string_lookup *lookup, const char *name)
669 while (lookup[i].string != NULL) {
670 if (strcmp(lookup[i].string, name) == 0)
671 return lookup[i].val;
677 u32 get_string_lookup(struct device_node *node, const char *name,
678 struct string_lookup *lookup)
681 int count, i, ret = 0;
683 count = of_property_count_strings(node, name);
685 for (i = 0; i < count; i++)
686 if (of_property_read_string_index(node, name, i,
688 ret |= parse_setting(lookup, string);
692 int get_val(struct device_node *node, const char *string)
696 if (of_property_read_u32(node, string, &ret))
701 struct clcd_panel *getPanel(struct device_node *node)
703 static struct clcd_panel panel;
705 panel.mode.refresh = get_val(node, "refresh");
706 panel.mode.xres = get_val(node, "xres");
707 panel.mode.yres = get_val(node, "yres");
708 panel.mode.pixclock = get_val(node, "pixclock");
709 panel.mode.left_margin = get_val(node, "left_margin");
710 panel.mode.right_margin = get_val(node, "right_margin");
711 panel.mode.upper_margin = get_val(node, "upper_margin");
712 panel.mode.lower_margin = get_val(node, "lower_margin");
713 panel.mode.hsync_len = get_val(node, "hsync_len");
714 panel.mode.vsync_len = get_val(node, "vsync_len");
715 panel.mode.sync = get_val(node, "sync");
716 panel.bpp = get_val(node, "bpp");
717 panel.width = (signed short) get_val(node, "width");
718 panel.height = (signed short) get_val(node, "height");
720 panel.mode.vmode = get_string_lookup(node, "vmode", vmode_lookups);
721 panel.tim2 = get_string_lookup(node, "tim2", tim2_lookups);
722 panel.cntl = get_string_lookup(node, "cntl", cntl_lookups);
723 panel.caps = get_string_lookup(node, "caps", caps_lookups);
728 struct clcd_panel *clcdfb_get_panel(const char *name)
730 struct device_node *node = NULL;
732 struct clcd_panel *panel = NULL;
735 node = of_find_compatible_node(node, NULL, "panel");
737 if (of_property_read_string(node, "mode", &mode) == 0)
738 if (strcmp(mode, name) == 0) {
739 panel = getPanel(node);
740 panel->mode.name = name;
742 } while (node != NULL);
748 static int clcdfb_dt_init(struct clcd_fb *fb)
751 struct device_node *node;
757 phys_addr_t fb_base, fb_size;
759 node = fb->dev->dev.of_node;
763 na = of_n_addr_cells(node);
764 ns = of_n_size_cells(node);
766 if (WARN_ON(of_property_read_string(node, "mode", &mode)))
769 fb->panel = clcdfb_get_panel(mode);
772 fb->fb.fix.smem_len = fb->panel->mode.xres * fb->panel->mode.yres * 2;
774 fb->board->name = "Device Tree CLCD PL111";
775 fb->board->caps = CLCD_CAP_5551 | CLCD_CAP_565;
776 fb->board->check = clcdfb_check;
777 fb->board->decode = clcdfb_decode;
779 if (of_property_read_u32(node, "use_dma", &use_dma))
783 fb->fb.screen_base = clcdfb_dma_alloc(&fb->dev->dev,
786 if (!fb->fb.screen_base) {
787 pr_err("CLCD: unable to map framebuffer\n");
791 fb->fb.fix.smem_start = dma;
792 fb->board->mmap = clcdfb_mmap_dma;
793 fb->board->remove = clcdfb_remove_dma;
795 prop = of_get_property(node, "framebuffer", &len);
796 if (WARN_ON(!prop || len < (na + ns) * sizeof(*prop)))
799 fb_base = of_read_number(prop, na);
800 fb_size = of_read_number(prop + na, ns);
802 fb->fb.fix.smem_start = fb_base;
803 fb->fb.screen_base = ioremap_wc(fb_base, fb_size);
804 fb->board->mmap = clcdfb_mmap_io;
805 fb->board->remove = clcdfb_remove_io;
810 #endif /* CONFIG_OF */
812 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
814 struct clcd_board *board = dev->dev.platform_data;
820 if (dev->dev.of_node) {
821 board = kzalloc(sizeof(struct clcd_board), GFP_KERNEL);
824 board->setup = clcdfb_dt_init;
830 ret = amba_request_regions(dev, NULL);
832 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
836 fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL);
838 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
846 dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
847 amba_part(dev), amba_rev(dev),
848 (unsigned long long)dev->res.start);
850 ret = fb->board->setup(fb);
854 ret = clcdfb_register(fb);
856 amba_set_drvdata(dev, fb);
860 fb->board->remove(fb);
864 amba_release_regions(dev);
869 static int clcdfb_remove(struct amba_device *dev)
871 struct clcd_fb *fb = amba_get_drvdata(dev);
873 amba_set_drvdata(dev, NULL);
876 unregister_framebuffer(&fb->fb);
878 fb_dealloc_cmap(&fb->fb.cmap);
880 clk_unprepare(fb->clk);
883 fb->board->remove(fb);
887 amba_release_regions(dev);
892 static struct amba_id clcdfb_id_table[] = {
900 MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
902 static struct amba_driver clcd_driver = {
904 .name = "clcd-pl11x",
906 .probe = clcdfb_probe,
907 .remove = clcdfb_remove,
908 .id_table = clcdfb_id_table,
911 static int __init amba_clcdfb_init(void)
913 if (fb_get_options("ambafb", NULL))
916 return amba_driver_register(&clcd_driver);
919 module_init(amba_clcdfb_init);
921 static void __exit amba_clcdfb_exit(void)
923 amba_driver_unregister(&clcd_driver);
926 module_exit(amba_clcdfb_exit);
928 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
929 MODULE_LICENSE("GPL");