1 /* linux/drivers/usb/phy/phy-samsung-usb.h
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
7 * OHCI-EXYNOS controllers.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/usb/phy.h>
21 /* Register definitions */
23 #define SAMSUNG_PHYPWR (0x00)
25 #define PHYPWR_NORMAL_MASK (0x19 << 0)
26 #define PHYPWR_OTG_DISABLE (0x1 << 4)
27 #define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
28 #define PHYPWR_FORCE_SUSPEND (0x1 << 1)
30 #define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
31 #define PHYPWR_SLEEP_PHY0 (0x1 << 5)
33 #define SAMSUNG_PHYCLK (0x04)
35 #define PHYCLK_MODE_USB11 (0x1 << 6)
36 #define PHYCLK_EXT_OSC (0x1 << 5)
37 #define PHYCLK_COMMON_ON_N (0x1 << 4)
38 #define PHYCLK_ID_PULL (0x1 << 2)
39 #define PHYCLK_CLKSEL_MASK (0x3 << 0)
40 #define PHYCLK_CLKSEL_48M (0x0 << 0)
41 #define PHYCLK_CLKSEL_12M (0x2 << 0)
42 #define PHYCLK_CLKSEL_24M (0x3 << 0)
44 #define SAMSUNG_RSTCON (0x08)
46 #define RSTCON_PHYLINK_SWRST (0x1 << 2)
47 #define RSTCON_HLINK_SWRST (0x1 << 1)
48 #define RSTCON_SWRST (0x1 << 0)
51 #define EXYNOS5_PHY_HOST_CTRL0 (0x00)
53 #define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
55 #define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
56 #define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
57 #define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
58 #define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
60 #define HOST_CTRL0_FSEL_MASK (0x7 << 16)
61 #define HOST_CTRL0_FSEL(_x) ((_x) << 16)
63 #define FSEL_CLKSEL_50M (0x7)
64 #define FSEL_CLKSEL_24M (0x5)
65 #define FSEL_CLKSEL_20M (0x4)
66 #define FSEL_CLKSEL_19200K (0x3)
67 #define FSEL_CLKSEL_12M (0x2)
68 #define FSEL_CLKSEL_10M (0x1)
69 #define FSEL_CLKSEL_9600K (0x0)
71 #define HOST_CTRL0_TESTBURNIN (0x1 << 11)
72 #define HOST_CTRL0_RETENABLE (0x1 << 10)
73 #define HOST_CTRL0_COMMONON_N (0x1 << 9)
74 #define HOST_CTRL0_SIDDQ (0x1 << 6)
75 #define HOST_CTRL0_FORCESLEEP (0x1 << 5)
76 #define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
77 #define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
78 #define HOST_CTRL0_UTMISWRST (0x1 << 2)
79 #define HOST_CTRL0_LINKSWRST (0x1 << 1)
80 #define HOST_CTRL0_PHYSWRST (0x1 << 0)
82 #define EXYNOS5_PHY_HOST_TUNE0 (0x04)
84 #define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
86 #define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
88 #define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
90 #define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
92 #define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
93 #define HSIC_CTRL_REFCLKSEL (0x2 << 23)
95 #define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
96 #define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
97 #define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
98 #define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
99 #define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
100 #define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
101 #define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
103 #define HSIC_CTRL_SIDDQ (0x1 << 6)
104 #define HSIC_CTRL_FORCESLEEP (0x1 << 5)
105 #define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
106 #define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
107 #define HSIC_CTRL_UTMISWRST (0x1 << 2)
108 #define HSIC_CTRL_PHYSWRST (0x1 << 0)
110 #define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
112 #define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
113 #define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
114 #define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
115 #define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
117 #define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
119 #define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
120 #define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
121 #define HOST_OHCICTRL_CNTSEL (0x1 << 1)
122 #define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
124 #define EXYNOS5_PHY_OTG_SYS (0x38)
126 #define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
127 #define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
128 #define OTG_SYS_PHY0_SWRST (0x1 << 12)
130 #define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
131 #define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
132 #define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
133 #define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
135 #define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
136 #define OTG_SYS_COMMON_ON (0x1 << 7)
138 #define OTG_SYS_FSEL_MASK (0x7 << 4)
139 #define OTG_SYS_FSEL(_x) ((_x) << 4)
141 #define OTG_SYS_FORCESLEEP (0x1 << 3)
142 #define OTG_SYS_OTGDISABLE (0x1 << 2)
143 #define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
144 #define OTG_SYS_FORCESUSPEND (0x1 << 0)
146 #define EXYNOS5_PHY_OTG_TUNE (0x40)
148 /* EXYNOS5: USB 3.0 DRD */
149 #define EXYNOS5_DRD_LINKSYSTEM (0x04)
151 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
152 #define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
153 #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
155 #define EXYNOS5_DRD_PHYUTMI (0x08)
157 #define PHYUTMI_OTGDISABLE (0x1 << 6)
158 #define PHYUTMI_FORCESUSPEND (0x1 << 1)
159 #define PHYUTMI_FORCESLEEP (0x1 << 0)
161 #define EXYNOS5_DRD_PHYPIPE (0x0c)
163 #define EXYNOS5_DRD_PHYCLKRST (0x10)
165 #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
166 #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
168 #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
169 #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
171 #define PHYCLKRST_SSC_EN (0x1 << 20)
172 #define PHYCLKRST_REF_SSP_EN (0x1 << 19)
173 #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
175 #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
176 #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
177 #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
178 #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
179 #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
180 #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
182 #define PHYCLKRST_FSEL_MASK (0x3f << 5)
183 #define PHYCLKRST_FSEL(_x) ((_x) << 5)
184 #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
185 #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
186 #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
187 #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
189 #define PHYCLKRST_RETENABLEN (0x1 << 4)
191 #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
192 #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
193 #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
195 #define PHYCLKRST_PORTRESET (0x1 << 1)
196 #define PHYCLKRST_COMMONONN (0x1 << 0)
198 #define EXYNOS5_DRD_PHYREG0 (0x14)
199 #define EXYNOS5_DRD_PHYREG1 (0x18)
201 #define EXYNOS5_DRD_PHYPARAM0 (0x1c)
203 #define PHYPARAM0_REF_USE_PAD (0x1 << 31)
204 #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
205 #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
207 #define EXYNOS5_DRD_PHYPARAM1 (0x20)
209 #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
210 #define PHYPARAM1_PCS_TXDEEMPH (0x1c)
212 #define EXYNOS5_DRD_PHYTERM (0x24)
214 #define EXYNOS5_DRD_PHYTEST (0x28)
216 #define PHYTEST_POWERDOWN_SSP (0x1 << 3)
217 #define PHYTEST_POWERDOWN_HSP (0x1 << 2)
219 #define EXYNOS5_DRD_PHYADP (0x2c)
221 #define EXYNOS5_DRD_PHYBATCHG (0x30)
223 #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
225 #define EXYNOS5_DRD_PHYRESUME (0x34)
226 #define EXYNOS5_DRD_LINKPORT (0x44)
229 #define MHZ (1000*1000)
236 #define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
237 #define S3C64XX_USBPHY_ENABLE (0x1 << 16)
238 #define EXYNOS_USBPHY_ENABLE (0x1 << 0)
239 #define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
241 enum samsung_cpu_type {
248 * struct samsung_usbphy_drvdata - driver data for various SoC variants
249 * @cpu_type: machine identifier
250 * @devphy_en_mask: device phy enable mask for PHY CONTROL register
251 * @hostphy_en_mask: host phy enable mask for PHY CONTROL register
252 * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
253 * mapped address of system controller.
254 * @hostphy_reg_offset: offset to HOST PHY CONTROL register from
255 * mapped address of system controller.
257 * Here we have a separate mask for device type phy.
258 * Having different masks for host and device type phy helps
259 * in setting independent masks in case of SoCs like S5PV210,
260 * in which PHY0 and PHY1 enable bits belong to same register
261 * placed at position 0 and 1 respectively.
262 * Although for newer SoCs like exynos these bits belong to
263 * different registers altogether placed at position 0.
265 struct samsung_usbphy_drvdata {
269 u32 devphy_reg_offset;
270 u32 hostphy_reg_offset;
274 * struct samsung_usbphy - transceiver driver state
275 * @phy: transceiver structure
276 * @plat: platform data
277 * @dev: The parent device supplied to the probe function
278 * @clk: usb phy clock
279 * @regs: usb phy controller registers memory base
280 * @pmuregs: USB device PHY_CONTROL register memory base
281 * @sysreg: USB2.0 PHY_CFG register memory base
282 * @ref_clk_freq: reference clock frequency selection
283 * @drv_data: driver data available for different SoCs
284 * @phy_type: Samsung SoCs specific phy types: #HOST
286 * @phy_usage: usage count for phy
287 * @lock: lock for phy operations
289 struct samsung_usbphy {
291 struct samsung_usbphy_data *plat;
295 void __iomem *pmuregs;
296 void __iomem *sysreg;
298 const struct samsung_usbphy_drvdata *drv_data;
299 enum samsung_usb_phy_type phy_type;
304 #define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
306 static const struct of_device_id samsung_usbphy_dt_match[];
308 static inline const struct samsung_usbphy_drvdata
309 *samsung_usbphy_get_driver_data(struct platform_device *pdev)
311 if (pdev->dev.of_node) {
312 const struct of_device_id *match;
313 match = of_match_node(samsung_usbphy_dt_match,
318 return (struct samsung_usbphy_drvdata *)
319 platform_get_device_id(pdev)->driver_data;
322 extern int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy);
323 extern void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, bool on);
324 extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
325 extern int samsung_usbphy_set_type(struct usb_phy *phy,
326 enum samsung_usb_phy_type phy_type);
327 extern int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy);