drivers/usb/musb/ux500_dma.c

   1 /*
   2  * drivers/usb/musb/ux500_dma.c
   3  *
   4  * U8500 DMA support code
   5  *
   6  * Copyright (C) 2009 STMicroelectronics
   7  * Copyright (C) 2011 ST-Ericsson SA
   8  * Authors:
   9  *      Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
  10  *      Praveena Nadahally <praveen.nadahally@stericsson.com>
  11  *      Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
  12  *
  13  * This program is free software: you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation, either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pfn.h>
  33 #include <linux/sizes.h>
  34 #include <linux/platform_data/usb-musb-ux500.h>
  35 #include "musb_core.h"
  36
  37 struct ux500_dma_channel {
  38         struct dma_channel channel;
  39         struct ux500_dma_controller *controller;
  40         struct musb_hw_ep *hw_ep;
  41         struct dma_chan *dma_chan;
  42         unsigned int cur_len;
  43         dma_cookie_t cookie;
  44         u8 ch_num;
  45         u8 is_tx;
  46         u8 is_allocated;
  47 };
  48
  49 struct ux500_dma_controller {
  50         struct dma_controller controller;
  51         struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
  52         struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
  53         u32     num_rx_channels;
  54         u32     num_tx_channels;
  55         void *private_data;
  56         dma_addr_t phy_base;
  57 };
  58
  59 /* Work function invoked from DMA callback to handle rx transfers. */
  60 static void ux500_dma_callback(void *private_data)
  61 {
  62         struct dma_channel *channel = private_data;
  63         struct ux500_dma_channel *ux500_channel = channel->private_data;
  64         struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
  65         struct musb *musb = hw_ep->musb;
  66         unsigned long flags;
  67
  68         dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
  69                 hw_ep->epnum);
  70
  71         spin_lock_irqsave(&musb->lock, flags);
  72         ux500_channel->channel.actual_len = ux500_channel->cur_len;
  73         ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
  74         musb_dma_completion(musb, hw_ep->epnum,
  75                 ux500_channel->is_tx);
  76         spin_unlock_irqrestore(&musb->lock, flags);
  77
  78 }
  79
  80 static bool ux500_configure_channel(struct dma_channel *channel,
  81                                 u16 packet_sz, u8 mode,
  82                                 dma_addr_t dma_addr, u32 len)
  83 {
  84         struct ux500_dma_channel *ux500_channel = channel->private_data;
  85         struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
  86         struct dma_chan *dma_chan = ux500_channel->dma_chan;
  87         struct dma_async_tx_descriptor *dma_desc;
  88         enum dma_transfer_direction direction;
  89         struct scatterlist sg;
  90         struct dma_slave_config slave_conf;
  91         enum dma_slave_buswidth addr_width;
  92         dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
  93                                         ux500_channel->controller->phy_base);
  94         struct musb *musb = ux500_channel->controller->private_data;
  95
  96         dev_dbg(musb->controller,
  97                 "packet_sz=%d, mode=%d, dma_addr=0x%llu, len=%d is_tx=%d\n",
  98                 packet_sz, mode, (unsigned long long) dma_addr,
  99                 len, ux500_channel->is_tx);
 100
 101         ux500_channel->cur_len = len;
 102
 103         sg_init_table(&sg, 1);
 104         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
 105                                             offset_in_page(dma_addr));
 106         sg_dma_address(&sg) = dma_addr;
 107         sg_dma_len(&sg) = len;
 108
 109         direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 110         addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
 111                                         DMA_SLAVE_BUSWIDTH_4_BYTES;
 112
 113         slave_conf.direction = direction;
 114         slave_conf.src_addr = usb_fifo_addr;
 115         slave_conf.src_addr_width = addr_width;
 116         slave_conf.src_maxburst = 16;
 117         slave_conf.dst_addr = usb_fifo_addr;
 118         slave_conf.dst_addr_width = addr_width;
 119         slave_conf.dst_maxburst = 16;
 120         slave_conf.device_fc = false;
 121
 122         dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
 123                                              (unsigned long) &slave_conf);
 124
 125         dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
 126                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 127         if (!dma_desc)
 128                 return false;
 129
 130         dma_desc->callback = ux500_dma_callback;
 131         dma_desc->callback_param = channel;
 132         ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
 133
 134         dma_async_issue_pending(dma_chan);
 135
 136         return true;
 137 }
 138
 139 static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
 140                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 141 {
 142         struct ux500_dma_controller *controller = container_of(c,
 143                         struct ux500_dma_controller, controller);
 144         struct ux500_dma_channel *ux500_channel = NULL;
 145         struct musb *musb = controller->private_data;
 146         u8 ch_num = hw_ep->epnum - 1;
 147         u32 max_ch;
 148
 149         /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
 150          * to specified hw_ep. For example DMA channel 0 can only be allocated
 151          * to hw_ep 1 and 9.
 152          */
 153         if (ch_num > 7)
 154                 ch_num -= 8;
 155
 156         max_ch = is_tx ? controller->num_tx_channels :
 157                         controller->num_rx_channels;
 158
 159         if (ch_num >= max_ch)
 160                 return NULL;
 161
 162         ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
 163                                 &(controller->rx_channel[ch_num]) ;
 164
 165         /* Check if channel is already used. */
 166         if (ux500_channel->is_allocated)
 167                 return NULL;
 168
 169         ux500_channel->hw_ep = hw_ep;
 170         ux500_channel->is_allocated = 1;
 171
 172         dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
 173                 hw_ep->epnum, is_tx, ch_num);
 174
 175         return &(ux500_channel->channel);
 176 }
 177
 178 static void ux500_dma_channel_release(struct dma_channel *channel)
 179 {
 180         struct ux500_dma_channel *ux500_channel = channel->private_data;
 181         struct musb *musb = ux500_channel->controller->private_data;
 182
 183         dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
 184
 185         if (ux500_channel->is_allocated) {
 186                 ux500_channel->is_allocated = 0;
 187                 channel->status = MUSB_DMA_STATUS_FREE;
 188                 channel->actual_len = 0;
 189         }
 190 }
 191
 192 static int ux500_dma_is_compatible(struct dma_channel *channel,
 193                 u16 maxpacket, void *buf, u32 length)
 194 {
 195         if ((maxpacket & 0x3)           ||
 196                 ((unsigned long int) buf & 0x3) ||
 197                 (length < 512)          ||
 198                 (length & 0x3))
 199                 return false;
 200         else
 201                 return true;
 202 }
 203
 204 static int ux500_dma_channel_program(struct dma_channel *channel,
 205                                 u16 packet_sz, u8 mode,
 206                                 dma_addr_t dma_addr, u32 len)
 207 {
 208         int ret;
 209
 210         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 211                 channel->status == MUSB_DMA_STATUS_BUSY);
 212
 213         if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
 214                 return false;
 215
 216         channel->status = MUSB_DMA_STATUS_BUSY;
 217         channel->actual_len = 0;
 218         ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
 219         if (!ret)
 220                 channel->status = MUSB_DMA_STATUS_FREE;
 221
 222         return ret;
 223 }
 224
 225 static int ux500_dma_channel_abort(struct dma_channel *channel)
 226 {
 227         struct ux500_dma_channel *ux500_channel = channel->private_data;
 228         struct ux500_dma_controller *controller = ux500_channel->controller;
 229         struct musb *musb = controller->private_data;
 230         void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
 231         u16 csr;
 232
 233         dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
 234                 ux500_channel->ch_num, ux500_channel->is_tx);
 235
 236         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 237                 if (ux500_channel->is_tx) {
 238                         csr = musb_readw(epio, MUSB_TXCSR);
 239                         csr &= ~(MUSB_TXCSR_AUTOSET |
 240                                  MUSB_TXCSR_DMAENAB |
 241                                  MUSB_TXCSR_DMAMODE);
 242                         musb_writew(epio, MUSB_TXCSR, csr);
 243                 } else {
 244                         csr = musb_readw(epio, MUSB_RXCSR);
 245                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 246                                  MUSB_RXCSR_DMAENAB |
 247                                  MUSB_RXCSR_DMAMODE);
 248                         musb_writew(epio, MUSB_RXCSR, csr);
 249                 }
 250
 251                 ux500_channel->dma_chan->device->
 252                                 device_control(ux500_channel->dma_chan,
 253                                         DMA_TERMINATE_ALL, 0);
 254                 channel->status = MUSB_DMA_STATUS_FREE;
 255         }
 256         return 0;
 257 }
 258
 259 static int ux500_dma_controller_stop(struct dma_controller *c)
 260 {
 261         struct ux500_dma_controller *controller = container_of(c,
 262                         struct ux500_dma_controller, controller);
 263         struct ux500_dma_channel *ux500_channel;
 264         struct dma_channel *channel;
 265         u8 ch_num;
 266
 267         for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
 268                 channel = &controller->rx_channel[ch_num].channel;
 269                 ux500_channel = channel->private_data;
 270
 271                 ux500_dma_channel_release(channel);
 272
 273                 if (ux500_channel->dma_chan)
 274                         dma_release_channel(ux500_channel->dma_chan);
 275         }
 276
 277         for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
 278                 channel = &controller->tx_channel[ch_num].channel;
 279                 ux500_channel = channel->private_data;
 280
 281                 ux500_dma_channel_release(channel);
 282
 283                 if (ux500_channel->dma_chan)
 284                         dma_release_channel(ux500_channel->dma_chan);
 285         }
 286
 287         return 0;
 288 }
 289
 290 static int ux500_dma_controller_start(struct dma_controller *c)
 291 {
 292         struct ux500_dma_controller *controller = container_of(c,
 293                         struct ux500_dma_controller, controller);
 294         struct ux500_dma_channel *ux500_channel = NULL;
 295         struct musb *musb = controller->private_data;
 296         struct device *dev = musb->controller;
 297         struct musb_hdrc_platform_data *plat = dev->platform_data;
 298         struct ux500_musb_board_data *data = plat->board_data;
 299         struct dma_channel *dma_channel = NULL;
 300         u32 ch_num;
 301         u8 dir;
 302         u8 is_tx = 0;
 303
 304         void **param_array;
 305         struct ux500_dma_channel *channel_array;
 306         u32 ch_count;
 307         dma_cap_mask_t mask;
 308
 309         if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
 310                 (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
 311                 return -EINVAL;
 312
 313         controller->num_rx_channels = data->num_rx_channels;
 314         controller->num_tx_channels = data->num_tx_channels;
 315
 316         dma_cap_zero(mask);
 317         dma_cap_set(DMA_SLAVE, mask);
 318
 319         /* Prepare the loop for RX channels */
 320         channel_array = controller->rx_channel;
 321         ch_count = data->num_rx_channels;
 322         param_array = data->dma_rx_param_array;
 323
 324         for (dir = 0; dir < 2; dir++) {
 325                 for (ch_num = 0; ch_num < ch_count; ch_num++) {
 326                         ux500_channel = &channel_array[ch_num];
 327                         ux500_channel->controller = controller;
 328                         ux500_channel->ch_num = ch_num;
 329                         ux500_channel->is_tx = is_tx;
 330
 331                         dma_channel = &(ux500_channel->channel);
 332                         dma_channel->private_data = ux500_channel;
 333                         dma_channel->status = MUSB_DMA_STATUS_FREE;
 334                         dma_channel->max_len = SZ_16M;
 335
 336                         ux500_channel->dma_chan = dma_request_channel(mask,
 337                                                         data->dma_filter,
 338                                                         param_array[ch_num]);
 339                         if (!ux500_channel->dma_chan) {
 340                                 ERR("Dma pipe allocation error dir=%d ch=%d\n",
 341                                         dir, ch_num);
 342
 343                                 /* Release already allocated channels */
 344                                 ux500_dma_controller_stop(c);
 345
 346                                 return -EBUSY;
 347                         }
 348
 349                 }
 350
 351                 /* Prepare the loop for TX channels */
 352                 channel_array = controller->tx_channel;
 353                 ch_count = data->num_tx_channels;
 354                 param_array = data->dma_tx_param_array;
 355                 is_tx = 1;
 356         }
 357
 358         return 0;
 359 }
 360
 361 void dma_controller_destroy(struct dma_controller *c)
 362 {
 363         struct ux500_dma_controller *controller = container_of(c,
 364                         struct ux500_dma_controller, controller);
 365
 366         kfree(controller);
 367 }
 368
 369 struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base)
 370 {
 371         struct ux500_dma_controller *controller;
 372         struct platform_device *pdev = to_platform_device(musb->controller);
 373         struct resource *iomem;
 374
 375         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 376         if (!controller)
 377                 goto kzalloc_fail;
 378
 379         controller->private_data = musb;
 380
 381         /* Save physical address for DMA controller. */
 382         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 383         if (!iomem) {
 384                 dev_err(musb->controller, "no memory resource defined\n");
 385                 goto plat_get_fail;
 386         }
 387
 388         controller->phy_base = (dma_addr_t) iomem->start;
 389
 390         controller->controller.start = ux500_dma_controller_start;
 391         controller->controller.stop = ux500_dma_controller_stop;
 392         controller->controller.channel_alloc = ux500_dma_channel_allocate;
 393         controller->controller.channel_release = ux500_dma_channel_release;
 394         controller->controller.channel_program = ux500_dma_channel_program;
 395         controller->controller.channel_abort = ux500_dma_channel_abort;
 396         controller->controller.is_compatible = ux500_dma_is_compatible;
 397
 398         return &controller->controller;
 399
 400 plat_get_fail:
 401         kfree(controller);
 402 kzalloc_fail:
 403         return NULL;
 404 }