drivers/usb/musb/tusb6010.c

   1 /*
   2  * TUSB6010 USB 2.0 OTG Dual Role controller
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Notes:
  12  * - Driver assumes that interface to external host (main CPU) is
  13  *   configured for NOR FLASH interface instead of VLYNQ serial
  14  *   interface.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/init.h>
  21 #include <linux/usb.h>
  22 #include <linux/irq.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #include "musb_core.h"
  27
  28 struct tusb6010_glue {
  29         struct device           *dev;
  30         struct platform_device  *musb;
  31 };
  32
  33 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
  34
  35 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
  36 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
  37
  38 /*
  39  * Checks the revision. We need to use the DMA register as 3.0 does not
  40  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  41  */
  42 u8 tusb_get_revision(struct musb *musb)
  43 {
  44         void __iomem    *tbase = musb->ctrl_base;
  45         u32             die_id;
  46         u8              rev;
  47
  48         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  49         if (TUSB_REV_MAJOR(rev) == 3) {
  50                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  51                                 TUSB_DIDR1_HI));
  52                 if (die_id >= TUSB_DIDR1_HI_REV_31)
  53                         rev |= 1;
  54         }
  55
  56         return rev;
  57 }
  58
  59 static int tusb_print_revision(struct musb *musb)
  60 {
  61         void __iomem    *tbase = musb->ctrl_base;
  62         u8              rev;
  63
  64         rev = tusb_get_revision(musb);
  65
  66         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  67                 "prcm",
  68                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  69                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  70                 "int",
  71                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  72                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  73                 "gpio",
  74                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  75                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  76                 "dma",
  77                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  78                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  79                 "dieid",
  80                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  81                 "rev",
  82                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  83
  84         return tusb_get_revision(musb);
  85 }
  86
  87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  88                                 | TUSB_PHY_OTG_CTRL_TESTM0)
  89
  90 /*
  91  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  92  * Disables power detection in PHY for the duration of idle.
  93  */
  94 static void tusb_wbus_quirk(struct musb *musb, int enabled)
  95 {
  96         void __iomem    *tbase = musb->ctrl_base;
  97         static u32      phy_otg_ctrl, phy_otg_ena;
  98         u32             tmp;
  99
 100         if (enabled) {
 101                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 102                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 103                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
 104                                 | phy_otg_ena | WBUS_QUIRK_MASK;
 105                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 106                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
 107                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
 108                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 109                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
 110                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 111                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 112         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
 113                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
 114                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
 115                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 116                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
 117                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 118                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
 119                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 120                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 121                 phy_otg_ctrl = 0;
 122                 phy_otg_ena = 0;
 123         }
 124 }
 125
 126 /*
 127  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
 128  * so both loading and unloading FIFOs need explicit byte counts.
 129  */
 130
 131 static inline void
 132 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
 133 {
 134         u32             val;
 135         int             i;
 136
 137         if (len > 4) {
 138                 for (i = 0; i < (len >> 2); i++) {
 139                         memcpy(&val, buf, 4);
 140                         musb_writel(fifo, 0, val);
 141                         buf += 4;
 142                 }
 143                 len %= 4;
 144         }
 145         if (len > 0) {
 146                 /* Write the rest 1 - 3 bytes to FIFO */
 147                 memcpy(&val, buf, len);
 148                 musb_writel(fifo, 0, val);
 149         }
 150 }
 151
 152 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
 153                                                 void __iomem *buf, u16 len)
 154 {
 155         u32             val;
 156         int             i;
 157
 158         if (len > 4) {
 159                 for (i = 0; i < (len >> 2); i++) {
 160                         val = musb_readl(fifo, 0);
 161                         memcpy(buf, &val, 4);
 162                         buf += 4;
 163                 }
 164                 len %= 4;
 165         }
 166         if (len > 0) {
 167                 /* Read the rest 1 - 3 bytes from FIFO */
 168                 val = musb_readl(fifo, 0);
 169                 memcpy(buf, &val, len);
 170         }
 171 }
 172
 173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
 174 {
 175         struct musb *musb = hw_ep->musb;
 176         void __iomem    *ep_conf = hw_ep->conf;
 177         void __iomem    *fifo = hw_ep->fifo;
 178         u8              epnum = hw_ep->epnum;
 179
 180         prefetch(buf);
 181
 182         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 183                         'T', epnum, fifo, len, buf);
 184
 185         if (epnum)
 186                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 187                         TUSB_EP_CONFIG_XFR_SIZE(len));
 188         else
 189                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
 190                         TUSB_EP0_CONFIG_XFR_SIZE(len));
 191
 192         if (likely((0x01 & (unsigned long) buf) == 0)) {
 193
 194                 /* Best case is 32bit-aligned destination address */
 195                 if ((0x02 & (unsigned long) buf) == 0) {
 196                         if (len >= 4) {
 197                                 writesl(fifo, buf, len >> 2);
 198                                 buf += (len & ~0x03);
 199                                 len &= 0x03;
 200                         }
 201                 } else {
 202                         if (len >= 2) {
 203                                 u32 val;
 204                                 int i;
 205
 206                                 /* Cannot use writesw, fifo is 32-bit */
 207                                 for (i = 0; i < (len >> 2); i++) {
 208                                         val = (u32)(*(u16 *)buf);
 209                                         buf += 2;
 210                                         val |= (*(u16 *)buf) << 16;
 211                                         buf += 2;
 212                                         musb_writel(fifo, 0, val);
 213                                 }
 214                                 len &= 0x03;
 215                         }
 216                 }
 217         }
 218
 219         if (len > 0)
 220                 tusb_fifo_write_unaligned(fifo, buf, len);
 221 }
 222
 223 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
 224 {
 225         struct musb *musb = hw_ep->musb;
 226         void __iomem    *ep_conf = hw_ep->conf;
 227         void __iomem    *fifo = hw_ep->fifo;
 228         u8              epnum = hw_ep->epnum;
 229
 230         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 231                         'R', epnum, fifo, len, buf);
 232
 233         if (epnum)
 234                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 235                         TUSB_EP_CONFIG_XFR_SIZE(len));
 236         else
 237                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
 238
 239         if (likely((0x01 & (unsigned long) buf) == 0)) {
 240
 241                 /* Best case is 32bit-aligned destination address */
 242                 if ((0x02 & (unsigned long) buf) == 0) {
 243                         if (len >= 4) {
 244                                 readsl(fifo, buf, len >> 2);
 245                                 buf += (len & ~0x03);
 246                                 len &= 0x03;
 247                         }
 248                 } else {
 249                         if (len >= 2) {
 250                                 u32 val;
 251                                 int i;
 252
 253                                 /* Cannot use readsw, fifo is 32-bit */
 254                                 for (i = 0; i < (len >> 2); i++) {
 255                                         val = musb_readl(fifo, 0);
 256                                         *(u16 *)buf = (u16)(val & 0xffff);
 257                                         buf += 2;
 258                                         *(u16 *)buf = (u16)(val >> 16);
 259                                         buf += 2;
 260                                 }
 261                                 len &= 0x03;
 262                         }
 263                 }
 264         }
 265
 266         if (len > 0)
 267                 tusb_fifo_read_unaligned(fifo, buf, len);
 268 }
 269
 270 static struct musb *the_musb;
 271
 272 /* This is used by gadget drivers, and OTG transceiver logic, allowing
 273  * at most mA current to be drawn from VBUS during a Default-B session
 274  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
 275  * mode), or low power Default-B sessions, something else supplies power.
 276  * Caller must take care of locking.
 277  */
 278 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
 279 {
 280         struct musb     *musb = the_musb;
 281         void __iomem    *tbase = musb->ctrl_base;
 282         u32             reg;
 283
 284         /* tps65030 seems to consume max 100mA, with maybe 60mA available
 285          * (measured on one board) for things other than tps and tusb.
 286          *
 287          * Boards sharing the CPU clock with CLKIN will need to prevent
 288          * certain idle sleep states while the USB link is active.
 289          *
 290          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
 291          * The actual current usage would be very board-specific.  For now,
 292          * it's simpler to just use an aggregate (also board-specific).
 293          */
 294         if (x->default_a || mA < (musb->min_power << 1))
 295                 mA = 0;
 296
 297         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 298         if (mA) {
 299                 musb->is_bus_powered = 1;
 300                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
 301         } else {
 302                 musb->is_bus_powered = 0;
 303                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 304         }
 305         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 306
 307         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
 308         return 0;
 309 }
 310
 311 /* workaround for issue 13:  change clock during chip idle
 312  * (to be fixed in rev3 silicon) ... symptoms include disconnect
 313  * or looping suspend/resume cycles
 314  */
 315 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
 316 {
 317         void __iomem    *tbase = musb->ctrl_base;
 318         u32             reg;
 319
 320         reg = musb_readl(tbase, TUSB_PRCM_CONF);
 321         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
 322
 323         /* 0 = refclk (clkin, XI)
 324          * 1 = PHY 60 MHz (internal PLL)
 325          * 2 = not supported
 326          * 3 = what?
 327          */
 328         if (mode > 0)
 329                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
 330
 331         musb_writel(tbase, TUSB_PRCM_CONF, reg);
 332
 333         /* FIXME tusb6010_platform_retime(mode == 0); */
 334 }
 335
 336 /*
 337  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
 338  * Other code ensures that we idle unless we're connected _and_ the
 339  * USB link is not suspended ... and tells us the relevant wakeup
 340  * events.  SW_EN for voltage is handled separately.
 341  */
 342 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
 343 {
 344         void __iomem    *tbase = musb->ctrl_base;
 345         u32             reg;
 346
 347         if ((wakeup_enables & TUSB_PRCM_WBUS)
 348                         && (tusb_get_revision(musb) == TUSB_REV_30))
 349                 tusb_wbus_quirk(musb, 1);
 350
 351         tusb_set_clock_source(musb, 0);
 352
 353         wakeup_enables |= TUSB_PRCM_WNORCS;
 354         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
 355
 356         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
 357          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
 358          * Presumably that's mostly to save power, hence WID is immaterial ...
 359          */
 360
 361         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 362         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
 363         if (is_host_active(musb)) {
 364                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 365                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 366         } else {
 367                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 368                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 369         }
 370         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
 371         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 372
 373         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
 374 }
 375
 376 /*
 377  * Updates cable VBUS status. Caller must take care of locking.
 378  */
 379 static int tusb_musb_vbus_status(struct musb *musb)
 380 {
 381         void __iomem    *tbase = musb->ctrl_base;
 382         u32             otg_stat, prcm_mngmt;
 383         int             ret = 0;
 384
 385         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 386         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
 387
 388         /* Temporarily enable VBUS detection if it was disabled for
 389          * suspend mode. Unless it's enabled otg_stat and devctl will
 390          * not show correct VBUS state.
 391          */
 392         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
 393                 u32 tmp = prcm_mngmt;
 394                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 395                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
 396                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 397                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
 398         }
 399
 400         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
 401                 ret = 1;
 402
 403         return ret;
 404 }
 405
 406 static struct timer_list musb_idle_timer;
 407
 408 static void musb_do_idle(unsigned long _musb)
 409 {
 410         struct musb     *musb = (void *)_musb;
 411         unsigned long   flags;
 412
 413         spin_lock_irqsave(&musb->lock, flags);
 414
 415         switch (musb->xceiv->state) {
 416         case OTG_STATE_A_WAIT_BCON:
 417                 if ((musb->a_wait_bcon != 0)
 418                         && (musb->idle_timeout == 0
 419                                 || time_after(jiffies, musb->idle_timeout))) {
 420                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
 421                                         otg_state_string(musb->xceiv->state));
 422                 }
 423                 /* FALLTHROUGH */
 424         case OTG_STATE_A_IDLE:
 425                 tusb_musb_set_vbus(musb, 0);
 426         default:
 427                 break;
 428         }
 429
 430         if (!musb->is_active) {
 431                 u32     wakeups;
 432
 433                 /* wait until khubd handles port change status */
 434                 if (is_host_active(musb) && (musb->port1_status >> 16))
 435                         goto done;
 436
 437                 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
 438                         wakeups = 0;
 439                 } else {
 440                         wakeups = TUSB_PRCM_WHOSTDISCON
 441                                 | TUSB_PRCM_WBUS
 442                                         | TUSB_PRCM_WVBUS;
 443                         if (is_otg_enabled(musb))
 444                                 wakeups |= TUSB_PRCM_WID;
 445                 }
 446                 tusb_allow_idle(musb, wakeups);
 447         }
 448 done:
 449         spin_unlock_irqrestore(&musb->lock, flags);
 450 }
 451
 452 /*
 453  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
 454  * like "disconnected" or "suspended".  We'll be woken out of it by
 455  * connect, resume, or disconnect.
 456  *
 457  * Needs to be called as the last function everywhere where there is
 458  * register access to TUSB6010 because of NOR flash wake-up.
 459  * Caller should own controller spinlock.
 460  *
 461  * Delay because peripheral enables D+ pullup 3msec after SE0, and
 462  * we don't want to treat that full speed J as a wakeup event.
 463  * ... peripherals must draw only suspend current after 10 msec.
 464  */
 465 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
 466 {
 467         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 468         static unsigned long    last_timer;
 469
 470         if (timeout == 0)
 471                 timeout = default_timeout;
 472
 473         /* Never idle if active, or when VBUS timeout is not set as host */
 474         if (musb->is_active || ((musb->a_wait_bcon == 0)
 475                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 476                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 477                         otg_state_string(musb->xceiv->state));
 478                 del_timer(&musb_idle_timer);
 479                 last_timer = jiffies;
 480                 return;
 481         }
 482
 483         if (time_after(last_timer, timeout)) {
 484                 if (!timer_pending(&musb_idle_timer))
 485                         last_timer = timeout;
 486                 else {
 487                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
 488                         return;
 489                 }
 490         }
 491         last_timer = timeout;
 492
 493         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
 494                 otg_state_string(musb->xceiv->state),
 495                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 496         mod_timer(&musb_idle_timer, timeout);
 497 }
 498
 499 /* ticks of 60 MHz clock */
 500 #define DEVCLOCK                60000000
 501 #define OTG_TIMER_MS(msecs)     ((msecs) \
 502                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
 503                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
 504                 : 0)
 505
 506 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
 507 {
 508         void __iomem    *tbase = musb->ctrl_base;
 509         u32             conf, prcm, timer;
 510         u8              devctl;
 511
 512         /* HDRC controls CPEN, but beware current surges during device
 513          * connect.  They can trigger transient overcurrent conditions
 514          * that must be ignored.
 515          */
 516
 517         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
 518         conf = musb_readl(tbase, TUSB_DEV_CONF);
 519         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 520
 521         if (is_on) {
 522                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
 523                 musb->xceiv->default_a = 1;
 524                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 525                 devctl |= MUSB_DEVCTL_SESSION;
 526
 527                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
 528                 MUSB_HST_MODE(musb);
 529         } else {
 530                 u32     otg_stat;
 531
 532                 timer = 0;
 533
 534                 /* If ID pin is grounded, we want to be a_idle */
 535                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 536                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
 537                         switch (musb->xceiv->state) {
 538                         case OTG_STATE_A_WAIT_VRISE:
 539                         case OTG_STATE_A_WAIT_BCON:
 540                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 541                                 break;
 542                         case OTG_STATE_A_WAIT_VFALL:
 543                                 musb->xceiv->state = OTG_STATE_A_IDLE;
 544                                 break;
 545                         default:
 546                                 musb->xceiv->state = OTG_STATE_A_IDLE;
 547                         }
 548                         musb->is_active = 0;
 549                         musb->xceiv->default_a = 1;
 550                         MUSB_HST_MODE(musb);
 551                 } else {
 552                         musb->is_active = 0;
 553                         musb->xceiv->default_a = 0;
 554                         musb->xceiv->state = OTG_STATE_B_IDLE;
 555                         MUSB_DEV_MODE(musb);
 556                 }
 557
 558                 devctl &= ~MUSB_DEVCTL_SESSION;
 559                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
 560         }
 561         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 562
 563         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
 564         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
 565         musb_writel(tbase, TUSB_DEV_CONF, conf);
 566         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 567
 568         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
 569                 otg_state_string(musb->xceiv->state),
 570                 musb_readb(musb->mregs, MUSB_DEVCTL),
 571                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
 572                 conf, prcm);
 573 }
 574
 575 /*
 576  * Sets the mode to OTG, peripheral or host by changing the ID detection.
 577  * Caller must take care of locking.
 578  *
 579  * Note that if a mini-A cable is plugged in the ID line will stay down as
 580  * the weak ID pull-up is not able to pull the ID up.
 581  *
 582  * REVISIT: It would be possible to add support for changing between host
 583  * and peripheral modes in non-OTG configurations by reconfiguring hardware
 584  * and then setting musb->board_mode. For now, only support OTG mode.
 585  */
 586 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
 587 {
 588         void __iomem    *tbase = musb->ctrl_base;
 589         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
 590
 591         if (musb->board_mode != MUSB_OTG) {
 592                 ERR("Changing mode currently only supported in OTG mode\n");
 593                 return -EINVAL;
 594         }
 595
 596         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 597         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 598         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 599         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
 600
 601         switch (musb_mode) {
 602
 603         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
 604                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 605                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 606                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
 607                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
 608                 break;
 609         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
 610                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 611                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 612                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 613                 break;
 614         case MUSB_OTG:          /* Use PHY ID detection */
 615                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 616                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 617                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 618                 break;
 619
 620         default:
 621                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
 622                 return -EINVAL;
 623         }
 624
 625         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
 626                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
 627         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
 628                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
 629         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
 630
 631         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 632         if ((musb_mode == MUSB_PERIPHERAL) &&
 633                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
 634                         INFO("Cannot be peripheral with mini-A cable "
 635                         "otg_stat: %08x\n", otg_stat);
 636
 637         return 0;
 638 }
 639
 640 static inline unsigned long
 641 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 642 {
 643         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 644         unsigned long   idle_timeout = 0;
 645
 646         /* ID pin */
 647         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
 648                 int     default_a;
 649
 650                 if (is_otg_enabled(musb))
 651                         default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
 652                 else
 653                         default_a = is_host_enabled(musb);
 654                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
 655                 musb->xceiv->default_a = default_a;
 656                 tusb_musb_set_vbus(musb, default_a);
 657
 658                 /* Don't allow idling immediately */
 659                 if (default_a)
 660                         idle_timeout = jiffies + (HZ * 3);
 661         }
 662
 663         /* VBUS state change */
 664         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
 665
 666                 /* B-dev state machine:  no vbus ~= disconnect */
 667                 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
 668                                 || !is_host_enabled(musb)) {
 669                         /* ? musb_root_disconnect(musb); */
 670                         musb->port1_status &=
 671                                 ~(USB_PORT_STAT_CONNECTION
 672                                 | USB_PORT_STAT_ENABLE
 673                                 | USB_PORT_STAT_LOW_SPEED
 674                                 | USB_PORT_STAT_HIGH_SPEED
 675                                 | USB_PORT_STAT_TEST
 676                                 );
 677
 678                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
 679                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
 680                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
 681                                         /* INTR_DISCONNECT can hide... */
 682                                         musb->xceiv->state = OTG_STATE_B_IDLE;
 683                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
 684                                 }
 685                                 musb->is_active = 0;
 686                         }
 687                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 688                                 otg_state_string(musb->xceiv->state), otg_stat);
 689                         idle_timeout = jiffies + (1 * HZ);
 690                         schedule_work(&musb->irq_work);
 691
 692                 } else /* A-dev state machine */ {
 693                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 694                                 otg_state_string(musb->xceiv->state), otg_stat);
 695
 696                         switch (musb->xceiv->state) {
 697                         case OTG_STATE_A_IDLE:
 698                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
 699                                 musb_platform_set_vbus(musb, 1);
 700
 701                                 /* CONNECT can wake if a_wait_bcon is set */
 702                                 if (musb->a_wait_bcon != 0)
 703                                         musb->is_active = 0;
 704                                 else
 705                                         musb->is_active = 1;
 706
 707                                 /*
 708                                  * OPT FS A TD.4.6 needs few seconds for
 709                                  * A_WAIT_VRISE
 710                                  */
 711                                 idle_timeout = jiffies + (2 * HZ);
 712
 713                                 break;
 714                         case OTG_STATE_A_WAIT_VRISE:
 715                                 /* ignore; A-session-valid < VBUS_VALID/2,
 716                                  * we monitor this with the timer
 717                                  */
 718                                 break;
 719                         case OTG_STATE_A_WAIT_VFALL:
 720                                 /* REVISIT this irq triggers during short
 721                                  * spikes caused by enumeration ...
 722                                  */
 723                                 if (musb->vbuserr_retry) {
 724                                         musb->vbuserr_retry--;
 725                                         tusb_musb_set_vbus(musb, 1);
 726                                 } else {
 727                                         musb->vbuserr_retry
 728                                                 = VBUSERR_RETRY_COUNT;
 729                                         tusb_musb_set_vbus(musb, 0);
 730                                 }
 731                                 break;
 732                         default:
 733                                 break;
 734                         }
 735                 }
 736         }
 737
 738         /* OTG timer expiration */
 739         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
 740                 u8      devctl;
 741
 742                 dev_dbg(musb->controller, "%s timer, %03x\n",
 743                         otg_state_string(musb->xceiv->state), otg_stat);
 744
 745                 switch (musb->xceiv->state) {
 746                 case OTG_STATE_A_WAIT_VRISE:
 747                         /* VBUS has probably been valid for a while now,
 748                          * but may well have bounced out of range a bit
 749                          */
 750                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 751                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
 752                                 if ((devctl & MUSB_DEVCTL_VBUS)
 753                                                 != MUSB_DEVCTL_VBUS) {
 754                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
 755                                         break;
 756                                 }
 757                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 758                                 musb->is_active = 0;
 759                                 idle_timeout = jiffies
 760                                         + msecs_to_jiffies(musb->a_wait_bcon);
 761                         } else {
 762                                 /* REVISIT report overcurrent to hub? */
 763                                 ERR("vbus too slow, devctl %02x\n", devctl);
 764                                 tusb_musb_set_vbus(musb, 0);
 765                         }
 766                         break;
 767                 case OTG_STATE_A_WAIT_BCON:
 768                         if (musb->a_wait_bcon != 0)
 769                                 idle_timeout = jiffies
 770                                         + msecs_to_jiffies(musb->a_wait_bcon);
 771                         break;
 772                 case OTG_STATE_A_SUSPEND:
 773                         break;
 774                 case OTG_STATE_B_WAIT_ACON:
 775                         break;
 776                 default:
 777                         break;
 778                 }
 779         }
 780         schedule_work(&musb->irq_work);
 781
 782         return idle_timeout;
 783 }
 784
 785 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
 786 {
 787         struct musb     *musb = __hci;
 788         void __iomem    *tbase = musb->ctrl_base;
 789         unsigned long   flags, idle_timeout = 0;
 790         u32             int_mask, int_src;
 791
 792         spin_lock_irqsave(&musb->lock, flags);
 793
 794         /* Mask all interrupts to allow using both edge and level GPIO irq */
 795         int_mask = musb_readl(tbase, TUSB_INT_MASK);
 796         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 797
 798         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
 799         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
 800
 801         musb->int_usb = (u8) int_src;
 802
 803         /* Acknowledge wake-up source interrupts */
 804         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
 805                 u32     reg;
 806                 u32     i;
 807
 808                 if (tusb_get_revision(musb) == TUSB_REV_30)
 809                         tusb_wbus_quirk(musb, 0);
 810
 811                 /* there are issues re-locking the PLL on wakeup ... */
 812
 813                 /* work around issue 8 */
 814                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
 815                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
 816                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
 817                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
 818                         if (reg == i)
 819                                 break;
 820                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
 821                 }
 822
 823                 /* work around issue 13 (2nd half) */
 824                 tusb_set_clock_source(musb, 1);
 825
 826                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
 827                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
 828                 if (reg & ~TUSB_PRCM_WNORCS) {
 829                         musb->is_active = 1;
 830                         schedule_work(&musb->irq_work);
 831                 }
 832                 dev_dbg(musb->controller, "wake %sactive %02x\n",
 833                                 musb->is_active ? "" : "in", reg);
 834
 835                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
 836         }
 837
 838         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
 839                 del_timer(&musb_idle_timer);
 840
 841         /* OTG state change reports (annoyingly) not issued by Mentor core */
 842         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
 843                                 | TUSB_INT_SRC_OTG_TIMEOUT
 844                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
 845                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
 846
 847         /* TX dma callback must be handled here, RX dma callback is
 848          * handled in tusb_omap_dma_cb.
 849          */
 850         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
 851                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
 852                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
 853
 854                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
 855                 real_dma_src = ~real_dma_src & dma_src;
 856                 if (tusb_dma_omap() && real_dma_src) {
 857                         int     tx_source = (real_dma_src & 0xffff);
 858                         int     i;
 859
 860                         for (i = 1; i <= 15; i++) {
 861                                 if (tx_source & (1 << i)) {
 862                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
 863                                         musb_dma_completion(musb, i, 1);
 864                                 }
 865                         }
 866                 }
 867                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
 868         }
 869
 870         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
 871         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
 872                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
 873
 874                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
 875                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
 876                 musb->int_tx = (musb_src & 0xffff);
 877         } else {
 878                 musb->int_rx = 0;
 879                 musb->int_tx = 0;
 880         }
 881
 882         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
 883                 musb_interrupt(musb);
 884
 885         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
 886         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
 887                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
 888
 889         tusb_musb_try_idle(musb, idle_timeout);
 890
 891         musb_writel(tbase, TUSB_INT_MASK, int_mask);
 892         spin_unlock_irqrestore(&musb->lock, flags);
 893
 894         return IRQ_HANDLED;
 895 }
 896
 897 static int dma_off;
 898
 899 /*
 900  * Enables TUSB6010. Caller must take care of locking.
 901  * REVISIT:
 902  * - Check what is unnecessary in MGC_HdrcStart()
 903  */
 904 static void tusb_musb_enable(struct musb *musb)
 905 {
 906         void __iomem    *tbase = musb->ctrl_base;
 907
 908         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
 909          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
 910         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
 911
 912         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
 913         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
 914         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 915         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 916
 917         /* Clear all subsystem interrups */
 918         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
 919         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
 920         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
 921
 922         /* Acknowledge pending interrupt(s) */
 923         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
 924
 925         /* Only 0 clock cycles for minimum interrupt de-assertion time and
 926          * interrupt polarity active low seems to work reliably here */
 927         musb_writel(tbase, TUSB_INT_CTRL_CONF,
 928                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
 929
 930         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
 931
 932         /* maybe force into the Default-A OTG state machine */
 933         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
 934                         & TUSB_DEV_OTG_STAT_ID_STATUS))
 935                 musb_writel(tbase, TUSB_INT_SRC_SET,
 936                                 TUSB_INT_SRC_ID_STATUS_CHNG);
 937
 938         if (is_dma_capable() && dma_off)
 939                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
 940                                 __FILE__, __func__);
 941         else
 942                 dma_off = 1;
 943 }
 944
 945 /*
 946  * Disables TUSB6010. Caller must take care of locking.
 947  */
 948 static void tusb_musb_disable(struct musb *musb)
 949 {
 950         void __iomem    *tbase = musb->ctrl_base;
 951
 952         /* FIXME stop DMA, IRQs, timers, ... */
 953
 954         /* disable all IRQs */
 955         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 956         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
 957         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 958         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 959
 960         del_timer(&musb_idle_timer);
 961
 962         if (is_dma_capable() && !dma_off) {
 963                 printk(KERN_WARNING "%s %s: dma still active\n",
 964                                 __FILE__, __func__);
 965                 dma_off = 1;
 966         }
 967 }
 968
 969 /*
 970  * Sets up TUSB6010 CPU interface specific signals and registers
 971  * Note: Settings optimized for OMAP24xx
 972  */
 973 static void tusb_setup_cpu_interface(struct musb *musb)
 974 {
 975         void __iomem    *tbase = musb->ctrl_base;
 976
 977         /*
 978          * Disable GPIO[5:0] pullups (used as output DMA requests)
 979          * Don't disable GPIO[7:6] as they are needed for wake-up.
 980          */
 981         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
 982
 983         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
 984         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
 985
 986         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
 987         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
 988
 989         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
 990          * de-assertion time 2 system clocks p 62 */
 991         musb_writel(tbase, TUSB_DMA_REQ_CONF,
 992                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
 993                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
 994                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
 995
 996         /* Set 0 wait count for synchronous burst access */
 997         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
 998 }
 999
1000 static int tusb_musb_start(struct musb *musb)
1001 {
1002         void __iomem    *tbase = musb->ctrl_base;
1003         int             ret = 0;
1004         unsigned long   flags;
1005         u32             reg;
1006
1007         if (musb->board_set_power)
1008                 ret = musb->board_set_power(1);
1009         if (ret != 0) {
1010                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1011                 return ret;
1012         }
1013
1014         spin_lock_irqsave(&musb->lock, flags);
1015
1016         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1017                 TUSB_PROD_TEST_RESET_VAL) {
1018                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1019                 goto err;
1020         }
1021
1022         ret = tusb_print_revision(musb);
1023         if (ret < 2) {
1024                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1025                                 ret);
1026                 goto err;
1027         }
1028
1029         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1030          * NOR FLASH interface is used */
1031         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1032
1033         /* Select PHY free running 60MHz as a system clock */
1034         tusb_set_clock_source(musb, 1);
1035
1036         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1037          * power saving, enable VBus detect and session end comparators,
1038          * enable IDpullup, enable VBus charging */
1039         musb_writel(tbase, TUSB_PRCM_MNGMT,
1040                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1041                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1042                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1043                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1044                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1045         tusb_setup_cpu_interface(musb);
1046
1047         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1048         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1049         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1050         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1051
1052         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1053         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1054         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1055
1056         spin_unlock_irqrestore(&musb->lock, flags);
1057
1058         return 0;
1059
1060 err:
1061         spin_unlock_irqrestore(&musb->lock, flags);
1062
1063         if (musb->board_set_power)
1064                 musb->board_set_power(0);
1065
1066         return -ENODEV;
1067 }
1068
1069 static int tusb_musb_init(struct musb *musb)
1070 {
1071         struct platform_device  *pdev;
1072         struct resource         *mem;
1073         void __iomem            *sync = NULL;
1074         int                     ret;
1075
1076         usb_nop_xceiv_register();
1077         musb->xceiv = otg_get_transceiver();
1078         if (!musb->xceiv)
1079                 return -ENODEV;
1080
1081         pdev = to_platform_device(musb->controller);
1082
1083         /* dma address for async dma */
1084         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085         musb->async = mem->start;
1086
1087         /* dma address for sync dma */
1088         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1089         if (!mem) {
1090                 pr_debug("no sync dma resource?\n");
1091                 ret = -ENODEV;
1092                 goto done;
1093         }
1094         musb->sync = mem->start;
1095
1096         sync = ioremap(mem->start, resource_size(mem));
1097         if (!sync) {
1098                 pr_debug("ioremap for sync failed\n");
1099                 ret = -ENOMEM;
1100                 goto done;
1101         }
1102         musb->sync_va = sync;
1103
1104         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1105          * FIFOs at 0x600, TUSB at 0x800
1106          */
1107         musb->mregs += TUSB_BASE_OFFSET;
1108
1109         ret = tusb_musb_start(musb);
1110         if (ret) {
1111                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1112                                 ret);
1113                 goto done;
1114         }
1115         musb->isr = tusb_musb_interrupt;
1116
1117         if (is_peripheral_enabled(musb)) {
1118                 musb->xceiv->set_power = tusb_draw_power;
1119                 the_musb = musb;
1120         }
1121
1122         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1123
1124 done:
1125         if (ret < 0) {
1126                 if (sync)
1127                         iounmap(sync);
1128
1129                 otg_put_transceiver(musb->xceiv);
1130                 usb_nop_xceiv_unregister();
1131         }
1132         return ret;
1133 }
1134
1135 static int tusb_musb_exit(struct musb *musb)
1136 {
1137         del_timer_sync(&musb_idle_timer);
1138         the_musb = NULL;
1139
1140         if (musb->board_set_power)
1141                 musb->board_set_power(0);
1142
1143         iounmap(musb->sync_va);
1144
1145         otg_put_transceiver(musb->xceiv);
1146         usb_nop_xceiv_unregister();
1147         return 0;
1148 }
1149
1150 static const struct musb_platform_ops tusb_ops = {
1151         .init           = tusb_musb_init,
1152         .exit           = tusb_musb_exit,
1153
1154         .enable         = tusb_musb_enable,
1155         .disable        = tusb_musb_disable,
1156
1157         .set_mode       = tusb_musb_set_mode,
1158         .try_idle       = tusb_musb_try_idle,
1159
1160         .vbus_status    = tusb_musb_vbus_status,
1161         .set_vbus       = tusb_musb_set_vbus,
1162 };
1163
1164 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1165
1166 static int __init tusb_probe(struct platform_device *pdev)
1167 {
1168         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
1169         struct platform_device          *musb;
1170         struct tusb6010_glue            *glue;
1171
1172         int                             ret = -ENOMEM;
1173
1174         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1175         if (!glue) {
1176                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1177                 goto err0;
1178         }
1179
1180         musb = platform_device_alloc("musb-hdrc", -1);
1181         if (!musb) {
1182                 dev_err(&pdev->dev, "failed to allocate musb device\n");
1183                 goto err1;
1184         }
1185
1186         musb->dev.parent                = &pdev->dev;
1187         musb->dev.dma_mask              = &tusb_dmamask;
1188         musb->dev.coherent_dma_mask     = tusb_dmamask;
1189
1190         glue->dev                       = &pdev->dev;
1191         glue->musb                      = musb;
1192
1193         pdata->platform_ops             = &tusb_ops;
1194
1195         platform_set_drvdata(pdev, glue);
1196
1197         ret = platform_device_add_resources(musb, pdev->resource,
1198                         pdev->num_resources);
1199         if (ret) {
1200                 dev_err(&pdev->dev, "failed to add resources\n");
1201                 goto err2;
1202         }
1203
1204         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1205         if (ret) {
1206                 dev_err(&pdev->dev, "failed to add platform_data\n");
1207                 goto err2;
1208         }
1209
1210         ret = platform_device_add(musb);
1211         if (ret) {
1212                 dev_err(&pdev->dev, "failed to register musb device\n");
1213                 goto err1;
1214         }
1215
1216         return 0;
1217
1218 err2:
1219         platform_device_put(musb);
1220
1221 err1:
1222         kfree(glue);
1223
1224 err0:
1225         return ret;
1226 }
1227
1228 static int __exit tusb_remove(struct platform_device *pdev)
1229 {
1230         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1231
1232         platform_device_del(glue->musb);
1233         platform_device_put(glue->musb);
1234         kfree(glue);
1235
1236         return 0;
1237 }
1238
1239 static struct platform_driver tusb_driver = {
1240         .remove         = __exit_p(tusb_remove),
1241         .driver         = {
1242                 .name   = "musb-tusb",
1243         },
1244 };
1245
1246 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1247 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1248 MODULE_LICENSE("GPL v2");
1249
1250 static int __init tusb_init(void)
1251 {
1252         return platform_driver_probe(&tusb_driver, tusb_probe);
1253 }
1254 subsys_initcall(tusb_init);
1255
1256 static void __exit tusb_exit(void)
1257 {
1258         platform_driver_unregister(&tusb_driver);
1259 }
1260 module_exit(tusb_exit);