2 * MUSB OTG peripheral driver ep0 handling
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/spinlock.h>
40 #include <linux/init.h>
41 #include <linux/device.h>
42 #include <linux/interrupt.h>
44 #include "musb_core.h"
46 /* ep0 is always musb->endpoints[0].ep_in */
47 #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
50 * locking note: we use only the controller lock, for simpler correctness.
51 * It's always held with IRQs blocked.
53 * It protects the ep0 request queue as well as ep0_state, not just the
54 * controller and indexed registers. And that lock stays held unless it
55 * needs to be dropped to allow reentering this driver ... like upcalls to
56 * the gadget driver, or adjusting endpoint halt status.
59 static char *decode_ep0stage(u8 stage)
62 case MUSB_EP0_STAGE_IDLE: return "idle";
63 case MUSB_EP0_STAGE_SETUP: return "setup";
64 case MUSB_EP0_STAGE_TX: return "in";
65 case MUSB_EP0_STAGE_RX: return "out";
66 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
67 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
68 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
73 /* handle a standard GET_STATUS request
74 * Context: caller holds controller lock
76 static int service_tx_status_request(
78 const struct usb_ctrlrequest *ctrlrequest)
80 void __iomem *mbase = musb->mregs;
82 u8 result[2], epnum = 0;
83 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
88 case USB_RECIP_DEVICE:
89 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
90 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
92 result[0] |= musb->g.b_hnp_enable
93 << USB_DEVICE_B_HNP_ENABLE;
94 result[0] |= musb->g.a_alt_hnp_support
95 << USB_DEVICE_A_ALT_HNP_SUPPORT;
96 result[0] |= musb->g.a_hnp_support
97 << USB_DEVICE_A_HNP_SUPPORT;
101 case USB_RECIP_INTERFACE:
105 case USB_RECIP_ENDPOINT: {
111 epnum = (u8) ctrlrequest->wIndex;
117 is_in = epnum & USB_DIR_IN;
120 ep = &musb->endpoints[epnum].ep_in;
122 ep = &musb->endpoints[epnum].ep_out;
124 regs = musb->endpoints[epnum].regs;
126 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
131 musb_ep_select(mbase, epnum);
133 tmp = musb_readw(regs, MUSB_TXCSR)
134 & MUSB_TXCSR_P_SENDSTALL;
136 tmp = musb_readw(regs, MUSB_RXCSR)
137 & MUSB_RXCSR_P_SENDSTALL;
138 musb_ep_select(mbase, 0);
140 result[0] = tmp ? 1 : 0;
144 /* class, vendor, etc ... delegate */
149 /* fill up the fifo; caller updates csr0 */
151 u16 len = le16_to_cpu(ctrlrequest->wLength);
155 musb_write_fifo(&musb->endpoints[0], len, result);
162 * handle a control-IN request, the end0 buffer contains the current request
163 * that is supposed to be a standard control request. Assumes the fifo to
164 * be at least 2 bytes long.
166 * @return 0 if the request was NOT HANDLED,
168 * > 0 when the request is processed
170 * Context: caller holds controller lock
173 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
175 int handled = 0; /* not handled */
177 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
178 == USB_TYPE_STANDARD) {
179 switch (ctrlrequest->bRequest) {
180 case USB_REQ_GET_STATUS:
181 handled = service_tx_status_request(musb,
185 /* case USB_REQ_SYNC_FRAME: */
195 * Context: caller holds controller lock
197 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
199 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
203 * Tries to start B-device HNP negotiation if enabled via sysfs
205 static inline void musb_try_b_hnp_enable(struct musb *musb)
207 void __iomem *mbase = musb->mregs;
210 dev_dbg(musb->controller, "HNP: Setting HR\n");
211 devctl = musb_readb(mbase, MUSB_DEVCTL);
212 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
216 * Handle all control requests with no DATA stage, including standard
218 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
219 * always delegated to the gadget driver
220 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
221 * always handled here, except for class/vendor/... features
223 * Context: caller holds controller lock
226 service_zero_data_request(struct musb *musb,
227 struct usb_ctrlrequest *ctrlrequest)
228 __releases(musb->lock)
229 __acquires(musb->lock)
231 int handled = -EINVAL;
232 void __iomem *mbase = musb->mregs;
233 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
235 /* the gadget driver handles everything except what we MUST handle */
236 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
237 == USB_TYPE_STANDARD) {
238 switch (ctrlrequest->bRequest) {
239 case USB_REQ_SET_ADDRESS:
240 /* change it after the status stage */
241 musb->set_address = true;
242 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
246 case USB_REQ_CLEAR_FEATURE:
248 case USB_RECIP_DEVICE:
249 if (ctrlrequest->wValue
250 != USB_DEVICE_REMOTE_WAKEUP)
252 musb->may_wakeup = 0;
255 case USB_RECIP_INTERFACE:
257 case USB_RECIP_ENDPOINT:{
259 ctrlrequest->wIndex & 0x0f;
260 struct musb_ep *musb_ep;
261 struct musb_hw_ep *ep;
262 struct musb_request *request;
267 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
268 ctrlrequest->wValue != USB_ENDPOINT_HALT)
271 ep = musb->endpoints + epnum;
273 is_in = ctrlrequest->wIndex & USB_DIR_IN;
275 musb_ep = &ep->ep_in;
277 musb_ep = &ep->ep_out;
282 /* Ignore request if endpoint is wedged */
286 musb_ep_select(mbase, epnum);
288 csr = musb_readw(regs, MUSB_TXCSR);
289 csr |= MUSB_TXCSR_CLRDATATOG |
290 MUSB_TXCSR_P_WZC_BITS;
291 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
292 MUSB_TXCSR_P_SENTSTALL |
293 MUSB_TXCSR_TXPKTRDY);
294 musb_writew(regs, MUSB_TXCSR, csr);
296 csr = musb_readw(regs, MUSB_RXCSR);
297 csr |= MUSB_RXCSR_CLRDATATOG |
298 MUSB_RXCSR_P_WZC_BITS;
299 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
300 MUSB_RXCSR_P_SENTSTALL);
301 musb_writew(regs, MUSB_RXCSR, csr);
304 /* Maybe start the first request in the queue */
305 request = next_request(musb_ep);
306 if (!musb_ep->busy && request) {
307 dev_dbg(musb->controller, "restarting the request\n");
308 musb_ep_restart(musb, request);
311 /* select ep0 again */
312 musb_ep_select(mbase, 0);
315 /* class, vendor, etc ... delegate */
321 case USB_REQ_SET_FEATURE:
323 case USB_RECIP_DEVICE:
325 switch (ctrlrequest->wValue) {
326 case USB_DEVICE_REMOTE_WAKEUP:
327 musb->may_wakeup = 1;
329 case USB_DEVICE_TEST_MODE:
330 if (musb->g.speed != USB_SPEED_HIGH)
332 if (ctrlrequest->wIndex & 0xff)
335 switch (ctrlrequest->wIndex >> 8) {
337 pr_debug("TEST_J\n");
344 pr_debug("TEST_K\n");
350 pr_debug("TEST_SE0_NAK\n");
356 pr_debug("TEST_PACKET\n");
363 pr_debug("TEST_FORCE_HS\n");
369 pr_debug("TEST_FORCE_FS\n");
374 /* TEST_FIFO_ACCESS */
375 pr_debug("TEST_FIFO_ACCESS\n");
377 MUSB_TEST_FIFO_ACCESS;
380 /* TEST_FORCE_HOST */
381 pr_debug("TEST_FORCE_HOST\n");
383 MUSB_TEST_FORCE_HOST;
389 /* enter test mode after irq */
391 musb->test_mode = true;
393 case USB_DEVICE_B_HNP_ENABLE:
396 musb->g.b_hnp_enable = 1;
397 musb_try_b_hnp_enable(musb);
399 case USB_DEVICE_A_HNP_SUPPORT:
402 musb->g.a_hnp_support = 1;
404 case USB_DEVICE_A_ALT_HNP_SUPPORT:
407 musb->g.a_alt_hnp_support = 1;
409 case USB_DEVICE_DEBUG_MODE:
419 case USB_RECIP_INTERFACE:
422 case USB_RECIP_ENDPOINT:{
424 ctrlrequest->wIndex & 0x0f;
425 struct musb_ep *musb_ep;
426 struct musb_hw_ep *ep;
431 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
432 ctrlrequest->wValue != USB_ENDPOINT_HALT)
435 ep = musb->endpoints + epnum;
437 is_in = ctrlrequest->wIndex & USB_DIR_IN;
439 musb_ep = &ep->ep_in;
441 musb_ep = &ep->ep_out;
445 musb_ep_select(mbase, epnum);
447 csr = musb_readw(regs, MUSB_TXCSR);
448 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
449 csr |= MUSB_TXCSR_FLUSHFIFO;
450 csr |= MUSB_TXCSR_P_SENDSTALL
451 | MUSB_TXCSR_CLRDATATOG
452 | MUSB_TXCSR_P_WZC_BITS;
453 musb_writew(regs, MUSB_TXCSR, csr);
455 csr = musb_readw(regs, MUSB_RXCSR);
456 csr |= MUSB_RXCSR_P_SENDSTALL
457 | MUSB_RXCSR_FLUSHFIFO
458 | MUSB_RXCSR_CLRDATATOG
459 | MUSB_RXCSR_P_WZC_BITS;
460 musb_writew(regs, MUSB_RXCSR, csr);
463 /* select ep0 again */
464 musb_ep_select(mbase, 0);
469 /* class, vendor, etc ... delegate */
475 /* delegate SET_CONFIGURATION, etc */
483 /* we have an ep0out data packet
484 * Context: caller holds controller lock
486 static void ep0_rxstate(struct musb *musb)
488 void __iomem *regs = musb->control_ep->regs;
489 struct musb_request *request;
490 struct usb_request *req;
493 request = next_ep0_request(musb);
494 req = &request->request;
496 /* read packet and ack; or stall because of gadget driver bug:
497 * should have provided the rx buffer before setup() returned.
500 void *buf = req->buf + req->actual;
501 unsigned len = req->length - req->actual;
503 /* read the buffer */
504 count = musb_readb(regs, MUSB_COUNT0);
506 req->status = -EOVERFLOW;
509 musb_read_fifo(&musb->endpoints[0], count, buf);
510 req->actual += count;
511 csr = MUSB_CSR0_P_SVDRXPKTRDY;
512 if (count < 64 || req->actual == req->length) {
513 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
514 csr |= MUSB_CSR0_P_DATAEND;
518 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
521 /* Completion handler may choose to stall, e.g. because the
522 * message just received holds invalid data.
526 musb_g_ep0_giveback(musb, req);
531 musb_ep_select(musb->mregs, 0);
532 musb_writew(regs, MUSB_CSR0, csr);
536 * transmitting to the host (IN), this code might be called from IRQ
537 * and from kernel thread.
539 * Context: caller holds controller lock
541 static void ep0_txstate(struct musb *musb)
543 void __iomem *regs = musb->control_ep->regs;
544 struct musb_request *req = next_ep0_request(musb);
545 struct usb_request *request;
546 u16 csr = MUSB_CSR0_TXPKTRDY;
552 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
556 request = &req->request;
559 fifo_src = (u8 *) request->buf + request->actual;
560 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
561 request->length - request->actual);
562 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
563 request->actual += fifo_count;
565 /* update the flags */
566 if (fifo_count < MUSB_MAX_END0_PACKET
567 || (request->actual == request->length
568 && !request->zero)) {
569 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
570 csr |= MUSB_CSR0_P_DATAEND;
574 /* report completions as soon as the fifo's loaded; there's no
575 * win in waiting till this last packet gets acked. (other than
576 * very precise fault reporting, needed by USB TMC; possible with
577 * this hardware, but not usable from portable gadget drivers.)
581 musb_g_ep0_giveback(musb, request);
587 /* send it out, triggering a "txpktrdy cleared" irq */
588 musb_ep_select(musb->mregs, 0);
589 musb_writew(regs, MUSB_CSR0, csr);
593 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
594 * Fields are left in USB byte-order.
596 * Context: caller holds controller lock.
599 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
601 struct musb_request *r;
602 void __iomem *regs = musb->control_ep->regs;
604 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
606 /* NOTE: earlier 2.6 versions changed setup packets to host
607 * order, but now USB packets always stay in USB byte order.
609 dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
612 le16_to_cpu(req->wValue),
613 le16_to_cpu(req->wIndex),
614 le16_to_cpu(req->wLength));
616 /* clean up any leftover transfers */
617 r = next_ep0_request(musb);
619 musb_g_ep0_giveback(musb, &r->request);
621 /* For zero-data requests we want to delay the STATUS stage to
622 * avoid SETUPEND errors. If we read data (OUT), delay accepting
623 * packets until there's a buffer to store them in.
625 * If we write data, the controller acts happier if we enable
626 * the TX FIFO right away, and give the controller a moment
629 musb->set_address = false;
630 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
631 if (req->wLength == 0) {
632 if (req->bRequestType & USB_DIR_IN)
633 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
634 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
635 } else if (req->bRequestType & USB_DIR_IN) {
636 musb->ep0_state = MUSB_EP0_STAGE_TX;
637 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
638 while ((musb_readw(regs, MUSB_CSR0)
639 & MUSB_CSR0_RXPKTRDY) != 0)
643 musb->ep0_state = MUSB_EP0_STAGE_RX;
647 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
648 __releases(musb->lock)
649 __acquires(musb->lock)
652 if (!musb->gadget_driver)
654 spin_unlock(&musb->lock);
655 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
656 spin_lock(&musb->lock);
661 * Handle peripheral ep0 interrupt
663 * Context: irq handler; we won't re-enter the driver that way.
665 irqreturn_t musb_g_ep0_irq(struct musb *musb)
669 void __iomem *mbase = musb->mregs;
670 void __iomem *regs = musb->endpoints[0].regs;
671 irqreturn_t retval = IRQ_NONE;
673 musb_ep_select(mbase, 0); /* select ep0 */
674 csr = musb_readw(regs, MUSB_CSR0);
675 len = musb_readb(regs, MUSB_COUNT0);
677 dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
679 musb_readb(mbase, MUSB_FADDR),
680 decode_ep0stage(musb->ep0_state));
682 /* I sent a stall.. need to acknowledge it now.. */
683 if (csr & MUSB_CSR0_P_SENTSTALL) {
684 musb_writew(regs, MUSB_CSR0,
685 csr & ~MUSB_CSR0_P_SENTSTALL);
686 retval = IRQ_HANDLED;
687 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
688 csr = musb_readw(regs, MUSB_CSR0);
691 /* request ended "early" */
692 if (csr & MUSB_CSR0_P_SETUPEND) {
693 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
694 retval = IRQ_HANDLED;
695 /* Transition into the early status phase */
696 switch (musb->ep0_state) {
697 case MUSB_EP0_STAGE_TX:
698 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
700 case MUSB_EP0_STAGE_RX:
701 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
704 ERR("SetupEnd came in a wrong ep0stage %s\n",
705 decode_ep0stage(musb->ep0_state));
707 csr = musb_readw(regs, MUSB_CSR0);
708 /* NOTE: request may need completion */
711 /* docs from Mentor only describe tx, rx, and idle/setup states.
712 * we need to handle nuances around status stages, and also the
713 * case where status and setup stages come back-to-back ...
715 switch (musb->ep0_state) {
717 case MUSB_EP0_STAGE_TX:
718 /* irq on clearing txpktrdy */
719 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
721 retval = IRQ_HANDLED;
725 case MUSB_EP0_STAGE_RX:
726 /* irq on set rxpktrdy */
727 if (csr & MUSB_CSR0_RXPKTRDY) {
729 retval = IRQ_HANDLED;
733 case MUSB_EP0_STAGE_STATUSIN:
734 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
736 /* update address (if needed) only @ the end of the
737 * status phase per usb spec, which also guarantees
738 * we get 10 msec to receive this irq... until this
739 * is done we won't see the next packet.
741 if (musb->set_address) {
742 musb->set_address = false;
743 musb_writeb(mbase, MUSB_FADDR, musb->address);
746 /* enter test mode if needed (exit by reset) */
747 else if (musb->test_mode) {
748 dev_dbg(musb->controller, "entering TESTMODE\n");
750 if (MUSB_TEST_PACKET == musb->test_mode_nr)
751 musb_load_testpacket(musb);
753 musb_writeb(mbase, MUSB_TESTMODE,
758 case MUSB_EP0_STAGE_STATUSOUT:
759 /* end of sequence #1: write to host (TX state) */
761 struct musb_request *req;
763 req = next_ep0_request(musb);
765 musb_g_ep0_giveback(musb, &req->request);
769 * In case when several interrupts can get coalesced,
770 * check to see if we've already received a SETUP packet...
772 if (csr & MUSB_CSR0_RXPKTRDY)
775 retval = IRQ_HANDLED;
776 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
779 case MUSB_EP0_STAGE_IDLE:
781 * This state is typically (but not always) indiscernible
782 * from the status states since the corresponding interrupts
783 * tend to happen within too little period of time (with only
784 * a zero-length packet in between) and so get coalesced...
786 retval = IRQ_HANDLED;
787 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
790 case MUSB_EP0_STAGE_SETUP:
792 if (csr & MUSB_CSR0_RXPKTRDY) {
793 struct usb_ctrlrequest setup;
797 ERR("SETUP packet len %d != 8 ?\n", len);
800 musb_read_setup(musb, &setup);
801 retval = IRQ_HANDLED;
803 /* sometimes the RESET won't be reported */
804 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
807 printk(KERN_NOTICE "%s: peripheral reset "
810 power = musb_readb(mbase, MUSB_POWER);
811 musb->g.speed = (power & MUSB_POWER_HSMODE)
812 ? USB_SPEED_HIGH : USB_SPEED_FULL;
816 switch (musb->ep0_state) {
818 /* sequence #3 (no data stage), includes requests
819 * we can't forward (notably SET_ADDRESS and the
820 * device/endpoint feature set/clear operations)
821 * plus SET_CONFIGURATION and others we must
823 case MUSB_EP0_STAGE_ACKWAIT:
824 handled = service_zero_data_request(
828 * We're expecting no data in any case, so
829 * always set the DATAEND bit -- doing this
830 * here helps avoid SetupEnd interrupt coming
831 * in the idle stage when we're stalling...
833 musb->ackpend |= MUSB_CSR0_P_DATAEND;
835 /* status stage might be immediate */
838 MUSB_EP0_STAGE_STATUSIN;
841 /* sequence #1 (IN to host), includes GET_STATUS
842 * requests that we can't forward, GET_DESCRIPTOR
843 * and others that we must
845 case MUSB_EP0_STAGE_TX:
846 handled = service_in_request(musb, &setup);
848 musb->ackpend = MUSB_CSR0_TXPKTRDY
849 | MUSB_CSR0_P_DATAEND;
851 MUSB_EP0_STAGE_STATUSOUT;
855 /* sequence #2 (OUT from host), always forward */
856 default: /* MUSB_EP0_STAGE_RX */
860 dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
862 decode_ep0stage(musb->ep0_state));
864 /* unless we need to delegate this to the gadget
865 * driver, we know how to wrap this up: csr0 has
866 * not yet been written.
870 else if (handled > 0)
873 handled = forward_to_driver(musb, &setup);
875 musb_ep_select(mbase, 0);
877 dev_dbg(musb->controller, "stall (%d)\n", handled);
878 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
879 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
881 musb_writew(regs, MUSB_CSR0,
888 case MUSB_EP0_STAGE_ACKWAIT:
889 /* This should not happen. But happens with tusb6010 with
890 * g_file_storage and high speed. Do nothing.
892 retval = IRQ_HANDLED;
898 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
899 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
908 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
914 static int musb_g_ep0_disable(struct usb_ep *e)
921 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
924 struct musb_request *req;
927 unsigned long lockflags;
935 regs = musb->control_ep->regs;
937 req = to_musb_request(r);
939 req->request.actual = 0;
940 req->request.status = -EINPROGRESS;
943 spin_lock_irqsave(&musb->lock, lockflags);
945 if (!list_empty(&ep->req_list)) {
950 switch (musb->ep0_state) {
951 case MUSB_EP0_STAGE_RX: /* control-OUT data */
952 case MUSB_EP0_STAGE_TX: /* control-IN data */
953 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
957 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
963 /* add request to the list */
964 list_add_tail(&req->list, &ep->req_list);
966 dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
967 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
968 req->request.length);
970 musb_ep_select(musb->mregs, 0);
972 /* sequence #1, IN ... start writing the data */
973 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
976 /* sequence #3, no-data ... issue IN status */
977 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
978 if (req->request.length)
981 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
982 musb_writew(regs, MUSB_CSR0,
983 musb->ackpend | MUSB_CSR0_P_DATAEND);
985 musb_g_ep0_giveback(ep->musb, r);
988 /* else for sequence #2 (OUT), caller provides a buffer
989 * before the next packet arrives. deferred responses
990 * (after SETUP is acked) are racey.
992 } else if (musb->ackpend) {
993 musb_writew(regs, MUSB_CSR0, musb->ackpend);
998 spin_unlock_irqrestore(&musb->lock, lockflags);
1002 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
1004 /* we just won't support this */
1008 static int musb_g_ep0_halt(struct usb_ep *e, int value)
1012 void __iomem *base, *regs;
1013 unsigned long flags;
1023 regs = musb->control_ep->regs;
1026 spin_lock_irqsave(&musb->lock, flags);
1028 if (!list_empty(&ep->req_list)) {
1033 musb_ep_select(base, 0);
1034 csr = musb->ackpend;
1036 switch (musb->ep0_state) {
1038 /* Stalls are usually issued after parsing SETUP packet, either
1039 * directly in irq context from setup() or else later.
1041 case MUSB_EP0_STAGE_TX: /* control-IN data */
1042 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
1043 case MUSB_EP0_STAGE_RX: /* control-OUT data */
1044 csr = musb_readw(regs, MUSB_CSR0);
1047 /* It's also OK to issue stalls during callbacks when a non-empty
1048 * DATA stage buffer has been read (or even written).
1050 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
1051 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
1053 csr |= MUSB_CSR0_P_SENDSTALL;
1054 musb_writew(regs, MUSB_CSR0, csr);
1055 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1059 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1064 spin_unlock_irqrestore(&musb->lock, flags);
1068 const struct usb_ep_ops musb_g_ep0_ops = {
1069 .enable = musb_g_ep0_enable,
1070 .disable = musb_g_ep0_disable,
1071 .alloc_request = musb_alloc_request,
1072 .free_request = musb_free_request,
1073 .queue = musb_g_ep0_queue,
1074 .dequeue = musb_g_ep0_dequeue,
1075 .set_halt = musb_g_ep0_halt,