2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
79 * - ISO not tested ... might work, but only weakly isochronous
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
91 /* ----------------------------------------------------------------------- */
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
96 /* Maps the buffer to dma */
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
104 request->map_state = UN_MAPPED;
106 if (!is_dma_capable() || !musb_ep->dma)
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
123 request->request.buf,
124 request->request.length,
128 request->map_state = MUSB_MAPPED;
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
136 request->map_state = PRE_MAPPED;
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
144 if (!is_buffer_mapped(request))
147 if (request->request.dma == DMA_ADDR_INVALID) {
148 dev_vdbg(musb->controller,
149 "not unmapping a never mapped buffer\n");
152 if (request->map_state == MUSB_MAPPED) {
153 dma_unmap_single(musb->controller,
154 request->request.dma,
155 request->request.length,
159 request->request.dma = DMA_ADDR_INVALID;
160 } else { /* PRE_MAPPED */
161 dma_sync_single_for_cpu(musb->controller,
162 request->request.dma,
163 request->request.length,
168 request->map_state = UN_MAPPED;
172 * Immediately complete a request.
174 * @param request the request to complete
175 * @param status the status to complete the request with
176 * Context: controller locked, IRQs blocked.
178 void musb_g_giveback(
180 struct usb_request *request,
182 __releases(ep->musb->lock)
183 __acquires(ep->musb->lock)
185 struct musb_request *req;
189 req = to_musb_request(request);
191 list_del(&req->list);
192 if (req->request.status == -EINPROGRESS)
193 req->request.status = status;
197 spin_unlock(&musb->lock);
198 unmap_dma_buffer(req, musb);
199 if (request->status == 0)
200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
201 ep->end_point.name, request,
202 req->request.actual, req->request.length);
204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
205 ep->end_point.name, request,
206 req->request.actual, req->request.length,
208 req->request.complete(&req->ep->end_point, &req->request);
209 spin_lock(&musb->lock);
213 /* ----------------------------------------------------------------------- */
216 * Abort requests queued to an endpoint using the status. Synchronous.
217 * caller locked controller and blocked irqs, and selected this ep.
219 static void nuke(struct musb_ep *ep, const int status)
221 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
248 value = c->channel_abort(ep->dma);
249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
251 c->channel_release(ep->dma);
255 while (!list_empty(&ep->req_list)) {
256 req = list_first_entry(&ep->req_list, struct musb_request, list);
257 musb_g_giveback(ep, &req->request, status);
261 /* ----------------------------------------------------------------------- */
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
275 return ep->packet_sz;
279 #ifdef CONFIG_USB_INVENTRA_DMA
281 /* Peripheral tx (IN) using Mentor DMA works as follows:
282 Only mode 0 is used for transfers <= wPktSize,
283 mode 1 is used for larger transfers,
285 One of the following happens:
286 - Host sends IN token which causes an endpoint interrupt
288 -> if DMA is currently busy, exit.
289 -> if queue is non-empty, txstate().
291 - Request is queued by the gadget driver.
292 -> if queue was previously empty, txstate()
297 | (data is transferred to the FIFO, then sent out when
298 | IN token(s) are recd from Host.
299 | -> DMA interrupt on completion
301 | -> stop DMA, ~DMAENAB,
302 | -> set TxPktRdy for last short pkt or zlp
303 | -> Complete Request
304 | -> Continue next request (call txstate)
305 |___________________________________|
307 * Non-Mentor DMA engines can of course work differently, such as by
308 * upleveling from irq-per-packet to irq-per-buffer.
314 * An endpoint is transmitting data. This can be called either from
315 * the IRQ routine or from ep.queue() to kickstart a request on an
318 * Context: controller locked, IRQs blocked, endpoint selected
320 static void txstate(struct musb *musb, struct musb_request *req)
322 u8 epnum = req->epnum;
323 struct musb_ep *musb_ep;
324 void __iomem *epio = musb->endpoints[epnum].regs;
325 struct usb_request *request;
326 u16 fifo_count = 0, csr;
331 /* Check if EP is disabled */
332 if (!musb_ep->desc) {
333 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
334 musb_ep->end_point.name);
338 /* we shouldn't get here while DMA is active ... but we do ... */
339 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
340 dev_dbg(musb->controller, "dma pending...\n");
344 /* read TXCSR before */
345 csr = musb_readw(epio, MUSB_TXCSR);
347 request = &req->request;
348 fifo_count = min(max_ep_writesize(musb, musb_ep),
349 (int)(request->length - request->actual));
351 if (csr & MUSB_TXCSR_TXPKTRDY) {
352 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
353 musb_ep->end_point.name, csr);
357 if (csr & MUSB_TXCSR_P_SENDSTALL) {
358 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
359 musb_ep->end_point.name, csr);
363 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
364 epnum, musb_ep->packet_sz, fifo_count,
367 #ifndef CONFIG_MUSB_PIO_ONLY
368 if (is_buffer_mapped(req)) {
369 struct dma_controller *c = musb->dma_controller;
372 /* setup DMA, then program endpoint CSR */
373 request_size = min_t(size_t, request->length - request->actual,
374 musb_ep->dma->max_len);
376 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
378 /* MUSB_TXCSR_P_ISO is still set correctly */
380 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
382 if (request_size < musb_ep->packet_sz)
383 musb_ep->dma->desired_mode = 0;
385 musb_ep->dma->desired_mode = 1;
387 use_dma = use_dma && c->channel_program(
388 musb_ep->dma, musb_ep->packet_sz,
389 musb_ep->dma->desired_mode,
390 request->dma + request->actual, request_size);
392 if (musb_ep->dma->desired_mode == 0) {
394 * We must not clear the DMAMODE bit
395 * before the DMAENAB bit -- and the
396 * latter doesn't always get cleared
397 * before we get here...
399 csr &= ~(MUSB_TXCSR_AUTOSET
400 | MUSB_TXCSR_DMAENAB);
401 musb_writew(epio, MUSB_TXCSR, csr
402 | MUSB_TXCSR_P_WZC_BITS);
403 csr &= ~MUSB_TXCSR_DMAMODE;
404 csr |= (MUSB_TXCSR_DMAENAB |
406 /* against programming guide */
408 csr |= (MUSB_TXCSR_DMAENAB
412 * Enable Autoset according to table
414 * bulk_split hb_mult Autoset_Enable
416 * 0 >0 No(High BW ISO)
420 if (!musb_ep->hb_mult ||
424 csr |= MUSB_TXCSR_AUTOSET;
426 csr &= ~MUSB_TXCSR_P_UNDERRUN;
428 musb_writew(epio, MUSB_TXCSR, csr);
432 #elif defined(CONFIG_USB_TI_CPPI_DMA)
433 /* program endpoint CSR first, then setup DMA */
434 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
435 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
437 musb_writew(epio, MUSB_TXCSR,
438 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
441 /* ensure writebuffer is empty */
442 csr = musb_readw(epio, MUSB_TXCSR);
444 /* NOTE host side sets DMAENAB later than this; both are
445 * OK since the transfer dma glue (between CPPI and Mentor
446 * fifos) just tells CPPI it could start. Data only moves
447 * to the USB TX fifo when both fifos are ready.
450 /* "mode" is irrelevant here; handle terminating ZLPs like
451 * PIO does, since the hardware RNDIS mode seems unreliable
452 * except for the last-packet-is-already-short case.
454 use_dma = use_dma && c->channel_program(
455 musb_ep->dma, musb_ep->packet_sz,
457 request->dma + request->actual,
460 c->channel_release(musb_ep->dma);
462 csr &= ~MUSB_TXCSR_DMAENAB;
463 musb_writew(epio, MUSB_TXCSR, csr);
464 /* invariant: prequest->buf is non-null */
466 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
467 use_dma = use_dma && c->channel_program(
468 musb_ep->dma, musb_ep->packet_sz,
470 request->dma + request->actual,
478 * Unmap the dma buffer back to cpu if dma channel
481 unmap_dma_buffer(req, musb);
483 musb_write_fifo(musb_ep->hw_ep, fifo_count,
484 (u8 *) (request->buf + request->actual));
485 request->actual += fifo_count;
486 csr |= MUSB_TXCSR_TXPKTRDY;
487 csr &= ~MUSB_TXCSR_P_UNDERRUN;
488 musb_writew(epio, MUSB_TXCSR, csr);
491 /* host may already have the data when this message shows... */
492 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
493 musb_ep->end_point.name, use_dma ? "dma" : "pio",
494 request->actual, request->length,
495 musb_readw(epio, MUSB_TXCSR),
497 musb_readw(epio, MUSB_TXMAXP));
501 * FIFO state update (e.g. data ready).
502 * Called from IRQ, with controller locked.
504 void musb_g_tx(struct musb *musb, u8 epnum)
507 struct musb_request *req;
508 struct usb_request *request;
509 u8 __iomem *mbase = musb->mregs;
510 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
511 void __iomem *epio = musb->endpoints[epnum].regs;
512 struct dma_channel *dma;
514 musb_ep_select(mbase, epnum);
515 req = next_request(musb_ep);
516 request = &req->request;
518 csr = musb_readw(epio, MUSB_TXCSR);
519 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
521 dma = is_dma_capable() ? musb_ep->dma : NULL;
524 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
525 * probably rates reporting as a host error.
527 if (csr & MUSB_TXCSR_P_SENTSTALL) {
528 csr |= MUSB_TXCSR_P_WZC_BITS;
529 csr &= ~MUSB_TXCSR_P_SENTSTALL;
530 musb_writew(epio, MUSB_TXCSR, csr);
534 if (csr & MUSB_TXCSR_P_UNDERRUN) {
535 /* We NAKed, no big deal... little reason to care. */
536 csr |= MUSB_TXCSR_P_WZC_BITS;
537 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
538 musb_writew(epio, MUSB_TXCSR, csr);
539 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
543 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
545 * SHOULD NOT HAPPEN... has with CPPI though, after
546 * changing SENDSTALL (and other cases); harmless?
548 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
555 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
557 csr |= MUSB_TXCSR_P_WZC_BITS;
558 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
559 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
560 musb_writew(epio, MUSB_TXCSR, csr);
561 /* Ensure writebuffer is empty. */
562 csr = musb_readw(epio, MUSB_TXCSR);
563 request->actual += musb_ep->dma->actual_len;
564 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
565 epnum, csr, musb_ep->dma->actual_len, request);
569 * First, maybe a terminating short packet. Some DMA
570 * engines might handle this by themselves.
572 if ((request->zero && request->length
573 && (request->length % musb_ep->packet_sz == 0)
574 && (request->actual == request->length))
575 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
576 || (is_dma && (!dma->desired_mode ||
578 (musb_ep->packet_sz - 1))))
582 * On DMA completion, FIFO may not be
585 if (csr & MUSB_TXCSR_TXPKTRDY)
588 dev_dbg(musb->controller, "sending zero pkt\n");
589 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
590 | MUSB_TXCSR_TXPKTRDY);
594 if (request->actual == request->length) {
595 musb_g_giveback(musb_ep, request, 0);
597 * In the giveback function the MUSB lock is
598 * released and acquired after sometime. During
599 * this time period the INDEX register could get
600 * changed by the gadget_queue function especially
601 * on SMP systems. Reselect the INDEX to be sure
602 * we are reading/modifying the right registers
604 musb_ep_select(mbase, epnum);
605 req = musb_ep->desc ? next_request(musb_ep) : NULL;
607 dev_dbg(musb->controller, "%s idle now\n",
608 musb_ep->end_point.name);
617 /* ------------------------------------------------------------ */
619 #ifdef CONFIG_USB_INVENTRA_DMA
621 /* Peripheral rx (OUT) using Mentor DMA works as follows:
622 - Only mode 0 is used.
624 - Request is queued by the gadget class driver.
625 -> if queue was previously empty, rxstate()
627 - Host sends OUT token which causes an endpoint interrupt
629 | -> if request queued, call rxstate
631 | | -> DMA interrupt on completion
635 | | -> if data recd = max expected
636 | | by the request, or host
637 | | sent a short packet,
638 | | complete the request,
639 | | and start the next one.
640 | |_____________________________________|
641 | else just wait for the host
642 | to send the next OUT token.
643 |__________________________________________________|
645 * Non-Mentor DMA engines can of course work differently.
651 * Context: controller locked, IRQs blocked, endpoint selected
653 static void rxstate(struct musb *musb, struct musb_request *req)
655 const u8 epnum = req->epnum;
656 struct usb_request *request = &req->request;
657 struct musb_ep *musb_ep;
658 void __iomem *epio = musb->endpoints[epnum].regs;
661 u16 csr = musb_readw(epio, MUSB_RXCSR);
662 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
665 if (hw_ep->is_shared_fifo)
666 musb_ep = &hw_ep->ep_in;
668 musb_ep = &hw_ep->ep_out;
670 fifo_count = musb_ep->packet_sz;
672 /* Check if EP is disabled */
673 if (!musb_ep->desc) {
674 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
675 musb_ep->end_point.name);
679 /* We shouldn't get here while DMA is active, but we do... */
680 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
681 dev_dbg(musb->controller, "DMA pending...\n");
685 if (csr & MUSB_RXCSR_P_SENDSTALL) {
686 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
687 musb_ep->end_point.name, csr);
691 if (is_cppi_enabled() && is_buffer_mapped(req)) {
692 struct dma_controller *c = musb->dma_controller;
693 struct dma_channel *channel = musb_ep->dma;
695 /* NOTE: CPPI won't actually stop advancing the DMA
696 * queue after short packet transfers, so this is almost
697 * always going to run as IRQ-per-packet DMA so that
698 * faults will be handled correctly.
700 if (c->channel_program(channel,
702 !request->short_not_ok,
703 request->dma + request->actual,
704 request->length - request->actual)) {
706 /* make sure that if an rxpkt arrived after the irq,
707 * the cppi engine will be ready to take it as soon
710 csr &= ~(MUSB_RXCSR_AUTOCLEAR
711 | MUSB_RXCSR_DMAMODE);
712 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
713 musb_writew(epio, MUSB_RXCSR, csr);
718 if (csr & MUSB_RXCSR_RXPKTRDY) {
719 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
722 * Enable Mode 1 on RX transfers only when short_not_ok flag
723 * is set. Currently short_not_ok flag is set only from
724 * file_storage and f_mass_storage drivers
727 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
732 if (request->actual < request->length) {
733 #ifdef CONFIG_USB_INVENTRA_DMA
734 if (is_buffer_mapped(req)) {
735 struct dma_controller *c;
736 struct dma_channel *channel;
740 c = musb->dma_controller;
741 channel = musb_ep->dma;
743 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
744 * mode 0 only. So we do not get endpoint interrupts due to DMA
745 * completion. We only get interrupts from DMA controller.
747 * We could operate in DMA mode 1 if we knew the size of the tranfer
748 * in advance. For mass storage class, request->length = what the host
749 * sends, so that'd work. But for pretty much everything else,
750 * request->length is routinely more than what the host sends. For
751 * most these gadgets, end of is signified either by a short packet,
752 * or filling the last byte of the buffer. (Sending extra data in
753 * that last pckate should trigger an overflow fault.) But in mode 1,
754 * we don't get DMA completion interrupt for short packets.
756 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
757 * to get endpoint interrupt on every DMA req, but that didn't seem
760 * REVISIT an updated g_file_storage can set req->short_not_ok, which
761 * then becomes usable as a runtime "use mode 1" hint...
764 /* Experimental: Mode1 works with mass storage use cases */
766 csr |= MUSB_RXCSR_AUTOCLEAR;
767 musb_writew(epio, MUSB_RXCSR, csr);
768 csr |= MUSB_RXCSR_DMAENAB;
769 musb_writew(epio, MUSB_RXCSR, csr);
772 * this special sequence (enabling and then
773 * disabling MUSB_RXCSR_DMAMODE) is required
774 * to get DMAReq to activate
776 musb_writew(epio, MUSB_RXCSR,
777 csr | MUSB_RXCSR_DMAMODE);
778 musb_writew(epio, MUSB_RXCSR, csr);
780 transfer_size = min(request->length - request->actual,
782 musb_ep->dma->desired_mode = 1;
785 if (!musb_ep->hb_mult &&
786 musb_ep->hw_ep->rx_double_buffered)
787 csr |= MUSB_RXCSR_AUTOCLEAR;
788 csr |= MUSB_RXCSR_DMAENAB;
789 musb_writew(epio, MUSB_RXCSR, csr);
791 transfer_size = min(request->length - request->actual,
792 (unsigned)fifo_count);
793 musb_ep->dma->desired_mode = 0;
796 use_dma = c->channel_program(
799 channel->desired_mode,
807 #elif defined(CONFIG_USB_UX500_DMA)
808 if ((is_buffer_mapped(req)) &&
809 (request->actual < request->length)) {
811 struct dma_controller *c;
812 struct dma_channel *channel;
813 int transfer_size = 0;
815 c = musb->dma_controller;
816 channel = musb_ep->dma;
818 /* In case first packet is short */
819 if (fifo_count < musb_ep->packet_sz)
820 transfer_size = fifo_count;
821 else if (request->short_not_ok)
822 transfer_size = min(request->length -
826 transfer_size = min(request->length -
828 (unsigned)fifo_count);
830 csr &= ~MUSB_RXCSR_DMAMODE;
831 csr |= (MUSB_RXCSR_DMAENAB |
832 MUSB_RXCSR_AUTOCLEAR);
834 musb_writew(epio, MUSB_RXCSR, csr);
836 if (transfer_size <= musb_ep->packet_sz) {
837 musb_ep->dma->desired_mode = 0;
839 musb_ep->dma->desired_mode = 1;
840 /* Mode must be set after DMAENAB */
841 csr |= MUSB_RXCSR_DMAMODE;
842 musb_writew(epio, MUSB_RXCSR, csr);
845 if (c->channel_program(channel,
847 channel->desired_mode,
854 #endif /* Mentor's DMA */
856 len = request->length - request->actual;
857 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
858 musb_ep->end_point.name,
862 fifo_count = min_t(unsigned, len, fifo_count);
864 #ifdef CONFIG_USB_TUSB_OMAP_DMA
865 if (tusb_dma_omap() && is_buffer_mapped(req)) {
866 struct dma_controller *c = musb->dma_controller;
867 struct dma_channel *channel = musb_ep->dma;
868 u32 dma_addr = request->dma + request->actual;
871 ret = c->channel_program(channel,
873 channel->desired_mode,
881 * Unmap the dma buffer back to cpu if dma channel
882 * programming fails. This buffer is mapped if the
883 * channel allocation is successful
885 if (is_buffer_mapped(req)) {
886 unmap_dma_buffer(req, musb);
889 * Clear DMAENAB and AUTOCLEAR for the
892 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
893 musb_writew(epio, MUSB_RXCSR, csr);
896 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
897 (request->buf + request->actual));
898 request->actual += fifo_count;
900 /* REVISIT if we left anything in the fifo, flush
901 * it and report -EOVERFLOW
905 csr |= MUSB_RXCSR_P_WZC_BITS;
906 csr &= ~MUSB_RXCSR_RXPKTRDY;
907 musb_writew(epio, MUSB_RXCSR, csr);
911 /* reach the end or short packet detected */
912 if (request->actual == request->length ||
913 fifo_count < musb_ep->packet_sz)
914 musb_g_giveback(musb_ep, request, 0);
918 * Data ready for a request; called from IRQ
920 void musb_g_rx(struct musb *musb, u8 epnum)
923 struct musb_request *req;
924 struct usb_request *request;
925 void __iomem *mbase = musb->mregs;
926 struct musb_ep *musb_ep;
927 void __iomem *epio = musb->endpoints[epnum].regs;
928 struct dma_channel *dma;
929 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
931 if (hw_ep->is_shared_fifo)
932 musb_ep = &hw_ep->ep_in;
934 musb_ep = &hw_ep->ep_out;
936 musb_ep_select(mbase, epnum);
938 req = next_request(musb_ep);
942 request = &req->request;
944 csr = musb_readw(epio, MUSB_RXCSR);
945 dma = is_dma_capable() ? musb_ep->dma : NULL;
947 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
948 csr, dma ? " (dma)" : "", request);
950 if (csr & MUSB_RXCSR_P_SENTSTALL) {
951 csr |= MUSB_RXCSR_P_WZC_BITS;
952 csr &= ~MUSB_RXCSR_P_SENTSTALL;
953 musb_writew(epio, MUSB_RXCSR, csr);
957 if (csr & MUSB_RXCSR_P_OVERRUN) {
958 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
959 csr &= ~MUSB_RXCSR_P_OVERRUN;
960 musb_writew(epio, MUSB_RXCSR, csr);
962 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
963 if (request->status == -EINPROGRESS)
964 request->status = -EOVERFLOW;
966 if (csr & MUSB_RXCSR_INCOMPRX) {
967 /* REVISIT not necessarily an error */
968 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
971 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
972 /* "should not happen"; likely RXPKTRDY pending for DMA */
973 dev_dbg(musb->controller, "%s busy, csr %04x\n",
974 musb_ep->end_point.name, csr);
978 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
979 csr &= ~(MUSB_RXCSR_AUTOCLEAR
981 | MUSB_RXCSR_DMAMODE);
982 musb_writew(epio, MUSB_RXCSR,
983 MUSB_RXCSR_P_WZC_BITS | csr);
985 request->actual += musb_ep->dma->actual_len;
987 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
989 musb_readw(epio, MUSB_RXCSR),
990 musb_ep->dma->actual_len, request);
992 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
993 defined(CONFIG_USB_UX500_DMA)
994 /* Autoclear doesn't clear RxPktRdy for short packets */
995 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
997 & (musb_ep->packet_sz - 1))) {
999 csr &= ~MUSB_RXCSR_RXPKTRDY;
1000 musb_writew(epio, MUSB_RXCSR, csr);
1003 /* incomplete, and not short? wait for next IN packet */
1004 if ((request->actual < request->length)
1005 && (musb_ep->dma->actual_len
1006 == musb_ep->packet_sz)) {
1007 /* In double buffer case, continue to unload fifo if
1008 * there is Rx packet in FIFO.
1010 csr = musb_readw(epio, MUSB_RXCSR);
1011 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
1012 hw_ep->rx_double_buffered)
1017 musb_g_giveback(musb_ep, request, 0);
1019 * In the giveback function the MUSB lock is
1020 * released and acquired after sometime. During
1021 * this time period the INDEX register could get
1022 * changed by the gadget_queue function especially
1023 * on SMP systems. Reselect the INDEX to be sure
1024 * we are reading/modifying the right registers
1026 musb_ep_select(mbase, epnum);
1028 req = next_request(musb_ep);
1032 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1033 defined(CONFIG_USB_UX500_DMA)
1036 /* Analyze request */
1040 /* ------------------------------------------------------------ */
1042 static int musb_gadget_enable(struct usb_ep *ep,
1043 const struct usb_endpoint_descriptor *desc)
1045 unsigned long flags;
1046 struct musb_ep *musb_ep;
1047 struct musb_hw_ep *hw_ep;
1050 void __iomem *mbase;
1054 int status = -EINVAL;
1059 musb_ep = to_musb_ep(ep);
1060 hw_ep = musb_ep->hw_ep;
1062 musb = musb_ep->musb;
1063 mbase = musb->mregs;
1064 epnum = musb_ep->current_epnum;
1066 spin_lock_irqsave(&musb->lock, flags);
1068 if (musb_ep->desc) {
1072 musb_ep->type = usb_endpoint_type(desc);
1074 /* check direction and (later) maxpacket size against endpoint */
1075 if (usb_endpoint_num(desc) != epnum)
1078 /* REVISIT this rules out high bandwidth periodic transfers */
1079 tmp = usb_endpoint_maxp(desc);
1080 if (tmp & ~0x07ff) {
1083 if (usb_endpoint_dir_in(desc))
1084 ok = musb->hb_iso_tx;
1086 ok = musb->hb_iso_rx;
1089 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1092 musb_ep->hb_mult = (tmp >> 11) & 3;
1094 musb_ep->hb_mult = 0;
1097 musb_ep->packet_sz = tmp & 0x7ff;
1098 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1100 /* enable the interrupts for the endpoint, set the endpoint
1101 * packet size (or fail), set the mode, clear the fifo
1103 musb_ep_select(mbase, epnum);
1104 if (usb_endpoint_dir_in(desc)) {
1106 if (hw_ep->is_shared_fifo)
1108 if (!musb_ep->is_in)
1111 if (tmp > hw_ep->max_packet_sz_tx) {
1112 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1116 musb->intrtxe |= (1 << epnum);
1117 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1119 /* REVISIT if can_bulk_split(), use by updating "tmp";
1120 * likewise high bandwidth periodic tx
1122 /* Set TXMAXP with the FIFO size of the endpoint
1123 * to disable double buffering mode.
1125 if (musb->double_buffer_not_ok) {
1126 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1128 if (can_bulk_split(musb, musb_ep->type))
1129 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1130 musb_ep->packet_sz) - 1;
1131 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1132 | (musb_ep->hb_mult << 11));
1135 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1136 if (musb_readw(regs, MUSB_TXCSR)
1137 & MUSB_TXCSR_FIFONOTEMPTY)
1138 csr |= MUSB_TXCSR_FLUSHFIFO;
1139 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1140 csr |= MUSB_TXCSR_P_ISO;
1142 /* set twice in case of double buffering */
1143 musb_writew(regs, MUSB_TXCSR, csr);
1144 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1145 musb_writew(regs, MUSB_TXCSR, csr);
1149 if (hw_ep->is_shared_fifo)
1154 if (tmp > hw_ep->max_packet_sz_rx) {
1155 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1159 musb->intrrxe |= (1 << epnum);
1160 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1162 /* REVISIT if can_bulk_combine() use by updating "tmp"
1163 * likewise high bandwidth periodic rx
1165 /* Set RXMAXP with the FIFO size of the endpoint
1166 * to disable double buffering mode.
1168 if (musb->double_buffer_not_ok)
1169 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1171 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1172 | (musb_ep->hb_mult << 11));
1174 /* force shared fifo to OUT-only mode */
1175 if (hw_ep->is_shared_fifo) {
1176 csr = musb_readw(regs, MUSB_TXCSR);
1177 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1178 musb_writew(regs, MUSB_TXCSR, csr);
1181 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1182 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1183 csr |= MUSB_RXCSR_P_ISO;
1184 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1185 csr |= MUSB_RXCSR_DISNYET;
1187 /* set twice in case of double buffering */
1188 musb_writew(regs, MUSB_RXCSR, csr);
1189 musb_writew(regs, MUSB_RXCSR, csr);
1192 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1193 * for some reason you run out of channels here.
1195 if (is_dma_capable() && musb->dma_controller) {
1196 struct dma_controller *c = musb->dma_controller;
1198 musb_ep->dma = c->channel_alloc(c, hw_ep,
1199 (desc->bEndpointAddress & USB_DIR_IN));
1201 musb_ep->dma = NULL;
1203 musb_ep->desc = desc;
1205 musb_ep->wedged = 0;
1208 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1209 musb_driver_name, musb_ep->end_point.name,
1210 ({ char *s; switch (musb_ep->type) {
1211 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1212 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1213 default: s = "iso"; break;
1215 musb_ep->is_in ? "IN" : "OUT",
1216 musb_ep->dma ? "dma, " : "",
1217 musb_ep->packet_sz);
1219 schedule_work(&musb->irq_work);
1222 spin_unlock_irqrestore(&musb->lock, flags);
1227 * Disable an endpoint flushing all requests queued.
1229 static int musb_gadget_disable(struct usb_ep *ep)
1231 unsigned long flags;
1234 struct musb_ep *musb_ep;
1238 musb_ep = to_musb_ep(ep);
1239 musb = musb_ep->musb;
1240 epnum = musb_ep->current_epnum;
1241 epio = musb->endpoints[epnum].regs;
1243 spin_lock_irqsave(&musb->lock, flags);
1244 musb_ep_select(musb->mregs, epnum);
1246 /* zero the endpoint sizes */
1247 if (musb_ep->is_in) {
1248 musb->intrtxe &= ~(1 << epnum);
1249 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1250 musb_writew(epio, MUSB_TXMAXP, 0);
1252 musb->intrrxe &= ~(1 << epnum);
1253 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1254 musb_writew(epio, MUSB_RXMAXP, 0);
1257 musb_ep->desc = NULL;
1258 musb_ep->end_point.desc = NULL;
1260 /* abort all pending DMA and requests */
1261 nuke(musb_ep, -ESHUTDOWN);
1263 schedule_work(&musb->irq_work);
1265 spin_unlock_irqrestore(&(musb->lock), flags);
1267 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1273 * Allocate a request for an endpoint.
1274 * Reused by ep0 code.
1276 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1278 struct musb_ep *musb_ep = to_musb_ep(ep);
1279 struct musb *musb = musb_ep->musb;
1280 struct musb_request *request = NULL;
1282 request = kzalloc(sizeof *request, gfp_flags);
1284 dev_dbg(musb->controller, "not enough memory\n");
1288 request->request.dma = DMA_ADDR_INVALID;
1289 request->epnum = musb_ep->current_epnum;
1290 request->ep = musb_ep;
1292 return &request->request;
1297 * Reused by ep0 code.
1299 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1301 kfree(to_musb_request(req));
1304 static LIST_HEAD(buffers);
1306 struct free_record {
1307 struct list_head list;
1314 * Context: controller locked, IRQs blocked.
1316 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1318 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1319 req->tx ? "TX/IN" : "RX/OUT",
1320 &req->request, req->request.length, req->epnum);
1322 musb_ep_select(musb->mregs, req->epnum);
1329 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1332 struct musb_ep *musb_ep;
1333 struct musb_request *request;
1336 unsigned long lockflags;
1343 musb_ep = to_musb_ep(ep);
1344 musb = musb_ep->musb;
1346 request = to_musb_request(req);
1347 request->musb = musb;
1349 if (request->ep != musb_ep)
1352 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1354 /* request is mine now... */
1355 request->request.actual = 0;
1356 request->request.status = -EINPROGRESS;
1357 request->epnum = musb_ep->current_epnum;
1358 request->tx = musb_ep->is_in;
1360 map_dma_buffer(request, musb, musb_ep);
1362 spin_lock_irqsave(&musb->lock, lockflags);
1364 /* don't queue if the ep is down */
1365 if (!musb_ep->desc) {
1366 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1367 req, ep->name, "disabled");
1368 status = -ESHUTDOWN;
1372 /* add request to the list */
1373 list_add_tail(&request->list, &musb_ep->req_list);
1375 /* it this is the head of the queue, start i/o ... */
1376 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1377 musb_ep_restart(musb, request);
1380 spin_unlock_irqrestore(&musb->lock, lockflags);
1384 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1386 struct musb_ep *musb_ep = to_musb_ep(ep);
1387 struct musb_request *req = to_musb_request(request);
1388 struct musb_request *r;
1389 unsigned long flags;
1391 struct musb *musb = musb_ep->musb;
1393 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1396 spin_lock_irqsave(&musb->lock, flags);
1398 list_for_each_entry(r, &musb_ep->req_list, list) {
1403 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1408 /* if the hardware doesn't have the request, easy ... */
1409 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1410 musb_g_giveback(musb_ep, request, -ECONNRESET);
1412 /* ... else abort the dma transfer ... */
1413 else if (is_dma_capable() && musb_ep->dma) {
1414 struct dma_controller *c = musb->dma_controller;
1416 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1417 if (c->channel_abort)
1418 status = c->channel_abort(musb_ep->dma);
1422 musb_g_giveback(musb_ep, request, -ECONNRESET);
1424 /* NOTE: by sticking to easily tested hardware/driver states,
1425 * we leave counting of in-flight packets imprecise.
1427 musb_g_giveback(musb_ep, request, -ECONNRESET);
1431 spin_unlock_irqrestore(&musb->lock, flags);
1436 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1437 * data but will queue requests.
1439 * exported to ep0 code
1441 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1443 struct musb_ep *musb_ep = to_musb_ep(ep);
1444 u8 epnum = musb_ep->current_epnum;
1445 struct musb *musb = musb_ep->musb;
1446 void __iomem *epio = musb->endpoints[epnum].regs;
1447 void __iomem *mbase;
1448 unsigned long flags;
1450 struct musb_request *request;
1455 mbase = musb->mregs;
1457 spin_lock_irqsave(&musb->lock, flags);
1459 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1464 musb_ep_select(mbase, epnum);
1466 request = next_request(musb_ep);
1469 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1474 /* Cannot portably stall with non-empty FIFO */
1475 if (musb_ep->is_in) {
1476 csr = musb_readw(epio, MUSB_TXCSR);
1477 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1478 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1484 musb_ep->wedged = 0;
1486 /* set/clear the stall and toggle bits */
1487 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1488 if (musb_ep->is_in) {
1489 csr = musb_readw(epio, MUSB_TXCSR);
1490 csr |= MUSB_TXCSR_P_WZC_BITS
1491 | MUSB_TXCSR_CLRDATATOG;
1493 csr |= MUSB_TXCSR_P_SENDSTALL;
1495 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1496 | MUSB_TXCSR_P_SENTSTALL);
1497 csr &= ~MUSB_TXCSR_TXPKTRDY;
1498 musb_writew(epio, MUSB_TXCSR, csr);
1500 csr = musb_readw(epio, MUSB_RXCSR);
1501 csr |= MUSB_RXCSR_P_WZC_BITS
1502 | MUSB_RXCSR_FLUSHFIFO
1503 | MUSB_RXCSR_CLRDATATOG;
1505 csr |= MUSB_RXCSR_P_SENDSTALL;
1507 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1508 | MUSB_RXCSR_P_SENTSTALL);
1509 musb_writew(epio, MUSB_RXCSR, csr);
1512 /* maybe start the first request in the queue */
1513 if (!musb_ep->busy && !value && request) {
1514 dev_dbg(musb->controller, "restarting the request\n");
1515 musb_ep_restart(musb, request);
1519 spin_unlock_irqrestore(&musb->lock, flags);
1524 * Sets the halt feature with the clear requests ignored
1526 static int musb_gadget_set_wedge(struct usb_ep *ep)
1528 struct musb_ep *musb_ep = to_musb_ep(ep);
1533 musb_ep->wedged = 1;
1535 return usb_ep_set_halt(ep);
1538 static int musb_gadget_fifo_status(struct usb_ep *ep)
1540 struct musb_ep *musb_ep = to_musb_ep(ep);
1541 void __iomem *epio = musb_ep->hw_ep->regs;
1542 int retval = -EINVAL;
1544 if (musb_ep->desc && !musb_ep->is_in) {
1545 struct musb *musb = musb_ep->musb;
1546 int epnum = musb_ep->current_epnum;
1547 void __iomem *mbase = musb->mregs;
1548 unsigned long flags;
1550 spin_lock_irqsave(&musb->lock, flags);
1552 musb_ep_select(mbase, epnum);
1553 /* FIXME return zero unless RXPKTRDY is set */
1554 retval = musb_readw(epio, MUSB_RXCOUNT);
1556 spin_unlock_irqrestore(&musb->lock, flags);
1561 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1563 struct musb_ep *musb_ep = to_musb_ep(ep);
1564 struct musb *musb = musb_ep->musb;
1565 u8 epnum = musb_ep->current_epnum;
1566 void __iomem *epio = musb->endpoints[epnum].regs;
1567 void __iomem *mbase;
1568 unsigned long flags;
1571 mbase = musb->mregs;
1573 spin_lock_irqsave(&musb->lock, flags);
1574 musb_ep_select(mbase, (u8) epnum);
1576 /* disable interrupts */
1577 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1579 if (musb_ep->is_in) {
1580 csr = musb_readw(epio, MUSB_TXCSR);
1581 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1582 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1584 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1585 * to interrupt current FIFO loading, but not flushing
1586 * the already loaded ones.
1588 csr &= ~MUSB_TXCSR_TXPKTRDY;
1589 musb_writew(epio, MUSB_TXCSR, csr);
1590 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1591 musb_writew(epio, MUSB_TXCSR, csr);
1594 csr = musb_readw(epio, MUSB_RXCSR);
1595 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1596 musb_writew(epio, MUSB_RXCSR, csr);
1597 musb_writew(epio, MUSB_RXCSR, csr);
1600 /* re-enable interrupt */
1601 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1602 spin_unlock_irqrestore(&musb->lock, flags);
1605 static const struct usb_ep_ops musb_ep_ops = {
1606 .enable = musb_gadget_enable,
1607 .disable = musb_gadget_disable,
1608 .alloc_request = musb_alloc_request,
1609 .free_request = musb_free_request,
1610 .queue = musb_gadget_queue,
1611 .dequeue = musb_gadget_dequeue,
1612 .set_halt = musb_gadget_set_halt,
1613 .set_wedge = musb_gadget_set_wedge,
1614 .fifo_status = musb_gadget_fifo_status,
1615 .fifo_flush = musb_gadget_fifo_flush
1618 /* ----------------------------------------------------------------------- */
1620 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1622 struct musb *musb = gadget_to_musb(gadget);
1624 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1627 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1629 struct musb *musb = gadget_to_musb(gadget);
1630 void __iomem *mregs = musb->mregs;
1631 unsigned long flags;
1632 int status = -EINVAL;
1636 spin_lock_irqsave(&musb->lock, flags);
1638 switch (musb->xceiv->state) {
1639 case OTG_STATE_B_PERIPHERAL:
1640 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1641 * that's part of the standard usb 1.1 state machine, and
1642 * doesn't affect OTG transitions.
1644 if (musb->may_wakeup && musb->is_suspended)
1647 case OTG_STATE_B_IDLE:
1648 /* Start SRP ... OTG not required. */
1649 devctl = musb_readb(mregs, MUSB_DEVCTL);
1650 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1651 devctl |= MUSB_DEVCTL_SESSION;
1652 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1653 devctl = musb_readb(mregs, MUSB_DEVCTL);
1655 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1656 devctl = musb_readb(mregs, MUSB_DEVCTL);
1661 while (devctl & MUSB_DEVCTL_SESSION) {
1662 devctl = musb_readb(mregs, MUSB_DEVCTL);
1667 spin_unlock_irqrestore(&musb->lock, flags);
1668 otg_start_srp(musb->xceiv->otg);
1669 spin_lock_irqsave(&musb->lock, flags);
1671 /* Block idling for at least 1s */
1672 musb_platform_try_idle(musb,
1673 jiffies + msecs_to_jiffies(1 * HZ));
1678 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1679 otg_state_string(musb->xceiv->state));
1685 power = musb_readb(mregs, MUSB_POWER);
1686 power |= MUSB_POWER_RESUME;
1687 musb_writeb(mregs, MUSB_POWER, power);
1688 dev_dbg(musb->controller, "issue wakeup\n");
1690 /* FIXME do this next chunk in a timer callback, no udelay */
1693 power = musb_readb(mregs, MUSB_POWER);
1694 power &= ~MUSB_POWER_RESUME;
1695 musb_writeb(mregs, MUSB_POWER, power);
1697 spin_unlock_irqrestore(&musb->lock, flags);
1702 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1704 struct musb *musb = gadget_to_musb(gadget);
1706 musb->is_self_powered = !!is_selfpowered;
1710 static void musb_pullup(struct musb *musb, int is_on)
1714 power = musb_readb(musb->mregs, MUSB_POWER);
1716 power |= MUSB_POWER_SOFTCONN;
1718 power &= ~MUSB_POWER_SOFTCONN;
1720 /* FIXME if on, HdrcStart; if off, HdrcStop */
1722 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1723 is_on ? "on" : "off");
1724 musb_writeb(musb->mregs, MUSB_POWER, power);
1728 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1730 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1733 * FIXME iff driver's softconnect flag is set (as it is during probe,
1734 * though that can clear it), just musb_pullup().
1741 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1743 struct musb *musb = gadget_to_musb(gadget);
1745 if (!musb->xceiv->set_power)
1747 return usb_phy_set_power(musb->xceiv, mA);
1750 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1752 struct musb *musb = gadget_to_musb(gadget);
1753 unsigned long flags;
1757 pm_runtime_get_sync(musb->controller);
1759 /* NOTE: this assumes we are sensing vbus; we'd rather
1760 * not pullup unless the B-session is active.
1762 spin_lock_irqsave(&musb->lock, flags);
1763 if (is_on != musb->softconnect) {
1764 musb->softconnect = is_on;
1765 musb_pullup(musb, is_on);
1767 spin_unlock_irqrestore(&musb->lock, flags);
1769 pm_runtime_put(musb->controller);
1774 static int musb_gadget_start(struct usb_gadget *g,
1775 struct usb_gadget_driver *driver);
1776 static int musb_gadget_stop(struct usb_gadget *g,
1777 struct usb_gadget_driver *driver);
1779 static const struct usb_gadget_ops musb_gadget_operations = {
1780 .get_frame = musb_gadget_get_frame,
1781 .wakeup = musb_gadget_wakeup,
1782 .set_selfpowered = musb_gadget_set_self_powered,
1783 /* .vbus_session = musb_gadget_vbus_session, */
1784 .vbus_draw = musb_gadget_vbus_draw,
1785 .pullup = musb_gadget_pullup,
1786 .udc_start = musb_gadget_start,
1787 .udc_stop = musb_gadget_stop,
1790 /* ----------------------------------------------------------------------- */
1794 /* Only this registration code "knows" the rule (from USB standards)
1795 * about there being only one external upstream port. It assumes
1796 * all peripheral ports are external...
1799 static void musb_gadget_release(struct device *dev)
1801 /* kref_put(WHAT) */
1802 dev_dbg(dev, "%s\n", __func__);
1807 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1809 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1811 memset(ep, 0, sizeof *ep);
1813 ep->current_epnum = epnum;
1818 INIT_LIST_HEAD(&ep->req_list);
1820 sprintf(ep->name, "ep%d%s", epnum,
1821 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1822 is_in ? "in" : "out"));
1823 ep->end_point.name = ep->name;
1824 INIT_LIST_HEAD(&ep->end_point.ep_list);
1826 ep->end_point.maxpacket = 64;
1827 ep->end_point.ops = &musb_g_ep0_ops;
1828 musb->g.ep0 = &ep->end_point;
1831 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1833 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1834 ep->end_point.ops = &musb_ep_ops;
1835 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1840 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1841 * to the rest of the driver state.
1843 static inline void musb_g_init_endpoints(struct musb *musb)
1846 struct musb_hw_ep *hw_ep;
1849 /* initialize endpoint list just once */
1850 INIT_LIST_HEAD(&(musb->g.ep_list));
1852 for (epnum = 0, hw_ep = musb->endpoints;
1853 epnum < musb->nr_endpoints;
1855 if (hw_ep->is_shared_fifo /* || !epnum */) {
1856 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1859 if (hw_ep->max_packet_sz_tx) {
1860 init_peripheral_ep(musb, &hw_ep->ep_in,
1864 if (hw_ep->max_packet_sz_rx) {
1865 init_peripheral_ep(musb, &hw_ep->ep_out,
1873 /* called once during driver setup to initialize and link into
1874 * the driver model; memory is zeroed.
1876 int musb_gadget_setup(struct musb *musb)
1880 /* REVISIT minor race: if (erroneously) setting up two
1881 * musb peripherals at the same time, only the bus lock
1885 musb->g.ops = &musb_gadget_operations;
1886 musb->g.max_speed = USB_SPEED_HIGH;
1887 musb->g.speed = USB_SPEED_UNKNOWN;
1889 /* this "gadget" abstracts/virtualizes the controller */
1890 dev_set_name(&musb->g.dev, "gadget");
1891 musb->g.dev.parent = musb->controller;
1892 musb->g.dev.dma_mask = musb->controller->dma_mask;
1893 musb->g.dev.release = musb_gadget_release;
1894 musb->g.name = musb_driver_name;
1898 musb_g_init_endpoints(musb);
1900 musb->is_active = 0;
1901 musb_platform_try_idle(musb, 0);
1903 status = device_register(&musb->g.dev);
1905 put_device(&musb->g.dev);
1908 status = usb_add_gadget_udc(musb->controller, &musb->g);
1914 musb->g.dev.parent = NULL;
1915 device_unregister(&musb->g.dev);
1919 void musb_gadget_cleanup(struct musb *musb)
1921 usb_del_gadget_udc(&musb->g);
1922 if (musb->g.dev.parent)
1923 device_unregister(&musb->g.dev);
1927 * Register the gadget driver. Used by gadget drivers when
1928 * registering themselves with the controller.
1930 * -EINVAL something went wrong (not driver)
1931 * -EBUSY another gadget is already using the controller
1932 * -ENOMEM no memory to perform the operation
1934 * @param driver the gadget driver
1935 * @return <0 if error, 0 if everything is fine
1937 static int musb_gadget_start(struct usb_gadget *g,
1938 struct usb_gadget_driver *driver)
1940 struct musb *musb = gadget_to_musb(g);
1941 struct usb_otg *otg = musb->xceiv->otg;
1942 struct usb_hcd *hcd = musb_to_hcd(musb);
1943 unsigned long flags;
1946 if (driver->max_speed < USB_SPEED_HIGH) {
1951 pm_runtime_get_sync(musb->controller);
1953 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1955 musb->softconnect = 0;
1956 musb->gadget_driver = driver;
1958 spin_lock_irqsave(&musb->lock, flags);
1959 musb->is_active = 1;
1961 otg_set_peripheral(otg, &musb->g);
1962 musb->xceiv->state = OTG_STATE_B_IDLE;
1963 spin_unlock_irqrestore(&musb->lock, flags);
1965 /* REVISIT: funcall to other code, which also
1966 * handles power budgeting ... this way also
1967 * ensures HdrcStart is indirectly called.
1969 retval = usb_add_hcd(hcd, 0, 0);
1971 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1975 if ((musb->xceiv->last_event == USB_EVENT_ID)
1977 otg_set_vbus(otg, 1);
1979 hcd->self.uses_pio_for_control = 1;
1981 if (musb->xceiv->last_event == USB_EVENT_NONE)
1982 pm_runtime_put(musb->controller);
1990 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1993 struct musb_hw_ep *hw_ep;
1995 /* don't disconnect if it's not connected */
1996 if (musb->g.speed == USB_SPEED_UNKNOWN)
1999 musb->g.speed = USB_SPEED_UNKNOWN;
2001 /* deactivate the hardware */
2002 if (musb->softconnect) {
2003 musb->softconnect = 0;
2004 musb_pullup(musb, 0);
2008 /* killing any outstanding requests will quiesce the driver;
2009 * then report disconnect
2012 for (i = 0, hw_ep = musb->endpoints;
2013 i < musb->nr_endpoints;
2015 musb_ep_select(musb->mregs, i);
2016 if (hw_ep->is_shared_fifo /* || !epnum */) {
2017 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2019 if (hw_ep->max_packet_sz_tx)
2020 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2021 if (hw_ep->max_packet_sz_rx)
2022 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2029 * Unregister the gadget driver. Used by gadget drivers when
2030 * unregistering themselves from the controller.
2032 * @param driver the gadget driver to unregister
2034 static int musb_gadget_stop(struct usb_gadget *g,
2035 struct usb_gadget_driver *driver)
2037 struct musb *musb = gadget_to_musb(g);
2038 unsigned long flags;
2040 if (musb->xceiv->last_event == USB_EVENT_NONE)
2041 pm_runtime_get_sync(musb->controller);
2044 * REVISIT always use otg_set_peripheral() here too;
2045 * this needs to shut down the OTG engine.
2048 spin_lock_irqsave(&musb->lock, flags);
2050 musb_hnp_stop(musb);
2052 (void) musb_gadget_vbus_draw(&musb->g, 0);
2054 musb->xceiv->state = OTG_STATE_UNDEFINED;
2055 stop_activity(musb, driver);
2056 otg_set_peripheral(musb->xceiv->otg, NULL);
2058 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2060 musb->is_active = 0;
2061 musb_platform_try_idle(musb, 0);
2062 spin_unlock_irqrestore(&musb->lock, flags);
2064 usb_remove_hcd(musb_to_hcd(musb));
2066 * FIXME we need to be able to register another
2067 * gadget driver here and have everything work;
2068 * that currently misbehaves.
2071 pm_runtime_put(musb->controller);
2076 /* ----------------------------------------------------------------------- */
2078 /* lifecycle operations called through plat_uds.c */
2080 void musb_g_resume(struct musb *musb)
2082 musb->is_suspended = 0;
2083 switch (musb->xceiv->state) {
2084 case OTG_STATE_B_IDLE:
2086 case OTG_STATE_B_WAIT_ACON:
2087 case OTG_STATE_B_PERIPHERAL:
2088 musb->is_active = 1;
2089 if (musb->gadget_driver && musb->gadget_driver->resume) {
2090 spin_unlock(&musb->lock);
2091 musb->gadget_driver->resume(&musb->g);
2092 spin_lock(&musb->lock);
2096 WARNING("unhandled RESUME transition (%s)\n",
2097 otg_state_string(musb->xceiv->state));
2101 /* called when SOF packets stop for 3+ msec */
2102 void musb_g_suspend(struct musb *musb)
2106 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2107 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2109 switch (musb->xceiv->state) {
2110 case OTG_STATE_B_IDLE:
2111 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2112 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2114 case OTG_STATE_B_PERIPHERAL:
2115 musb->is_suspended = 1;
2116 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2117 spin_unlock(&musb->lock);
2118 musb->gadget_driver->suspend(&musb->g);
2119 spin_lock(&musb->lock);
2123 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2124 * A_PERIPHERAL may need care too
2126 WARNING("unhandled SUSPEND transition (%s)\n",
2127 otg_state_string(musb->xceiv->state));
2131 /* Called during SRP */
2132 void musb_g_wakeup(struct musb *musb)
2134 musb_gadget_wakeup(&musb->g);
2137 /* called when VBUS drops below session threshold, and in other cases */
2138 void musb_g_disconnect(struct musb *musb)
2140 void __iomem *mregs = musb->mregs;
2141 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2143 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2146 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2148 /* don't draw vbus until new b-default session */
2149 (void) musb_gadget_vbus_draw(&musb->g, 0);
2151 musb->g.speed = USB_SPEED_UNKNOWN;
2152 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2153 spin_unlock(&musb->lock);
2154 musb->gadget_driver->disconnect(&musb->g);
2155 spin_lock(&musb->lock);
2158 switch (musb->xceiv->state) {
2160 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2161 otg_state_string(musb->xceiv->state));
2162 musb->xceiv->state = OTG_STATE_A_IDLE;
2163 MUSB_HST_MODE(musb);
2165 case OTG_STATE_A_PERIPHERAL:
2166 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2167 MUSB_HST_MODE(musb);
2169 case OTG_STATE_B_WAIT_ACON:
2170 case OTG_STATE_B_HOST:
2171 case OTG_STATE_B_PERIPHERAL:
2172 case OTG_STATE_B_IDLE:
2173 musb->xceiv->state = OTG_STATE_B_IDLE;
2175 case OTG_STATE_B_SRP_INIT:
2179 musb->is_active = 0;
2182 void musb_g_reset(struct musb *musb)
2183 __releases(musb->lock)
2184 __acquires(musb->lock)
2186 void __iomem *mbase = musb->mregs;
2187 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2190 dev_dbg(musb->controller, "<== %s driver '%s'\n",
2191 (devctl & MUSB_DEVCTL_BDEVICE)
2192 ? "B-Device" : "A-Device",
2194 ? musb->gadget_driver->driver.name
2198 /* report disconnect, if we didn't already (flushing EP state) */
2199 if (musb->g.speed != USB_SPEED_UNKNOWN)
2200 musb_g_disconnect(musb);
2203 else if (devctl & MUSB_DEVCTL_HR)
2204 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2207 /* what speed did we negotiate? */
2208 power = musb_readb(mbase, MUSB_POWER);
2209 musb->g.speed = (power & MUSB_POWER_HSMODE)
2210 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2212 /* start in USB_STATE_DEFAULT */
2213 musb->is_active = 1;
2214 musb->is_suspended = 0;
2215 MUSB_DEV_MODE(musb);
2217 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2219 musb->may_wakeup = 0;
2220 musb->g.b_hnp_enable = 0;
2221 musb->g.a_alt_hnp_support = 0;
2222 musb->g.a_hnp_support = 0;
2224 /* Normal reset, as B-Device;
2225 * or else after HNP, as A-Device
2227 if (devctl & MUSB_DEVCTL_BDEVICE) {
2228 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2229 musb->g.is_a_peripheral = 0;
2231 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2232 musb->g.is_a_peripheral = 1;
2235 /* start with default limits on VBUS power draw */
2236 (void) musb_gadget_vbus_draw(&musb->g, 8);