2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
79 * - ISO not tested ... might work, but only weakly isochronous
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
91 /* ----------------------------------------------------------------------- */
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
96 /* Maps the buffer to dma */
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
104 request->map_state = UN_MAPPED;
106 if (!is_dma_capable() || !musb_ep->dma)
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
123 request->request.buf,
124 request->request.length,
128 request->map_state = MUSB_MAPPED;
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
136 request->map_state = PRE_MAPPED;
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
144 struct musb_ep *musb_ep = request->ep;
146 if (!is_buffer_mapped(request) || !musb_ep->dma)
149 if (request->request.dma == DMA_ADDR_INVALID) {
150 dev_vdbg(musb->controller,
151 "not unmapping a never mapped buffer\n");
154 if (request->map_state == MUSB_MAPPED) {
155 dma_unmap_single(musb->controller,
156 request->request.dma,
157 request->request.length,
161 request->request.dma = DMA_ADDR_INVALID;
162 } else { /* PRE_MAPPED */
163 dma_sync_single_for_cpu(musb->controller,
164 request->request.dma,
165 request->request.length,
170 request->map_state = UN_MAPPED;
174 * Immediately complete a request.
176 * @param request the request to complete
177 * @param status the status to complete the request with
178 * Context: controller locked, IRQs blocked.
180 void musb_g_giveback(
182 struct usb_request *request,
184 __releases(ep->musb->lock)
185 __acquires(ep->musb->lock)
187 struct musb_request *req;
191 req = to_musb_request(request);
193 list_del(&req->list);
194 if (req->request.status == -EINPROGRESS)
195 req->request.status = status;
199 spin_unlock(&musb->lock);
201 if (!dma_mapping_error(&musb->g.dev, request->dma))
202 unmap_dma_buffer(req, musb);
204 if (request->status == 0)
205 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
206 ep->end_point.name, request,
207 req->request.actual, req->request.length);
209 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
210 ep->end_point.name, request,
211 req->request.actual, req->request.length,
213 req->request.complete(&req->ep->end_point, &req->request);
214 spin_lock(&musb->lock);
218 /* ----------------------------------------------------------------------- */
221 * Abort requests queued to an endpoint using the status. Synchronous.
222 * caller locked controller and blocked irqs, and selected this ep.
224 static void nuke(struct musb_ep *ep, const int status)
226 struct musb *musb = ep->musb;
227 struct musb_request *req = NULL;
228 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
232 if (is_dma_capable() && ep->dma) {
233 struct dma_controller *c = ep->musb->dma_controller;
238 * The programming guide says that we must not clear
239 * the DMAMODE bit before DMAENAB, so we only
240 * clear it in the second write...
242 musb_writew(epio, MUSB_TXCSR,
243 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_TXCSR,
245 0 | MUSB_TXCSR_FLUSHFIFO);
247 musb_writew(epio, MUSB_RXCSR,
248 0 | MUSB_RXCSR_FLUSHFIFO);
249 musb_writew(epio, MUSB_RXCSR,
250 0 | MUSB_RXCSR_FLUSHFIFO);
253 value = c->channel_abort(ep->dma);
254 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
256 c->channel_release(ep->dma);
260 while (!list_empty(&ep->req_list)) {
261 req = list_first_entry(&ep->req_list, struct musb_request, list);
262 musb_g_giveback(ep, &req->request, status);
266 /* ----------------------------------------------------------------------- */
268 /* Data transfers - pure PIO, pure DMA, or mixed mode */
271 * This assumes the separate CPPI engine is responding to DMA requests
272 * from the usb core ... sequenced a bit differently from mentor dma.
275 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
277 if (can_bulk_split(musb, ep->type))
278 return ep->hw_ep->max_packet_sz_tx;
280 return ep->packet_sz;
284 #ifdef CONFIG_USB_INVENTRA_DMA
286 /* Peripheral tx (IN) using Mentor DMA works as follows:
287 Only mode 0 is used for transfers <= wPktSize,
288 mode 1 is used for larger transfers,
290 One of the following happens:
291 - Host sends IN token which causes an endpoint interrupt
293 -> if DMA is currently busy, exit.
294 -> if queue is non-empty, txstate().
296 - Request is queued by the gadget driver.
297 -> if queue was previously empty, txstate()
302 | (data is transferred to the FIFO, then sent out when
303 | IN token(s) are recd from Host.
304 | -> DMA interrupt on completion
306 | -> stop DMA, ~DMAENAB,
307 | -> set TxPktRdy for last short pkt or zlp
308 | -> Complete Request
309 | -> Continue next request (call txstate)
310 |___________________________________|
312 * Non-Mentor DMA engines can of course work differently, such as by
313 * upleveling from irq-per-packet to irq-per-buffer.
319 * An endpoint is transmitting data. This can be called either from
320 * the IRQ routine or from ep.queue() to kickstart a request on an
323 * Context: controller locked, IRQs blocked, endpoint selected
325 static void txstate(struct musb *musb, struct musb_request *req)
327 u8 epnum = req->epnum;
328 struct musb_ep *musb_ep;
329 void __iomem *epio = musb->endpoints[epnum].regs;
330 struct usb_request *request;
331 u16 fifo_count = 0, csr;
336 /* Check if EP is disabled */
337 if (!musb_ep->desc) {
338 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
339 musb_ep->end_point.name);
343 /* we shouldn't get here while DMA is active ... but we do ... */
344 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
345 dev_dbg(musb->controller, "dma pending...\n");
349 /* read TXCSR before */
350 csr = musb_readw(epio, MUSB_TXCSR);
352 request = &req->request;
353 fifo_count = min(max_ep_writesize(musb, musb_ep),
354 (int)(request->length - request->actual));
356 if (csr & MUSB_TXCSR_TXPKTRDY) {
357 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
358 musb_ep->end_point.name, csr);
362 if (csr & MUSB_TXCSR_P_SENDSTALL) {
363 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
364 musb_ep->end_point.name, csr);
368 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
369 epnum, musb_ep->packet_sz, fifo_count,
372 #ifndef CONFIG_MUSB_PIO_ONLY
373 if (is_buffer_mapped(req)) {
374 struct dma_controller *c = musb->dma_controller;
377 /* setup DMA, then program endpoint CSR */
378 request_size = min_t(size_t, request->length - request->actual,
379 musb_ep->dma->max_len);
381 use_dma = (request->dma != DMA_ADDR_INVALID && request_size);
383 /* MUSB_TXCSR_P_ISO is still set correctly */
385 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
387 if (request_size < musb_ep->packet_sz)
388 musb_ep->dma->desired_mode = 0;
390 musb_ep->dma->desired_mode = 1;
392 use_dma = use_dma && c->channel_program(
393 musb_ep->dma, musb_ep->packet_sz,
394 musb_ep->dma->desired_mode,
395 request->dma + request->actual, request_size);
397 if (musb_ep->dma->desired_mode == 0) {
399 * We must not clear the DMAMODE bit
400 * before the DMAENAB bit -- and the
401 * latter doesn't always get cleared
402 * before we get here...
404 csr &= ~(MUSB_TXCSR_AUTOSET
405 | MUSB_TXCSR_DMAENAB);
406 musb_writew(epio, MUSB_TXCSR, csr
407 | MUSB_TXCSR_P_WZC_BITS);
408 csr &= ~MUSB_TXCSR_DMAMODE;
409 csr |= (MUSB_TXCSR_DMAENAB |
411 /* against programming guide */
413 csr |= (MUSB_TXCSR_DMAENAB
417 * Enable Autoset according to table
419 * bulk_split hb_mult Autoset_Enable
421 * 0 >0 No(High BW ISO)
425 if (!musb_ep->hb_mult ||
429 csr |= MUSB_TXCSR_AUTOSET;
431 csr &= ~MUSB_TXCSR_P_UNDERRUN;
433 musb_writew(epio, MUSB_TXCSR, csr);
437 #elif defined(CONFIG_USB_TI_CPPI_DMA)
438 /* program endpoint CSR first, then setup DMA */
439 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
440 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
442 musb_writew(epio, MUSB_TXCSR,
443 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
446 /* ensure writebuffer is empty */
447 csr = musb_readw(epio, MUSB_TXCSR);
449 /* NOTE host side sets DMAENAB later than this; both are
450 * OK since the transfer dma glue (between CPPI and Mentor
451 * fifos) just tells CPPI it could start. Data only moves
452 * to the USB TX fifo when both fifos are ready.
455 /* "mode" is irrelevant here; handle terminating ZLPs like
456 * PIO does, since the hardware RNDIS mode seems unreliable
457 * except for the last-packet-is-already-short case.
459 use_dma = use_dma && c->channel_program(
460 musb_ep->dma, musb_ep->packet_sz,
462 request->dma + request->actual,
465 c->channel_release(musb_ep->dma);
467 csr &= ~MUSB_TXCSR_DMAENAB;
468 musb_writew(epio, MUSB_TXCSR, csr);
469 /* invariant: prequest->buf is non-null */
471 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
472 use_dma = use_dma && c->channel_program(
473 musb_ep->dma, musb_ep->packet_sz,
475 request->dma + request->actual,
483 * Unmap the dma buffer back to cpu if dma channel
486 unmap_dma_buffer(req, musb);
488 musb_write_fifo(musb_ep->hw_ep, fifo_count,
489 (u8 *) (request->buf + request->actual));
490 request->actual += fifo_count;
491 csr |= MUSB_TXCSR_TXPKTRDY;
492 csr &= ~MUSB_TXCSR_P_UNDERRUN;
493 musb_writew(epio, MUSB_TXCSR, csr);
496 /* host may already have the data when this message shows... */
497 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
498 musb_ep->end_point.name, use_dma ? "dma" : "pio",
499 request->actual, request->length,
500 musb_readw(epio, MUSB_TXCSR),
502 musb_readw(epio, MUSB_TXMAXP));
506 * FIFO state update (e.g. data ready).
507 * Called from IRQ, with controller locked.
509 void musb_g_tx(struct musb *musb, u8 epnum)
512 struct musb_request *req;
513 struct usb_request *request;
514 u8 __iomem *mbase = musb->mregs;
515 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
516 void __iomem *epio = musb->endpoints[epnum].regs;
517 struct dma_channel *dma;
519 musb_ep_select(mbase, epnum);
520 req = next_request(musb_ep);
521 request = &req->request;
523 csr = musb_readw(epio, MUSB_TXCSR);
524 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
526 dma = is_dma_capable() ? musb_ep->dma : NULL;
529 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
530 * probably rates reporting as a host error.
532 if (csr & MUSB_TXCSR_P_SENTSTALL) {
533 csr |= MUSB_TXCSR_P_WZC_BITS;
534 csr &= ~MUSB_TXCSR_P_SENTSTALL;
535 musb_writew(epio, MUSB_TXCSR, csr);
539 if (csr & MUSB_TXCSR_P_UNDERRUN) {
540 /* We NAKed, no big deal... little reason to care. */
541 csr |= MUSB_TXCSR_P_WZC_BITS;
542 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
543 musb_writew(epio, MUSB_TXCSR, csr);
544 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
548 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
550 * SHOULD NOT HAPPEN... has with CPPI though, after
551 * changing SENDSTALL (and other cases); harmless?
553 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
560 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
562 csr |= MUSB_TXCSR_P_WZC_BITS;
563 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
564 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
565 musb_writew(epio, MUSB_TXCSR, csr);
566 /* Ensure writebuffer is empty. */
567 csr = musb_readw(epio, MUSB_TXCSR);
568 request->actual += musb_ep->dma->actual_len;
569 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
570 epnum, csr, musb_ep->dma->actual_len, request);
574 * First, maybe a terminating short packet. Some DMA
575 * engines might handle this by themselves.
577 if ((request->zero && request->length
578 && (request->length % musb_ep->packet_sz == 0)
579 && (request->actual == request->length))
580 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
581 || (is_dma && (!dma->desired_mode ||
583 (musb_ep->packet_sz - 1))))
587 * On DMA completion, FIFO may not be
590 if (csr & MUSB_TXCSR_TXPKTRDY)
593 dev_dbg(musb->controller, "sending zero pkt\n");
594 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
595 | MUSB_TXCSR_TXPKTRDY);
599 if (request->actual == request->length) {
600 musb_g_giveback(musb_ep, request, 0);
602 * In the giveback function the MUSB lock is
603 * released and acquired after sometime. During
604 * this time period the INDEX register could get
605 * changed by the gadget_queue function especially
606 * on SMP systems. Reselect the INDEX to be sure
607 * we are reading/modifying the right registers
609 musb_ep_select(mbase, epnum);
610 req = musb_ep->desc ? next_request(musb_ep) : NULL;
612 dev_dbg(musb->controller, "%s idle now\n",
613 musb_ep->end_point.name);
622 /* ------------------------------------------------------------ */
624 #ifdef CONFIG_USB_INVENTRA_DMA
626 /* Peripheral rx (OUT) using Mentor DMA works as follows:
627 - Only mode 0 is used.
629 - Request is queued by the gadget class driver.
630 -> if queue was previously empty, rxstate()
632 - Host sends OUT token which causes an endpoint interrupt
634 | -> if request queued, call rxstate
636 | | -> DMA interrupt on completion
640 | | -> if data recd = max expected
641 | | by the request, or host
642 | | sent a short packet,
643 | | complete the request,
644 | | and start the next one.
645 | |_____________________________________|
646 | else just wait for the host
647 | to send the next OUT token.
648 |__________________________________________________|
650 * Non-Mentor DMA engines can of course work differently.
656 * Context: controller locked, IRQs blocked, endpoint selected
658 static void rxstate(struct musb *musb, struct musb_request *req)
660 const u8 epnum = req->epnum;
661 struct usb_request *request = &req->request;
662 struct musb_ep *musb_ep;
663 void __iomem *epio = musb->endpoints[epnum].regs;
666 u16 csr = musb_readw(epio, MUSB_RXCSR);
667 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
670 if (hw_ep->is_shared_fifo)
671 musb_ep = &hw_ep->ep_in;
673 musb_ep = &hw_ep->ep_out;
675 fifo_count = musb_ep->packet_sz;
677 /* Check if EP is disabled */
678 if (!musb_ep->desc) {
679 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
680 musb_ep->end_point.name);
684 /* We shouldn't get here while DMA is active, but we do... */
685 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
686 dev_dbg(musb->controller, "DMA pending...\n");
690 if (csr & MUSB_RXCSR_P_SENDSTALL) {
691 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
692 musb_ep->end_point.name, csr);
696 if (is_cppi_enabled() && is_buffer_mapped(req)) {
697 struct dma_controller *c = musb->dma_controller;
698 struct dma_channel *channel = musb_ep->dma;
700 /* NOTE: CPPI won't actually stop advancing the DMA
701 * queue after short packet transfers, so this is almost
702 * always going to run as IRQ-per-packet DMA so that
703 * faults will be handled correctly.
705 if (c->channel_program(channel,
707 !request->short_not_ok,
708 request->dma + request->actual,
709 request->length - request->actual)) {
711 /* make sure that if an rxpkt arrived after the irq,
712 * the cppi engine will be ready to take it as soon
715 csr &= ~(MUSB_RXCSR_AUTOCLEAR
716 | MUSB_RXCSR_DMAMODE);
717 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
718 musb_writew(epio, MUSB_RXCSR, csr);
723 if (csr & MUSB_RXCSR_RXPKTRDY) {
724 fifo_count = musb_readw(epio, MUSB_RXCOUNT);
727 * Enable Mode 1 on RX transfers only when short_not_ok flag
728 * is set. Currently short_not_ok flag is set only from
729 * file_storage and f_mass_storage drivers
732 if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
737 if (request->actual < request->length) {
738 #ifdef CONFIG_USB_INVENTRA_DMA
739 if (is_buffer_mapped(req)) {
740 struct dma_controller *c;
741 struct dma_channel *channel;
745 c = musb->dma_controller;
746 channel = musb_ep->dma;
748 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
749 * mode 0 only. So we do not get endpoint interrupts due to DMA
750 * completion. We only get interrupts from DMA controller.
752 * We could operate in DMA mode 1 if we knew the size of the tranfer
753 * in advance. For mass storage class, request->length = what the host
754 * sends, so that'd work. But for pretty much everything else,
755 * request->length is routinely more than what the host sends. For
756 * most these gadgets, end of is signified either by a short packet,
757 * or filling the last byte of the buffer. (Sending extra data in
758 * that last pckate should trigger an overflow fault.) But in mode 1,
759 * we don't get DMA completion interrupt for short packets.
761 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
762 * to get endpoint interrupt on every DMA req, but that didn't seem
765 * REVISIT an updated g_file_storage can set req->short_not_ok, which
766 * then becomes usable as a runtime "use mode 1" hint...
769 /* Experimental: Mode1 works with mass storage use cases */
771 csr |= MUSB_RXCSR_AUTOCLEAR;
772 musb_writew(epio, MUSB_RXCSR, csr);
773 csr |= MUSB_RXCSR_DMAENAB;
774 musb_writew(epio, MUSB_RXCSR, csr);
777 * this special sequence (enabling and then
778 * disabling MUSB_RXCSR_DMAMODE) is required
779 * to get DMAReq to activate
781 musb_writew(epio, MUSB_RXCSR,
782 csr | MUSB_RXCSR_DMAMODE);
783 musb_writew(epio, MUSB_RXCSR, csr);
785 transfer_size = min(request->length - request->actual,
787 musb_ep->dma->desired_mode = 1;
790 if (!musb_ep->hb_mult &&
791 musb_ep->hw_ep->rx_double_buffered)
792 csr |= MUSB_RXCSR_AUTOCLEAR;
793 csr |= MUSB_RXCSR_DMAENAB;
794 musb_writew(epio, MUSB_RXCSR, csr);
796 transfer_size = min(request->length - request->actual,
797 (unsigned)fifo_count);
798 musb_ep->dma->desired_mode = 0;
801 use_dma = c->channel_program(
804 channel->desired_mode,
812 #elif defined(CONFIG_USB_UX500_DMA)
813 if ((is_buffer_mapped(req)) &&
814 (request->actual < request->length)) {
816 struct dma_controller *c;
817 struct dma_channel *channel;
818 int transfer_size = 0;
820 c = musb->dma_controller;
821 channel = musb_ep->dma;
823 /* In case first packet is short */
824 if (fifo_count < musb_ep->packet_sz)
825 transfer_size = fifo_count;
826 else if (request->short_not_ok)
827 transfer_size = min(request->length -
831 transfer_size = min(request->length -
833 (unsigned)fifo_count);
835 csr &= ~MUSB_RXCSR_DMAMODE;
836 csr |= (MUSB_RXCSR_DMAENAB |
837 MUSB_RXCSR_AUTOCLEAR);
839 musb_writew(epio, MUSB_RXCSR, csr);
841 if (transfer_size <= musb_ep->packet_sz) {
842 musb_ep->dma->desired_mode = 0;
844 musb_ep->dma->desired_mode = 1;
845 /* Mode must be set after DMAENAB */
846 csr |= MUSB_RXCSR_DMAMODE;
847 musb_writew(epio, MUSB_RXCSR, csr);
850 if (c->channel_program(channel,
852 channel->desired_mode,
859 #endif /* Mentor's DMA */
861 len = request->length - request->actual;
862 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
863 musb_ep->end_point.name,
867 fifo_count = min_t(unsigned, len, fifo_count);
869 #ifdef CONFIG_USB_TUSB_OMAP_DMA
870 if (tusb_dma_omap() && is_buffer_mapped(req)) {
871 struct dma_controller *c = musb->dma_controller;
872 struct dma_channel *channel = musb_ep->dma;
873 u32 dma_addr = request->dma + request->actual;
876 ret = c->channel_program(channel,
878 channel->desired_mode,
886 * Unmap the dma buffer back to cpu if dma channel
887 * programming fails. This buffer is mapped if the
888 * channel allocation is successful
890 if (is_buffer_mapped(req)) {
891 unmap_dma_buffer(req, musb);
894 * Clear DMAENAB and AUTOCLEAR for the
897 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
898 musb_writew(epio, MUSB_RXCSR, csr);
901 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
902 (request->buf + request->actual));
903 request->actual += fifo_count;
905 /* REVISIT if we left anything in the fifo, flush
906 * it and report -EOVERFLOW
910 csr |= MUSB_RXCSR_P_WZC_BITS;
911 csr &= ~MUSB_RXCSR_RXPKTRDY;
912 musb_writew(epio, MUSB_RXCSR, csr);
916 /* reach the end or short packet detected */
917 if (request->actual == request->length ||
918 fifo_count < musb_ep->packet_sz)
919 musb_g_giveback(musb_ep, request, 0);
923 * Data ready for a request; called from IRQ
925 void musb_g_rx(struct musb *musb, u8 epnum)
928 struct musb_request *req;
929 struct usb_request *request;
930 void __iomem *mbase = musb->mregs;
931 struct musb_ep *musb_ep;
932 void __iomem *epio = musb->endpoints[epnum].regs;
933 struct dma_channel *dma;
934 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
936 if (hw_ep->is_shared_fifo)
937 musb_ep = &hw_ep->ep_in;
939 musb_ep = &hw_ep->ep_out;
941 musb_ep_select(mbase, epnum);
943 req = next_request(musb_ep);
947 request = &req->request;
949 csr = musb_readw(epio, MUSB_RXCSR);
950 dma = is_dma_capable() ? musb_ep->dma : NULL;
952 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
953 csr, dma ? " (dma)" : "", request);
955 if (csr & MUSB_RXCSR_P_SENTSTALL) {
956 csr |= MUSB_RXCSR_P_WZC_BITS;
957 csr &= ~MUSB_RXCSR_P_SENTSTALL;
958 musb_writew(epio, MUSB_RXCSR, csr);
962 if (csr & MUSB_RXCSR_P_OVERRUN) {
963 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
964 csr &= ~MUSB_RXCSR_P_OVERRUN;
965 musb_writew(epio, MUSB_RXCSR, csr);
967 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
968 if (request->status == -EINPROGRESS)
969 request->status = -EOVERFLOW;
971 if (csr & MUSB_RXCSR_INCOMPRX) {
972 /* REVISIT not necessarily an error */
973 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
976 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
977 /* "should not happen"; likely RXPKTRDY pending for DMA */
978 dev_dbg(musb->controller, "%s busy, csr %04x\n",
979 musb_ep->end_point.name, csr);
983 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
984 csr &= ~(MUSB_RXCSR_AUTOCLEAR
986 | MUSB_RXCSR_DMAMODE);
987 musb_writew(epio, MUSB_RXCSR,
988 MUSB_RXCSR_P_WZC_BITS | csr);
990 request->actual += musb_ep->dma->actual_len;
992 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
994 musb_readw(epio, MUSB_RXCSR),
995 musb_ep->dma->actual_len, request);
997 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
998 defined(CONFIG_USB_UX500_DMA)
999 /* Autoclear doesn't clear RxPktRdy for short packets */
1000 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
1002 & (musb_ep->packet_sz - 1))) {
1004 csr &= ~MUSB_RXCSR_RXPKTRDY;
1005 musb_writew(epio, MUSB_RXCSR, csr);
1008 /* incomplete, and not short? wait for next IN packet */
1009 if ((request->actual < request->length)
1010 && (musb_ep->dma->actual_len
1011 == musb_ep->packet_sz)) {
1012 /* In double buffer case, continue to unload fifo if
1013 * there is Rx packet in FIFO.
1015 csr = musb_readw(epio, MUSB_RXCSR);
1016 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
1017 hw_ep->rx_double_buffered)
1022 musb_g_giveback(musb_ep, request, 0);
1024 * In the giveback function the MUSB lock is
1025 * released and acquired after sometime. During
1026 * this time period the INDEX register could get
1027 * changed by the gadget_queue function especially
1028 * on SMP systems. Reselect the INDEX to be sure
1029 * we are reading/modifying the right registers
1031 musb_ep_select(mbase, epnum);
1033 req = next_request(musb_ep);
1037 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
1038 defined(CONFIG_USB_UX500_DMA)
1041 /* Analyze request */
1045 /* ------------------------------------------------------------ */
1047 static int musb_gadget_enable(struct usb_ep *ep,
1048 const struct usb_endpoint_descriptor *desc)
1050 unsigned long flags;
1051 struct musb_ep *musb_ep;
1052 struct musb_hw_ep *hw_ep;
1055 void __iomem *mbase;
1059 int status = -EINVAL;
1064 musb_ep = to_musb_ep(ep);
1065 hw_ep = musb_ep->hw_ep;
1067 musb = musb_ep->musb;
1068 mbase = musb->mregs;
1069 epnum = musb_ep->current_epnum;
1071 spin_lock_irqsave(&musb->lock, flags);
1073 if (musb_ep->desc) {
1077 musb_ep->type = usb_endpoint_type(desc);
1079 /* check direction and (later) maxpacket size against endpoint */
1080 if (usb_endpoint_num(desc) != epnum)
1083 /* REVISIT this rules out high bandwidth periodic transfers */
1084 tmp = usb_endpoint_maxp(desc);
1085 if (tmp & ~0x07ff) {
1088 if (usb_endpoint_dir_in(desc))
1089 ok = musb->hb_iso_tx;
1091 ok = musb->hb_iso_rx;
1094 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1097 musb_ep->hb_mult = (tmp >> 11) & 3;
1099 musb_ep->hb_mult = 0;
1102 musb_ep->packet_sz = tmp & 0x7ff;
1103 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1105 /* enable the interrupts for the endpoint, set the endpoint
1106 * packet size (or fail), set the mode, clear the fifo
1108 musb_ep_select(mbase, epnum);
1109 if (usb_endpoint_dir_in(desc)) {
1111 if (hw_ep->is_shared_fifo)
1113 if (!musb_ep->is_in)
1116 if (tmp > hw_ep->max_packet_sz_tx) {
1117 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1121 musb->intrtxe |= (1 << epnum);
1122 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1124 /* REVISIT if can_bulk_split(), use by updating "tmp";
1125 * likewise high bandwidth periodic tx
1127 /* Set TXMAXP with the FIFO size of the endpoint
1128 * to disable double buffering mode.
1130 if (musb->double_buffer_not_ok) {
1131 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1133 if (can_bulk_split(musb, musb_ep->type))
1134 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx /
1135 musb_ep->packet_sz) - 1;
1136 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1137 | (musb_ep->hb_mult << 11));
1140 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1141 if (musb_readw(regs, MUSB_TXCSR)
1142 & MUSB_TXCSR_FIFONOTEMPTY)
1143 csr |= MUSB_TXCSR_FLUSHFIFO;
1144 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1145 csr |= MUSB_TXCSR_P_ISO;
1147 /* set twice in case of double buffering */
1148 musb_writew(regs, MUSB_TXCSR, csr);
1149 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1150 musb_writew(regs, MUSB_TXCSR, csr);
1154 if (hw_ep->is_shared_fifo)
1159 if (tmp > hw_ep->max_packet_sz_rx) {
1160 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1164 musb->intrrxe |= (1 << epnum);
1165 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe);
1167 /* REVISIT if can_bulk_combine() use by updating "tmp"
1168 * likewise high bandwidth periodic rx
1170 /* Set RXMAXP with the FIFO size of the endpoint
1171 * to disable double buffering mode.
1173 if (musb->double_buffer_not_ok)
1174 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1176 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1177 | (musb_ep->hb_mult << 11));
1179 /* force shared fifo to OUT-only mode */
1180 if (hw_ep->is_shared_fifo) {
1181 csr = musb_readw(regs, MUSB_TXCSR);
1182 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1183 musb_writew(regs, MUSB_TXCSR, csr);
1186 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1187 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1188 csr |= MUSB_RXCSR_P_ISO;
1189 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1190 csr |= MUSB_RXCSR_DISNYET;
1192 /* set twice in case of double buffering */
1193 musb_writew(regs, MUSB_RXCSR, csr);
1194 musb_writew(regs, MUSB_RXCSR, csr);
1197 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1198 * for some reason you run out of channels here.
1200 if (is_dma_capable() && musb->dma_controller) {
1201 struct dma_controller *c = musb->dma_controller;
1203 musb_ep->dma = c->channel_alloc(c, hw_ep,
1204 (desc->bEndpointAddress & USB_DIR_IN));
1206 musb_ep->dma = NULL;
1208 musb_ep->desc = desc;
1210 musb_ep->wedged = 0;
1213 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1214 musb_driver_name, musb_ep->end_point.name,
1215 ({ char *s; switch (musb_ep->type) {
1216 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1217 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1218 default: s = "iso"; break;
1220 musb_ep->is_in ? "IN" : "OUT",
1221 musb_ep->dma ? "dma, " : "",
1222 musb_ep->packet_sz);
1224 schedule_work(&musb->irq_work);
1227 spin_unlock_irqrestore(&musb->lock, flags);
1232 * Disable an endpoint flushing all requests queued.
1234 static int musb_gadget_disable(struct usb_ep *ep)
1236 unsigned long flags;
1239 struct musb_ep *musb_ep;
1243 musb_ep = to_musb_ep(ep);
1244 musb = musb_ep->musb;
1245 epnum = musb_ep->current_epnum;
1246 epio = musb->endpoints[epnum].regs;
1248 spin_lock_irqsave(&musb->lock, flags);
1249 musb_ep_select(musb->mregs, epnum);
1251 /* zero the endpoint sizes */
1252 if (musb_ep->is_in) {
1253 musb->intrtxe &= ~(1 << epnum);
1254 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
1255 musb_writew(epio, MUSB_TXMAXP, 0);
1257 musb->intrrxe &= ~(1 << epnum);
1258 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
1259 musb_writew(epio, MUSB_RXMAXP, 0);
1262 musb_ep->desc = NULL;
1263 musb_ep->end_point.desc = NULL;
1265 /* abort all pending DMA and requests */
1266 nuke(musb_ep, -ESHUTDOWN);
1268 schedule_work(&musb->irq_work);
1270 spin_unlock_irqrestore(&(musb->lock), flags);
1272 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1278 * Allocate a request for an endpoint.
1279 * Reused by ep0 code.
1281 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1283 struct musb_ep *musb_ep = to_musb_ep(ep);
1284 struct musb *musb = musb_ep->musb;
1285 struct musb_request *request = NULL;
1287 request = kzalloc(sizeof *request, gfp_flags);
1289 dev_dbg(musb->controller, "not enough memory\n");
1293 request->request.dma = DMA_ADDR_INVALID;
1294 request->epnum = musb_ep->current_epnum;
1295 request->ep = musb_ep;
1297 return &request->request;
1302 * Reused by ep0 code.
1304 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1306 kfree(to_musb_request(req));
1309 static LIST_HEAD(buffers);
1311 struct free_record {
1312 struct list_head list;
1319 * Context: controller locked, IRQs blocked.
1321 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1323 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1324 req->tx ? "TX/IN" : "RX/OUT",
1325 &req->request, req->request.length, req->epnum);
1327 musb_ep_select(musb->mregs, req->epnum);
1334 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1337 struct musb_ep *musb_ep;
1338 struct musb_request *request;
1341 unsigned long lockflags;
1348 musb_ep = to_musb_ep(ep);
1349 musb = musb_ep->musb;
1351 request = to_musb_request(req);
1352 request->musb = musb;
1354 if (request->ep != musb_ep)
1357 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1359 /* request is mine now... */
1360 request->request.actual = 0;
1361 request->request.status = -EINPROGRESS;
1362 request->epnum = musb_ep->current_epnum;
1363 request->tx = musb_ep->is_in;
1365 map_dma_buffer(request, musb, musb_ep);
1367 spin_lock_irqsave(&musb->lock, lockflags);
1369 /* don't queue if the ep is down */
1370 if (!musb_ep->desc) {
1371 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1372 req, ep->name, "disabled");
1373 status = -ESHUTDOWN;
1377 /* add request to the list */
1378 list_add_tail(&request->list, &musb_ep->req_list);
1380 /* it this is the head of the queue, start i/o ... */
1381 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1382 musb_ep_restart(musb, request);
1385 spin_unlock_irqrestore(&musb->lock, lockflags);
1389 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1391 struct musb_ep *musb_ep = to_musb_ep(ep);
1392 struct musb_request *req = to_musb_request(request);
1393 struct musb_request *r;
1394 unsigned long flags;
1396 struct musb *musb = musb_ep->musb;
1398 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1401 spin_lock_irqsave(&musb->lock, flags);
1403 list_for_each_entry(r, &musb_ep->req_list, list) {
1408 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1413 /* if the hardware doesn't have the request, easy ... */
1414 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1415 musb_g_giveback(musb_ep, request, -ECONNRESET);
1417 /* ... else abort the dma transfer ... */
1418 else if (is_dma_capable() && musb_ep->dma) {
1419 struct dma_controller *c = musb->dma_controller;
1421 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1422 if (c->channel_abort)
1423 status = c->channel_abort(musb_ep->dma);
1427 musb_g_giveback(musb_ep, request, -ECONNRESET);
1429 /* NOTE: by sticking to easily tested hardware/driver states,
1430 * we leave counting of in-flight packets imprecise.
1432 musb_g_giveback(musb_ep, request, -ECONNRESET);
1436 spin_unlock_irqrestore(&musb->lock, flags);
1441 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1442 * data but will queue requests.
1444 * exported to ep0 code
1446 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1448 struct musb_ep *musb_ep = to_musb_ep(ep);
1449 u8 epnum = musb_ep->current_epnum;
1450 struct musb *musb = musb_ep->musb;
1451 void __iomem *epio = musb->endpoints[epnum].regs;
1452 void __iomem *mbase;
1453 unsigned long flags;
1455 struct musb_request *request;
1460 mbase = musb->mregs;
1462 spin_lock_irqsave(&musb->lock, flags);
1464 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1469 musb_ep_select(mbase, epnum);
1471 request = next_request(musb_ep);
1474 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1479 /* Cannot portably stall with non-empty FIFO */
1480 if (musb_ep->is_in) {
1481 csr = musb_readw(epio, MUSB_TXCSR);
1482 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1483 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1489 musb_ep->wedged = 0;
1491 /* set/clear the stall and toggle bits */
1492 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1493 if (musb_ep->is_in) {
1494 csr = musb_readw(epio, MUSB_TXCSR);
1495 csr |= MUSB_TXCSR_P_WZC_BITS
1496 | MUSB_TXCSR_CLRDATATOG;
1498 csr |= MUSB_TXCSR_P_SENDSTALL;
1500 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1501 | MUSB_TXCSR_P_SENTSTALL);
1502 csr &= ~MUSB_TXCSR_TXPKTRDY;
1503 musb_writew(epio, MUSB_TXCSR, csr);
1505 csr = musb_readw(epio, MUSB_RXCSR);
1506 csr |= MUSB_RXCSR_P_WZC_BITS
1507 | MUSB_RXCSR_FLUSHFIFO
1508 | MUSB_RXCSR_CLRDATATOG;
1510 csr |= MUSB_RXCSR_P_SENDSTALL;
1512 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1513 | MUSB_RXCSR_P_SENTSTALL);
1514 musb_writew(epio, MUSB_RXCSR, csr);
1517 /* maybe start the first request in the queue */
1518 if (!musb_ep->busy && !value && request) {
1519 dev_dbg(musb->controller, "restarting the request\n");
1520 musb_ep_restart(musb, request);
1524 spin_unlock_irqrestore(&musb->lock, flags);
1529 * Sets the halt feature with the clear requests ignored
1531 static int musb_gadget_set_wedge(struct usb_ep *ep)
1533 struct musb_ep *musb_ep = to_musb_ep(ep);
1538 musb_ep->wedged = 1;
1540 return usb_ep_set_halt(ep);
1543 static int musb_gadget_fifo_status(struct usb_ep *ep)
1545 struct musb_ep *musb_ep = to_musb_ep(ep);
1546 void __iomem *epio = musb_ep->hw_ep->regs;
1547 int retval = -EINVAL;
1549 if (musb_ep->desc && !musb_ep->is_in) {
1550 struct musb *musb = musb_ep->musb;
1551 int epnum = musb_ep->current_epnum;
1552 void __iomem *mbase = musb->mregs;
1553 unsigned long flags;
1555 spin_lock_irqsave(&musb->lock, flags);
1557 musb_ep_select(mbase, epnum);
1558 /* FIXME return zero unless RXPKTRDY is set */
1559 retval = musb_readw(epio, MUSB_RXCOUNT);
1561 spin_unlock_irqrestore(&musb->lock, flags);
1566 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1568 struct musb_ep *musb_ep = to_musb_ep(ep);
1569 struct musb *musb = musb_ep->musb;
1570 u8 epnum = musb_ep->current_epnum;
1571 void __iomem *epio = musb->endpoints[epnum].regs;
1572 void __iomem *mbase;
1573 unsigned long flags;
1576 mbase = musb->mregs;
1578 spin_lock_irqsave(&musb->lock, flags);
1579 musb_ep_select(mbase, (u8) epnum);
1581 /* disable interrupts */
1582 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum));
1584 if (musb_ep->is_in) {
1585 csr = musb_readw(epio, MUSB_TXCSR);
1586 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1587 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1589 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1590 * to interrupt current FIFO loading, but not flushing
1591 * the already loaded ones.
1593 csr &= ~MUSB_TXCSR_TXPKTRDY;
1594 musb_writew(epio, MUSB_TXCSR, csr);
1595 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1596 musb_writew(epio, MUSB_TXCSR, csr);
1599 csr = musb_readw(epio, MUSB_RXCSR);
1600 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1601 musb_writew(epio, MUSB_RXCSR, csr);
1602 musb_writew(epio, MUSB_RXCSR, csr);
1605 /* re-enable interrupt */
1606 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe);
1607 spin_unlock_irqrestore(&musb->lock, flags);
1610 static const struct usb_ep_ops musb_ep_ops = {
1611 .enable = musb_gadget_enable,
1612 .disable = musb_gadget_disable,
1613 .alloc_request = musb_alloc_request,
1614 .free_request = musb_free_request,
1615 .queue = musb_gadget_queue,
1616 .dequeue = musb_gadget_dequeue,
1617 .set_halt = musb_gadget_set_halt,
1618 .set_wedge = musb_gadget_set_wedge,
1619 .fifo_status = musb_gadget_fifo_status,
1620 .fifo_flush = musb_gadget_fifo_flush
1623 /* ----------------------------------------------------------------------- */
1625 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1627 struct musb *musb = gadget_to_musb(gadget);
1629 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1632 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1634 struct musb *musb = gadget_to_musb(gadget);
1635 void __iomem *mregs = musb->mregs;
1636 unsigned long flags;
1637 int status = -EINVAL;
1641 spin_lock_irqsave(&musb->lock, flags);
1643 switch (musb->xceiv->state) {
1644 case OTG_STATE_B_PERIPHERAL:
1645 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1646 * that's part of the standard usb 1.1 state machine, and
1647 * doesn't affect OTG transitions.
1649 if (musb->may_wakeup && musb->is_suspended)
1652 case OTG_STATE_B_IDLE:
1653 /* Start SRP ... OTG not required. */
1654 devctl = musb_readb(mregs, MUSB_DEVCTL);
1655 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1656 devctl |= MUSB_DEVCTL_SESSION;
1657 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1658 devctl = musb_readb(mregs, MUSB_DEVCTL);
1660 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1661 devctl = musb_readb(mregs, MUSB_DEVCTL);
1666 while (devctl & MUSB_DEVCTL_SESSION) {
1667 devctl = musb_readb(mregs, MUSB_DEVCTL);
1672 spin_unlock_irqrestore(&musb->lock, flags);
1673 otg_start_srp(musb->xceiv->otg);
1674 spin_lock_irqsave(&musb->lock, flags);
1676 /* Block idling for at least 1s */
1677 musb_platform_try_idle(musb,
1678 jiffies + msecs_to_jiffies(1 * HZ));
1683 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1684 otg_state_string(musb->xceiv->state));
1690 power = musb_readb(mregs, MUSB_POWER);
1691 power |= MUSB_POWER_RESUME;
1692 musb_writeb(mregs, MUSB_POWER, power);
1693 dev_dbg(musb->controller, "issue wakeup\n");
1695 /* FIXME do this next chunk in a timer callback, no udelay */
1698 power = musb_readb(mregs, MUSB_POWER);
1699 power &= ~MUSB_POWER_RESUME;
1700 musb_writeb(mregs, MUSB_POWER, power);
1702 spin_unlock_irqrestore(&musb->lock, flags);
1707 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1709 struct musb *musb = gadget_to_musb(gadget);
1711 musb->is_self_powered = !!is_selfpowered;
1715 static void musb_pullup(struct musb *musb, int is_on)
1719 power = musb_readb(musb->mregs, MUSB_POWER);
1721 power |= MUSB_POWER_SOFTCONN;
1723 power &= ~MUSB_POWER_SOFTCONN;
1725 /* FIXME if on, HdrcStart; if off, HdrcStop */
1727 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1728 is_on ? "on" : "off");
1729 musb_writeb(musb->mregs, MUSB_POWER, power);
1733 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1735 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1738 * FIXME iff driver's softconnect flag is set (as it is during probe,
1739 * though that can clear it), just musb_pullup().
1746 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1748 struct musb *musb = gadget_to_musb(gadget);
1750 if (!musb->xceiv->set_power)
1752 return usb_phy_set_power(musb->xceiv, mA);
1755 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1757 struct musb *musb = gadget_to_musb(gadget);
1758 unsigned long flags;
1762 pm_runtime_get_sync(musb->controller);
1764 /* NOTE: this assumes we are sensing vbus; we'd rather
1765 * not pullup unless the B-session is active.
1767 spin_lock_irqsave(&musb->lock, flags);
1768 if (is_on != musb->softconnect) {
1769 musb->softconnect = is_on;
1770 musb_pullup(musb, is_on);
1772 spin_unlock_irqrestore(&musb->lock, flags);
1774 pm_runtime_put(musb->controller);
1779 static int musb_gadget_start(struct usb_gadget *g,
1780 struct usb_gadget_driver *driver);
1781 static int musb_gadget_stop(struct usb_gadget *g,
1782 struct usb_gadget_driver *driver);
1784 static const struct usb_gadget_ops musb_gadget_operations = {
1785 .get_frame = musb_gadget_get_frame,
1786 .wakeup = musb_gadget_wakeup,
1787 .set_selfpowered = musb_gadget_set_self_powered,
1788 /* .vbus_session = musb_gadget_vbus_session, */
1789 .vbus_draw = musb_gadget_vbus_draw,
1790 .pullup = musb_gadget_pullup,
1791 .udc_start = musb_gadget_start,
1792 .udc_stop = musb_gadget_stop,
1795 /* ----------------------------------------------------------------------- */
1799 /* Only this registration code "knows" the rule (from USB standards)
1800 * about there being only one external upstream port. It assumes
1801 * all peripheral ports are external...
1804 static void musb_gadget_release(struct device *dev)
1806 /* kref_put(WHAT) */
1807 dev_dbg(dev, "%s\n", __func__);
1812 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1814 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1816 memset(ep, 0, sizeof *ep);
1818 ep->current_epnum = epnum;
1823 INIT_LIST_HEAD(&ep->req_list);
1825 sprintf(ep->name, "ep%d%s", epnum,
1826 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1827 is_in ? "in" : "out"));
1828 ep->end_point.name = ep->name;
1829 INIT_LIST_HEAD(&ep->end_point.ep_list);
1831 ep->end_point.maxpacket = 64;
1832 ep->end_point.ops = &musb_g_ep0_ops;
1833 musb->g.ep0 = &ep->end_point;
1836 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1838 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1839 ep->end_point.ops = &musb_ep_ops;
1840 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1845 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1846 * to the rest of the driver state.
1848 static inline void musb_g_init_endpoints(struct musb *musb)
1851 struct musb_hw_ep *hw_ep;
1854 /* initialize endpoint list just once */
1855 INIT_LIST_HEAD(&(musb->g.ep_list));
1857 for (epnum = 0, hw_ep = musb->endpoints;
1858 epnum < musb->nr_endpoints;
1860 if (hw_ep->is_shared_fifo /* || !epnum */) {
1861 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1864 if (hw_ep->max_packet_sz_tx) {
1865 init_peripheral_ep(musb, &hw_ep->ep_in,
1869 if (hw_ep->max_packet_sz_rx) {
1870 init_peripheral_ep(musb, &hw_ep->ep_out,
1878 /* called once during driver setup to initialize and link into
1879 * the driver model; memory is zeroed.
1881 int musb_gadget_setup(struct musb *musb)
1885 /* REVISIT minor race: if (erroneously) setting up two
1886 * musb peripherals at the same time, only the bus lock
1890 musb->g.ops = &musb_gadget_operations;
1891 musb->g.max_speed = USB_SPEED_HIGH;
1892 musb->g.speed = USB_SPEED_UNKNOWN;
1894 /* this "gadget" abstracts/virtualizes the controller */
1895 dev_set_name(&musb->g.dev, "gadget");
1896 musb->g.dev.parent = musb->controller;
1897 musb->g.dev.dma_mask = musb->controller->dma_mask;
1898 musb->g.dev.release = musb_gadget_release;
1899 musb->g.name = musb_driver_name;
1903 musb_g_init_endpoints(musb);
1905 musb->is_active = 0;
1906 musb_platform_try_idle(musb, 0);
1908 status = device_register(&musb->g.dev);
1910 put_device(&musb->g.dev);
1913 status = usb_add_gadget_udc(musb->controller, &musb->g);
1919 musb->g.dev.parent = NULL;
1920 device_unregister(&musb->g.dev);
1924 void musb_gadget_cleanup(struct musb *musb)
1926 usb_del_gadget_udc(&musb->g);
1927 if (musb->g.dev.parent)
1928 device_unregister(&musb->g.dev);
1932 * Register the gadget driver. Used by gadget drivers when
1933 * registering themselves with the controller.
1935 * -EINVAL something went wrong (not driver)
1936 * -EBUSY another gadget is already using the controller
1937 * -ENOMEM no memory to perform the operation
1939 * @param driver the gadget driver
1940 * @return <0 if error, 0 if everything is fine
1942 static int musb_gadget_start(struct usb_gadget *g,
1943 struct usb_gadget_driver *driver)
1945 struct musb *musb = gadget_to_musb(g);
1946 struct usb_otg *otg = musb->xceiv->otg;
1947 struct usb_hcd *hcd = musb_to_hcd(musb);
1948 unsigned long flags;
1951 if (driver->max_speed < USB_SPEED_HIGH) {
1956 pm_runtime_get_sync(musb->controller);
1958 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1960 musb->softconnect = 0;
1961 musb->gadget_driver = driver;
1963 spin_lock_irqsave(&musb->lock, flags);
1964 musb->is_active = 1;
1966 otg_set_peripheral(otg, &musb->g);
1967 musb->xceiv->state = OTG_STATE_B_IDLE;
1968 spin_unlock_irqrestore(&musb->lock, flags);
1970 /* REVISIT: funcall to other code, which also
1971 * handles power budgeting ... this way also
1972 * ensures HdrcStart is indirectly called.
1974 retval = usb_add_hcd(hcd, 0, 0);
1976 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1980 if ((musb->xceiv->last_event == USB_EVENT_ID)
1982 otg_set_vbus(otg, 1);
1984 hcd->self.uses_pio_for_control = 1;
1986 if (musb->xceiv->last_event == USB_EVENT_NONE)
1987 pm_runtime_put(musb->controller);
1995 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1998 struct musb_hw_ep *hw_ep;
2000 /* don't disconnect if it's not connected */
2001 if (musb->g.speed == USB_SPEED_UNKNOWN)
2004 musb->g.speed = USB_SPEED_UNKNOWN;
2006 /* deactivate the hardware */
2007 if (musb->softconnect) {
2008 musb->softconnect = 0;
2009 musb_pullup(musb, 0);
2013 /* killing any outstanding requests will quiesce the driver;
2014 * then report disconnect
2017 for (i = 0, hw_ep = musb->endpoints;
2018 i < musb->nr_endpoints;
2020 musb_ep_select(musb->mregs, i);
2021 if (hw_ep->is_shared_fifo /* || !epnum */) {
2022 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2024 if (hw_ep->max_packet_sz_tx)
2025 nuke(&hw_ep->ep_in, -ESHUTDOWN);
2026 if (hw_ep->max_packet_sz_rx)
2027 nuke(&hw_ep->ep_out, -ESHUTDOWN);
2034 * Unregister the gadget driver. Used by gadget drivers when
2035 * unregistering themselves from the controller.
2037 * @param driver the gadget driver to unregister
2039 static int musb_gadget_stop(struct usb_gadget *g,
2040 struct usb_gadget_driver *driver)
2042 struct musb *musb = gadget_to_musb(g);
2043 unsigned long flags;
2045 if (musb->xceiv->last_event == USB_EVENT_NONE)
2046 pm_runtime_get_sync(musb->controller);
2049 * REVISIT always use otg_set_peripheral() here too;
2050 * this needs to shut down the OTG engine.
2053 spin_lock_irqsave(&musb->lock, flags);
2055 musb_hnp_stop(musb);
2057 (void) musb_gadget_vbus_draw(&musb->g, 0);
2059 musb->xceiv->state = OTG_STATE_UNDEFINED;
2060 stop_activity(musb, driver);
2061 otg_set_peripheral(musb->xceiv->otg, NULL);
2063 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2065 musb->is_active = 0;
2066 musb_platform_try_idle(musb, 0);
2067 spin_unlock_irqrestore(&musb->lock, flags);
2069 usb_remove_hcd(musb_to_hcd(musb));
2071 * FIXME we need to be able to register another
2072 * gadget driver here and have everything work;
2073 * that currently misbehaves.
2076 pm_runtime_put(musb->controller);
2081 /* ----------------------------------------------------------------------- */
2083 /* lifecycle operations called through plat_uds.c */
2085 void musb_g_resume(struct musb *musb)
2087 musb->is_suspended = 0;
2088 switch (musb->xceiv->state) {
2089 case OTG_STATE_B_IDLE:
2091 case OTG_STATE_B_WAIT_ACON:
2092 case OTG_STATE_B_PERIPHERAL:
2093 musb->is_active = 1;
2094 if (musb->gadget_driver && musb->gadget_driver->resume) {
2095 spin_unlock(&musb->lock);
2096 musb->gadget_driver->resume(&musb->g);
2097 spin_lock(&musb->lock);
2101 WARNING("unhandled RESUME transition (%s)\n",
2102 otg_state_string(musb->xceiv->state));
2106 /* called when SOF packets stop for 3+ msec */
2107 void musb_g_suspend(struct musb *musb)
2111 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2112 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2114 switch (musb->xceiv->state) {
2115 case OTG_STATE_B_IDLE:
2116 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2117 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2119 case OTG_STATE_B_PERIPHERAL:
2120 musb->is_suspended = 1;
2121 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2122 spin_unlock(&musb->lock);
2123 musb->gadget_driver->suspend(&musb->g);
2124 spin_lock(&musb->lock);
2128 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2129 * A_PERIPHERAL may need care too
2131 WARNING("unhandled SUSPEND transition (%s)\n",
2132 otg_state_string(musb->xceiv->state));
2136 /* Called during SRP */
2137 void musb_g_wakeup(struct musb *musb)
2139 musb_gadget_wakeup(&musb->g);
2142 /* called when VBUS drops below session threshold, and in other cases */
2143 void musb_g_disconnect(struct musb *musb)
2145 void __iomem *mregs = musb->mregs;
2146 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2148 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2151 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2153 /* don't draw vbus until new b-default session */
2154 (void) musb_gadget_vbus_draw(&musb->g, 0);
2156 musb->g.speed = USB_SPEED_UNKNOWN;
2157 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2158 spin_unlock(&musb->lock);
2159 musb->gadget_driver->disconnect(&musb->g);
2160 spin_lock(&musb->lock);
2163 switch (musb->xceiv->state) {
2165 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2166 otg_state_string(musb->xceiv->state));
2167 musb->xceiv->state = OTG_STATE_A_IDLE;
2168 MUSB_HST_MODE(musb);
2170 case OTG_STATE_A_PERIPHERAL:
2171 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2172 MUSB_HST_MODE(musb);
2174 case OTG_STATE_B_WAIT_ACON:
2175 case OTG_STATE_B_HOST:
2176 case OTG_STATE_B_PERIPHERAL:
2177 case OTG_STATE_B_IDLE:
2178 musb->xceiv->state = OTG_STATE_B_IDLE;
2180 case OTG_STATE_B_SRP_INIT:
2184 musb->is_active = 0;
2187 void musb_g_reset(struct musb *musb)
2188 __releases(musb->lock)
2189 __acquires(musb->lock)
2191 void __iomem *mbase = musb->mregs;
2192 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2195 dev_dbg(musb->controller, "<== %s driver '%s'\n",
2196 (devctl & MUSB_DEVCTL_BDEVICE)
2197 ? "B-Device" : "A-Device",
2199 ? musb->gadget_driver->driver.name
2203 /* report disconnect, if we didn't already (flushing EP state) */
2204 if (musb->g.speed != USB_SPEED_UNKNOWN)
2205 musb_g_disconnect(musb);
2208 else if (devctl & MUSB_DEVCTL_HR)
2209 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2212 /* what speed did we negotiate? */
2213 power = musb_readb(mbase, MUSB_POWER);
2214 musb->g.speed = (power & MUSB_POWER_HSMODE)
2215 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2217 /* start in USB_STATE_DEFAULT */
2218 musb->is_active = 1;
2219 musb->is_suspended = 0;
2220 MUSB_DEV_MODE(musb);
2222 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2224 musb->may_wakeup = 0;
2225 musb->g.b_hnp_enable = 0;
2226 musb->g.a_alt_hnp_support = 0;
2227 musb->g.a_hnp_support = 0;
2229 /* Normal reset, as B-Device;
2230 * or else after HNP, as A-Device
2232 if (devctl & MUSB_DEVCTL_BDEVICE) {
2233 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2234 musb->g.is_a_peripheral = 0;
2236 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2237 musb->g.is_a_peripheral = 1;
2240 /* start with default limits on VBUS power draw */
2241 (void) musb_gadget_vbus_draw(&musb->g, 8);