2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
103 #include "musb_core.h"
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111 #define MUSB_VERSION "6.0"
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124 /*-------------------------------------------------------------------------*/
126 static inline struct musb *dev_to_musb(struct device *dev)
128 return dev_get_drvdata(dev);
131 /*-------------------------------------------------------------------------*/
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
136 void __iomem *addr = phy->io_priv;
142 pm_runtime_get_sync(phy->io_dev);
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173 pm_runtime_put(phy->io_dev);
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
180 void __iomem *addr = phy->io_priv;
186 pm_runtime_get_sync(phy->io_dev);
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211 pm_runtime_put(phy->io_dev);
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
225 /*-------------------------------------------------------------------------*/
227 static u32 musb_default_fifo_offset(u8 epnum)
229 return 0x20 + (epnum * 4);
232 /* "flat" mapping: each endpoint has its own i/o address */
233 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
237 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239 return 0x100 + (0x10 * epnum) + offset;
242 /* "indexed" mapping: INDEX register controls register bank select */
243 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245 musb_writeb(mbase, MUSB_INDEX, epnum);
248 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250 return 0x10 + offset;
253 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
255 return __raw_readb(addr + offset);
258 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
260 __raw_writeb(data, addr + offset);
263 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
265 return __raw_readw(addr + offset);
268 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
270 __raw_writew(data, addr + offset);
273 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
275 return __raw_readl(addr + offset);
278 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
280 __raw_writel(data, addr + offset);
284 * Load an endpoint's FIFO
286 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
289 struct musb *musb = hw_ep->musb;
290 void __iomem *fifo = hw_ep->fifo;
292 if (unlikely(len == 0))
297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
298 'T', hw_ep->epnum, fifo, len, src);
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
307 iowrite32_rep(fifo, src + index, len >> 2);
308 index += len & ~0x03;
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
316 iowrite16_rep(fifo, src + index, len >> 1);
317 index += len & ~0x01;
321 musb_writeb(fifo, 0, src[index]);
324 iowrite8_rep(fifo, src, len);
329 * Unload an endpoint's FIFO
331 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
333 struct musb *musb = hw_ep->musb;
334 void __iomem *fifo = hw_ep->fifo;
336 if (unlikely(len == 0))
339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
340 'R', hw_ep->epnum, fifo, len, dst);
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
349 ioread32_rep(fifo, dst, len >> 2);
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
358 ioread16_rep(fifo, dst, len >> 1);
363 dst[index] = musb_readb(fifo, 0);
366 ioread8_rep(fifo, dst, len);
371 * Old style IO functions
373 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374 EXPORT_SYMBOL_GPL(musb_readb);
376 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377 EXPORT_SYMBOL_GPL(musb_writeb);
379 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readw);
382 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383 EXPORT_SYMBOL_GPL(musb_writew);
385 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readl);
388 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389 EXPORT_SYMBOL_GPL(musb_writel);
392 * New style IO functions
394 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
399 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
404 /*-------------------------------------------------------------------------*/
406 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
407 static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
423 /* implicit CRC16 then EOP to end */
426 void musb_load_testpacket(struct musb *musb)
428 void __iomem *regs = musb->endpoints[0].regs;
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
436 /*-------------------------------------------------------------------------*/
439 * Handles OTG hnp timeouts, such as b_ase0_brst
441 static void musb_otg_timer_func(unsigned long data)
443 struct musb *musb = (struct musb *)data;
446 spin_lock_irqsave(&musb->lock, flags);
447 switch (musb->xceiv->otg->state) {
448 case OTG_STATE_B_WAIT_ACON:
449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
450 musb_g_disconnect(musb);
451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
454 case OTG_STATE_A_SUSPEND:
455 case OTG_STATE_A_WAIT_BCON:
456 dev_dbg(musb->controller, "HNP: %s timeout\n",
457 usb_otg_state_string(musb->xceiv->otg->state));
458 musb_platform_set_vbus(musb, 0);
459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
463 usb_otg_state_string(musb->xceiv->otg->state));
465 spin_unlock_irqrestore(&musb->lock, flags);
469 * Stops the HNP transition. Caller must take care of locking.
471 void musb_hnp_stop(struct musb *musb)
473 struct usb_hcd *hcd = musb->hcd;
474 void __iomem *mbase = musb->mregs;
477 dev_dbg(musb->controller, "HNP: stop from %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
480 switch (musb->xceiv->otg->state) {
481 case OTG_STATE_A_PERIPHERAL:
482 musb_g_disconnect(musb);
483 dev_dbg(musb->controller, "HNP: back to %s\n",
484 usb_otg_state_string(musb->xceiv->otg->state));
486 case OTG_STATE_B_HOST:
487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
489 hcd->self.is_b_host = 0;
490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
510 static void musb_disable_interrupts(struct musb *musb);
511 static void musb_recover_from_babble(struct musb *musb);
514 * Interrupt Service Routine to record USB "global" interrupts.
515 * Since these do not happen often and signify things of
516 * paramount importance, it seems OK to check them individually;
517 * the order of the tests is specified in the manual
519 * @param musb instance pointer
520 * @param int_usb register contents
525 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
528 irqreturn_t handled = IRQ_NONE;
530 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
533 /* in host mode, the peripheral may issue remote wakeup.
534 * in peripheral mode, the host may resume the link.
535 * spurious RESUME irqs happen too, paired with SUSPEND.
537 if (int_usb & MUSB_INTR_RESUME) {
538 handled = IRQ_HANDLED;
539 dev_dbg(musb->controller, "RESUME (%s)\n",
540 usb_otg_state_string(musb->xceiv->otg->state));
542 if (devctl & MUSB_DEVCTL_HM) {
543 switch (musb->xceiv->otg->state) {
544 case OTG_STATE_A_SUSPEND:
545 /* remote wakeup? later, GetPortStatus
546 * will stop RESUME signaling
549 musb->port1_status |=
550 (USB_PORT_STAT_C_SUSPEND << 16)
551 | MUSB_PORT_STAT_RESUME;
552 musb->rh_timer = jiffies
553 + msecs_to_jiffies(20);
554 musb->need_finish_resume = 1;
556 musb->xceiv->otg->state = OTG_STATE_A_HOST;
558 musb_host_resume_root_hub(musb);
560 case OTG_STATE_B_WAIT_ACON:
561 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
566 WARNING("bogus %s RESUME (%s)\n",
568 usb_otg_state_string(musb->xceiv->otg->state));
571 switch (musb->xceiv->otg->state) {
572 case OTG_STATE_A_SUSPEND:
573 /* possibly DISCONNECT is upcoming */
574 musb->xceiv->otg->state = OTG_STATE_A_HOST;
575 musb_host_resume_root_hub(musb);
577 case OTG_STATE_B_WAIT_ACON:
578 case OTG_STATE_B_PERIPHERAL:
579 /* disconnect while suspended? we may
580 * not get a disconnect irq...
582 if ((devctl & MUSB_DEVCTL_VBUS)
583 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
585 musb->int_usb |= MUSB_INTR_DISCONNECT;
586 musb->int_usb &= ~MUSB_INTR_SUSPEND;
591 case OTG_STATE_B_IDLE:
592 musb->int_usb &= ~MUSB_INTR_SUSPEND;
595 WARNING("bogus %s RESUME (%s)\n",
597 usb_otg_state_string(musb->xceiv->otg->state));
602 /* see manual for the order of the tests */
603 if (int_usb & MUSB_INTR_SESSREQ) {
604 void __iomem *mbase = musb->mregs;
606 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
607 && (devctl & MUSB_DEVCTL_BDEVICE)) {
608 dev_dbg(musb->controller, "SessReq while on B state\n");
612 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
613 usb_otg_state_string(musb->xceiv->otg->state));
615 /* IRQ arrives from ID pin sense or (later, if VBUS power
616 * is removed) SRP. responses are time critical:
617 * - turn on VBUS (with silicon-specific mechanism)
618 * - go through A_WAIT_VRISE
619 * - ... to A_WAIT_BCON.
620 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
622 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
623 musb->ep0_stage = MUSB_EP0_START;
624 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
626 musb_platform_set_vbus(musb, 1);
628 handled = IRQ_HANDLED;
631 if (int_usb & MUSB_INTR_VBUSERROR) {
634 /* During connection as an A-Device, we may see a short
635 * current spikes causing voltage drop, because of cable
636 * and peripheral capacitance combined with vbus draw.
637 * (So: less common with truly self-powered devices, where
638 * vbus doesn't act like a power supply.)
640 * Such spikes are short; usually less than ~500 usec, max
641 * of ~2 msec. That is, they're not sustained overcurrent
642 * errors, though they're reported using VBUSERROR irqs.
644 * Workarounds: (a) hardware: use self powered devices.
645 * (b) software: ignore non-repeated VBUS errors.
647 * REVISIT: do delays from lots of DEBUG_KERNEL checks
648 * make trouble here, keeping VBUS < 4.4V ?
650 switch (musb->xceiv->otg->state) {
651 case OTG_STATE_A_HOST:
652 /* recovery is dicey once we've gotten past the
653 * initial stages of enumeration, but if VBUS
654 * stayed ok at the other end of the link, and
655 * another reset is due (at least for high speed,
656 * to redo the chirp etc), it might work OK...
658 case OTG_STATE_A_WAIT_BCON:
659 case OTG_STATE_A_WAIT_VRISE:
660 if (musb->vbuserr_retry) {
661 void __iomem *mbase = musb->mregs;
663 musb->vbuserr_retry--;
665 devctl |= MUSB_DEVCTL_SESSION;
666 musb_writeb(mbase, MUSB_DEVCTL, devctl);
668 musb->port1_status |=
669 USB_PORT_STAT_OVERCURRENT
670 | (USB_PORT_STAT_C_OVERCURRENT << 16);
677 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
678 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
679 usb_otg_state_string(musb->xceiv->otg->state),
682 switch (devctl & MUSB_DEVCTL_VBUS) {
683 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
684 s = "<SessEnd"; break;
685 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
686 s = "<AValid"; break;
687 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
688 s = "<VBusValid"; break;
689 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
693 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
696 /* go through A_WAIT_VFALL then start a new session */
698 musb_platform_set_vbus(musb, 0);
699 handled = IRQ_HANDLED;
702 if (int_usb & MUSB_INTR_SUSPEND) {
703 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
704 usb_otg_state_string(musb->xceiv->otg->state), devctl);
705 handled = IRQ_HANDLED;
707 switch (musb->xceiv->otg->state) {
708 case OTG_STATE_A_PERIPHERAL:
709 /* We also come here if the cable is removed, since
710 * this silicon doesn't report ID-no-longer-grounded.
712 * We depend on T(a_wait_bcon) to shut us down, and
713 * hope users don't do anything dicey during this
714 * undesired detour through A_WAIT_BCON.
717 musb_host_resume_root_hub(musb);
718 musb_root_disconnect(musb);
719 musb_platform_try_idle(musb, jiffies
720 + msecs_to_jiffies(musb->a_wait_bcon
721 ? : OTG_TIME_A_WAIT_BCON));
724 case OTG_STATE_B_IDLE:
725 if (!musb->is_active)
727 case OTG_STATE_B_PERIPHERAL:
728 musb_g_suspend(musb);
729 musb->is_active = musb->g.b_hnp_enable;
730 if (musb->is_active) {
731 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
732 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
733 mod_timer(&musb->otg_timer, jiffies
735 OTG_TIME_B_ASE0_BRST));
738 case OTG_STATE_A_WAIT_BCON:
739 if (musb->a_wait_bcon != 0)
740 musb_platform_try_idle(musb, jiffies
741 + msecs_to_jiffies(musb->a_wait_bcon));
743 case OTG_STATE_A_HOST:
744 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
745 musb->is_active = musb->hcd->self.b_hnp_enable;
747 case OTG_STATE_B_HOST:
748 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
749 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
752 /* "should not happen" */
758 if (int_usb & MUSB_INTR_CONNECT) {
759 struct usb_hcd *hcd = musb->hcd;
761 handled = IRQ_HANDLED;
764 musb->ep0_stage = MUSB_EP0_START;
766 musb->intrtxe = musb->epmask;
767 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
768 musb->intrrxe = musb->epmask & 0xfffe;
769 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
770 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
771 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
772 |USB_PORT_STAT_HIGH_SPEED
773 |USB_PORT_STAT_ENABLE
775 musb->port1_status |= USB_PORT_STAT_CONNECTION
776 |(USB_PORT_STAT_C_CONNECTION << 16);
778 /* high vs full speed is just a guess until after reset */
779 if (devctl & MUSB_DEVCTL_LSDEV)
780 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
782 /* indicate new connection to OTG machine */
783 switch (musb->xceiv->otg->state) {
784 case OTG_STATE_B_PERIPHERAL:
785 if (int_usb & MUSB_INTR_SUSPEND) {
786 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
787 int_usb &= ~MUSB_INTR_SUSPEND;
790 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
792 case OTG_STATE_B_WAIT_ACON:
793 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
795 musb->xceiv->otg->state = OTG_STATE_B_HOST;
797 musb->hcd->self.is_b_host = 1;
798 del_timer(&musb->otg_timer);
801 if ((devctl & MUSB_DEVCTL_VBUS)
802 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
803 musb->xceiv->otg->state = OTG_STATE_A_HOST;
805 hcd->self.is_b_host = 0;
810 musb_host_poke_root_hub(musb);
812 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
813 usb_otg_state_string(musb->xceiv->otg->state), devctl);
816 if (int_usb & MUSB_INTR_DISCONNECT) {
817 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
818 usb_otg_state_string(musb->xceiv->otg->state),
819 MUSB_MODE(musb), devctl);
820 handled = IRQ_HANDLED;
822 switch (musb->xceiv->otg->state) {
823 case OTG_STATE_A_HOST:
824 case OTG_STATE_A_SUSPEND:
825 musb_host_resume_root_hub(musb);
826 musb_root_disconnect(musb);
827 if (musb->a_wait_bcon != 0)
828 musb_platform_try_idle(musb, jiffies
829 + msecs_to_jiffies(musb->a_wait_bcon));
831 case OTG_STATE_B_HOST:
832 /* REVISIT this behaves for "real disconnect"
833 * cases; make sure the other transitions from
834 * from B_HOST act right too. The B_HOST code
835 * in hnp_stop() is currently not used...
837 musb_root_disconnect(musb);
839 musb->hcd->self.is_b_host = 0;
840 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
842 musb_g_disconnect(musb);
844 case OTG_STATE_A_PERIPHERAL:
846 musb_root_disconnect(musb);
848 case OTG_STATE_B_WAIT_ACON:
850 case OTG_STATE_B_PERIPHERAL:
851 case OTG_STATE_B_IDLE:
852 musb_g_disconnect(musb);
855 WARNING("unhandled DISCONNECT transition (%s)\n",
856 usb_otg_state_string(musb->xceiv->otg->state));
861 /* mentor saves a bit: bus reset and babble share the same irq.
862 * only host sees babble; only peripheral sees bus reset.
864 if (int_usb & MUSB_INTR_RESET) {
865 handled = IRQ_HANDLED;
866 if (devctl & MUSB_DEVCTL_HM) {
867 u8 power = musb_readl(musb->mregs, MUSB_POWER);
870 * Looks like non-HS BABBLE can be ignored, but
871 * HS BABBLE is an error condition.
873 * For HS the solution is to avoid babble in the first
874 * place and fix what caused BABBLE.
876 * When HS BABBLE happens what we can depends on which
877 * platform MUSB is running, because some platforms
878 * implemented proprietary means for 'recovering' from
879 * Babble conditions. One such platform is AM335x. In
880 * most cases, however, the only thing we can do is drop
883 if (power & MUSB_POWER_HSMODE) {
884 dev_err(musb->controller, "Babble\n");
886 if (is_host_active(musb)) {
887 musb_disable_interrupts(musb);
888 musb_recover_from_babble(musb);
892 dev_dbg(musb->controller, "BUS RESET as %s\n",
893 usb_otg_state_string(musb->xceiv->otg->state));
894 switch (musb->xceiv->otg->state) {
895 case OTG_STATE_A_SUSPEND:
898 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
899 /* never use invalid T(a_wait_bcon) */
900 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
901 usb_otg_state_string(musb->xceiv->otg->state),
903 mod_timer(&musb->otg_timer, jiffies
904 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
906 case OTG_STATE_A_PERIPHERAL:
907 del_timer(&musb->otg_timer);
910 case OTG_STATE_B_WAIT_ACON:
911 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
912 usb_otg_state_string(musb->xceiv->otg->state));
913 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 case OTG_STATE_B_IDLE:
917 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
919 case OTG_STATE_B_PERIPHERAL:
923 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
924 usb_otg_state_string(musb->xceiv->otg->state));
930 /* REVISIT ... this would be for multiplexing periodic endpoints, or
931 * supporting transfer phasing to prevent exceeding ISO bandwidth
932 * limits of a given frame or microframe.
934 * It's not needed for peripheral side, which dedicates endpoints;
935 * though it _might_ use SOF irqs for other purposes.
937 * And it's not currently needed for host side, which also dedicates
938 * endpoints, relies on TX/RX interval registers, and isn't claimed
939 * to support ISO transfers yet.
941 if (int_usb & MUSB_INTR_SOF) {
942 void __iomem *mbase = musb->mregs;
943 struct musb_hw_ep *ep;
947 dev_dbg(musb->controller, "START_OF_FRAME\n");
948 handled = IRQ_HANDLED;
950 /* start any periodic Tx transfers waiting for current frame */
951 frame = musb_readw(mbase, MUSB_FRAME);
952 ep = musb->endpoints;
953 for (epnum = 1; (epnum < musb->nr_endpoints)
954 && (musb->epmask >= (1 << epnum));
957 * FIXME handle framecounter wraps (12 bits)
958 * eliminate duplicated StartUrb logic
960 if (ep->dwWaitFrame >= frame) {
962 pr_debug("SOF --> periodic TX%s on %d\n",
963 ep->tx_channel ? " DMA" : "",
966 musb_h_tx_start(musb, epnum);
968 cppi_hostdma_start(musb, epnum);
970 } /* end of for loop */
974 schedule_work(&musb->irq_work);
979 /*-------------------------------------------------------------------------*/
981 static void musb_disable_interrupts(struct musb *musb)
983 void __iomem *mbase = musb->mregs;
986 /* disable interrupts */
987 musb_writeb(mbase, MUSB_INTRUSBE, 0);
989 musb_writew(mbase, MUSB_INTRTXE, 0);
991 musb_writew(mbase, MUSB_INTRRXE, 0);
993 /* flush pending interrupts */
994 temp = musb_readb(mbase, MUSB_INTRUSB);
995 temp = musb_readw(mbase, MUSB_INTRTX);
996 temp = musb_readw(mbase, MUSB_INTRRX);
999 static void musb_enable_interrupts(struct musb *musb)
1001 void __iomem *regs = musb->mregs;
1003 /* Set INT enable registers, enable interrupts */
1004 musb->intrtxe = musb->epmask;
1005 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1006 musb->intrrxe = musb->epmask & 0xfffe;
1007 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1008 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1012 static void musb_generic_disable(struct musb *musb)
1014 void __iomem *mbase = musb->mregs;
1016 musb_disable_interrupts(musb);
1019 musb_writeb(mbase, MUSB_DEVCTL, 0);
1023 * Program the HDRC to start (enable interrupts, dma, etc.).
1025 void musb_start(struct musb *musb)
1027 void __iomem *regs = musb->mregs;
1028 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1030 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1032 musb_enable_interrupts(musb);
1033 musb_writeb(regs, MUSB_TESTMODE, 0);
1035 /* put into basic highspeed mode and start session */
1036 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1038 /* ENSUSPEND wedges tusb */
1039 /* | MUSB_POWER_ENSUSPEND */
1042 musb->is_active = 0;
1043 devctl = musb_readb(regs, MUSB_DEVCTL);
1044 devctl &= ~MUSB_DEVCTL_SESSION;
1046 /* session started after:
1047 * (a) ID-grounded irq, host mode;
1048 * (b) vbus present/connect IRQ, peripheral mode;
1049 * (c) peripheral initiates, using SRP
1051 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1052 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1053 musb->is_active = 1;
1055 devctl |= MUSB_DEVCTL_SESSION;
1058 musb_platform_enable(musb);
1059 musb_writeb(regs, MUSB_DEVCTL, devctl);
1063 * Make the HDRC stop (disable interrupts, etc.);
1064 * reversible by musb_start
1065 * called on gadget driver unregister
1066 * with controller locked, irqs blocked
1067 * acts as a NOP unless some role activated the hardware
1069 void musb_stop(struct musb *musb)
1071 /* stop IRQs, timers, ... */
1072 musb_platform_disable(musb);
1073 musb_generic_disable(musb);
1074 dev_dbg(musb->controller, "HDRC disabled\n");
1077 * - mark host and/or peripheral drivers unusable/inactive
1078 * - disable DMA (and enable it in HdrcStart)
1079 * - make sure we can musb_start() after musb_stop(); with
1080 * OTG mode, gadget driver module rmmod/modprobe cycles that
1083 musb_platform_try_idle(musb, 0);
1086 static void musb_shutdown(struct platform_device *pdev)
1088 struct musb *musb = dev_to_musb(&pdev->dev);
1089 unsigned long flags;
1091 pm_runtime_get_sync(musb->controller);
1093 musb_host_cleanup(musb);
1094 musb_gadget_cleanup(musb);
1096 spin_lock_irqsave(&musb->lock, flags);
1097 musb_platform_disable(musb);
1098 musb_generic_disable(musb);
1099 spin_unlock_irqrestore(&musb->lock, flags);
1101 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1102 musb_platform_exit(musb);
1104 pm_runtime_put(musb->controller);
1105 /* FIXME power down */
1109 /*-------------------------------------------------------------------------*/
1112 * The silicon either has hard-wired endpoint configurations, or else
1113 * "dynamic fifo" sizing. The driver has support for both, though at this
1114 * writing only the dynamic sizing is very well tested. Since we switched
1115 * away from compile-time hardware parameters, we can no longer rely on
1116 * dead code elimination to leave only the relevant one in the object file.
1118 * We don't currently use dynamic fifo setup capability to do anything
1119 * more than selecting one of a bunch of predefined configurations.
1121 static ushort fifo_mode;
1123 /* "modprobe ... fifo_mode=1" etc */
1124 module_param(fifo_mode, ushort, 0);
1125 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1128 * tables defining fifo_mode values. define more if you like.
1129 * for host side, make sure both halves of ep1 are set up.
1132 /* mode 0 - fits in 2KB */
1133 static struct musb_fifo_cfg mode_0_cfg[] = {
1134 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1137 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1138 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1141 /* mode 1 - fits in 4KB */
1142 static struct musb_fifo_cfg mode_1_cfg[] = {
1143 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1144 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1145 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1146 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1147 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1150 /* mode 2 - fits in 4KB */
1151 static struct musb_fifo_cfg mode_2_cfg[] = {
1152 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1153 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1154 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1155 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1156 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1157 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1160 /* mode 3 - fits in 4KB */
1161 static struct musb_fifo_cfg mode_3_cfg[] = {
1162 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1163 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1164 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1165 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1166 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1167 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1170 /* mode 4 - fits in 16KB */
1171 static struct musb_fifo_cfg mode_4_cfg[] = {
1172 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1173 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1174 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1175 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1176 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1177 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1178 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1179 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1180 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1181 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1182 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1183 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1184 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1185 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1186 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1187 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1188 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1189 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1190 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1191 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1192 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1193 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1194 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1195 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1196 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1197 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1198 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1201 /* mode 5 - fits in 8KB */
1202 static struct musb_fifo_cfg mode_5_cfg[] = {
1203 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1204 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1205 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1206 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1207 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1208 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1209 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1210 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1211 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1212 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1213 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1214 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1215 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1216 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1217 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1218 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1219 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1220 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1221 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1222 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1223 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1224 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1225 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1226 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1227 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1228 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1229 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1233 * configure a fifo; for non-shared endpoints, this may be called
1234 * once for a tx fifo and once for an rx fifo.
1236 * returns negative errno or offset for next fifo.
1239 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1240 const struct musb_fifo_cfg *cfg, u16 offset)
1242 void __iomem *mbase = musb->mregs;
1244 u16 maxpacket = cfg->maxpacket;
1245 u16 c_off = offset >> 3;
1248 /* expect hw_ep has already been zero-initialized */
1250 size = ffs(max(maxpacket, (u16) 8)) - 1;
1251 maxpacket = 1 << size;
1254 if (cfg->mode == BUF_DOUBLE) {
1255 if ((offset + (maxpacket << 1)) >
1256 (1 << (musb->config->ram_bits + 2)))
1258 c_size |= MUSB_FIFOSZ_DPB;
1260 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1264 /* configure the FIFO */
1265 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1267 /* EP0 reserved endpoint for control, bidirectional;
1268 * EP1 reserved for bulk, two unidirectional halves.
1270 if (hw_ep->epnum == 1)
1271 musb->bulk_ep = hw_ep;
1272 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1273 switch (cfg->style) {
1275 musb_write_txfifosz(mbase, c_size);
1276 musb_write_txfifoadd(mbase, c_off);
1277 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1278 hw_ep->max_packet_sz_tx = maxpacket;
1281 musb_write_rxfifosz(mbase, c_size);
1282 musb_write_rxfifoadd(mbase, c_off);
1283 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284 hw_ep->max_packet_sz_rx = maxpacket;
1287 musb_write_txfifosz(mbase, c_size);
1288 musb_write_txfifoadd(mbase, c_off);
1289 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1290 hw_ep->max_packet_sz_rx = maxpacket;
1292 musb_write_rxfifosz(mbase, c_size);
1293 musb_write_rxfifoadd(mbase, c_off);
1294 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1295 hw_ep->max_packet_sz_tx = maxpacket;
1297 hw_ep->is_shared_fifo = true;
1301 /* NOTE rx and tx endpoint irqs aren't managed separately,
1302 * which happens to be ok
1304 musb->epmask |= (1 << hw_ep->epnum);
1306 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1309 static struct musb_fifo_cfg ep0_cfg = {
1310 .style = FIFO_RXTX, .maxpacket = 64,
1313 static int ep_config_from_table(struct musb *musb)
1315 const struct musb_fifo_cfg *cfg;
1318 struct musb_hw_ep *hw_ep = musb->endpoints;
1320 if (musb->config->fifo_cfg) {
1321 cfg = musb->config->fifo_cfg;
1322 n = musb->config->fifo_cfg_size;
1326 switch (fifo_mode) {
1332 n = ARRAY_SIZE(mode_0_cfg);
1336 n = ARRAY_SIZE(mode_1_cfg);
1340 n = ARRAY_SIZE(mode_2_cfg);
1344 n = ARRAY_SIZE(mode_3_cfg);
1348 n = ARRAY_SIZE(mode_4_cfg);
1352 n = ARRAY_SIZE(mode_5_cfg);
1356 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1357 musb_driver_name, fifo_mode);
1361 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1362 /* assert(offset > 0) */
1364 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1365 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1368 for (i = 0; i < n; i++) {
1369 u8 epn = cfg->hw_ep_num;
1371 if (epn >= musb->config->num_eps) {
1372 pr_debug("%s: invalid ep %d\n",
1373 musb_driver_name, epn);
1376 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1378 pr_debug("%s: mem overrun, ep %d\n",
1379 musb_driver_name, epn);
1383 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1386 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1388 n + 1, musb->config->num_eps * 2 - 1,
1389 offset, (1 << (musb->config->ram_bits + 2)));
1391 if (!musb->bulk_ep) {
1392 pr_debug("%s: missing bulk\n", musb_driver_name);
1401 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1402 * @param musb the controller
1404 static int ep_config_from_hw(struct musb *musb)
1407 struct musb_hw_ep *hw_ep;
1408 void __iomem *mbase = musb->mregs;
1411 dev_dbg(musb->controller, "<== static silicon ep config\n");
1413 /* FIXME pick up ep0 maxpacket size */
1415 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1416 musb_ep_select(mbase, epnum);
1417 hw_ep = musb->endpoints + epnum;
1419 ret = musb_read_fifosize(musb, hw_ep, epnum);
1423 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1425 /* pick an RX/TX endpoint for bulk */
1426 if (hw_ep->max_packet_sz_tx < 512
1427 || hw_ep->max_packet_sz_rx < 512)
1430 /* REVISIT: this algorithm is lazy, we should at least
1431 * try to pick a double buffered endpoint.
1435 musb->bulk_ep = hw_ep;
1438 if (!musb->bulk_ep) {
1439 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1448 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1449 * configure endpoints, or take their config from silicon
1451 static int musb_core_init(u16 musb_type, struct musb *musb)
1455 char aInfo[90], aRevision[32], aDate[12];
1456 void __iomem *mbase = musb->mregs;
1460 /* log core options (read using indexed model) */
1461 reg = musb_read_configdata(mbase);
1463 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1464 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1465 strcat(aInfo, ", dyn FIFOs");
1466 musb->dyn_fifo = true;
1468 if (reg & MUSB_CONFIGDATA_MPRXE) {
1469 strcat(aInfo, ", bulk combine");
1470 musb->bulk_combine = true;
1472 if (reg & MUSB_CONFIGDATA_MPTXE) {
1473 strcat(aInfo, ", bulk split");
1474 musb->bulk_split = true;
1476 if (reg & MUSB_CONFIGDATA_HBRXE) {
1477 strcat(aInfo, ", HB-ISO Rx");
1478 musb->hb_iso_rx = true;
1480 if (reg & MUSB_CONFIGDATA_HBTXE) {
1481 strcat(aInfo, ", HB-ISO Tx");
1482 musb->hb_iso_tx = true;
1484 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1485 strcat(aInfo, ", SoftConn");
1487 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1488 musb_driver_name, reg, aInfo);
1491 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1492 musb->is_multipoint = 1;
1495 musb->is_multipoint = 0;
1497 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1499 "%s: kernel must blacklist external hubs\n",
1504 /* log release info */
1505 musb->hwvers = musb_read_hwvers(mbase);
1506 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1507 MUSB_HWVERS_MINOR(musb->hwvers),
1508 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1509 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1510 musb_driver_name, type, aRevision, aDate);
1513 musb_configure_ep0(musb);
1515 /* discover endpoint configuration */
1516 musb->nr_endpoints = 1;
1520 status = ep_config_from_table(musb);
1522 status = ep_config_from_hw(musb);
1527 /* finish init, and print endpoint config */
1528 for (i = 0; i < musb->nr_endpoints; i++) {
1529 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1531 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1532 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1533 if (musb->io.quirks & MUSB_IN_TUSB) {
1534 hw_ep->fifo_async = musb->async + 0x400 +
1535 musb->io.fifo_offset(i);
1536 hw_ep->fifo_sync = musb->sync + 0x400 +
1537 musb->io.fifo_offset(i);
1538 hw_ep->fifo_sync_va =
1539 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1542 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1544 hw_ep->conf = mbase + 0x400 +
1545 (((i - 1) & 0xf) << 2);
1549 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1550 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1551 hw_ep->rx_reinit = 1;
1552 hw_ep->tx_reinit = 1;
1554 if (hw_ep->max_packet_sz_tx) {
1555 dev_dbg(musb->controller,
1556 "%s: hw_ep %d%s, %smax %d\n",
1557 musb_driver_name, i,
1558 hw_ep->is_shared_fifo ? "shared" : "tx",
1559 hw_ep->tx_double_buffered
1560 ? "doublebuffer, " : "",
1561 hw_ep->max_packet_sz_tx);
1563 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1564 dev_dbg(musb->controller,
1565 "%s: hw_ep %d%s, %smax %d\n",
1566 musb_driver_name, i,
1568 hw_ep->rx_double_buffered
1569 ? "doublebuffer, " : "",
1570 hw_ep->max_packet_sz_rx);
1572 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1573 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1579 /*-------------------------------------------------------------------------*/
1582 * handle all the irqs defined by the HDRC core. for now we expect: other
1583 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1584 * will be assigned, and the irq will already have been acked.
1586 * called in irq context with spinlock held, irqs blocked
1588 irqreturn_t musb_interrupt(struct musb *musb)
1590 irqreturn_t retval = IRQ_NONE;
1591 unsigned long status;
1592 unsigned long epnum;
1595 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1598 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1600 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1601 is_host_active(musb) ? "host" : "peripheral",
1602 musb->int_usb, musb->int_tx, musb->int_rx);
1605 * According to Mentor Graphics' documentation, flowchart on page 98,
1606 * IRQ should be handled as follows:
1609 * . Session Request IRQ
1614 * . Reset/Babble IRQ
1615 * . SOF IRQ (we're not using this one)
1620 * We will be following that flowchart in order to avoid any problems
1621 * that might arise with internal Finite State Machine.
1625 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1627 if (musb->int_tx & 1) {
1628 if (is_host_active(musb))
1629 retval |= musb_h_ep0_irq(musb);
1631 retval |= musb_g_ep0_irq(musb);
1633 /* we have just handled endpoint 0 IRQ, clear it */
1634 musb->int_tx &= ~BIT(0);
1637 status = musb->int_tx;
1639 for_each_set_bit(epnum, &status, 16) {
1640 retval = IRQ_HANDLED;
1641 if (is_host_active(musb))
1642 musb_host_tx(musb, epnum);
1644 musb_g_tx(musb, epnum);
1647 status = musb->int_rx;
1649 for_each_set_bit(epnum, &status, 16) {
1650 retval = IRQ_HANDLED;
1651 if (is_host_active(musb))
1652 musb_host_rx(musb, epnum);
1654 musb_g_rx(musb, epnum);
1659 EXPORT_SYMBOL_GPL(musb_interrupt);
1661 #ifndef CONFIG_MUSB_PIO_ONLY
1662 static bool use_dma = 1;
1664 /* "modprobe ... use_dma=0" etc */
1665 module_param(use_dma, bool, 0);
1666 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1668 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1670 /* called with controller lock already held */
1673 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1674 if (!is_cppi_enabled()) {
1676 if (is_host_active(musb))
1677 musb_h_ep0_irq(musb);
1679 musb_g_ep0_irq(musb);
1683 /* endpoints 1..15 */
1685 if (is_host_active(musb))
1686 musb_host_tx(musb, epnum);
1688 musb_g_tx(musb, epnum);
1691 if (is_host_active(musb))
1692 musb_host_rx(musb, epnum);
1694 musb_g_rx(musb, epnum);
1698 EXPORT_SYMBOL_GPL(musb_dma_completion);
1704 /*-------------------------------------------------------------------------*/
1707 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1709 struct musb *musb = dev_to_musb(dev);
1710 unsigned long flags;
1713 spin_lock_irqsave(&musb->lock, flags);
1714 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1715 spin_unlock_irqrestore(&musb->lock, flags);
1721 musb_mode_store(struct device *dev, struct device_attribute *attr,
1722 const char *buf, size_t n)
1724 struct musb *musb = dev_to_musb(dev);
1725 unsigned long flags;
1728 spin_lock_irqsave(&musb->lock, flags);
1729 if (sysfs_streq(buf, "host"))
1730 status = musb_platform_set_mode(musb, MUSB_HOST);
1731 else if (sysfs_streq(buf, "peripheral"))
1732 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1733 else if (sysfs_streq(buf, "otg"))
1734 status = musb_platform_set_mode(musb, MUSB_OTG);
1737 spin_unlock_irqrestore(&musb->lock, flags);
1739 return (status == 0) ? n : status;
1741 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1744 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1745 const char *buf, size_t n)
1747 struct musb *musb = dev_to_musb(dev);
1748 unsigned long flags;
1751 if (sscanf(buf, "%lu", &val) < 1) {
1752 dev_err(dev, "Invalid VBUS timeout ms value\n");
1756 spin_lock_irqsave(&musb->lock, flags);
1757 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1758 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1759 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1760 musb->is_active = 0;
1761 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1762 spin_unlock_irqrestore(&musb->lock, flags);
1768 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1770 struct musb *musb = dev_to_musb(dev);
1771 unsigned long flags;
1775 spin_lock_irqsave(&musb->lock, flags);
1776 val = musb->a_wait_bcon;
1777 /* FIXME get_vbus_status() is normally #defined as false...
1778 * and is effectively TUSB-specific.
1780 vbus = musb_platform_get_vbus_status(musb);
1781 spin_unlock_irqrestore(&musb->lock, flags);
1783 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1784 vbus ? "on" : "off", val);
1786 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1788 /* Gadget drivers can't know that a host is connected so they might want
1789 * to start SRP, but users can. This allows userspace to trigger SRP.
1792 musb_srp_store(struct device *dev, struct device_attribute *attr,
1793 const char *buf, size_t n)
1795 struct musb *musb = dev_to_musb(dev);
1798 if (sscanf(buf, "%hu", &srp) != 1
1800 dev_err(dev, "SRP: Value must be 1\n");
1805 musb_g_wakeup(musb);
1809 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1811 static struct attribute *musb_attributes[] = {
1812 &dev_attr_mode.attr,
1813 &dev_attr_vbus.attr,
1818 static const struct attribute_group musb_attr_group = {
1819 .attrs = musb_attributes,
1822 /* Only used to provide driver mode change events */
1823 static void musb_irq_work(struct work_struct *data)
1825 struct musb *musb = container_of(data, struct musb, irq_work);
1827 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1828 musb->xceiv_old_state = musb->xceiv->otg->state;
1829 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1833 static void musb_recover_from_babble(struct musb *musb)
1839 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1840 * it some slack and wait for 10us.
1844 ret = musb_platform_recover(musb);
1846 musb_enable_interrupts(musb);
1850 /* drop session bit */
1851 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1852 devctl &= ~MUSB_DEVCTL_SESSION;
1853 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1855 /* tell usbcore about it */
1856 musb_root_disconnect(musb);
1859 * When a babble condition occurs, the musb controller
1860 * removes the session bit and the endpoint config is lost.
1863 ret = ep_config_from_table(musb);
1865 ret = ep_config_from_hw(musb);
1867 /* restart session */
1872 /* --------------------------------------------------------------------------
1876 static struct musb *allocate_instance(struct device *dev,
1877 struct musb_hdrc_config *config, void __iomem *mbase)
1880 struct musb_hw_ep *ep;
1884 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1888 INIT_LIST_HEAD(&musb->control);
1889 INIT_LIST_HEAD(&musb->in_bulk);
1890 INIT_LIST_HEAD(&musb->out_bulk);
1892 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1893 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1894 musb->mregs = mbase;
1895 musb->ctrl_base = mbase;
1896 musb->nIrq = -ENODEV;
1897 musb->config = config;
1898 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1899 for (epnum = 0, ep = musb->endpoints;
1900 epnum < musb->config->num_eps;
1906 musb->controller = dev;
1908 ret = musb_host_alloc(musb);
1912 dev_set_drvdata(dev, musb);
1920 static void musb_free(struct musb *musb)
1922 /* this has multiple entry modes. it handles fault cleanup after
1923 * probe(), where things may be partially set up, as well as rmmod
1924 * cleanup after everything's been de-activated.
1928 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1931 if (musb->nIrq >= 0) {
1933 disable_irq_wake(musb->nIrq);
1934 free_irq(musb->nIrq, musb);
1937 musb_host_free(musb);
1940 static void musb_deassert_reset(struct work_struct *work)
1943 unsigned long flags;
1945 musb = container_of(work, struct musb, deassert_reset_work.work);
1947 spin_lock_irqsave(&musb->lock, flags);
1949 if (musb->port1_status & USB_PORT_STAT_RESET)
1950 musb_port_reset(musb, false);
1952 spin_unlock_irqrestore(&musb->lock, flags);
1956 * Perform generic per-controller initialization.
1958 * @dev: the controller (already clocked, etc)
1960 * @ctrl: virtual address of controller registers,
1961 * not yet corrected for platform-specific offsets
1964 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1968 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1970 /* The driver might handle more features than the board; OK.
1971 * Fail when the board needs a feature that's not enabled.
1974 dev_dbg(dev, "no platform_data?\n");
1980 musb = allocate_instance(dev, plat->config, ctrl);
1986 spin_lock_init(&musb->lock);
1987 musb->board_set_power = plat->set_power;
1988 musb->min_power = plat->min_power;
1989 musb->ops = plat->platform_ops;
1990 musb->port_mode = plat->mode;
1993 * Initialize the default IO functions. At least omap2430 needs
1994 * these early. We initialize the platform specific IO functions
1997 musb_readb = musb_default_readb;
1998 musb_writeb = musb_default_writeb;
1999 musb_readw = musb_default_readw;
2000 musb_writew = musb_default_writew;
2001 musb_readl = musb_default_readl;
2002 musb_writel = musb_default_writel;
2004 /* We need musb_read/write functions initialized for PM */
2005 pm_runtime_use_autosuspend(musb->controller);
2006 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2007 pm_runtime_irq_safe(musb->controller);
2008 pm_runtime_enable(musb->controller);
2010 /* The musb_platform_init() call:
2011 * - adjusts musb->mregs
2012 * - sets the musb->isr
2013 * - may initialize an integrated transceiver
2014 * - initializes musb->xceiv, usually by otg_get_phy()
2015 * - stops powering VBUS
2017 * There are various transceiver configurations. Blackfin,
2018 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2019 * external/discrete ones in various flavors (twl4030 family,
2020 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2022 status = musb_platform_init(musb);
2031 if (musb->ops->quirks)
2032 musb->io.quirks = musb->ops->quirks;
2034 /* At least tusb6010 has it's own offsets.. */
2035 if (musb->ops->ep_offset)
2036 musb->io.ep_offset = musb->ops->ep_offset;
2037 if (musb->ops->ep_select)
2038 musb->io.ep_select = musb->ops->ep_select;
2040 /* ..and some devices use indexed offset or flat offset */
2041 if (musb->io.quirks & MUSB_INDEXED_EP) {
2042 musb->io.ep_offset = musb_indexed_ep_offset;
2043 musb->io.ep_select = musb_indexed_ep_select;
2045 musb->io.ep_offset = musb_flat_ep_offset;
2046 musb->io.ep_select = musb_flat_ep_select;
2049 if (musb->ops->fifo_mode)
2050 fifo_mode = musb->ops->fifo_mode;
2054 if (musb->ops->fifo_offset)
2055 musb->io.fifo_offset = musb->ops->fifo_offset;
2057 musb->io.fifo_offset = musb_default_fifo_offset;
2059 if (musb->ops->readb)
2060 musb_readb = musb->ops->readb;
2061 if (musb->ops->writeb)
2062 musb_writeb = musb->ops->writeb;
2063 if (musb->ops->readw)
2064 musb_readw = musb->ops->readw;
2065 if (musb->ops->writew)
2066 musb_writew = musb->ops->writew;
2067 if (musb->ops->readl)
2068 musb_readl = musb->ops->readl;
2069 if (musb->ops->writel)
2070 musb_writel = musb->ops->writel;
2072 if (musb->ops->read_fifo)
2073 musb->io.read_fifo = musb->ops->read_fifo;
2075 musb->io.read_fifo = musb_default_read_fifo;
2077 if (musb->ops->write_fifo)
2078 musb->io.write_fifo = musb->ops->write_fifo;
2080 musb->io.write_fifo = musb_default_write_fifo;
2082 if (!musb->xceiv->io_ops) {
2083 musb->xceiv->io_dev = musb->controller;
2084 musb->xceiv->io_priv = musb->mregs;
2085 musb->xceiv->io_ops = &musb_ulpi_access;
2088 pm_runtime_get_sync(musb->controller);
2090 if (use_dma && dev->dma_mask) {
2091 musb->dma_controller = dma_controller_create(musb, musb->mregs);
2092 if (IS_ERR(musb->dma_controller)) {
2093 status = PTR_ERR(musb->dma_controller);
2098 /* be sure interrupts are disabled before connecting ISR */
2099 musb_platform_disable(musb);
2100 musb_generic_disable(musb);
2102 /* Init IRQ workqueue before request_irq */
2103 INIT_WORK(&musb->irq_work, musb_irq_work);
2104 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2105 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2107 /* setup musb parts of the core (especially endpoints) */
2108 status = musb_core_init(plat->config->multipoint
2109 ? MUSB_CONTROLLER_MHDRC
2110 : MUSB_CONTROLLER_HDRC, musb);
2114 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2116 /* attach to the IRQ */
2117 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2118 dev_err(dev, "request_irq %d failed!\n", nIrq);
2123 /* FIXME this handles wakeup irqs wrong */
2124 if (enable_irq_wake(nIrq) == 0) {
2126 device_init_wakeup(dev, 1);
2131 /* program PHY to use external vBus if required */
2132 if (plat->extvbus) {
2133 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2134 busctl |= MUSB_ULPI_USE_EXTVBUS;
2135 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2138 if (musb->xceiv->otg->default_a) {
2139 MUSB_HST_MODE(musb);
2140 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2142 MUSB_DEV_MODE(musb);
2143 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2146 switch (musb->port_mode) {
2147 case MUSB_PORT_MODE_HOST:
2148 status = musb_host_setup(musb, plat->power);
2151 status = musb_platform_set_mode(musb, MUSB_HOST);
2153 case MUSB_PORT_MODE_GADGET:
2154 status = musb_gadget_setup(musb);
2157 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2159 case MUSB_PORT_MODE_DUAL_ROLE:
2160 status = musb_host_setup(musb, plat->power);
2163 status = musb_gadget_setup(musb);
2165 musb_host_cleanup(musb);
2168 status = musb_platform_set_mode(musb, MUSB_OTG);
2171 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2178 status = musb_init_debugfs(musb);
2182 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2186 pm_runtime_put(musb->controller);
2191 musb_exit_debugfs(musb);
2194 musb_gadget_cleanup(musb);
2195 musb_host_cleanup(musb);
2198 cancel_work_sync(&musb->irq_work);
2199 cancel_delayed_work_sync(&musb->finish_resume_work);
2200 cancel_delayed_work_sync(&musb->deassert_reset_work);
2201 if (musb->dma_controller)
2202 dma_controller_destroy(musb->dma_controller);
2204 pm_runtime_put_sync(musb->controller);
2208 device_init_wakeup(dev, 0);
2209 musb_platform_exit(musb);
2212 pm_runtime_disable(musb->controller);
2213 dev_err(musb->controller,
2214 "musb_init_controller failed with status %d\n", status);
2224 /*-------------------------------------------------------------------------*/
2226 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2227 * bridge to a platform device; this driver then suffices.
2229 static int musb_probe(struct platform_device *pdev)
2231 struct device *dev = &pdev->dev;
2232 int irq = platform_get_irq_byname(pdev, "mc");
2233 struct resource *iomem;
2239 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2240 base = devm_ioremap_resource(dev, iomem);
2242 return PTR_ERR(base);
2244 return musb_init_controller(dev, irq, base);
2247 static int musb_remove(struct platform_device *pdev)
2249 struct device *dev = &pdev->dev;
2250 struct musb *musb = dev_to_musb(dev);
2252 /* this gets called on rmmod.
2253 * - Host mode: host may still be active
2254 * - Peripheral mode: peripheral is deactivated (or never-activated)
2255 * - OTG mode: both roles are deactivated (or never-activated)
2257 musb_exit_debugfs(musb);
2258 musb_shutdown(pdev);
2260 if (musb->dma_controller)
2261 dma_controller_destroy(musb->dma_controller);
2263 cancel_work_sync(&musb->irq_work);
2264 cancel_delayed_work_sync(&musb->finish_resume_work);
2265 cancel_delayed_work_sync(&musb->deassert_reset_work);
2267 device_init_wakeup(dev, 0);
2273 static void musb_save_context(struct musb *musb)
2276 void __iomem *musb_base = musb->mregs;
2279 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2280 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2281 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2282 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2283 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2284 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2285 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2287 for (i = 0; i < musb->config->num_eps; ++i) {
2288 struct musb_hw_ep *hw_ep;
2290 hw_ep = &musb->endpoints[i];
2298 musb_writeb(musb_base, MUSB_INDEX, i);
2299 musb->context.index_regs[i].txmaxp =
2300 musb_readw(epio, MUSB_TXMAXP);
2301 musb->context.index_regs[i].txcsr =
2302 musb_readw(epio, MUSB_TXCSR);
2303 musb->context.index_regs[i].rxmaxp =
2304 musb_readw(epio, MUSB_RXMAXP);
2305 musb->context.index_regs[i].rxcsr =
2306 musb_readw(epio, MUSB_RXCSR);
2308 if (musb->dyn_fifo) {
2309 musb->context.index_regs[i].txfifoadd =
2310 musb_read_txfifoadd(musb_base);
2311 musb->context.index_regs[i].rxfifoadd =
2312 musb_read_rxfifoadd(musb_base);
2313 musb->context.index_regs[i].txfifosz =
2314 musb_read_txfifosz(musb_base);
2315 musb->context.index_regs[i].rxfifosz =
2316 musb_read_rxfifosz(musb_base);
2319 musb->context.index_regs[i].txtype =
2320 musb_readb(epio, MUSB_TXTYPE);
2321 musb->context.index_regs[i].txinterval =
2322 musb_readb(epio, MUSB_TXINTERVAL);
2323 musb->context.index_regs[i].rxtype =
2324 musb_readb(epio, MUSB_RXTYPE);
2325 musb->context.index_regs[i].rxinterval =
2326 musb_readb(epio, MUSB_RXINTERVAL);
2328 musb->context.index_regs[i].txfunaddr =
2329 musb_read_txfunaddr(musb_base, i);
2330 musb->context.index_regs[i].txhubaddr =
2331 musb_read_txhubaddr(musb_base, i);
2332 musb->context.index_regs[i].txhubport =
2333 musb_read_txhubport(musb_base, i);
2335 musb->context.index_regs[i].rxfunaddr =
2336 musb_read_rxfunaddr(musb_base, i);
2337 musb->context.index_regs[i].rxhubaddr =
2338 musb_read_rxhubaddr(musb_base, i);
2339 musb->context.index_regs[i].rxhubport =
2340 musb_read_rxhubport(musb_base, i);
2344 static void musb_restore_context(struct musb *musb)
2347 void __iomem *musb_base = musb->mregs;
2348 void __iomem *ep_target_regs;
2352 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2353 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2354 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2356 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2357 power = musb_readb(musb_base, MUSB_POWER);
2358 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2359 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2360 power |= musb->context.power;
2361 musb_writeb(musb_base, MUSB_POWER, power);
2363 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2364 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2365 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2366 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2368 for (i = 0; i < musb->config->num_eps; ++i) {
2369 struct musb_hw_ep *hw_ep;
2371 hw_ep = &musb->endpoints[i];
2379 musb_writeb(musb_base, MUSB_INDEX, i);
2380 musb_writew(epio, MUSB_TXMAXP,
2381 musb->context.index_regs[i].txmaxp);
2382 musb_writew(epio, MUSB_TXCSR,
2383 musb->context.index_regs[i].txcsr);
2384 musb_writew(epio, MUSB_RXMAXP,
2385 musb->context.index_regs[i].rxmaxp);
2386 musb_writew(epio, MUSB_RXCSR,
2387 musb->context.index_regs[i].rxcsr);
2389 if (musb->dyn_fifo) {
2390 musb_write_txfifosz(musb_base,
2391 musb->context.index_regs[i].txfifosz);
2392 musb_write_rxfifosz(musb_base,
2393 musb->context.index_regs[i].rxfifosz);
2394 musb_write_txfifoadd(musb_base,
2395 musb->context.index_regs[i].txfifoadd);
2396 musb_write_rxfifoadd(musb_base,
2397 musb->context.index_regs[i].rxfifoadd);
2400 musb_writeb(epio, MUSB_TXTYPE,
2401 musb->context.index_regs[i].txtype);
2402 musb_writeb(epio, MUSB_TXINTERVAL,
2403 musb->context.index_regs[i].txinterval);
2404 musb_writeb(epio, MUSB_RXTYPE,
2405 musb->context.index_regs[i].rxtype);
2406 musb_writeb(epio, MUSB_RXINTERVAL,
2408 musb->context.index_regs[i].rxinterval);
2409 musb_write_txfunaddr(musb_base, i,
2410 musb->context.index_regs[i].txfunaddr);
2411 musb_write_txhubaddr(musb_base, i,
2412 musb->context.index_regs[i].txhubaddr);
2413 musb_write_txhubport(musb_base, i,
2414 musb->context.index_regs[i].txhubport);
2417 musb_read_target_reg_base(i, musb_base);
2419 musb_write_rxfunaddr(ep_target_regs,
2420 musb->context.index_regs[i].rxfunaddr);
2421 musb_write_rxhubaddr(ep_target_regs,
2422 musb->context.index_regs[i].rxhubaddr);
2423 musb_write_rxhubport(ep_target_regs,
2424 musb->context.index_regs[i].rxhubport);
2426 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2429 static int musb_suspend(struct device *dev)
2431 struct musb *musb = dev_to_musb(dev);
2432 unsigned long flags;
2434 spin_lock_irqsave(&musb->lock, flags);
2436 if (is_peripheral_active(musb)) {
2437 /* FIXME force disconnect unless we know USB will wake
2438 * the system up quickly enough to respond ...
2440 } else if (is_host_active(musb)) {
2441 /* we know all the children are suspended; sometimes
2442 * they will even be wakeup-enabled.
2446 musb_save_context(musb);
2448 spin_unlock_irqrestore(&musb->lock, flags);
2452 static int musb_resume(struct device *dev)
2454 struct musb *musb = dev_to_musb(dev);
2459 * For static cmos like DaVinci, register values were preserved
2460 * unless for some reason the whole soc powered down or the USB
2461 * module got reset through the PSC (vs just being disabled).
2463 * For the DSPS glue layer though, a full register restore has to
2464 * be done. As it shouldn't harm other platforms, we do it
2468 musb_restore_context(musb);
2470 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2471 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2472 if ((devctl & mask) != (musb->context.devctl & mask))
2473 musb->port1_status = 0;
2474 if (musb->need_finish_resume) {
2475 musb->need_finish_resume = 0;
2476 schedule_delayed_work(&musb->finish_resume_work,
2477 msecs_to_jiffies(20));
2481 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2484 pm_runtime_disable(dev);
2485 pm_runtime_set_active(dev);
2486 pm_runtime_enable(dev);
2490 static int musb_runtime_suspend(struct device *dev)
2492 struct musb *musb = dev_to_musb(dev);
2494 musb_save_context(musb);
2499 static int musb_runtime_resume(struct device *dev)
2501 struct musb *musb = dev_to_musb(dev);
2502 static int first = 1;
2505 * When pm_runtime_get_sync called for the first time in driver
2506 * init, some of the structure is still not initialized which is
2507 * used in restore function. But clock needs to be
2508 * enabled before any register access, so
2509 * pm_runtime_get_sync has to be called.
2510 * Also context restore without save does not make
2514 musb_restore_context(musb);
2517 if (musb->need_finish_resume) {
2518 musb->need_finish_resume = 0;
2519 schedule_delayed_work(&musb->finish_resume_work,
2520 msecs_to_jiffies(20));
2526 static const struct dev_pm_ops musb_dev_pm_ops = {
2527 .suspend = musb_suspend,
2528 .resume = musb_resume,
2529 .runtime_suspend = musb_runtime_suspend,
2530 .runtime_resume = musb_runtime_resume,
2533 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2535 #define MUSB_DEV_PM_OPS NULL
2538 static struct platform_driver musb_driver = {
2540 .name = (char *)musb_driver_name,
2541 .bus = &platform_bus_type,
2542 .pm = MUSB_DEV_PM_OPS,
2544 .probe = musb_probe,
2545 .remove = musb_remove,
2546 .shutdown = musb_shutdown,
2549 module_platform_driver(musb_driver);