2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
35 #define DRIVER_AUTHOR "Sarah Sharp"
36 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
41 static int link_quirk;
42 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45 static unsigned int quirks;
46 module_param(quirks, uint, S_IRUGO);
47 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49 /* TODO: copied from ehci-hcd.c - can this be refactored? */
51 * xhci_handshake - spin reading hc until handshake completes or fails
52 * @ptr: address of hc register to be read
53 * @mask: bits to look at in result of read
54 * @done: value of those bits when handshake succeeds
55 * @usec: timeout in microseconds
57 * Returns negative errno, or zero on success
59 * Success happens when the "mask" bits have the specified value (hardware
60 * handshake done). There are two failure modes: "usec" have passed (major
61 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 if (result == ~(u32)0) /* card removed */
81 * Disable interrupts and begin the xHCI halting process.
83 void xhci_quiesce(struct xhci_hcd *xhci)
90 halted = readl(&xhci->op_regs->status) & STS_HALT;
94 cmd = readl(&xhci->op_regs->command);
96 writel(cmd, &xhci->op_regs->command);
100 * Force HC into halt state.
102 * Disable any IRQs and clear the run/stop bit.
103 * HC will complete any current and actively pipelined transactions, and
104 * should halt within 16 ms of the run/stop bit being cleared.
105 * Read HC Halted bit in the status register to see when the HC is finished.
107 int xhci_halt(struct xhci_hcd *xhci)
110 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
113 ret = xhci_handshake(&xhci->op_regs->status,
114 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 xhci->xhc_state |= XHCI_STATE_HALTED;
117 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
119 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
125 * Set the run bit and wait for the host to be running.
127 static int xhci_start(struct xhci_hcd *xhci)
132 temp = readl(&xhci->op_regs->command);
134 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 writel(temp, &xhci->op_regs->command);
139 * Wait for the HCHalted Status bit to be 0 to indicate the host is
142 ret = xhci_handshake(&xhci->op_regs->status,
143 STS_HALT, 0, XHCI_MAX_HALT_USEC);
144 if (ret == -ETIMEDOUT)
145 xhci_err(xhci, "Host took too long to start, "
146 "waited %u microseconds.\n",
149 /* clear state flags. Including dying, halted or removing */
158 * This resets pipelines, timers, counters, state machines, etc.
159 * Transactions will be terminated immediately, and operational registers
160 * will be set to their defaults.
162 int xhci_reset(struct xhci_hcd *xhci)
168 state = readl(&xhci->op_regs->status);
169 if ((state & STS_HALT) == 0) {
170 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
174 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
175 command = readl(&xhci->op_regs->command);
176 command |= CMD_RESET;
177 writel(command, &xhci->op_regs->command);
179 /* Existing Intel xHCI controllers require a delay of 1 mS,
180 * after setting the CMD_RESET bit, and before accessing any
181 * HC registers. This allows the HC to complete the
182 * reset operation and be ready for HC register access.
183 * Without this delay, the subsequent HC register access,
184 * may result in a system hang very rarely.
186 if (xhci->quirks & XHCI_INTEL_HOST)
189 ret = xhci_handshake(&xhci->op_regs->command,
190 CMD_RESET, 0, 10 * 1000 * 1000);
194 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
195 "Wait for controller to be ready for doorbell rings");
197 * xHCI cannot write to any doorbells or operational registers other
198 * than status until the "Controller Not Ready" flag is cleared.
200 ret = xhci_handshake(&xhci->op_regs->status,
201 STS_CNR, 0, 10 * 1000 * 1000);
203 for (i = 0; i < 2; ++i) {
204 xhci->bus_state[i].port_c_suspend = 0;
205 xhci->bus_state[i].suspended_ports = 0;
206 xhci->bus_state[i].resuming_ports = 0;
213 static int xhci_free_msi(struct xhci_hcd *xhci)
217 if (!xhci->msix_entries)
220 for (i = 0; i < xhci->msix_count; i++)
221 if (xhci->msix_entries[i].vector)
222 free_irq(xhci->msix_entries[i].vector,
230 static int xhci_setup_msi(struct xhci_hcd *xhci)
233 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
235 ret = pci_enable_msi(pdev);
237 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
238 "failed to allocate MSI entry");
242 ret = request_irq(pdev->irq, xhci_msi_irq,
243 0, "xhci_hcd", xhci_to_hcd(xhci));
245 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
246 "disable MSI interrupt");
247 pci_disable_msi(pdev);
255 * free all IRQs request
257 static void xhci_free_irq(struct xhci_hcd *xhci)
259 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
262 /* return if using legacy interrupt */
263 if (xhci_to_hcd(xhci)->irq > 0)
266 ret = xhci_free_msi(xhci);
270 free_irq(pdev->irq, xhci_to_hcd(xhci));
278 static int xhci_setup_msix(struct xhci_hcd *xhci)
281 struct usb_hcd *hcd = xhci_to_hcd(xhci);
282 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
285 * calculate number of msi-x vectors supported.
286 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
287 * with max number of interrupters based on the xhci HCSPARAMS1.
288 * - num_online_cpus: maximum msi-x vectors per CPUs core.
289 * Add additional 1 vector to ensure always available interrupt.
291 xhci->msix_count = min(num_online_cpus() + 1,
292 HCS_MAX_INTRS(xhci->hcs_params1));
295 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
297 if (!xhci->msix_entries) {
298 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
302 for (i = 0; i < xhci->msix_count; i++) {
303 xhci->msix_entries[i].entry = i;
304 xhci->msix_entries[i].vector = 0;
307 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "Failed to enable MSI-X");
314 for (i = 0; i < xhci->msix_count; i++) {
315 ret = request_irq(xhci->msix_entries[i].vector,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
322 hcd->msix_enabled = 1;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 pci_disable_msix(pdev);
330 kfree(xhci->msix_entries);
331 xhci->msix_entries = NULL;
335 /* Free any IRQs and disable MSI-X */
336 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338 struct usb_hcd *hcd = xhci_to_hcd(xhci);
339 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 if (xhci->quirks & XHCI_PLAT)
346 if (xhci->msix_entries) {
347 pci_disable_msix(pdev);
348 kfree(xhci->msix_entries);
349 xhci->msix_entries = NULL;
351 pci_disable_msi(pdev);
354 hcd->msix_enabled = 0;
358 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
362 if (xhci->msix_entries) {
363 for (i = 0; i < xhci->msix_count; i++)
364 synchronize_irq(xhci->msix_entries[i].vector);
368 static int xhci_try_enable_msi(struct usb_hcd *hcd)
370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
371 struct pci_dev *pdev;
374 /* The xhci platform device has set up IRQs through usb_add_hcd. */
375 if (xhci->quirks & XHCI_PLAT)
378 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 * Some Fresco Logic host controllers advertise MSI, but fail to
381 * generate interrupts. Don't even try to enable MSI.
383 if (xhci->quirks & XHCI_BROKEN_MSI)
386 /* unregister the legacy interrupt */
388 free_irq(hcd->irq, hcd);
391 ret = xhci_setup_msix(xhci);
393 /* fall back to msi*/
394 ret = xhci_setup_msi(xhci);
397 /* hcd->irq is 0, we have MSI */
401 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
406 if (!strlen(hcd->irq_descr))
407 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
408 hcd->driver->description, hcd->self.busnum);
410 /* fall back to legacy interrupt*/
411 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
412 hcd->irq_descr, hcd);
414 xhci_err(xhci, "request interrupt %d failed\n",
418 hcd->irq = pdev->irq;
424 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
429 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
433 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439 static void compliance_mode_recovery(unsigned long arg)
441 struct xhci_hcd *xhci;
446 xhci = (struct xhci_hcd *)arg;
448 for (i = 0; i < xhci->num_usb3_ports; i++) {
449 temp = readl(xhci->usb3_ports[i]);
450 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 * Compliance Mode Detected. Letting USB Core
453 * handle the Warm Reset
455 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
456 "Compliance mode detected->port %d",
458 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
459 "Attempting compliance mode recovery");
460 hcd = xhci->shared_hcd;
462 if (hcd->state == HC_STATE_SUSPENDED)
463 usb_hcd_resume_root_hub(hcd);
465 usb_hcd_poll_rh_status(hcd);
469 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
470 mod_timer(&xhci->comp_mode_recovery_timer,
471 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
475 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
476 * that causes ports behind that hardware to enter compliance mode sometimes.
477 * The quirk creates a timer that polls every 2 seconds the link state of
478 * each host controller's port and recovers it by issuing a Warm reset
479 * if Compliance mode is detected, otherwise the port will become "dead" (no
480 * device connections or disconnections will be detected anymore). Becasue no
481 * status event is generated when entering compliance mode (per xhci spec),
482 * this quirk is needed on systems that have the failing hardware installed.
484 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486 xhci->port_status_u0 = 0;
487 setup_timer(&xhci->comp_mode_recovery_timer,
488 compliance_mode_recovery, (unsigned long)xhci);
489 xhci->comp_mode_recovery_timer.expires = jiffies +
490 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492 set_timer_slack(&xhci->comp_mode_recovery_timer,
493 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
494 add_timer(&xhci->comp_mode_recovery_timer);
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode recovery timer initialized");
500 * This function identifies the systems that have installed the SN65LVPE502CP
501 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507 const char *dmi_product_name, *dmi_sys_vendor;
509 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
510 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
511 if (!dmi_product_name || !dmi_sys_vendor)
514 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
517 if (strstr(dmi_product_name, "Z420") ||
518 strstr(dmi_product_name, "Z620") ||
519 strstr(dmi_product_name, "Z820") ||
520 strstr(dmi_product_name, "Z1 Workstation"))
526 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
533 * Initialize memory for HCD and xHC (one-time init).
535 * Program the PAGESIZE register, initialize the device context array, create
536 * device contexts (?), set up a command ring segment (or two?), create event
537 * ring (one for now).
539 int xhci_init(struct usb_hcd *hcd)
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
545 spin_lock_init(&xhci->lock);
546 if (xhci->hci_version == 0x95 && link_quirk) {
547 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
548 "QUIRK: Not clearing Link TRB chain bits.");
549 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
552 "xHCI doesn't need link TRB QUIRK");
554 retval = xhci_mem_init(xhci, GFP_KERNEL);
555 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557 /* Initializing Compliance Mode Recovery Data If Needed */
558 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
559 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
560 compliance_mode_recovery_timer_init(xhci);
566 /*-------------------------------------------------------------------------*/
569 static int xhci_run_finished(struct xhci_hcd *xhci)
571 if (xhci_start(xhci)) {
575 xhci->shared_hcd->state = HC_STATE_RUNNING;
576 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578 if (xhci->quirks & XHCI_NEC_HOST)
579 xhci_ring_cmd_db(xhci);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
582 "Finished xhci_run for USB3 roothub");
587 * Start the HC after it was halted.
589 * This function is called by the USB core when the HC driver is added.
590 * Its opposite is xhci_stop().
592 * xhci_init() must be called once before this function can be called.
593 * Reset the HC, enable device slot contexts, program DCBAAP, and
594 * set command ring pointer and event ring pointer.
596 * Setup MSI-X vectors and enable interrupts.
598 int xhci_run(struct usb_hcd *hcd)
603 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 hcd->uses_new_polling = 1;
610 if (!usb_hcd_is_primary_hcd(hcd))
611 return xhci_run_finished(xhci);
613 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615 ret = xhci_try_enable_msi(hcd);
619 xhci_dbg(xhci, "Command ring memory map follows:\n");
620 xhci_debug_ring(xhci, xhci->cmd_ring);
621 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
622 xhci_dbg_cmd_ptrs(xhci);
624 xhci_dbg(xhci, "ERST memory map follows:\n");
625 xhci_dbg_erst(xhci, &xhci->erst);
626 xhci_dbg(xhci, "Event ring:\n");
627 xhci_debug_ring(xhci, xhci->event_ring);
628 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
629 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
630 temp_64 &= ~ERST_PTR_MASK;
631 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
632 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "// Set the interrupt modulation register");
636 temp = readl(&xhci->ir_set->irq_control);
637 temp &= ~ER_IRQ_INTERVAL_MASK;
639 writel(temp, &xhci->ir_set->irq_control);
641 /* Set the HCD state before we enable the irqs */
642 temp = readl(&xhci->op_regs->command);
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
645 "// Enable interrupts, cmd = 0x%x.", temp);
646 writel(temp, &xhci->op_regs->command);
648 temp = readl(&xhci->ir_set->irq_pending);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
650 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
651 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
652 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
653 xhci_print_ir_set(xhci, 0);
655 if (xhci->quirks & XHCI_NEC_HOST) {
656 struct xhci_command *command;
657 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
660 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
661 TRB_TYPE(TRB_NEC_GET_FW));
663 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
664 "Finished xhci_run for USB2 roothub");
667 EXPORT_SYMBOL_GPL(xhci_run);
672 * This function is called by the USB core when the HC driver is removed.
673 * Its opposite is xhci_run().
675 * Disable device contexts, disable IRQs, and quiesce the HC.
676 * Reset the HC, finish any completed transactions, and cleanup memory.
678 void xhci_stop(struct usb_hcd *hcd)
681 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
683 mutex_lock(&xhci->mutex);
685 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
686 spin_lock_irq(&xhci->lock);
688 xhci->xhc_state |= XHCI_STATE_HALTED;
689 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
693 spin_unlock_irq(&xhci->lock);
696 if (!usb_hcd_is_primary_hcd(hcd)) {
697 mutex_unlock(&xhci->mutex);
701 xhci_cleanup_msix(xhci);
703 /* Deleting Compliance Mode Recovery Timer */
704 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
705 (!(xhci_all_ports_seen_u0(xhci)))) {
706 del_timer_sync(&xhci->comp_mode_recovery_timer);
707 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
708 "%s: compliance mode recovery timer deleted",
712 if (xhci->quirks & XHCI_AMD_PLL_FIX)
715 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
716 "// Disabling event ring interrupts");
717 temp = readl(&xhci->op_regs->status);
718 writel(temp & ~STS_EINT, &xhci->op_regs->status);
719 temp = readl(&xhci->ir_set->irq_pending);
720 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
721 xhci_print_ir_set(xhci, 0);
723 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
724 xhci_mem_cleanup(xhci);
725 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
726 "xhci_stop completed - status = %x",
727 readl(&xhci->op_regs->status));
728 mutex_unlock(&xhci->mutex);
732 * Shutdown HC (not bus-specific)
734 * This is called when the machine is rebooting or halting. We assume that the
735 * machine will be powered off, and the HC's internal state will be reset.
736 * Don't bother to free memory.
738 * This will only ever be called with the main usb_hcd (the USB3 roothub).
740 void xhci_shutdown(struct usb_hcd *hcd)
742 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
744 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
745 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
747 spin_lock_irq(&xhci->lock);
749 /* Workaround for spurious wakeups at shutdown with HSW */
750 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
752 spin_unlock_irq(&xhci->lock);
754 xhci_cleanup_msix(xhci);
756 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
757 "xhci_shutdown completed - status = %x",
758 readl(&xhci->op_regs->status));
760 /* Yet another workaround for spurious wakeups at shutdown with HSW */
761 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
762 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
766 static void xhci_save_registers(struct xhci_hcd *xhci)
768 xhci->s3.command = readl(&xhci->op_regs->command);
769 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
770 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
771 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
772 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
773 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
774 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
775 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
776 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
779 static void xhci_restore_registers(struct xhci_hcd *xhci)
781 writel(xhci->s3.command, &xhci->op_regs->command);
782 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
783 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
784 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
785 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
786 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
787 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
788 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
789 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
792 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
796 /* step 2: initialize command ring buffer */
797 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
798 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
799 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
800 xhci->cmd_ring->dequeue) &
801 (u64) ~CMD_RING_RSVD_BITS) |
802 xhci->cmd_ring->cycle_state;
803 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
804 "// Setting command ring address to 0x%llx",
805 (long unsigned long) val_64);
806 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
810 * The whole command ring must be cleared to zero when we suspend the host.
812 * The host doesn't save the command ring pointer in the suspend well, so we
813 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
814 * aligned, because of the reserved bits in the command ring dequeue pointer
815 * register. Therefore, we can't just set the dequeue pointer back in the
816 * middle of the ring (TRBs are 16-byte aligned).
818 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
820 struct xhci_ring *ring;
821 struct xhci_segment *seg;
823 ring = xhci->cmd_ring;
827 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
828 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
829 cpu_to_le32(~TRB_CYCLE);
831 } while (seg != ring->deq_seg);
833 /* Reset the software enqueue and dequeue pointers */
834 ring->deq_seg = ring->first_seg;
835 ring->dequeue = ring->first_seg->trbs;
836 ring->enq_seg = ring->deq_seg;
837 ring->enqueue = ring->dequeue;
839 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
841 * Ring is now zeroed, so the HW should look for change of ownership
842 * when the cycle bit is set to 1.
844 ring->cycle_state = 1;
847 * Reset the hardware dequeue pointer.
848 * Yes, this will need to be re-written after resume, but we're paranoid
849 * and want to make sure the hardware doesn't access bogus memory
850 * because, say, the BIOS or an SMI started the host without changing
851 * the command ring pointers.
853 xhci_set_cmd_ring_deq(xhci);
856 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
859 __le32 __iomem **port_array;
863 spin_lock_irqsave(&xhci->lock, flags);
865 /* disble usb3 ports Wake bits*/
866 port_index = xhci->num_usb3_ports;
867 port_array = xhci->usb3_ports;
868 while (port_index--) {
869 t1 = readl(port_array[port_index]);
870 t1 = xhci_port_state_to_neutral(t1);
871 t2 = t1 & ~PORT_WAKE_BITS;
873 writel(t2, port_array[port_index]);
876 /* disble usb2 ports Wake bits*/
877 port_index = xhci->num_usb2_ports;
878 port_array = xhci->usb2_ports;
879 while (port_index--) {
880 t1 = readl(port_array[port_index]);
881 t1 = xhci_port_state_to_neutral(t1);
882 t2 = t1 & ~PORT_WAKE_BITS;
884 writel(t2, port_array[port_index]);
887 spin_unlock_irqrestore(&xhci->lock, flags);
891 * Stop HC (not bus-specific)
893 * This is called when the machine transition into S3/S4 mode.
896 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
899 unsigned int delay = XHCI_MAX_HALT_USEC;
900 struct usb_hcd *hcd = xhci_to_hcd(xhci);
906 if (hcd->state != HC_STATE_SUSPENDED ||
907 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
910 /* Clear root port wake on bits if wakeup not allowed. */
912 xhci_disable_port_wake_on_bits(xhci);
914 /* Don't poll the roothubs on bus suspend. */
915 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
916 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
917 del_timer_sync(&hcd->rh_timer);
918 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
919 del_timer_sync(&xhci->shared_hcd->rh_timer);
921 spin_lock_irq(&xhci->lock);
922 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
923 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
924 /* step 1: stop endpoint */
925 /* skipped assuming that port suspend has done */
927 /* step 2: clear Run/Stop bit */
928 command = readl(&xhci->op_regs->command);
930 writel(command, &xhci->op_regs->command);
932 /* Some chips from Fresco Logic need an extraordinary delay */
933 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
935 if (xhci_handshake(&xhci->op_regs->status,
936 STS_HALT, STS_HALT, delay)) {
937 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
938 spin_unlock_irq(&xhci->lock);
941 xhci_clear_command_ring(xhci);
943 /* step 3: save registers */
944 xhci_save_registers(xhci);
946 /* step 4: set CSS flag */
947 command = readl(&xhci->op_regs->command);
949 writel(command, &xhci->op_regs->command);
950 if (xhci_handshake(&xhci->op_regs->status,
951 STS_SAVE, 0, 10 * 1000)) {
952 xhci_warn(xhci, "WARN: xHC save state timeout\n");
953 spin_unlock_irq(&xhci->lock);
956 spin_unlock_irq(&xhci->lock);
959 * Deleting Compliance Mode Recovery Timer because the xHCI Host
960 * is about to be suspended.
962 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
963 (!(xhci_all_ports_seen_u0(xhci)))) {
964 del_timer_sync(&xhci->comp_mode_recovery_timer);
965 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
966 "%s: compliance mode recovery timer deleted",
970 /* step 5: remove core well power */
971 /* synchronize irq when using MSI-X */
972 xhci_msix_sync_irqs(xhci);
976 EXPORT_SYMBOL_GPL(xhci_suspend);
979 * start xHC (not bus-specific)
981 * This is called when the machine transition from S3/S4 mode.
984 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
986 u32 command, temp = 0, status;
987 struct usb_hcd *hcd = xhci_to_hcd(xhci);
988 struct usb_hcd *secondary_hcd;
990 bool comp_timer_running = false;
995 /* Wait a bit if either of the roothubs need to settle from the
996 * transition into bus suspend.
998 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1000 xhci->bus_state[1].next_statechange))
1003 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1004 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1006 spin_lock_irq(&xhci->lock);
1007 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1011 /* step 1: restore register */
1012 xhci_restore_registers(xhci);
1013 /* step 2: initialize command ring buffer */
1014 xhci_set_cmd_ring_deq(xhci);
1015 /* step 3: restore state and start state*/
1016 /* step 3: set CRS flag */
1017 command = readl(&xhci->op_regs->command);
1019 writel(command, &xhci->op_regs->command);
1020 if (xhci_handshake(&xhci->op_regs->status,
1021 STS_RESTORE, 0, 10 * 1000)) {
1022 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1023 spin_unlock_irq(&xhci->lock);
1026 temp = readl(&xhci->op_regs->status);
1029 /* If restore operation fails, re-initialize the HC during resume */
1030 if ((temp & STS_SRE) || hibernated) {
1032 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1033 !(xhci_all_ports_seen_u0(xhci))) {
1034 del_timer_sync(&xhci->comp_mode_recovery_timer);
1035 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1036 "Compliance Mode Recovery Timer deleted!");
1039 /* Let the USB core know _both_ roothubs lost power. */
1040 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1041 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1043 xhci_dbg(xhci, "Stop HCD\n");
1046 spin_unlock_irq(&xhci->lock);
1047 xhci_cleanup_msix(xhci);
1049 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1050 temp = readl(&xhci->op_regs->status);
1051 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1052 temp = readl(&xhci->ir_set->irq_pending);
1053 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1054 xhci_print_ir_set(xhci, 0);
1056 xhci_dbg(xhci, "cleaning up memory\n");
1057 xhci_mem_cleanup(xhci);
1058 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1059 readl(&xhci->op_regs->status));
1061 /* USB core calls the PCI reinit and start functions twice:
1062 * first with the primary HCD, and then with the secondary HCD.
1063 * If we don't do the same, the host will never be started.
1065 if (!usb_hcd_is_primary_hcd(hcd))
1066 secondary_hcd = hcd;
1068 secondary_hcd = xhci->shared_hcd;
1070 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1071 retval = xhci_init(hcd->primary_hcd);
1074 comp_timer_running = true;
1076 xhci_dbg(xhci, "Start the primary HCD\n");
1077 retval = xhci_run(hcd->primary_hcd);
1079 xhci_dbg(xhci, "Start the secondary HCD\n");
1080 retval = xhci_run(secondary_hcd);
1082 hcd->state = HC_STATE_SUSPENDED;
1083 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1087 /* step 4: set Run/Stop bit */
1088 command = readl(&xhci->op_regs->command);
1090 writel(command, &xhci->op_regs->command);
1091 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1094 /* step 5: walk topology and initialize portsc,
1095 * portpmsc and portli
1097 /* this is done in bus_resume */
1099 /* step 6: restart each of the previously
1100 * Running endpoints by ringing their doorbells
1103 spin_unlock_irq(&xhci->lock);
1107 /* Resume root hubs only when have pending events. */
1108 status = readl(&xhci->op_regs->status);
1109 if (status & STS_EINT) {
1110 usb_hcd_resume_root_hub(xhci->shared_hcd);
1111 usb_hcd_resume_root_hub(hcd);
1116 * If system is subject to the Quirk, Compliance Mode Timer needs to
1117 * be re-initialized Always after a system resume. Ports are subject
1118 * to suffer the Compliance Mode issue again. It doesn't matter if
1119 * ports have entered previously to U0 before system's suspension.
1121 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1122 compliance_mode_recovery_timer_init(xhci);
1124 /* Re-enable port polling. */
1125 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1126 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1127 usb_hcd_poll_rh_status(xhci->shared_hcd);
1128 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1129 usb_hcd_poll_rh_status(hcd);
1133 EXPORT_SYMBOL_GPL(xhci_resume);
1134 #endif /* CONFIG_PM */
1136 /*-------------------------------------------------------------------------*/
1139 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1140 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1141 * value to right shift 1 for the bitmask.
1143 * Index = (epnum * 2) + direction - 1,
1144 * where direction = 0 for OUT, 1 for IN.
1145 * For control endpoints, the IN index is used (OUT index is unused), so
1146 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1148 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1151 if (usb_endpoint_xfer_control(desc))
1152 index = (unsigned int) (usb_endpoint_num(desc)*2);
1154 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1155 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1159 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1160 * address from the XHCI endpoint index.
1162 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1164 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1165 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1166 return direction | number;
1169 /* Find the flag for this endpoint (for use in the control context). Use the
1170 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1173 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1175 return 1 << (xhci_get_endpoint_index(desc) + 1);
1178 /* Find the flag for this endpoint (for use in the control context). Use the
1179 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1182 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1184 return 1 << (ep_index + 1);
1187 /* Compute the last valid endpoint context index. Basically, this is the
1188 * endpoint index plus one. For slot contexts with more than valid endpoint,
1189 * we find the most significant bit set in the added contexts flags.
1190 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1191 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1193 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1195 return fls(added_ctxs) - 1;
1198 /* Returns 1 if the arguments are OK;
1199 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1201 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1202 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1204 struct xhci_hcd *xhci;
1205 struct xhci_virt_device *virt_dev;
1207 if (!hcd || (check_ep && !ep) || !udev) {
1208 pr_debug("xHCI %s called with invalid args\n", func);
1211 if (!udev->parent) {
1212 pr_debug("xHCI %s called for root hub\n", func);
1216 xhci = hcd_to_xhci(hcd);
1217 if (check_virt_dev) {
1218 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1219 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1224 virt_dev = xhci->devs[udev->slot_id];
1225 if (virt_dev->udev != udev) {
1226 xhci_dbg(xhci, "xHCI %s called with udev and "
1227 "virt_dev does not match\n", func);
1232 if (xhci->xhc_state & XHCI_STATE_HALTED)
1238 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1239 struct usb_device *udev, struct xhci_command *command,
1240 bool ctx_change, bool must_succeed);
1243 * Full speed devices may have a max packet size greater than 8 bytes, but the
1244 * USB core doesn't know that until it reads the first 8 bytes of the
1245 * descriptor. If the usb_device's max packet size changes after that point,
1246 * we need to issue an evaluate context command and wait on it.
1248 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1249 unsigned int ep_index, struct urb *urb)
1251 struct xhci_container_ctx *out_ctx;
1252 struct xhci_input_control_ctx *ctrl_ctx;
1253 struct xhci_ep_ctx *ep_ctx;
1254 struct xhci_command *command;
1255 int max_packet_size;
1256 int hw_max_packet_size;
1259 out_ctx = xhci->devs[slot_id]->out_ctx;
1260 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1261 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1262 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1263 if (hw_max_packet_size != max_packet_size) {
1264 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1265 "Max Packet Size for ep 0 changed.");
1266 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1267 "Max packet size in usb_device = %d",
1269 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1270 "Max packet size in xHCI HW = %d",
1271 hw_max_packet_size);
1272 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1273 "Issuing evaluate context command.");
1275 /* Set up the input context flags for the command */
1276 /* FIXME: This won't work if a non-default control endpoint
1277 * changes max packet sizes.
1280 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1284 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1285 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1287 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1290 goto command_cleanup;
1292 /* Set up the modified control endpoint 0 */
1293 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1294 xhci->devs[slot_id]->out_ctx, ep_index);
1296 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1297 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1298 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1300 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1301 ctrl_ctx->drop_flags = 0;
1303 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1304 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1305 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1306 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1308 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1311 /* Clean up the input context for later use by bandwidth
1314 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1316 kfree(command->completion);
1323 * non-error returns are a promise to giveback() the urb later
1324 * we drop ownership so next owner (or urb unlink) can get it
1326 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1328 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1329 struct xhci_td *buffer;
1330 unsigned long flags;
1332 unsigned int slot_id, ep_index;
1333 struct urb_priv *urb_priv;
1336 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1337 true, true, __func__) <= 0)
1340 slot_id = urb->dev->slot_id;
1341 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1343 if (!HCD_HW_ACCESSIBLE(hcd)) {
1344 if (!in_interrupt())
1345 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1350 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1351 size = urb->number_of_packets;
1352 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1353 urb->transfer_buffer_length > 0 &&
1354 urb->transfer_flags & URB_ZERO_PACKET &&
1355 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1360 urb_priv = kzalloc(sizeof(struct urb_priv) +
1361 size * sizeof(struct xhci_td *), mem_flags);
1365 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1371 for (i = 0; i < size; i++) {
1372 urb_priv->td[i] = buffer;
1376 urb_priv->length = size;
1377 urb_priv->td_cnt = 0;
1378 urb->hcpriv = urb_priv;
1380 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1381 /* Check to see if the max packet size for the default control
1382 * endpoint changed during FS device enumeration
1384 if (urb->dev->speed == USB_SPEED_FULL) {
1385 ret = xhci_check_maxpacket(xhci, slot_id,
1388 xhci_urb_free_priv(urb_priv);
1394 /* We have a spinlock and interrupts disabled, so we must pass
1395 * atomic context to this function, which may allocate memory.
1397 spin_lock_irqsave(&xhci->lock, flags);
1398 if (xhci->xhc_state & XHCI_STATE_DYING)
1400 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1404 spin_unlock_irqrestore(&xhci->lock, flags);
1405 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1406 spin_lock_irqsave(&xhci->lock, flags);
1407 if (xhci->xhc_state & XHCI_STATE_DYING)
1409 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1410 EP_GETTING_STREAMS) {
1411 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1412 "is transitioning to using streams.\n");
1414 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1415 EP_GETTING_NO_STREAMS) {
1416 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1417 "is transitioning to "
1418 "not having streams.\n");
1421 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1426 spin_unlock_irqrestore(&xhci->lock, flags);
1427 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1428 spin_lock_irqsave(&xhci->lock, flags);
1429 if (xhci->xhc_state & XHCI_STATE_DYING)
1431 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1435 spin_unlock_irqrestore(&xhci->lock, flags);
1437 spin_lock_irqsave(&xhci->lock, flags);
1438 if (xhci->xhc_state & XHCI_STATE_DYING)
1440 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1444 spin_unlock_irqrestore(&xhci->lock, flags);
1449 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1450 "non-responsive xHCI host.\n",
1451 urb->ep->desc.bEndpointAddress, urb);
1454 xhci_urb_free_priv(urb_priv);
1456 spin_unlock_irqrestore(&xhci->lock, flags);
1460 /* Get the right ring for the given URB.
1461 * If the endpoint supports streams, boundary check the URB's stream ID.
1462 * If the endpoint doesn't support streams, return the singular endpoint ring.
1464 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1467 unsigned int slot_id;
1468 unsigned int ep_index;
1469 unsigned int stream_id;
1470 struct xhci_virt_ep *ep;
1472 slot_id = urb->dev->slot_id;
1473 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1474 stream_id = urb->stream_id;
1475 ep = &xhci->devs[slot_id]->eps[ep_index];
1476 /* Common case: no streams */
1477 if (!(ep->ep_state & EP_HAS_STREAMS))
1480 if (stream_id == 0) {
1482 "WARN: Slot ID %u, ep index %u has streams, "
1483 "but URB has no stream ID.\n",
1488 if (stream_id < ep->stream_info->num_streams)
1489 return ep->stream_info->stream_rings[stream_id];
1492 "WARN: Slot ID %u, ep index %u has "
1493 "stream IDs 1 to %u allocated, "
1494 "but stream ID %u is requested.\n",
1496 ep->stream_info->num_streams - 1,
1502 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1503 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1504 * should pick up where it left off in the TD, unless a Set Transfer Ring
1505 * Dequeue Pointer is issued.
1507 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1508 * the ring. Since the ring is a contiguous structure, they can't be physically
1509 * removed. Instead, there are two options:
1511 * 1) If the HC is in the middle of processing the URB to be canceled, we
1512 * simply move the ring's dequeue pointer past those TRBs using the Set
1513 * Transfer Ring Dequeue Pointer command. This will be the common case,
1514 * when drivers timeout on the last submitted URB and attempt to cancel.
1516 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1517 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1518 * HC will need to invalidate the any TRBs it has cached after the stop
1519 * endpoint command, as noted in the xHCI 0.95 errata.
1521 * 3) The TD may have completed by the time the Stop Endpoint Command
1522 * completes, so software needs to handle that case too.
1524 * This function should protect against the TD enqueueing code ringing the
1525 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1526 * It also needs to account for multiple cancellations on happening at the same
1527 * time for the same endpoint.
1529 * Note that this function can be called in any context, or so says
1530 * usb_hcd_unlink_urb()
1532 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1534 unsigned long flags;
1537 struct xhci_hcd *xhci;
1538 struct urb_priv *urb_priv;
1540 unsigned int ep_index;
1541 struct xhci_ring *ep_ring;
1542 struct xhci_virt_ep *ep;
1543 struct xhci_command *command;
1545 xhci = hcd_to_xhci(hcd);
1546 spin_lock_irqsave(&xhci->lock, flags);
1547 /* Make sure the URB hasn't completed or been unlinked already */
1548 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1549 if (ret || !urb->hcpriv)
1551 temp = readl(&xhci->op_regs->status);
1552 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1553 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1554 "HW died, freeing TD.");
1555 urb_priv = urb->hcpriv;
1556 for (i = urb_priv->td_cnt;
1557 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1559 td = urb_priv->td[i];
1560 if (!list_empty(&td->td_list))
1561 list_del_init(&td->td_list);
1562 if (!list_empty(&td->cancelled_td_list))
1563 list_del_init(&td->cancelled_td_list);
1566 usb_hcd_unlink_urb_from_ep(hcd, urb);
1567 spin_unlock_irqrestore(&xhci->lock, flags);
1568 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1569 xhci_urb_free_priv(urb_priv);
1572 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1573 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1574 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1575 "Ep 0x%x: URB %p to be canceled on "
1576 "non-responsive xHCI host.",
1577 urb->ep->desc.bEndpointAddress, urb);
1578 /* Let the stop endpoint command watchdog timer (which set this
1579 * state) finish cleaning up the endpoint TD lists. We must
1580 * have caught it in the middle of dropping a lock and giving
1586 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1587 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1588 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1594 urb_priv = urb->hcpriv;
1595 i = urb_priv->td_cnt;
1596 if (i < urb_priv->length)
1597 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1598 "Cancel URB %p, dev %s, ep 0x%x, "
1599 "starting at offset 0x%llx",
1600 urb, urb->dev->devpath,
1601 urb->ep->desc.bEndpointAddress,
1602 (unsigned long long) xhci_trb_virt_to_dma(
1603 urb_priv->td[i]->start_seg,
1604 urb_priv->td[i]->first_trb));
1606 for (; i < urb_priv->length; i++) {
1607 td = urb_priv->td[i];
1608 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1611 /* Queue a stop endpoint command, but only if this is
1612 * the first cancellation to be handled.
1614 if (!(ep->ep_state & EP_HALT_PENDING)) {
1615 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1620 ep->ep_state |= EP_HALT_PENDING;
1621 ep->stop_cmds_pending++;
1622 ep->stop_cmd_timer.expires = jiffies +
1623 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1624 add_timer(&ep->stop_cmd_timer);
1625 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1627 xhci_ring_cmd_db(xhci);
1630 spin_unlock_irqrestore(&xhci->lock, flags);
1634 /* Drop an endpoint from a new bandwidth configuration for this device.
1635 * Only one call to this function is allowed per endpoint before
1636 * check_bandwidth() or reset_bandwidth() must be called.
1637 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1638 * add the endpoint to the schedule with possibly new parameters denoted by a
1639 * different endpoint descriptor in usb_host_endpoint.
1640 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1643 * The USB core will not allow URBs to be queued to an endpoint that is being
1644 * disabled, so there's no need for mutual exclusion to protect
1645 * the xhci->devs[slot_id] structure.
1647 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1648 struct usb_host_endpoint *ep)
1650 struct xhci_hcd *xhci;
1651 struct xhci_container_ctx *in_ctx, *out_ctx;
1652 struct xhci_input_control_ctx *ctrl_ctx;
1653 unsigned int ep_index;
1654 struct xhci_ep_ctx *ep_ctx;
1656 u32 new_add_flags, new_drop_flags;
1659 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1662 xhci = hcd_to_xhci(hcd);
1663 if (xhci->xhc_state & XHCI_STATE_DYING)
1666 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1667 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1668 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1669 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1670 __func__, drop_flag);
1674 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1675 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1676 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1678 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1683 ep_index = xhci_get_endpoint_index(&ep->desc);
1684 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1685 /* If the HC already knows the endpoint is disabled,
1686 * or the HCD has noted it is disabled, ignore this request
1688 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1689 cpu_to_le32(EP_STATE_DISABLED)) ||
1690 le32_to_cpu(ctrl_ctx->drop_flags) &
1691 xhci_get_endpoint_flag(&ep->desc)) {
1692 /* Do not warn when called after a usb_device_reset */
1693 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1694 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1699 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1700 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1702 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1703 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1705 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1707 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1708 (unsigned int) ep->desc.bEndpointAddress,
1710 (unsigned int) new_drop_flags,
1711 (unsigned int) new_add_flags);
1715 /* Add an endpoint to a new possible bandwidth configuration for this device.
1716 * Only one call to this function is allowed per endpoint before
1717 * check_bandwidth() or reset_bandwidth() must be called.
1718 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1719 * add the endpoint to the schedule with possibly new parameters denoted by a
1720 * different endpoint descriptor in usb_host_endpoint.
1721 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1724 * The USB core will not allow URBs to be queued to an endpoint until the
1725 * configuration or alt setting is installed in the device, so there's no need
1726 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1728 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1729 struct usb_host_endpoint *ep)
1731 struct xhci_hcd *xhci;
1732 struct xhci_container_ctx *in_ctx;
1733 unsigned int ep_index;
1734 struct xhci_input_control_ctx *ctrl_ctx;
1736 u32 new_add_flags, new_drop_flags;
1737 struct xhci_virt_device *virt_dev;
1740 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1742 /* So we won't queue a reset ep command for a root hub */
1746 xhci = hcd_to_xhci(hcd);
1747 if (xhci->xhc_state & XHCI_STATE_DYING)
1750 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1751 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1752 /* FIXME when we have to issue an evaluate endpoint command to
1753 * deal with ep0 max packet size changing once we get the
1756 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1757 __func__, added_ctxs);
1761 virt_dev = xhci->devs[udev->slot_id];
1762 in_ctx = virt_dev->in_ctx;
1763 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1765 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1770 ep_index = xhci_get_endpoint_index(&ep->desc);
1771 /* If this endpoint is already in use, and the upper layers are trying
1772 * to add it again without dropping it, reject the addition.
1774 if (virt_dev->eps[ep_index].ring &&
1775 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1776 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1777 "without dropping it.\n",
1778 (unsigned int) ep->desc.bEndpointAddress);
1782 /* If the HCD has already noted the endpoint is enabled,
1783 * ignore this request.
1785 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1786 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1792 * Configuration and alternate setting changes must be done in
1793 * process context, not interrupt context (or so documenation
1794 * for usb_set_interface() and usb_set_configuration() claim).
1796 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1797 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1798 __func__, ep->desc.bEndpointAddress);
1802 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1803 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1805 /* If xhci_endpoint_disable() was called for this endpoint, but the
1806 * xHC hasn't been notified yet through the check_bandwidth() call,
1807 * this re-adds a new state for the endpoint from the new endpoint
1808 * descriptors. We must drop and re-add this endpoint, so we leave the
1811 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1813 /* Store the usb_device pointer for later use */
1816 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1817 (unsigned int) ep->desc.bEndpointAddress,
1819 (unsigned int) new_drop_flags,
1820 (unsigned int) new_add_flags);
1824 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1826 struct xhci_input_control_ctx *ctrl_ctx;
1827 struct xhci_ep_ctx *ep_ctx;
1828 struct xhci_slot_ctx *slot_ctx;
1831 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1833 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1838 /* When a device's add flag and drop flag are zero, any subsequent
1839 * configure endpoint command will leave that endpoint's state
1840 * untouched. Make sure we don't leave any old state in the input
1841 * endpoint contexts.
1843 ctrl_ctx->drop_flags = 0;
1844 ctrl_ctx->add_flags = 0;
1845 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1846 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1847 /* Endpoint 0 is always valid */
1848 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1849 for (i = 1; i < 31; ++i) {
1850 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1851 ep_ctx->ep_info = 0;
1852 ep_ctx->ep_info2 = 0;
1854 ep_ctx->tx_info = 0;
1858 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1859 struct usb_device *udev, u32 *cmd_status)
1863 switch (*cmd_status) {
1864 case COMP_CMD_ABORT:
1866 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1870 dev_warn(&udev->dev,
1871 "Not enough host controller resources for new device state.\n");
1873 /* FIXME: can we allocate more resources for the HC? */
1876 case COMP_2ND_BW_ERR:
1877 dev_warn(&udev->dev,
1878 "Not enough bandwidth for new device state.\n");
1880 /* FIXME: can we go back to the old state? */
1883 /* the HCD set up something wrong */
1884 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1886 "and endpoint is not disabled.\n");
1890 dev_warn(&udev->dev,
1891 "ERROR: Incompatible device for endpoint configure command.\n");
1895 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1896 "Successful Endpoint Configure command");
1900 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1908 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1909 struct usb_device *udev, u32 *cmd_status)
1912 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1914 switch (*cmd_status) {
1915 case COMP_CMD_ABORT:
1917 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1921 dev_warn(&udev->dev,
1922 "WARN: xHCI driver setup invalid evaluate context command.\n");
1926 dev_warn(&udev->dev,
1927 "WARN: slot not enabled for evaluate context command.\n");
1930 case COMP_CTX_STATE:
1931 dev_warn(&udev->dev,
1932 "WARN: invalid context state for evaluate context command.\n");
1933 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1937 dev_warn(&udev->dev,
1938 "ERROR: Incompatible device for evaluate context command.\n");
1942 /* Max Exit Latency too large error */
1943 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1947 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1948 "Successful evaluate context command");
1952 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1960 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1961 struct xhci_input_control_ctx *ctrl_ctx)
1963 u32 valid_add_flags;
1964 u32 valid_drop_flags;
1966 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1967 * (bit 1). The default control endpoint is added during the Address
1968 * Device command and is never removed until the slot is disabled.
1970 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1971 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1973 /* Use hweight32 to count the number of ones in the add flags, or
1974 * number of endpoints added. Don't count endpoints that are changed
1975 * (both added and dropped).
1977 return hweight32(valid_add_flags) -
1978 hweight32(valid_add_flags & valid_drop_flags);
1981 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1982 struct xhci_input_control_ctx *ctrl_ctx)
1984 u32 valid_add_flags;
1985 u32 valid_drop_flags;
1987 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1988 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1990 return hweight32(valid_drop_flags) -
1991 hweight32(valid_add_flags & valid_drop_flags);
1995 * We need to reserve the new number of endpoints before the configure endpoint
1996 * command completes. We can't subtract the dropped endpoints from the number
1997 * of active endpoints until the command completes because we can oversubscribe
1998 * the host in this case:
2000 * - the first configure endpoint command drops more endpoints than it adds
2001 * - a second configure endpoint command that adds more endpoints is queued
2002 * - the first configure endpoint command fails, so the config is unchanged
2003 * - the second command may succeed, even though there isn't enough resources
2005 * Must be called with xhci->lock held.
2007 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2008 struct xhci_input_control_ctx *ctrl_ctx)
2012 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2013 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2014 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2015 "Not enough ep ctxs: "
2016 "%u active, need to add %u, limit is %u.",
2017 xhci->num_active_eps, added_eps,
2018 xhci->limit_active_eps);
2021 xhci->num_active_eps += added_eps;
2022 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2023 "Adding %u ep ctxs, %u now active.", added_eps,
2024 xhci->num_active_eps);
2029 * The configure endpoint was failed by the xHC for some other reason, so we
2030 * need to revert the resources that failed configuration would have used.
2032 * Must be called with xhci->lock held.
2034 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2035 struct xhci_input_control_ctx *ctrl_ctx)
2039 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2040 xhci->num_active_eps -= num_failed_eps;
2041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2042 "Removing %u failed ep ctxs, %u now active.",
2044 xhci->num_active_eps);
2048 * Now that the command has completed, clean up the active endpoint count by
2049 * subtracting out the endpoints that were dropped (but not changed).
2051 * Must be called with xhci->lock held.
2053 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2054 struct xhci_input_control_ctx *ctrl_ctx)
2056 u32 num_dropped_eps;
2058 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2059 xhci->num_active_eps -= num_dropped_eps;
2060 if (num_dropped_eps)
2061 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2062 "Removing %u dropped ep ctxs, %u now active.",
2064 xhci->num_active_eps);
2067 static unsigned int xhci_get_block_size(struct usb_device *udev)
2069 switch (udev->speed) {
2071 case USB_SPEED_FULL:
2073 case USB_SPEED_HIGH:
2075 case USB_SPEED_SUPER:
2077 case USB_SPEED_UNKNOWN:
2078 case USB_SPEED_WIRELESS:
2080 /* Should never happen */
2086 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2088 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2090 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2095 /* If we are changing a LS/FS device under a HS hub,
2096 * make sure (if we are activating a new TT) that the HS bus has enough
2097 * bandwidth for this new TT.
2099 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2100 struct xhci_virt_device *virt_dev,
2103 struct xhci_interval_bw_table *bw_table;
2104 struct xhci_tt_bw_info *tt_info;
2106 /* Find the bandwidth table for the root port this TT is attached to. */
2107 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2108 tt_info = virt_dev->tt_info;
2109 /* If this TT already had active endpoints, the bandwidth for this TT
2110 * has already been added. Removing all periodic endpoints (and thus
2111 * making the TT enactive) will only decrease the bandwidth used.
2115 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2116 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2120 /* Not sure why we would have no new active endpoints...
2122 * Maybe because of an Evaluate Context change for a hub update or a
2123 * control endpoint 0 max packet size change?
2124 * FIXME: skip the bandwidth calculation in that case.
2129 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2130 struct xhci_virt_device *virt_dev)
2132 unsigned int bw_reserved;
2134 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2135 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2138 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2139 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2146 * This algorithm is a very conservative estimate of the worst-case scheduling
2147 * scenario for any one interval. The hardware dynamically schedules the
2148 * packets, so we can't tell which microframe could be the limiting factor in
2149 * the bandwidth scheduling. This only takes into account periodic endpoints.
2151 * Obviously, we can't solve an NP complete problem to find the minimum worst
2152 * case scenario. Instead, we come up with an estimate that is no less than
2153 * the worst case bandwidth used for any one microframe, but may be an
2156 * We walk the requirements for each endpoint by interval, starting with the
2157 * smallest interval, and place packets in the schedule where there is only one
2158 * possible way to schedule packets for that interval. In order to simplify
2159 * this algorithm, we record the largest max packet size for each interval, and
2160 * assume all packets will be that size.
2162 * For interval 0, we obviously must schedule all packets for each interval.
2163 * The bandwidth for interval 0 is just the amount of data to be transmitted
2164 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2165 * the number of packets).
2167 * For interval 1, we have two possible microframes to schedule those packets
2168 * in. For this algorithm, if we can schedule the same number of packets for
2169 * each possible scheduling opportunity (each microframe), we will do so. The
2170 * remaining number of packets will be saved to be transmitted in the gaps in
2171 * the next interval's scheduling sequence.
2173 * As we move those remaining packets to be scheduled with interval 2 packets,
2174 * we have to double the number of remaining packets to transmit. This is
2175 * because the intervals are actually powers of 2, and we would be transmitting
2176 * the previous interval's packets twice in this interval. We also have to be
2177 * sure that when we look at the largest max packet size for this interval, we
2178 * also look at the largest max packet size for the remaining packets and take
2179 * the greater of the two.
2181 * The algorithm continues to evenly distribute packets in each scheduling
2182 * opportunity, and push the remaining packets out, until we get to the last
2183 * interval. Then those packets and their associated overhead are just added
2184 * to the bandwidth used.
2186 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2187 struct xhci_virt_device *virt_dev,
2190 unsigned int bw_reserved;
2191 unsigned int max_bandwidth;
2192 unsigned int bw_used;
2193 unsigned int block_size;
2194 struct xhci_interval_bw_table *bw_table;
2195 unsigned int packet_size = 0;
2196 unsigned int overhead = 0;
2197 unsigned int packets_transmitted = 0;
2198 unsigned int packets_remaining = 0;
2201 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2202 return xhci_check_ss_bw(xhci, virt_dev);
2204 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2205 max_bandwidth = HS_BW_LIMIT;
2206 /* Convert percent of bus BW reserved to blocks reserved */
2207 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2209 max_bandwidth = FS_BW_LIMIT;
2210 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2213 bw_table = virt_dev->bw_table;
2214 /* We need to translate the max packet size and max ESIT payloads into
2215 * the units the hardware uses.
2217 block_size = xhci_get_block_size(virt_dev->udev);
2219 /* If we are manipulating a LS/FS device under a HS hub, double check
2220 * that the HS bus has enough bandwidth if we are activing a new TT.
2222 if (virt_dev->tt_info) {
2223 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2224 "Recalculating BW for rootport %u",
2225 virt_dev->real_port);
2226 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2227 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2228 "newly activated TT.\n");
2231 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2232 "Recalculating BW for TT slot %u port %u",
2233 virt_dev->tt_info->slot_id,
2234 virt_dev->tt_info->ttport);
2236 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2237 "Recalculating BW for rootport %u",
2238 virt_dev->real_port);
2241 /* Add in how much bandwidth will be used for interval zero, or the
2242 * rounded max ESIT payload + number of packets * largest overhead.
2244 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2245 bw_table->interval_bw[0].num_packets *
2246 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2248 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2249 unsigned int bw_added;
2250 unsigned int largest_mps;
2251 unsigned int interval_overhead;
2254 * How many packets could we transmit in this interval?
2255 * If packets didn't fit in the previous interval, we will need
2256 * to transmit that many packets twice within this interval.
2258 packets_remaining = 2 * packets_remaining +
2259 bw_table->interval_bw[i].num_packets;
2261 /* Find the largest max packet size of this or the previous
2264 if (list_empty(&bw_table->interval_bw[i].endpoints))
2267 struct xhci_virt_ep *virt_ep;
2268 struct list_head *ep_entry;
2270 ep_entry = bw_table->interval_bw[i].endpoints.next;
2271 virt_ep = list_entry(ep_entry,
2272 struct xhci_virt_ep, bw_endpoint_list);
2273 /* Convert to blocks, rounding up */
2274 largest_mps = DIV_ROUND_UP(
2275 virt_ep->bw_info.max_packet_size,
2278 if (largest_mps > packet_size)
2279 packet_size = largest_mps;
2281 /* Use the larger overhead of this or the previous interval. */
2282 interval_overhead = xhci_get_largest_overhead(
2283 &bw_table->interval_bw[i]);
2284 if (interval_overhead > overhead)
2285 overhead = interval_overhead;
2287 /* How many packets can we evenly distribute across
2288 * (1 << (i + 1)) possible scheduling opportunities?
2290 packets_transmitted = packets_remaining >> (i + 1);
2292 /* Add in the bandwidth used for those scheduled packets */
2293 bw_added = packets_transmitted * (overhead + packet_size);
2295 /* How many packets do we have remaining to transmit? */
2296 packets_remaining = packets_remaining % (1 << (i + 1));
2298 /* What largest max packet size should those packets have? */
2299 /* If we've transmitted all packets, don't carry over the
2300 * largest packet size.
2302 if (packets_remaining == 0) {
2305 } else if (packets_transmitted > 0) {
2306 /* Otherwise if we do have remaining packets, and we've
2307 * scheduled some packets in this interval, take the
2308 * largest max packet size from endpoints with this
2311 packet_size = largest_mps;
2312 overhead = interval_overhead;
2314 /* Otherwise carry over packet_size and overhead from the last
2315 * time we had a remainder.
2317 bw_used += bw_added;
2318 if (bw_used > max_bandwidth) {
2319 xhci_warn(xhci, "Not enough bandwidth. "
2320 "Proposed: %u, Max: %u\n",
2321 bw_used, max_bandwidth);
2326 * Ok, we know we have some packets left over after even-handedly
2327 * scheduling interval 15. We don't know which microframes they will
2328 * fit into, so we over-schedule and say they will be scheduled every
2331 if (packets_remaining > 0)
2332 bw_used += overhead + packet_size;
2334 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2335 unsigned int port_index = virt_dev->real_port - 1;
2337 /* OK, we're manipulating a HS device attached to a
2338 * root port bandwidth domain. Include the number of active TTs
2339 * in the bandwidth used.
2341 bw_used += TT_HS_OVERHEAD *
2342 xhci->rh_bw[port_index].num_active_tts;
2345 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2346 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2347 "Available: %u " "percent",
2348 bw_used, max_bandwidth, bw_reserved,
2349 (max_bandwidth - bw_used - bw_reserved) * 100 /
2352 bw_used += bw_reserved;
2353 if (bw_used > max_bandwidth) {
2354 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2355 bw_used, max_bandwidth);
2359 bw_table->bw_used = bw_used;
2363 static bool xhci_is_async_ep(unsigned int ep_type)
2365 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2366 ep_type != ISOC_IN_EP &&
2367 ep_type != INT_IN_EP);
2370 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2372 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2375 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2377 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2379 if (ep_bw->ep_interval == 0)
2380 return SS_OVERHEAD_BURST +
2381 (ep_bw->mult * ep_bw->num_packets *
2382 (SS_OVERHEAD + mps));
2383 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2384 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2385 1 << ep_bw->ep_interval);
2389 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2390 struct xhci_bw_info *ep_bw,
2391 struct xhci_interval_bw_table *bw_table,
2392 struct usb_device *udev,
2393 struct xhci_virt_ep *virt_ep,
2394 struct xhci_tt_bw_info *tt_info)
2396 struct xhci_interval_bw *interval_bw;
2397 int normalized_interval;
2399 if (xhci_is_async_ep(ep_bw->type))
2402 if (udev->speed == USB_SPEED_SUPER) {
2403 if (xhci_is_sync_in_ep(ep_bw->type))
2404 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2405 xhci_get_ss_bw_consumed(ep_bw);
2407 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2408 xhci_get_ss_bw_consumed(ep_bw);
2412 /* SuperSpeed endpoints never get added to intervals in the table, so
2413 * this check is only valid for HS/FS/LS devices.
2415 if (list_empty(&virt_ep->bw_endpoint_list))
2417 /* For LS/FS devices, we need to translate the interval expressed in
2418 * microframes to frames.
2420 if (udev->speed == USB_SPEED_HIGH)
2421 normalized_interval = ep_bw->ep_interval;
2423 normalized_interval = ep_bw->ep_interval - 3;
2425 if (normalized_interval == 0)
2426 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2427 interval_bw = &bw_table->interval_bw[normalized_interval];
2428 interval_bw->num_packets -= ep_bw->num_packets;
2429 switch (udev->speed) {
2431 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2433 case USB_SPEED_FULL:
2434 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2436 case USB_SPEED_HIGH:
2437 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2439 case USB_SPEED_SUPER:
2440 case USB_SPEED_UNKNOWN:
2441 case USB_SPEED_WIRELESS:
2442 /* Should never happen because only LS/FS/HS endpoints will get
2443 * added to the endpoint list.
2448 tt_info->active_eps -= 1;
2449 list_del_init(&virt_ep->bw_endpoint_list);
2452 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2453 struct xhci_bw_info *ep_bw,
2454 struct xhci_interval_bw_table *bw_table,
2455 struct usb_device *udev,
2456 struct xhci_virt_ep *virt_ep,
2457 struct xhci_tt_bw_info *tt_info)
2459 struct xhci_interval_bw *interval_bw;
2460 struct xhci_virt_ep *smaller_ep;
2461 int normalized_interval;
2463 if (xhci_is_async_ep(ep_bw->type))
2466 if (udev->speed == USB_SPEED_SUPER) {
2467 if (xhci_is_sync_in_ep(ep_bw->type))
2468 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2469 xhci_get_ss_bw_consumed(ep_bw);
2471 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2472 xhci_get_ss_bw_consumed(ep_bw);
2476 /* For LS/FS devices, we need to translate the interval expressed in
2477 * microframes to frames.
2479 if (udev->speed == USB_SPEED_HIGH)
2480 normalized_interval = ep_bw->ep_interval;
2482 normalized_interval = ep_bw->ep_interval - 3;
2484 if (normalized_interval == 0)
2485 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2486 interval_bw = &bw_table->interval_bw[normalized_interval];
2487 interval_bw->num_packets += ep_bw->num_packets;
2488 switch (udev->speed) {
2490 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2492 case USB_SPEED_FULL:
2493 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2495 case USB_SPEED_HIGH:
2496 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2498 case USB_SPEED_SUPER:
2499 case USB_SPEED_UNKNOWN:
2500 case USB_SPEED_WIRELESS:
2501 /* Should never happen because only LS/FS/HS endpoints will get
2502 * added to the endpoint list.
2508 tt_info->active_eps += 1;
2509 /* Insert the endpoint into the list, largest max packet size first. */
2510 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2512 if (ep_bw->max_packet_size >=
2513 smaller_ep->bw_info.max_packet_size) {
2514 /* Add the new ep before the smaller endpoint */
2515 list_add_tail(&virt_ep->bw_endpoint_list,
2516 &smaller_ep->bw_endpoint_list);
2520 /* Add the new endpoint at the end of the list. */
2521 list_add_tail(&virt_ep->bw_endpoint_list,
2522 &interval_bw->endpoints);
2525 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2526 struct xhci_virt_device *virt_dev,
2529 struct xhci_root_port_bw_info *rh_bw_info;
2530 if (!virt_dev->tt_info)
2533 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2534 if (old_active_eps == 0 &&
2535 virt_dev->tt_info->active_eps != 0) {
2536 rh_bw_info->num_active_tts += 1;
2537 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2538 } else if (old_active_eps != 0 &&
2539 virt_dev->tt_info->active_eps == 0) {
2540 rh_bw_info->num_active_tts -= 1;
2541 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2545 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2546 struct xhci_virt_device *virt_dev,
2547 struct xhci_container_ctx *in_ctx)
2549 struct xhci_bw_info ep_bw_info[31];
2551 struct xhci_input_control_ctx *ctrl_ctx;
2552 int old_active_eps = 0;
2554 if (virt_dev->tt_info)
2555 old_active_eps = virt_dev->tt_info->active_eps;
2557 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2559 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2564 for (i = 0; i < 31; i++) {
2565 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2568 /* Make a copy of the BW info in case we need to revert this */
2569 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2570 sizeof(ep_bw_info[i]));
2571 /* Drop the endpoint from the interval table if the endpoint is
2572 * being dropped or changed.
2574 if (EP_IS_DROPPED(ctrl_ctx, i))
2575 xhci_drop_ep_from_interval_table(xhci,
2576 &virt_dev->eps[i].bw_info,
2582 /* Overwrite the information stored in the endpoints' bw_info */
2583 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2584 for (i = 0; i < 31; i++) {
2585 /* Add any changed or added endpoints to the interval table */
2586 if (EP_IS_ADDED(ctrl_ctx, i))
2587 xhci_add_ep_to_interval_table(xhci,
2588 &virt_dev->eps[i].bw_info,
2595 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2596 /* Ok, this fits in the bandwidth we have.
2597 * Update the number of active TTs.
2599 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2603 /* We don't have enough bandwidth for this, revert the stored info. */
2604 for (i = 0; i < 31; i++) {
2605 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2608 /* Drop the new copies of any added or changed endpoints from
2609 * the interval table.
2611 if (EP_IS_ADDED(ctrl_ctx, i)) {
2612 xhci_drop_ep_from_interval_table(xhci,
2613 &virt_dev->eps[i].bw_info,
2619 /* Revert the endpoint back to its old information */
2620 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2621 sizeof(ep_bw_info[i]));
2622 /* Add any changed or dropped endpoints back into the table */
2623 if (EP_IS_DROPPED(ctrl_ctx, i))
2624 xhci_add_ep_to_interval_table(xhci,
2625 &virt_dev->eps[i].bw_info,
2635 /* Issue a configure endpoint command or evaluate context command
2636 * and wait for it to finish.
2638 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2639 struct usb_device *udev,
2640 struct xhci_command *command,
2641 bool ctx_change, bool must_succeed)
2644 unsigned long flags;
2645 struct xhci_input_control_ctx *ctrl_ctx;
2646 struct xhci_virt_device *virt_dev;
2651 spin_lock_irqsave(&xhci->lock, flags);
2652 virt_dev = xhci->devs[udev->slot_id];
2654 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2656 spin_unlock_irqrestore(&xhci->lock, flags);
2657 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2662 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2663 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2664 spin_unlock_irqrestore(&xhci->lock, flags);
2665 xhci_warn(xhci, "Not enough host resources, "
2666 "active endpoint contexts = %u\n",
2667 xhci->num_active_eps);
2670 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2671 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2672 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2673 xhci_free_host_resources(xhci, ctrl_ctx);
2674 spin_unlock_irqrestore(&xhci->lock, flags);
2675 xhci_warn(xhci, "Not enough bandwidth\n");
2680 ret = xhci_queue_configure_endpoint(xhci, command,
2681 command->in_ctx->dma,
2682 udev->slot_id, must_succeed);
2684 ret = xhci_queue_evaluate_context(xhci, command,
2685 command->in_ctx->dma,
2686 udev->slot_id, must_succeed);
2688 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2689 xhci_free_host_resources(xhci, ctrl_ctx);
2690 spin_unlock_irqrestore(&xhci->lock, flags);
2691 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2692 "FIXME allocate a new ring segment");
2695 xhci_ring_cmd_db(xhci);
2696 spin_unlock_irqrestore(&xhci->lock, flags);
2698 /* Wait for the configure endpoint command to complete */
2699 wait_for_completion(command->completion);
2702 ret = xhci_configure_endpoint_result(xhci, udev,
2705 ret = xhci_evaluate_context_result(xhci, udev,
2708 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2709 spin_lock_irqsave(&xhci->lock, flags);
2710 /* If the command failed, remove the reserved resources.
2711 * Otherwise, clean up the estimate to include dropped eps.
2714 xhci_free_host_resources(xhci, ctrl_ctx);
2716 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2717 spin_unlock_irqrestore(&xhci->lock, flags);
2722 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2723 struct xhci_virt_device *vdev, int i)
2725 struct xhci_virt_ep *ep = &vdev->eps[i];
2727 if (ep->ep_state & EP_HAS_STREAMS) {
2728 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2729 xhci_get_endpoint_address(i));
2730 xhci_free_stream_info(xhci, ep->stream_info);
2731 ep->stream_info = NULL;
2732 ep->ep_state &= ~EP_HAS_STREAMS;
2736 /* Called after one or more calls to xhci_add_endpoint() or
2737 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2738 * to call xhci_reset_bandwidth().
2740 * Since we are in the middle of changing either configuration or
2741 * installing a new alt setting, the USB core won't allow URBs to be
2742 * enqueued for any endpoint on the old config or interface. Nothing
2743 * else should be touching the xhci->devs[slot_id] structure, so we
2744 * don't need to take the xhci->lock for manipulating that.
2746 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2750 struct xhci_hcd *xhci;
2751 struct xhci_virt_device *virt_dev;
2752 struct xhci_input_control_ctx *ctrl_ctx;
2753 struct xhci_slot_ctx *slot_ctx;
2754 struct xhci_command *command;
2756 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2759 xhci = hcd_to_xhci(hcd);
2760 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2761 (xhci->xhc_state & XHCI_STATE_REMOVING))
2764 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2765 virt_dev = xhci->devs[udev->slot_id];
2767 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2771 command->in_ctx = virt_dev->in_ctx;
2773 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2774 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2776 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2779 goto command_cleanup;
2781 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2782 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2783 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2785 /* Don't issue the command if there's no endpoints to update. */
2786 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2787 ctrl_ctx->drop_flags == 0) {
2789 goto command_cleanup;
2791 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2792 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2793 for (i = 31; i >= 1; i--) {
2794 __le32 le32 = cpu_to_le32(BIT(i));
2796 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2797 || (ctrl_ctx->add_flags & le32) || i == 1) {
2798 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2799 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2803 xhci_dbg(xhci, "New Input Control Context:\n");
2804 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2805 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2807 ret = xhci_configure_endpoint(xhci, udev, command,
2810 /* Callee should call reset_bandwidth() */
2811 goto command_cleanup;
2813 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2814 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2815 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2817 /* Free any rings that were dropped, but not changed. */
2818 for (i = 1; i < 31; ++i) {
2819 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2820 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2821 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2822 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2825 xhci_zero_in_ctx(xhci, virt_dev);
2827 * Install any rings for completely new endpoints or changed endpoints,
2828 * and free or cache any old rings from changed endpoints.
2830 for (i = 1; i < 31; ++i) {
2831 if (!virt_dev->eps[i].new_ring)
2833 /* Only cache or free the old ring if it exists.
2834 * It may not if this is the first add of an endpoint.
2836 if (virt_dev->eps[i].ring) {
2837 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2839 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2840 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2841 virt_dev->eps[i].new_ring = NULL;
2844 kfree(command->completion);
2850 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2852 struct xhci_hcd *xhci;
2853 struct xhci_virt_device *virt_dev;
2856 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2859 xhci = hcd_to_xhci(hcd);
2861 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2862 virt_dev = xhci->devs[udev->slot_id];
2863 /* Free any rings allocated for added endpoints */
2864 for (i = 0; i < 31; ++i) {
2865 if (virt_dev->eps[i].new_ring) {
2866 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2867 virt_dev->eps[i].new_ring = NULL;
2870 xhci_zero_in_ctx(xhci, virt_dev);
2873 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2874 struct xhci_container_ctx *in_ctx,
2875 struct xhci_container_ctx *out_ctx,
2876 struct xhci_input_control_ctx *ctrl_ctx,
2877 u32 add_flags, u32 drop_flags)
2879 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2880 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2881 xhci_slot_copy(xhci, in_ctx, out_ctx);
2882 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2884 xhci_dbg(xhci, "Input Context:\n");
2885 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2888 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2889 unsigned int slot_id, unsigned int ep_index,
2890 struct xhci_dequeue_state *deq_state)
2892 struct xhci_input_control_ctx *ctrl_ctx;
2893 struct xhci_container_ctx *in_ctx;
2894 struct xhci_ep_ctx *ep_ctx;
2898 in_ctx = xhci->devs[slot_id]->in_ctx;
2899 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2901 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2906 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2907 xhci->devs[slot_id]->out_ctx, ep_index);
2908 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2909 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2910 deq_state->new_deq_ptr);
2912 xhci_warn(xhci, "WARN Cannot submit config ep after "
2913 "reset ep command\n");
2914 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2915 deq_state->new_deq_seg,
2916 deq_state->new_deq_ptr);
2919 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2921 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2922 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2923 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2924 added_ctxs, added_ctxs);
2927 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2928 unsigned int ep_index, struct xhci_td *td)
2930 struct xhci_dequeue_state deq_state;
2931 struct xhci_virt_ep *ep;
2932 struct usb_device *udev = td->urb->dev;
2934 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2935 "Cleaning up stalled endpoint ring");
2936 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2937 /* We need to move the HW's dequeue pointer past this TD,
2938 * or it will attempt to resend it on the next doorbell ring.
2940 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2941 ep_index, ep->stopped_stream, td, &deq_state);
2943 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2946 /* HW with the reset endpoint quirk will use the saved dequeue state to
2947 * issue a configure endpoint command later.
2949 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2950 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2951 "Queueing new dequeue state");
2952 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2953 ep_index, ep->stopped_stream, &deq_state);
2955 /* Better hope no one uses the input context between now and the
2956 * reset endpoint completion!
2957 * XXX: No idea how this hardware will react when stream rings
2960 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2961 "Setting up input context for "
2962 "configure endpoint command");
2963 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2964 ep_index, &deq_state);
2968 /* Called when clearing halted device. The core should have sent the control
2969 * message to clear the device halt condition. The host side of the halt should
2970 * already be cleared with a reset endpoint command issued when the STALL tx
2971 * event was received.
2973 * Context: in_interrupt
2976 void xhci_endpoint_reset(struct usb_hcd *hcd,
2977 struct usb_host_endpoint *ep)
2979 struct xhci_hcd *xhci;
2981 xhci = hcd_to_xhci(hcd);
2984 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2985 * The Reset Endpoint Command may only be issued to endpoints in the
2986 * Halted state. If software wishes reset the Data Toggle or Sequence
2987 * Number of an endpoint that isn't in the Halted state, then software
2988 * may issue a Configure Endpoint Command with the Drop and Add bits set
2989 * for the target endpoint. that is in the Stopped state.
2992 /* For now just print debug to follow the situation */
2993 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2994 ep->desc.bEndpointAddress);
2997 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2998 struct usb_device *udev, struct usb_host_endpoint *ep,
2999 unsigned int slot_id)
3002 unsigned int ep_index;
3003 unsigned int ep_state;
3007 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3010 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3011 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3012 " descriptor for ep 0x%x does not support streams\n",
3013 ep->desc.bEndpointAddress);
3017 ep_index = xhci_get_endpoint_index(&ep->desc);
3018 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3019 if (ep_state & EP_HAS_STREAMS ||
3020 ep_state & EP_GETTING_STREAMS) {
3021 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3022 "already has streams set up.\n",
3023 ep->desc.bEndpointAddress);
3024 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3025 "dynamic stream context array reallocation.\n");
3028 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3029 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3030 "endpoint 0x%x; URBs are pending.\n",
3031 ep->desc.bEndpointAddress);
3037 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3038 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3040 unsigned int max_streams;
3042 /* The stream context array size must be a power of two */
3043 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3045 * Find out how many primary stream array entries the host controller
3046 * supports. Later we may use secondary stream arrays (similar to 2nd
3047 * level page entries), but that's an optional feature for xHCI host
3048 * controllers. xHCs must support at least 4 stream IDs.
3050 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3051 if (*num_stream_ctxs > max_streams) {
3052 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3054 *num_stream_ctxs = max_streams;
3055 *num_streams = max_streams;
3059 /* Returns an error code if one of the endpoint already has streams.
3060 * This does not change any data structures, it only checks and gathers
3063 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3064 struct usb_device *udev,
3065 struct usb_host_endpoint **eps, unsigned int num_eps,
3066 unsigned int *num_streams, u32 *changed_ep_bitmask)
3068 unsigned int max_streams;
3069 unsigned int endpoint_flag;
3073 for (i = 0; i < num_eps; i++) {
3074 ret = xhci_check_streams_endpoint(xhci, udev,
3075 eps[i], udev->slot_id);
3079 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3080 if (max_streams < (*num_streams - 1)) {
3081 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3082 eps[i]->desc.bEndpointAddress,
3084 *num_streams = max_streams+1;
3087 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3088 if (*changed_ep_bitmask & endpoint_flag)
3090 *changed_ep_bitmask |= endpoint_flag;
3095 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3096 struct usb_device *udev,
3097 struct usb_host_endpoint **eps, unsigned int num_eps)
3099 u32 changed_ep_bitmask = 0;
3100 unsigned int slot_id;
3101 unsigned int ep_index;
3102 unsigned int ep_state;
3105 slot_id = udev->slot_id;
3106 if (!xhci->devs[slot_id])
3109 for (i = 0; i < num_eps; i++) {
3110 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3111 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3112 /* Are streams already being freed for the endpoint? */
3113 if (ep_state & EP_GETTING_NO_STREAMS) {
3114 xhci_warn(xhci, "WARN Can't disable streams for "
3116 "streams are being disabled already\n",
3117 eps[i]->desc.bEndpointAddress);
3120 /* Are there actually any streams to free? */
3121 if (!(ep_state & EP_HAS_STREAMS) &&
3122 !(ep_state & EP_GETTING_STREAMS)) {
3123 xhci_warn(xhci, "WARN Can't disable streams for "
3125 "streams are already disabled!\n",
3126 eps[i]->desc.bEndpointAddress);
3127 xhci_warn(xhci, "WARN xhci_free_streams() called "
3128 "with non-streams endpoint\n");
3131 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3133 return changed_ep_bitmask;
3137 * The USB device drivers use this function (through the HCD interface in USB
3138 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3139 * coordinate mass storage command queueing across multiple endpoints (basically
3140 * a stream ID == a task ID).
3142 * Setting up streams involves allocating the same size stream context array
3143 * for each endpoint and issuing a configure endpoint command for all endpoints.
3145 * Don't allow the call to succeed if one endpoint only supports one stream
3146 * (which means it doesn't support streams at all).
3148 * Drivers may get less stream IDs than they asked for, if the host controller
3149 * hardware or endpoints claim they can't support the number of requested
3152 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3153 struct usb_host_endpoint **eps, unsigned int num_eps,
3154 unsigned int num_streams, gfp_t mem_flags)
3157 struct xhci_hcd *xhci;
3158 struct xhci_virt_device *vdev;
3159 struct xhci_command *config_cmd;
3160 struct xhci_input_control_ctx *ctrl_ctx;
3161 unsigned int ep_index;
3162 unsigned int num_stream_ctxs;
3163 unsigned long flags;
3164 u32 changed_ep_bitmask = 0;
3169 /* Add one to the number of streams requested to account for
3170 * stream 0 that is reserved for xHCI usage.
3173 xhci = hcd_to_xhci(hcd);
3174 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3177 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3178 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3179 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3180 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3184 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3186 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3189 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3191 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3193 xhci_free_command(xhci, config_cmd);
3197 /* Check to make sure all endpoints are not already configured for
3198 * streams. While we're at it, find the maximum number of streams that
3199 * all the endpoints will support and check for duplicate endpoints.
3201 spin_lock_irqsave(&xhci->lock, flags);
3202 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3203 num_eps, &num_streams, &changed_ep_bitmask);
3205 xhci_free_command(xhci, config_cmd);
3206 spin_unlock_irqrestore(&xhci->lock, flags);
3209 if (num_streams <= 1) {
3210 xhci_warn(xhci, "WARN: endpoints can't handle "
3211 "more than one stream.\n");
3212 xhci_free_command(xhci, config_cmd);
3213 spin_unlock_irqrestore(&xhci->lock, flags);
3216 vdev = xhci->devs[udev->slot_id];
3217 /* Mark each endpoint as being in transition, so
3218 * xhci_urb_enqueue() will reject all URBs.
3220 for (i = 0; i < num_eps; i++) {
3221 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3222 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3224 spin_unlock_irqrestore(&xhci->lock, flags);
3226 /* Setup internal data structures and allocate HW data structures for
3227 * streams (but don't install the HW structures in the input context
3228 * until we're sure all memory allocation succeeded).
3230 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3231 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3232 num_stream_ctxs, num_streams);
3234 for (i = 0; i < num_eps; i++) {
3235 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3236 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3238 num_streams, mem_flags);
3239 if (!vdev->eps[ep_index].stream_info)
3241 /* Set maxPstreams in endpoint context and update deq ptr to
3242 * point to stream context array. FIXME
3246 /* Set up the input context for a configure endpoint command. */
3247 for (i = 0; i < num_eps; i++) {
3248 struct xhci_ep_ctx *ep_ctx;
3250 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3251 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3253 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3254 vdev->out_ctx, ep_index);
3255 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3256 vdev->eps[ep_index].stream_info);
3258 /* Tell the HW to drop its old copy of the endpoint context info
3259 * and add the updated copy from the input context.
3261 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3262 vdev->out_ctx, ctrl_ctx,
3263 changed_ep_bitmask, changed_ep_bitmask);
3265 /* Issue and wait for the configure endpoint command */
3266 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3269 /* xHC rejected the configure endpoint command for some reason, so we
3270 * leave the old ring intact and free our internal streams data
3276 spin_lock_irqsave(&xhci->lock, flags);
3277 for (i = 0; i < num_eps; i++) {
3278 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3279 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3280 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3281 udev->slot_id, ep_index);
3282 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3284 xhci_free_command(xhci, config_cmd);
3285 spin_unlock_irqrestore(&xhci->lock, flags);
3287 /* Subtract 1 for stream 0, which drivers can't use */
3288 return num_streams - 1;
3291 /* If it didn't work, free the streams! */
3292 for (i = 0; i < num_eps; i++) {
3293 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3294 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3295 vdev->eps[ep_index].stream_info = NULL;
3296 /* FIXME Unset maxPstreams in endpoint context and
3297 * update deq ptr to point to normal string ring.
3299 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3300 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3301 xhci_endpoint_zero(xhci, vdev, eps[i]);
3303 xhci_free_command(xhci, config_cmd);
3307 /* Transition the endpoint from using streams to being a "normal" endpoint
3310 * Modify the endpoint context state, submit a configure endpoint command,
3311 * and free all endpoint rings for streams if that completes successfully.
3313 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3314 struct usb_host_endpoint **eps, unsigned int num_eps,
3318 struct xhci_hcd *xhci;
3319 struct xhci_virt_device *vdev;
3320 struct xhci_command *command;
3321 struct xhci_input_control_ctx *ctrl_ctx;
3322 unsigned int ep_index;
3323 unsigned long flags;
3324 u32 changed_ep_bitmask;
3326 xhci = hcd_to_xhci(hcd);
3327 vdev = xhci->devs[udev->slot_id];
3329 /* Set up a configure endpoint command to remove the streams rings */
3330 spin_lock_irqsave(&xhci->lock, flags);
3331 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3332 udev, eps, num_eps);
3333 if (changed_ep_bitmask == 0) {
3334 spin_unlock_irqrestore(&xhci->lock, flags);
3338 /* Use the xhci_command structure from the first endpoint. We may have
3339 * allocated too many, but the driver may call xhci_free_streams() for
3340 * each endpoint it grouped into one call to xhci_alloc_streams().
3342 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3343 command = vdev->eps[ep_index].stream_info->free_streams_command;
3344 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3346 spin_unlock_irqrestore(&xhci->lock, flags);
3347 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3352 for (i = 0; i < num_eps; i++) {
3353 struct xhci_ep_ctx *ep_ctx;
3355 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3356 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3357 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3358 EP_GETTING_NO_STREAMS;
3360 xhci_endpoint_copy(xhci, command->in_ctx,
3361 vdev->out_ctx, ep_index);
3362 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3363 &vdev->eps[ep_index]);
3365 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3366 vdev->out_ctx, ctrl_ctx,
3367 changed_ep_bitmask, changed_ep_bitmask);
3368 spin_unlock_irqrestore(&xhci->lock, flags);
3370 /* Issue and wait for the configure endpoint command,
3371 * which must succeed.
3373 ret = xhci_configure_endpoint(xhci, udev, command,
3376 /* xHC rejected the configure endpoint command for some reason, so we
3377 * leave the streams rings intact.
3382 spin_lock_irqsave(&xhci->lock, flags);
3383 for (i = 0; i < num_eps; i++) {
3384 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3385 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3386 vdev->eps[ep_index].stream_info = NULL;
3387 /* FIXME Unset maxPstreams in endpoint context and
3388 * update deq ptr to point to normal string ring.
3390 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3391 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3393 spin_unlock_irqrestore(&xhci->lock, flags);
3399 * Deletes endpoint resources for endpoints that were active before a Reset
3400 * Device command, or a Disable Slot command. The Reset Device command leaves
3401 * the control endpoint intact, whereas the Disable Slot command deletes it.
3403 * Must be called with xhci->lock held.
3405 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3406 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3409 unsigned int num_dropped_eps = 0;
3410 unsigned int drop_flags = 0;
3412 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3413 if (virt_dev->eps[i].ring) {
3414 drop_flags |= 1 << i;
3418 xhci->num_active_eps -= num_dropped_eps;
3419 if (num_dropped_eps)
3420 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3421 "Dropped %u ep ctxs, flags = 0x%x, "
3423 num_dropped_eps, drop_flags,
3424 xhci->num_active_eps);
3428 * This submits a Reset Device Command, which will set the device state to 0,
3429 * set the device address to 0, and disable all the endpoints except the default
3430 * control endpoint. The USB core should come back and call
3431 * xhci_address_device(), and then re-set up the configuration. If this is
3432 * called because of a usb_reset_and_verify_device(), then the old alternate
3433 * settings will be re-installed through the normal bandwidth allocation
3436 * Wait for the Reset Device command to finish. Remove all structures
3437 * associated with the endpoints that were disabled. Clear the input device
3438 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3440 * If the virt_dev to be reset does not exist or does not match the udev,
3441 * it means the device is lost, possibly due to the xHC restore error and
3442 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3443 * re-allocate the device.
3445 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3448 unsigned long flags;
3449 struct xhci_hcd *xhci;
3450 unsigned int slot_id;
3451 struct xhci_virt_device *virt_dev;
3452 struct xhci_command *reset_device_cmd;
3453 int last_freed_endpoint;
3454 struct xhci_slot_ctx *slot_ctx;
3455 int old_active_eps = 0;
3457 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3460 xhci = hcd_to_xhci(hcd);
3461 slot_id = udev->slot_id;
3462 virt_dev = xhci->devs[slot_id];
3464 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3465 "not exist. Re-allocate the device\n", slot_id);
3466 ret = xhci_alloc_dev(hcd, udev);
3473 if (virt_dev->tt_info)
3474 old_active_eps = virt_dev->tt_info->active_eps;
3476 if (virt_dev->udev != udev) {
3477 /* If the virt_dev and the udev does not match, this virt_dev
3478 * may belong to another udev.
3479 * Re-allocate the device.
3481 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3482 "not match the udev. Re-allocate the device\n",
3484 ret = xhci_alloc_dev(hcd, udev);
3491 /* If device is not setup, there is no point in resetting it */
3492 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3493 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3494 SLOT_STATE_DISABLED)
3497 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3498 /* Allocate the command structure that holds the struct completion.
3499 * Assume we're in process context, since the normal device reset
3500 * process has to wait for the device anyway. Storage devices are
3501 * reset as part of error handling, so use GFP_NOIO instead of
3504 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3505 if (!reset_device_cmd) {
3506 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3510 /* Attempt to submit the Reset Device command to the command ring */
3511 spin_lock_irqsave(&xhci->lock, flags);
3513 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3515 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3516 spin_unlock_irqrestore(&xhci->lock, flags);
3517 goto command_cleanup;
3519 xhci_ring_cmd_db(xhci);
3520 spin_unlock_irqrestore(&xhci->lock, flags);
3522 /* Wait for the Reset Device command to finish */
3523 wait_for_completion(reset_device_cmd->completion);
3525 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3526 * unless we tried to reset a slot ID that wasn't enabled,
3527 * or the device wasn't in the addressed or configured state.
3529 ret = reset_device_cmd->status;
3531 case COMP_CMD_ABORT:
3533 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3535 goto command_cleanup;
3536 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3537 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3538 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3540 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3541 xhci_dbg(xhci, "Not freeing device rings.\n");
3542 /* Don't treat this as an error. May change my mind later. */
3544 goto command_cleanup;
3546 xhci_dbg(xhci, "Successful reset device command.\n");
3549 if (xhci_is_vendor_info_code(xhci, ret))
3551 xhci_warn(xhci, "Unknown completion code %u for "
3552 "reset device command.\n", ret);
3554 goto command_cleanup;
3557 /* Free up host controller endpoint resources */
3558 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3559 spin_lock_irqsave(&xhci->lock, flags);
3560 /* Don't delete the default control endpoint resources */
3561 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3562 spin_unlock_irqrestore(&xhci->lock, flags);
3565 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3566 last_freed_endpoint = 1;
3567 for (i = 1; i < 31; ++i) {
3568 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3570 if (ep->ep_state & EP_HAS_STREAMS) {
3571 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3572 xhci_get_endpoint_address(i));
3573 xhci_free_stream_info(xhci, ep->stream_info);
3574 ep->stream_info = NULL;
3575 ep->ep_state &= ~EP_HAS_STREAMS;
3579 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3580 last_freed_endpoint = i;
3582 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3583 xhci_drop_ep_from_interval_table(xhci,
3584 &virt_dev->eps[i].bw_info,
3589 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3591 /* If necessary, update the number of active TTs on this root port */
3592 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3594 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3595 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3599 xhci_free_command(xhci, reset_device_cmd);
3604 * At this point, the struct usb_device is about to go away, the device has
3605 * disconnected, and all traffic has been stopped and the endpoints have been
3606 * disabled. Free any HC data structures associated with that device.
3608 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3610 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3611 struct xhci_virt_device *virt_dev;
3612 unsigned long flags;
3615 struct xhci_command *command;
3617 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3621 #ifndef CONFIG_USB_DEFAULT_PERSIST
3623 * We called pm_runtime_get_noresume when the device was attached.
3624 * Decrement the counter here to allow controller to runtime suspend
3625 * if no devices remain.
3627 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3628 pm_runtime_put_noidle(hcd->self.controller);
3631 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3632 /* If the host is halted due to driver unload, we still need to free the
3635 if (ret <= 0 && ret != -ENODEV) {
3640 virt_dev = xhci->devs[udev->slot_id];
3642 /* Stop any wayward timer functions (which may grab the lock) */
3643 for (i = 0; i < 31; ++i) {
3644 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3645 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3648 spin_lock_irqsave(&xhci->lock, flags);
3649 /* Don't disable the slot if the host controller is dead. */
3650 state = readl(&xhci->op_regs->status);
3651 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3652 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3653 xhci_free_virt_device(xhci, udev->slot_id);
3654 spin_unlock_irqrestore(&xhci->lock, flags);
3659 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3661 spin_unlock_irqrestore(&xhci->lock, flags);
3662 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3665 xhci_ring_cmd_db(xhci);
3666 spin_unlock_irqrestore(&xhci->lock, flags);
3669 * Event command completion handler will free any data structures
3670 * associated with the slot. XXX Can free sleep?
3675 * Checks if we have enough host controller resources for the default control
3678 * Must be called with xhci->lock held.
3680 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3682 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3683 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3684 "Not enough ep ctxs: "
3685 "%u active, need to add 1, limit is %u.",
3686 xhci->num_active_eps, xhci->limit_active_eps);
3689 xhci->num_active_eps += 1;
3690 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3691 "Adding 1 ep ctx, %u now active.",
3692 xhci->num_active_eps);
3698 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3699 * timed out, or allocating memory failed. Returns 1 on success.
3701 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3703 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3704 unsigned long flags;
3706 struct xhci_command *command;
3708 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3712 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3713 mutex_lock(&xhci->mutex);
3714 spin_lock_irqsave(&xhci->lock, flags);
3715 command->completion = &xhci->addr_dev;
3716 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3718 spin_unlock_irqrestore(&xhci->lock, flags);
3719 mutex_unlock(&xhci->mutex);
3720 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3724 xhci_ring_cmd_db(xhci);
3725 spin_unlock_irqrestore(&xhci->lock, flags);
3727 wait_for_completion(command->completion);
3728 slot_id = xhci->slot_id;
3729 mutex_unlock(&xhci->mutex);
3731 if (!slot_id || command->status != COMP_SUCCESS) {
3732 xhci_err(xhci, "Error while assigning device slot ID\n");
3733 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3735 readl(&xhci->cap_regs->hcs_params1)));
3740 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3741 spin_lock_irqsave(&xhci->lock, flags);
3742 ret = xhci_reserve_host_control_ep_resources(xhci);
3744 spin_unlock_irqrestore(&xhci->lock, flags);
3745 xhci_warn(xhci, "Not enough host resources, "
3746 "active endpoint contexts = %u\n",
3747 xhci->num_active_eps);
3750 spin_unlock_irqrestore(&xhci->lock, flags);
3752 /* Use GFP_NOIO, since this function can be called from
3753 * xhci_discover_or_reset_device(), which may be called as part of
3754 * mass storage driver error handling.
3756 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3757 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3760 udev->slot_id = slot_id;
3762 #ifndef CONFIG_USB_DEFAULT_PERSIST
3764 * If resetting upon resume, we can't put the controller into runtime
3765 * suspend if there is a device attached.
3767 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3768 pm_runtime_get_noresume(hcd->self.controller);
3773 /* Is this a LS or FS device under a HS hub? */
3774 /* Hub or peripherial? */
3778 /* Disable slot, if we can do it without mem alloc */
3779 spin_lock_irqsave(&xhci->lock, flags);
3780 command->completion = NULL;
3781 command->status = 0;
3782 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3784 xhci_ring_cmd_db(xhci);
3785 spin_unlock_irqrestore(&xhci->lock, flags);
3790 * Issue an Address Device command and optionally send a corresponding
3791 * SetAddress request to the device.
3793 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3794 enum xhci_setup_dev setup)
3796 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3797 unsigned long flags;
3798 struct xhci_virt_device *virt_dev;
3800 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3801 struct xhci_slot_ctx *slot_ctx;
3802 struct xhci_input_control_ctx *ctrl_ctx;
3804 struct xhci_command *command = NULL;
3806 mutex_lock(&xhci->mutex);
3808 if (xhci->xhc_state) /* dying, removing or halted */
3811 if (!udev->slot_id) {
3812 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3813 "Bad Slot ID %d", udev->slot_id);
3818 virt_dev = xhci->devs[udev->slot_id];
3820 if (WARN_ON(!virt_dev)) {
3822 * In plug/unplug torture test with an NEC controller,
3823 * a zero-dereference was observed once due to virt_dev = 0.
3824 * Print useful debug rather than crash if it is observed again!
3826 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3832 if (setup == SETUP_CONTEXT_ONLY) {
3833 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3834 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3835 SLOT_STATE_DEFAULT) {
3836 xhci_dbg(xhci, "Slot already in default state\n");
3841 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3847 command->in_ctx = virt_dev->in_ctx;
3848 command->completion = &xhci->addr_dev;
3850 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3851 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3853 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3859 * If this is the first Set Address since device plug-in or
3860 * virt_device realloaction after a resume with an xHCI power loss,
3861 * then set up the slot context.
3863 if (!slot_ctx->dev_info)
3864 xhci_setup_addressable_virt_dev(xhci, udev);
3865 /* Otherwise, update the control endpoint ring enqueue pointer. */
3867 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3868 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3869 ctrl_ctx->drop_flags = 0;
3871 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3872 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3873 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3874 le32_to_cpu(slot_ctx->dev_info) >> 27);
3876 spin_lock_irqsave(&xhci->lock, flags);
3877 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3878 udev->slot_id, setup);
3880 spin_unlock_irqrestore(&xhci->lock, flags);
3881 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3882 "FIXME: allocate a command ring segment");
3885 xhci_ring_cmd_db(xhci);
3886 spin_unlock_irqrestore(&xhci->lock, flags);
3888 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3889 wait_for_completion(command->completion);
3891 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3892 * the SetAddress() "recovery interval" required by USB and aborting the
3893 * command on a timeout.
3895 switch (command->status) {
3896 case COMP_CMD_ABORT:
3898 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3901 case COMP_CTX_STATE:
3903 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3904 act, udev->slot_id);
3908 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3912 dev_warn(&udev->dev,
3913 "ERROR: Incompatible device for setup %s command\n", act);
3917 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3918 "Successful setup %s command", act);
3922 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3923 act, command->status);
3924 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3925 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3926 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3932 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3933 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3934 "Op regs DCBAA ptr = %#016llx", temp_64);
3935 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3936 "Slot ID %d dcbaa entry @%p = %#016llx",
3938 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3939 (unsigned long long)
3940 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3941 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3942 "Output Context DMA address = %#08llx",
3943 (unsigned long long)virt_dev->out_ctx->dma);
3944 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3945 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3946 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3947 le32_to_cpu(slot_ctx->dev_info) >> 27);
3948 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3949 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3951 * USB core uses address 1 for the roothubs, so we add one to the
3952 * address given back to us by the HC.
3954 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3955 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3956 le32_to_cpu(slot_ctx->dev_info) >> 27);
3957 /* Zero the input context control for later use */
3958 ctrl_ctx->add_flags = 0;
3959 ctrl_ctx->drop_flags = 0;
3961 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3962 "Internal device address = %d",
3963 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3965 mutex_unlock(&xhci->mutex);
3970 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3972 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3975 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3977 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3981 * Transfer the port index into real index in the HW port status
3982 * registers. Caculate offset between the port's PORTSC register
3983 * and port status base. Divide the number of per port register
3984 * to get the real index. The raw port number bases 1.
3986 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3988 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3989 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3990 __le32 __iomem *addr;
3993 if (hcd->speed < HCD_USB3)
3994 addr = xhci->usb2_ports[port1 - 1];
3996 addr = xhci->usb3_ports[port1 - 1];
3998 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4003 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4004 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4006 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4007 struct usb_device *udev, u16 max_exit_latency)
4009 struct xhci_virt_device *virt_dev;
4010 struct xhci_command *command;
4011 struct xhci_input_control_ctx *ctrl_ctx;
4012 struct xhci_slot_ctx *slot_ctx;
4013 unsigned long flags;
4016 spin_lock_irqsave(&xhci->lock, flags);
4018 virt_dev = xhci->devs[udev->slot_id];
4021 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4022 * xHC was re-initialized. Exit latency will be set later after
4023 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4026 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4027 spin_unlock_irqrestore(&xhci->lock, flags);
4031 /* Attempt to issue an Evaluate Context command to change the MEL. */
4032 command = xhci->lpm_command;
4033 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4035 spin_unlock_irqrestore(&xhci->lock, flags);
4036 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4041 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4042 spin_unlock_irqrestore(&xhci->lock, flags);
4044 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4045 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4046 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4047 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4048 slot_ctx->dev_state = 0;
4050 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4051 "Set up evaluate context for LPM MEL change.");
4052 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4053 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4055 /* Issue and wait for the evaluate context command. */
4056 ret = xhci_configure_endpoint(xhci, udev, command,
4058 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4059 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4062 spin_lock_irqsave(&xhci->lock, flags);
4063 virt_dev->current_mel = max_exit_latency;
4064 spin_unlock_irqrestore(&xhci->lock, flags);
4071 /* BESL to HIRD Encoding array for USB2 LPM */
4072 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4073 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4075 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4076 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4077 struct usb_device *udev)
4079 int u2del, besl, besl_host;
4080 int besl_device = 0;
4083 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4084 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4086 if (field & USB_BESL_SUPPORT) {
4087 for (besl_host = 0; besl_host < 16; besl_host++) {
4088 if (xhci_besl_encoding[besl_host] >= u2del)
4091 /* Use baseline BESL value as default */
4092 if (field & USB_BESL_BASELINE_VALID)
4093 besl_device = USB_GET_BESL_BASELINE(field);
4094 else if (field & USB_BESL_DEEP_VALID)
4095 besl_device = USB_GET_BESL_DEEP(field);
4100 besl_host = (u2del - 51) / 75 + 1;
4103 besl = besl_host + besl_device;
4110 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4111 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4118 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4120 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4121 l1 = udev->l1_params.timeout / 256;
4123 /* device has preferred BESLD */
4124 if (field & USB_BESL_DEEP_VALID) {
4125 besld = USB_GET_BESL_DEEP(field);
4129 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4132 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4133 struct usb_device *udev, int enable)
4135 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4136 __le32 __iomem **port_array;
4137 __le32 __iomem *pm_addr, *hlpm_addr;
4138 u32 pm_val, hlpm_val, field;
4139 unsigned int port_num;
4140 unsigned long flags;
4141 int hird, exit_latency;
4144 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4148 if (!udev->parent || udev->parent->parent ||
4149 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4152 if (udev->usb2_hw_lpm_capable != 1)
4155 spin_lock_irqsave(&xhci->lock, flags);
4157 port_array = xhci->usb2_ports;
4158 port_num = udev->portnum - 1;
4159 pm_addr = port_array[port_num] + PORTPMSC;
4160 pm_val = readl(pm_addr);
4161 hlpm_addr = port_array[port_num] + PORTHLPMC;
4162 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4164 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4165 enable ? "enable" : "disable", port_num + 1);
4168 /* Host supports BESL timeout instead of HIRD */
4169 if (udev->usb2_hw_lpm_besl_capable) {
4170 /* if device doesn't have a preferred BESL value use a
4171 * default one which works with mixed HIRD and BESL
4172 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4174 if ((field & USB_BESL_SUPPORT) &&
4175 (field & USB_BESL_BASELINE_VALID))
4176 hird = USB_GET_BESL_BASELINE(field);
4178 hird = udev->l1_params.besl;
4180 exit_latency = xhci_besl_encoding[hird];
4181 spin_unlock_irqrestore(&xhci->lock, flags);
4183 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4184 * input context for link powermanagement evaluate
4185 * context commands. It is protected by hcd->bandwidth
4186 * mutex and is shared by all devices. We need to set
4187 * the max ext latency in USB 2 BESL LPM as well, so
4188 * use the same mutex and xhci_change_max_exit_latency()
4190 mutex_lock(hcd->bandwidth_mutex);
4191 ret = xhci_change_max_exit_latency(xhci, udev,
4193 mutex_unlock(hcd->bandwidth_mutex);
4197 spin_lock_irqsave(&xhci->lock, flags);
4199 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4200 writel(hlpm_val, hlpm_addr);
4204 hird = xhci_calculate_hird_besl(xhci, udev);
4207 pm_val &= ~PORT_HIRD_MASK;
4208 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4209 writel(pm_val, pm_addr);
4210 pm_val = readl(pm_addr);
4212 writel(pm_val, pm_addr);
4216 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4217 writel(pm_val, pm_addr);
4220 if (udev->usb2_hw_lpm_besl_capable) {
4221 spin_unlock_irqrestore(&xhci->lock, flags);
4222 mutex_lock(hcd->bandwidth_mutex);
4223 xhci_change_max_exit_latency(xhci, udev, 0);
4224 mutex_unlock(hcd->bandwidth_mutex);
4229 spin_unlock_irqrestore(&xhci->lock, flags);
4233 /* check if a usb2 port supports a given extened capability protocol
4234 * only USB2 ports extended protocol capability values are cached.
4235 * Return 1 if capability is supported
4237 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4238 unsigned capability)
4240 u32 port_offset, port_count;
4243 for (i = 0; i < xhci->num_ext_caps; i++) {
4244 if (xhci->ext_caps[i] & capability) {
4245 /* port offsets starts at 1 */
4246 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4247 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4248 if (port >= port_offset &&
4249 port < port_offset + port_count)
4256 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4258 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4259 int portnum = udev->portnum - 1;
4261 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4265 /* we only support lpm for non-hub device connected to root hub yet */
4266 if (!udev->parent || udev->parent->parent ||
4267 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4270 if (xhci->hw_lpm_support == 1 &&
4271 xhci_check_usb2_port_capability(
4272 xhci, portnum, XHCI_HLC)) {
4273 udev->usb2_hw_lpm_capable = 1;
4274 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4275 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4276 if (xhci_check_usb2_port_capability(xhci, portnum,
4278 udev->usb2_hw_lpm_besl_capable = 1;
4284 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4286 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4287 static unsigned long long xhci_service_interval_to_ns(
4288 struct usb_endpoint_descriptor *desc)
4290 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4293 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4294 enum usb3_link_state state)
4296 unsigned long long sel;
4297 unsigned long long pel;
4298 unsigned int max_sel_pel;
4303 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4304 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4305 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4306 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4310 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4311 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4312 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4316 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4318 return USB3_LPM_DISABLED;
4321 if (sel <= max_sel_pel && pel <= max_sel_pel)
4322 return USB3_LPM_DEVICE_INITIATED;
4324 if (sel > max_sel_pel)
4325 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4326 "due to long SEL %llu ms\n",
4329 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4330 "due to long PEL %llu ms\n",
4332 return USB3_LPM_DISABLED;
4335 /* The U1 timeout should be the maximum of the following values:
4336 * - For control endpoints, U1 system exit latency (SEL) * 3
4337 * - For bulk endpoints, U1 SEL * 5
4338 * - For interrupt endpoints:
4339 * - Notification EPs, U1 SEL * 3
4340 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4341 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4343 static unsigned long long xhci_calculate_intel_u1_timeout(
4344 struct usb_device *udev,
4345 struct usb_endpoint_descriptor *desc)
4347 unsigned long long timeout_ns;
4351 ep_type = usb_endpoint_type(desc);
4353 case USB_ENDPOINT_XFER_CONTROL:
4354 timeout_ns = udev->u1_params.sel * 3;
4356 case USB_ENDPOINT_XFER_BULK:
4357 timeout_ns = udev->u1_params.sel * 5;
4359 case USB_ENDPOINT_XFER_INT:
4360 intr_type = usb_endpoint_interrupt_type(desc);
4361 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4362 timeout_ns = udev->u1_params.sel * 3;
4365 /* Otherwise the calculation is the same as isoc eps */
4366 case USB_ENDPOINT_XFER_ISOC:
4367 timeout_ns = xhci_service_interval_to_ns(desc);
4368 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4369 if (timeout_ns < udev->u1_params.sel * 2)
4370 timeout_ns = udev->u1_params.sel * 2;
4379 /* Returns the hub-encoded U1 timeout value. */
4380 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4381 struct usb_device *udev,
4382 struct usb_endpoint_descriptor *desc)
4384 unsigned long long timeout_ns;
4386 if (xhci->quirks & XHCI_INTEL_HOST)
4387 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4389 timeout_ns = udev->u1_params.sel;
4391 /* The U1 timeout is encoded in 1us intervals.
4392 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4394 if (timeout_ns == USB3_LPM_DISABLED)
4397 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4399 /* If the necessary timeout value is bigger than what we can set in the
4400 * USB 3.0 hub, we have to disable hub-initiated U1.
4402 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4404 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4405 "due to long timeout %llu ms\n", timeout_ns);
4406 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4409 /* The U2 timeout should be the maximum of:
4410 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4411 * - largest bInterval of any active periodic endpoint (to avoid going
4412 * into lower power link states between intervals).
4413 * - the U2 Exit Latency of the device
4415 static unsigned long long xhci_calculate_intel_u2_timeout(
4416 struct usb_device *udev,
4417 struct usb_endpoint_descriptor *desc)
4419 unsigned long long timeout_ns;
4420 unsigned long long u2_del_ns;
4422 timeout_ns = 10 * 1000 * 1000;
4424 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4425 (xhci_service_interval_to_ns(desc) > timeout_ns))
4426 timeout_ns = xhci_service_interval_to_ns(desc);
4428 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4429 if (u2_del_ns > timeout_ns)
4430 timeout_ns = u2_del_ns;
4435 /* Returns the hub-encoded U2 timeout value. */
4436 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4437 struct usb_device *udev,
4438 struct usb_endpoint_descriptor *desc)
4440 unsigned long long timeout_ns;
4442 if (xhci->quirks & XHCI_INTEL_HOST)
4443 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4445 timeout_ns = udev->u2_params.sel;
4447 /* The U2 timeout is encoded in 256us intervals */
4448 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4449 /* If the necessary timeout value is bigger than what we can set in the
4450 * USB 3.0 hub, we have to disable hub-initiated U2.
4452 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4454 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4455 "due to long timeout %llu ms\n", timeout_ns);
4456 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4459 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4460 struct usb_device *udev,
4461 struct usb_endpoint_descriptor *desc,
4462 enum usb3_link_state state,
4465 if (state == USB3_LPM_U1)
4466 return xhci_calculate_u1_timeout(xhci, udev, desc);
4467 else if (state == USB3_LPM_U2)
4468 return xhci_calculate_u2_timeout(xhci, udev, desc);
4470 return USB3_LPM_DISABLED;
4473 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4474 struct usb_device *udev,
4475 struct usb_endpoint_descriptor *desc,
4476 enum usb3_link_state state,
4481 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4482 desc, state, timeout);
4484 /* If we found we can't enable hub-initiated LPM, or
4485 * the U1 or U2 exit latency was too high to allow
4486 * device-initiated LPM as well, just stop searching.
4488 if (alt_timeout == USB3_LPM_DISABLED ||
4489 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4490 *timeout = alt_timeout;
4493 if (alt_timeout > *timeout)
4494 *timeout = alt_timeout;
4498 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4499 struct usb_device *udev,
4500 struct usb_host_interface *alt,
4501 enum usb3_link_state state,
4506 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4507 if (xhci_update_timeout_for_endpoint(xhci, udev,
4508 &alt->endpoint[j].desc, state, timeout))
4515 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4516 enum usb3_link_state state)
4518 struct usb_device *parent;
4519 unsigned int num_hubs;
4521 if (state == USB3_LPM_U2)
4524 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4525 for (parent = udev->parent, num_hubs = 0; parent->parent;
4526 parent = parent->parent)
4532 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4533 " below second-tier hub.\n");
4534 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4535 "to decrease power consumption.\n");
4539 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4540 struct usb_device *udev,
4541 enum usb3_link_state state)
4543 if (xhci->quirks & XHCI_INTEL_HOST)
4544 return xhci_check_intel_tier_policy(udev, state);
4549 /* Returns the U1 or U2 timeout that should be enabled.
4550 * If the tier check or timeout setting functions return with a non-zero exit
4551 * code, that means the timeout value has been finalized and we shouldn't look
4552 * at any more endpoints.
4554 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4555 struct usb_device *udev, enum usb3_link_state state)
4557 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4558 struct usb_host_config *config;
4561 u16 timeout = USB3_LPM_DISABLED;
4563 if (state == USB3_LPM_U1)
4565 else if (state == USB3_LPM_U2)
4568 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4573 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4576 /* Gather some information about the currently installed configuration
4577 * and alternate interface settings.
4579 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4583 config = udev->actconfig;
4587 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4588 struct usb_driver *driver;
4589 struct usb_interface *intf = config->interface[i];
4594 /* Check if any currently bound drivers want hub-initiated LPM
4597 if (intf->dev.driver) {
4598 driver = to_usb_driver(intf->dev.driver);
4599 if (driver && driver->disable_hub_initiated_lpm) {
4600 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4601 "at request of driver %s\n",
4602 state_name, driver->name);
4603 return xhci_get_timeout_no_hub_lpm(udev, state);
4607 /* Not sure how this could happen... */
4608 if (!intf->cur_altsetting)
4611 if (xhci_update_timeout_for_interface(xhci, udev,
4612 intf->cur_altsetting,
4619 static int calculate_max_exit_latency(struct usb_device *udev,
4620 enum usb3_link_state state_changed,
4621 u16 hub_encoded_timeout)
4623 unsigned long long u1_mel_us = 0;
4624 unsigned long long u2_mel_us = 0;
4625 unsigned long long mel_us = 0;
4631 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4632 hub_encoded_timeout == USB3_LPM_DISABLED);
4633 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4634 hub_encoded_timeout == USB3_LPM_DISABLED);
4636 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4637 hub_encoded_timeout != USB3_LPM_DISABLED);
4638 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4639 hub_encoded_timeout != USB3_LPM_DISABLED);
4641 /* If U1 was already enabled and we're not disabling it,
4642 * or we're going to enable U1, account for the U1 max exit latency.
4644 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4646 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4647 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4649 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4651 if (u1_mel_us > u2_mel_us)
4655 /* xHCI host controller max exit latency field is only 16 bits wide. */
4656 if (mel_us > MAX_EXIT) {
4657 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4658 "is too big.\n", mel_us);
4664 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4665 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4666 struct usb_device *udev, enum usb3_link_state state)
4668 struct xhci_hcd *xhci;
4669 u16 hub_encoded_timeout;
4673 xhci = hcd_to_xhci(hcd);
4674 /* The LPM timeout values are pretty host-controller specific, so don't
4675 * enable hub-initiated timeouts unless the vendor has provided
4676 * information about their timeout algorithm.
4678 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4679 !xhci->devs[udev->slot_id])
4680 return USB3_LPM_DISABLED;
4682 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4683 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4685 /* Max Exit Latency is too big, disable LPM. */
4686 hub_encoded_timeout = USB3_LPM_DISABLED;
4690 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4693 return hub_encoded_timeout;
4696 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4697 struct usb_device *udev, enum usb3_link_state state)
4699 struct xhci_hcd *xhci;
4702 xhci = hcd_to_xhci(hcd);
4703 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4704 !xhci->devs[udev->slot_id])
4707 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4708 return xhci_change_max_exit_latency(xhci, udev, mel);
4710 #else /* CONFIG_PM */
4712 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4713 struct usb_device *udev, int enable)
4718 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4723 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4724 struct usb_device *udev, enum usb3_link_state state)
4726 return USB3_LPM_DISABLED;
4729 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4730 struct usb_device *udev, enum usb3_link_state state)
4734 #endif /* CONFIG_PM */
4736 /*-------------------------------------------------------------------------*/
4738 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4739 * internal data structures for the device.
4741 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4742 struct usb_tt *tt, gfp_t mem_flags)
4744 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4745 struct xhci_virt_device *vdev;
4746 struct xhci_command *config_cmd;
4747 struct xhci_input_control_ctx *ctrl_ctx;
4748 struct xhci_slot_ctx *slot_ctx;
4749 unsigned long flags;
4750 unsigned think_time;
4753 /* Ignore root hubs */
4757 vdev = xhci->devs[hdev->slot_id];
4759 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4762 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4764 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4767 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4769 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4771 xhci_free_command(xhci, config_cmd);
4775 spin_lock_irqsave(&xhci->lock, flags);
4776 if (hdev->speed == USB_SPEED_HIGH &&
4777 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4778 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4779 xhci_free_command(xhci, config_cmd);
4780 spin_unlock_irqrestore(&xhci->lock, flags);
4784 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4785 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4786 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4787 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4789 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4790 * but it may be already set to 1 when setup an xHCI virtual
4791 * device, so clear it anyway.
4794 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4795 else if (hdev->speed == USB_SPEED_FULL)
4796 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4798 if (xhci->hci_version > 0x95) {
4799 xhci_dbg(xhci, "xHCI version %x needs hub "
4800 "TT think time and number of ports\n",
4801 (unsigned int) xhci->hci_version);
4802 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4803 /* Set TT think time - convert from ns to FS bit times.
4804 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4805 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4807 * xHCI 1.0: this field shall be 0 if the device is not a
4810 think_time = tt->think_time;
4811 if (think_time != 0)
4812 think_time = (think_time / 666) - 1;
4813 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4814 slot_ctx->tt_info |=
4815 cpu_to_le32(TT_THINK_TIME(think_time));
4817 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4818 "TT think time or number of ports\n",
4819 (unsigned int) xhci->hci_version);
4821 slot_ctx->dev_state = 0;
4822 spin_unlock_irqrestore(&xhci->lock, flags);
4824 xhci_dbg(xhci, "Set up %s for hub device.\n",
4825 (xhci->hci_version > 0x95) ?
4826 "configure endpoint" : "evaluate context");
4827 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4828 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4830 /* Issue and wait for the configure endpoint or
4831 * evaluate context command.
4833 if (xhci->hci_version > 0x95)
4834 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4837 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4840 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4841 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4843 xhci_free_command(xhci, config_cmd);
4847 int xhci_get_frame(struct usb_hcd *hcd)
4849 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4850 /* EHCI mods by the periodic size. Why? */
4851 return readl(&xhci->run_regs->microframe_index) >> 3;
4854 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4856 struct xhci_hcd *xhci;
4857 struct device *dev = hcd->self.controller;
4860 /* Accept arbitrarily long scatter-gather lists */
4861 hcd->self.sg_tablesize = ~0;
4863 /* support to build packet from discontinuous buffers */
4864 hcd->self.no_sg_constraint = 1;
4866 /* XHCI controllers don't stop the ep queue on short packets :| */
4867 hcd->self.no_stop_on_short = 1;
4869 xhci = hcd_to_xhci(hcd);
4871 if (usb_hcd_is_primary_hcd(hcd)) {
4872 xhci->main_hcd = hcd;
4873 /* Mark the first roothub as being USB 2.0.
4874 * The xHCI driver will register the USB 3.0 roothub.
4876 hcd->speed = HCD_USB2;
4877 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4879 * USB 2.0 roothub under xHCI has an integrated TT,
4880 * (rate matching hub) as opposed to having an OHCI/UHCI
4881 * companion controller.
4885 if (xhci->sbrn == 0x31) {
4886 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4887 hcd->speed = HCD_USB31;
4889 /* xHCI private pointer was set in xhci_pci_probe for the second
4890 * registered roothub.
4895 mutex_init(&xhci->mutex);
4896 xhci->cap_regs = hcd->regs;
4897 xhci->op_regs = hcd->regs +
4898 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4899 xhci->run_regs = hcd->regs +
4900 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4901 /* Cache read-only capability registers */
4902 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4903 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4904 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4905 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4906 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4907 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4908 if (xhci->hci_version > 0x100)
4909 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4910 xhci_print_registers(xhci);
4912 xhci->quirks |= quirks;
4914 get_quirks(dev, xhci);
4916 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4917 * success event after a short transfer. This quirk will ignore such
4920 if (xhci->hci_version > 0x96)
4921 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4923 /* Make sure the HC is halted. */
4924 retval = xhci_halt(xhci);
4928 xhci_dbg(xhci, "Resetting HCD\n");
4929 /* Reset the internal HC memory state and registers. */
4930 retval = xhci_reset(xhci);
4933 xhci_dbg(xhci, "Reset complete\n");
4935 /* Set dma_mask and coherent_dma_mask to 64-bits,
4936 * if xHC supports 64-bit addressing */
4937 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4938 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4939 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4940 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4943 * This is to avoid error in cases where a 32-bit USB
4944 * controller is used on a 64-bit capable system.
4946 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4949 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4950 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4953 xhci_dbg(xhci, "Calling HCD init\n");
4954 /* Initialize HCD and host controller data structures. */
4955 retval = xhci_init(hcd);
4958 xhci_dbg(xhci, "Called HCD init\n");
4960 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4961 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4965 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4967 static const struct hc_driver xhci_hc_driver = {
4968 .description = "xhci-hcd",
4969 .product_desc = "xHCI Host Controller",
4970 .hcd_priv_size = sizeof(struct xhci_hcd *),
4973 * generic hardware linkage
4976 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4979 * basic lifecycle operations
4981 .reset = NULL, /* set in xhci_init_driver() */
4984 .shutdown = xhci_shutdown,
4987 * managing i/o requests and associated device resources
4989 .urb_enqueue = xhci_urb_enqueue,
4990 .urb_dequeue = xhci_urb_dequeue,
4991 .alloc_dev = xhci_alloc_dev,
4992 .free_dev = xhci_free_dev,
4993 .alloc_streams = xhci_alloc_streams,
4994 .free_streams = xhci_free_streams,
4995 .add_endpoint = xhci_add_endpoint,
4996 .drop_endpoint = xhci_drop_endpoint,
4997 .endpoint_reset = xhci_endpoint_reset,
4998 .check_bandwidth = xhci_check_bandwidth,
4999 .reset_bandwidth = xhci_reset_bandwidth,
5000 .address_device = xhci_address_device,
5001 .enable_device = xhci_enable_device,
5002 .update_hub_device = xhci_update_hub_device,
5003 .reset_device = xhci_discover_or_reset_device,
5006 * scheduling support
5008 .get_frame_number = xhci_get_frame,
5013 .hub_control = xhci_hub_control,
5014 .hub_status_data = xhci_hub_status_data,
5015 .bus_suspend = xhci_bus_suspend,
5016 .bus_resume = xhci_bus_resume,
5019 * call back when device connected and addressed
5021 .update_device = xhci_update_device,
5022 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5023 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5024 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5025 .find_raw_port_number = xhci_find_raw_port_number,
5028 void xhci_init_driver(struct hc_driver *drv,
5029 const struct xhci_driver_overrides *over)
5033 /* Copy the generic table to drv then apply the overrides */
5034 *drv = xhci_hc_driver;
5037 drv->hcd_priv_size += over->extra_priv_size;
5039 drv->reset = over->reset;
5041 drv->start = over->start;
5044 EXPORT_SYMBOL_GPL(xhci_init_driver);
5046 MODULE_DESCRIPTION(DRIVER_DESC);
5047 MODULE_AUTHOR(DRIVER_AUTHOR);
5048 MODULE_LICENSE("GPL");
5050 static int __init xhci_hcd_init(void)
5053 * Check the compiler generated sizes of structures that must be laid
5054 * out in specific ways for hardware access.
5056 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5057 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5058 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5059 /* xhci_device_control has eight fields, and also
5060 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5062 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5063 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5064 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5065 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5066 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5067 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5068 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5077 * If an init function is provided, an exit function must also be provided
5078 * to allow module unload.
5080 static void __exit xhci_hcd_fini(void) { }
5082 module_init(xhci_hcd_init);
5083 module_exit(xhci_hcd_fini);