drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 126 {
 127         /* Enqueue pointer can be left pointing to the link TRB,
 128          * we must handle that
 129          */
 130         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 131                 return ring->enq_seg->next->trbs;
 132         return ring->enqueue;
 133 }
 134
 135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 136  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 137  * effect the ring dequeue or enqueue pointers.
 138  */
 139 static void next_trb(struct xhci_hcd *xhci,
 140                 struct xhci_ring *ring,
 141                 struct xhci_segment **seg,
 142                 union xhci_trb **trb)
 143 {
 144         if (last_trb(xhci, ring, *seg, *trb)) {
 145                 *seg = (*seg)->next;
 146                 *trb = ((*seg)->trbs);
 147         } else {
 148                 (*trb)++;
 149         }
 150 }
 151
 152 /*
 153  * See Cycle bit rules. SW is the consumer for the event ring only.
 154  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 155  */
 156 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 157 {
 158         unsigned long long addr;
 159
 160         ring->deq_updates++;
 161
 162         /*
 163          * If this is not event ring, and the dequeue pointer
 164          * is not on a link TRB, there is one more usable TRB
 165          */
 166         if (ring->type != TYPE_EVENT &&
 167                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 168                 ring->num_trbs_free++;
 169
 170         do {
 171                 /*
 172                  * Update the dequeue pointer further if that was a link TRB or
 173                  * we're at the end of an event ring segment (which doesn't have
 174                  * link TRBS)
 175                  */
 176                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 177                         if (ring->type == TYPE_EVENT &&
 178                                         last_trb_on_last_seg(xhci, ring,
 179                                                 ring->deq_seg, ring->dequeue)) {
 180                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 181                         }
 182                         ring->deq_seg = ring->deq_seg->next;
 183                         ring->dequeue = ring->deq_seg->trbs;
 184                 } else {
 185                         ring->dequeue++;
 186                 }
 187         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 188
 189         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 190 }
 191
 192 /*
 193  * See Cycle bit rules. SW is the consumer for the event ring only.
 194  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 195  *
 196  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 197  * chain bit is set), then set the chain bit in all the following link TRBs.
 198  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 199  * have their chain bit cleared (so that each Link TRB is a separate TD).
 200  *
 201  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 202  * set, but other sections talk about dealing with the chain bit set.  This was
 203  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 204  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 205  *
 206  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 207  *                      prepare_transfer()?
 208  */
 209 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 210                         bool more_trbs_coming)
 211 {
 212         u32 chain;
 213         union xhci_trb *next;
 214         unsigned long long addr;
 215
 216         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 217         /* If this is not event ring, there is one less usable TRB */
 218         if (ring->type != TYPE_EVENT &&
 219                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 220                 ring->num_trbs_free--;
 221         next = ++(ring->enqueue);
 222
 223         ring->enq_updates++;
 224         /* Update the dequeue pointer further if that was a link TRB or we're at
 225          * the end of an event ring segment (which doesn't have link TRBS)
 226          */
 227         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 228                 if (ring->type != TYPE_EVENT) {
 229                         /*
 230                          * If the caller doesn't plan on enqueueing more
 231                          * TDs before ringing the doorbell, then we
 232                          * don't want to give the link TRB to the
 233                          * hardware just yet.  We'll give the link TRB
 234                          * back in prepare_ring() just before we enqueue
 235                          * the TD at the top of the ring.
 236                          */
 237                         if (!chain && !more_trbs_coming)
 238                                 break;
 239
 240                         /* If we're not dealing with 0.95 hardware or
 241                          * isoc rings on AMD 0.96 host,
 242                          * carry over the chain bit of the previous TRB
 243                          * (which may mean the chain bit is cleared).
 244                          */
 245                         if (!(ring->type == TYPE_ISOC &&
 246                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 247                                                 && !xhci_link_trb_quirk(xhci)) {
 248                                 next->link.control &=
 249                                         cpu_to_le32(~TRB_CHAIN);
 250                                 next->link.control |=
 251                                         cpu_to_le32(chain);
 252                         }
 253                         /* Give this link TRB to the hardware */
 254                         wmb();
 255                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 256
 257                         /* Toggle the cycle bit after the last ring segment. */
 258                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 259                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 260                         }
 261                 }
 262                 ring->enq_seg = ring->enq_seg->next;
 263                 ring->enqueue = ring->enq_seg->trbs;
 264                 next = ring->enqueue;
 265         }
 266         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 267 }
 268
 269 /*
 270  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 271  * enqueue pointer will not advance into dequeue segment. See rules above.
 272  */
 273 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 274                 unsigned int num_trbs)
 275 {
 276         int num_trbs_in_deq_seg;
 277
 278         if (ring->num_trbs_free < num_trbs)
 279                 return 0;
 280
 281         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 282                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 283                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 284                         return 0;
 285         }
 286
 287         return 1;
 288 }
 289
 290 /* Ring the host controller doorbell after placing a command on the ring */
 291 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 292 {
 293         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 294                 return;
 295
 296         xhci_dbg(xhci, "// Ding dong!\n");
 297         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 298         /* Flush PCI posted writes */
 299         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 300 }
 301
 302 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 303 {
 304         u64 temp_64;
 305         int ret;
 306
 307         xhci_dbg(xhci, "Abort command ring\n");
 308
 309         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 310                 xhci_dbg(xhci, "The command ring isn't running, "
 311                                 "Have the command ring been stopped?\n");
 312                 return 0;
 313         }
 314
 315         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 316         if (!(temp_64 & CMD_RING_RUNNING)) {
 317                 xhci_dbg(xhci, "Command ring had been stopped\n");
 318                 return 0;
 319         }
 320         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 321         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 322                         &xhci->op_regs->cmd_ring);
 323
 324         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 325          * time the completion od all xHCI commands, including
 326          * the Command Abort operation. If software doesn't see
 327          * CRR negated in a timely manner (e.g. longer than 5
 328          * seconds), then it should assume that the there are
 329          * larger problems with the xHC and assert HCRST.
 330          */
 331         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 332                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 333         if (ret < 0) {
 334                 xhci_err(xhci, "Stopped the command ring failed, "
 335                                 "maybe the host is dead\n");
 336                 xhci->xhc_state |= XHCI_STATE_DYING;
 337                 xhci_quiesce(xhci);
 338                 xhci_halt(xhci);
 339                 return -ESHUTDOWN;
 340         }
 341
 342         return 0;
 343 }
 344
 345 static int xhci_queue_cd(struct xhci_hcd *xhci,
 346                 struct xhci_command *command,
 347                 union xhci_trb *cmd_trb)
 348 {
 349         struct xhci_cd *cd;
 350         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 351         if (!cd)
 352                 return -ENOMEM;
 353         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 354
 355         cd->command = command;
 356         cd->cmd_trb = cmd_trb;
 357         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * Cancel the command which has issue.
 364  *
 365  * Some commands may hang due to waiting for acknowledgement from
 366  * usb device. It is outside of the xHC's ability to control and
 367  * will cause the command ring is blocked. When it occurs software
 368  * should intervene to recover the command ring.
 369  * See Section 4.6.1.1 and 4.6.1.2
 370  */
 371 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 372                 union xhci_trb *cmd_trb)
 373 {
 374         int retval = 0;
 375         unsigned long flags;
 376
 377         spin_lock_irqsave(&xhci->lock, flags);
 378
 379         if (xhci->xhc_state & XHCI_STATE_DYING) {
 380                 xhci_warn(xhci, "Abort the command ring,"
 381                                 " but the xHCI is dead.\n");
 382                 retval = -ESHUTDOWN;
 383                 goto fail;
 384         }
 385
 386         /* queue the cmd desriptor to cancel_cmd_list */
 387         retval = xhci_queue_cd(xhci, command, cmd_trb);
 388         if (retval) {
 389                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 390                 goto fail;
 391         }
 392
 393         /* abort command ring */
 394         retval = xhci_abort_cmd_ring(xhci);
 395         if (retval) {
 396                 xhci_err(xhci, "Abort command ring failed\n");
 397                 if (unlikely(retval == -ESHUTDOWN)) {
 398                         spin_unlock_irqrestore(&xhci->lock, flags);
 399                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 400                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 401                         return retval;
 402                 }
 403         }
 404
 405 fail:
 406         spin_unlock_irqrestore(&xhci->lock, flags);
 407         return retval;
 408 }
 409
 410 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 411                 unsigned int slot_id,
 412                 unsigned int ep_index,
 413                 unsigned int stream_id)
 414 {
 415         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 416         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 417         unsigned int ep_state = ep->ep_state;
 418
 419         /* Don't ring the doorbell for this endpoint if there are pending
 420          * cancellations because we don't want to interrupt processing.
 421          * We don't want to restart any stream rings if there's a set dequeue
 422          * pointer command pending because the device can choose to start any
 423          * stream once the endpoint is on the HW schedule.
 424          * FIXME - check all the stream rings for pending cancellations.
 425          */
 426         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 427             (ep_state & EP_HALTED))
 428                 return;
 429         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 430         /* The CPU has better things to do at this point than wait for a
 431          * write-posting flush.  It'll get there soon enough.
 432          */
 433 }
 434
 435 /* Ring the doorbell for any rings with pending URBs */
 436 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 437                 unsigned int slot_id,
 438                 unsigned int ep_index)
 439 {
 440         unsigned int stream_id;
 441         struct xhci_virt_ep *ep;
 442
 443         ep = &xhci->devs[slot_id]->eps[ep_index];
 444
 445         /* A ring has pending URBs if its TD list is not empty */
 446         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 447                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 448                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 449                 return;
 450         }
 451
 452         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 453                         stream_id++) {
 454                 struct xhci_stream_info *stream_info = ep->stream_info;
 455                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 456                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 457                                                 stream_id);
 458         }
 459 }
 460
 461 /*
 462  * Find the segment that trb is in.  Start searching in start_seg.
 463  * If we must move past a segment that has a link TRB with a toggle cycle state
 464  * bit set, then we will toggle the value pointed at by cycle_state.
 465  */
 466 static struct xhci_segment *find_trb_seg(
 467                 struct xhci_segment *start_seg,
 468                 union xhci_trb  *trb, int *cycle_state)
 469 {
 470         struct xhci_segment *cur_seg = start_seg;
 471         struct xhci_generic_trb *generic_trb;
 472
 473         while (cur_seg->trbs > trb ||
 474                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 475                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 476                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 477                         *cycle_state ^= 0x1;
 478                 cur_seg = cur_seg->next;
 479                 if (cur_seg == start_seg)
 480                         /* Looped over the entire list.  Oops! */
 481                         return NULL;
 482         }
 483         return cur_seg;
 484 }
 485
 486
 487 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 488                 unsigned int slot_id, unsigned int ep_index,
 489                 unsigned int stream_id)
 490 {
 491         struct xhci_virt_ep *ep;
 492
 493         ep = &xhci->devs[slot_id]->eps[ep_index];
 494         /* Common case: no streams */
 495         if (!(ep->ep_state & EP_HAS_STREAMS))
 496                 return ep->ring;
 497
 498         if (stream_id == 0) {
 499                 xhci_warn(xhci,
 500                                 "WARN: Slot ID %u, ep index %u has streams, "
 501                                 "but URB has no stream ID.\n",
 502                                 slot_id, ep_index);
 503                 return NULL;
 504         }
 505
 506         if (stream_id < ep->stream_info->num_streams)
 507                 return ep->stream_info->stream_rings[stream_id];
 508
 509         xhci_warn(xhci,
 510                         "WARN: Slot ID %u, ep index %u has "
 511                         "stream IDs 1 to %u allocated, "
 512                         "but stream ID %u is requested.\n",
 513                         slot_id, ep_index,
 514                         ep->stream_info->num_streams - 1,
 515                         stream_id);
 516         return NULL;
 517 }
 518
 519 /* Get the right ring for the given URB.
 520  * If the endpoint supports streams, boundary check the URB's stream ID.
 521  * If the endpoint doesn't support streams, return the singular endpoint ring.
 522  */
 523 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 524                 struct urb *urb)
 525 {
 526         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 527                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 528 }
 529
 530 /*
 531  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 532  * Record the new state of the xHC's endpoint ring dequeue segment,
 533  * dequeue pointer, and new consumer cycle state in state.
 534  * Update our internal representation of the ring's dequeue pointer.
 535  *
 536  * We do this in three jumps:
 537  *  - First we update our new ring state to be the same as when the xHC stopped.
 538  *  - Then we traverse the ring to find the segment that contains
 539  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 540  *    any link TRBs with the toggle cycle bit set.
 541  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 542  *    if we've moved it past a link TRB with the toggle cycle bit set.
 543  *
 544  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 545  * with correct __le32 accesses they should work fine.  Only users of this are
 546  * in here.
 547  */
 548 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 549                 unsigned int slot_id, unsigned int ep_index,
 550                 unsigned int stream_id, struct xhci_td *cur_td,
 551                 struct xhci_dequeue_state *state)
 552 {
 553         struct xhci_virt_device *dev = xhci->devs[slot_id];
 554         struct xhci_ring *ep_ring;
 555         struct xhci_generic_trb *trb;
 556         struct xhci_ep_ctx *ep_ctx;
 557         dma_addr_t addr;
 558
 559         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 560                         ep_index, stream_id);
 561         if (!ep_ring) {
 562                 xhci_warn(xhci, "WARN can't find new dequeue state "
 563                                 "for invalid stream ID %u.\n",
 564                                 stream_id);
 565                 return;
 566         }
 567         state->new_cycle_state = 0;
 568         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 569         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 570                         dev->eps[ep_index].stopped_trb,
 571                         &state->new_cycle_state);
 572         if (!state->new_deq_seg) {
 573                 WARN_ON(1);
 574                 return;
 575         }
 576
 577         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 578         xhci_dbg(xhci, "Finding endpoint context\n");
 579         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 580         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 581
 582         state->new_deq_ptr = cur_td->last_trb;
 583         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 584         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 585                         state->new_deq_ptr,
 586                         &state->new_cycle_state);
 587         if (!state->new_deq_seg) {
 588                 WARN_ON(1);
 589                 return;
 590         }
 591
 592         trb = &state->new_deq_ptr->generic;
 593         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 594             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 595                 state->new_cycle_state ^= 0x1;
 596         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 597
 598         /*
 599          * If there is only one segment in a ring, find_trb_seg()'s while loop
 600          * will not run, and it will return before it has a chance to see if it
 601          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 602          * ended just before the link TRB on a one-segment ring, or if the TD
 603          * wrapped around the top of the ring, because it doesn't have the TD in
 604          * question.  Look for the one-segment case where stalled TRB's address
 605          * is greater than the new dequeue pointer address.
 606          */
 607         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 608                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 609                 state->new_cycle_state ^= 0x1;
 610         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 611
 612         /* Don't update the ring cycle state for the producer (us). */
 613         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 614                         state->new_deq_seg);
 615         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 616         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 617                         (unsigned long long) addr);
 618 }
 619
 620 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 621  * (The last TRB actually points to the ring enqueue pointer, which is not part
 622  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 623  */
 624 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 625                 struct xhci_td *cur_td, bool flip_cycle)
 626 {
 627         struct xhci_segment *cur_seg;
 628         union xhci_trb *cur_trb;
 629
 630         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 631                         true;
 632                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 633                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 634                         /* Unchain any chained Link TRBs, but
 635                          * leave the pointers intact.
 636                          */
 637                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 638                         /* Flip the cycle bit (link TRBs can't be the first
 639                          * or last TRB).
 640                          */
 641                         if (flip_cycle)
 642                                 cur_trb->generic.field[3] ^=
 643                                         cpu_to_le32(TRB_CYCLE);
 644                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 645                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 646                                         "in seg %p (0x%llx dma)\n",
 647                                         cur_trb,
 648                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 649                                         cur_seg,
 650                                         (unsigned long long)cur_seg->dma);
 651                 } else {
 652                         cur_trb->generic.field[0] = 0;
 653                         cur_trb->generic.field[1] = 0;
 654                         cur_trb->generic.field[2] = 0;
 655                         /* Preserve only the cycle bit of this TRB */
 656                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 657                         /* Flip the cycle bit except on the first or last TRB */
 658                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 659                                         cur_trb != cur_td->last_trb)
 660                                 cur_trb->generic.field[3] ^=
 661                                         cpu_to_le32(TRB_CYCLE);
 662                         cur_trb->generic.field[3] |= cpu_to_le32(
 663                                 TRB_TYPE(TRB_TR_NOOP));
 664                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 665                                         (unsigned long long)
 666                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 667                 }
 668                 if (cur_trb == cur_td->last_trb)
 669                         break;
 670         }
 671 }
 672
 673 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 674                 unsigned int ep_index, unsigned int stream_id,
 675                 struct xhci_segment *deq_seg,
 676                 union xhci_trb *deq_ptr, u32 cycle_state);
 677
 678 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 679                 unsigned int slot_id, unsigned int ep_index,
 680                 unsigned int stream_id,
 681                 struct xhci_dequeue_state *deq_state)
 682 {
 683         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 684
 685         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 686                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 687                         deq_state->new_deq_seg,
 688                         (unsigned long long)deq_state->new_deq_seg->dma,
 689                         deq_state->new_deq_ptr,
 690                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 691                         deq_state->new_cycle_state);
 692         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 693                         deq_state->new_deq_seg,
 694                         deq_state->new_deq_ptr,
 695                         (u32) deq_state->new_cycle_state);
 696         /* Stop the TD queueing code from ringing the doorbell until
 697          * this command completes.  The HC won't set the dequeue pointer
 698          * if the ring is running, and ringing the doorbell starts the
 699          * ring running.
 700          */
 701         ep->ep_state |= SET_DEQ_PENDING;
 702 }
 703
 704 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 705                 struct xhci_virt_ep *ep)
 706 {
 707         ep->ep_state &= ~EP_HALT_PENDING;
 708         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 709          * timer is running on another CPU, we don't decrement stop_cmds_pending
 710          * (since we didn't successfully stop the watchdog timer).
 711          */
 712         if (del_timer(&ep->stop_cmd_timer))
 713                 ep->stop_cmds_pending--;
 714 }
 715
 716 /* Must be called with xhci->lock held in interrupt context */
 717 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 718                 struct xhci_td *cur_td, int status, char *adjective)
 719 {
 720         struct usb_hcd *hcd;
 721         struct urb      *urb;
 722         struct urb_priv *urb_priv;
 723
 724         urb = cur_td->urb;
 725         urb_priv = urb->hcpriv;
 726         urb_priv->td_cnt++;
 727         hcd = bus_to_hcd(urb->dev->bus);
 728
 729         /* Only giveback urb when this is the last td in urb */
 730         if (urb_priv->td_cnt == urb_priv->length) {
 731                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 732                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 733                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 734                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 735                                         usb_amd_quirk_pll_enable();
 736                         }
 737                 }
 738                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 739
 740                 spin_unlock(&xhci->lock);
 741                 usb_hcd_giveback_urb(hcd, urb, status);
 742                 xhci_urb_free_priv(xhci, urb_priv);
 743                 spin_lock(&xhci->lock);
 744         }
 745 }
 746
 747 /*
 748  * When we get a command completion for a Stop Endpoint Command, we need to
 749  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 750  *
 751  *  1. If the HW was in the middle of processing the TD that needs to be
 752  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 753  *     in the TD with a Set Dequeue Pointer Command.
 754  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 755  *     bit cleared) so that the HW will skip over them.
 756  */
 757 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 758                 union xhci_trb *trb, struct xhci_event_cmd *event)
 759 {
 760         unsigned int slot_id;
 761         unsigned int ep_index;
 762         struct xhci_virt_device *virt_dev;
 763         struct xhci_ring *ep_ring;
 764         struct xhci_virt_ep *ep;
 765         struct list_head *entry;
 766         struct xhci_td *cur_td = NULL;
 767         struct xhci_td *last_unlinked_td;
 768
 769         struct xhci_dequeue_state deq_state;
 770
 771         if (unlikely(TRB_TO_SUSPEND_PORT(
 772                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 773                 slot_id = TRB_TO_SLOT_ID(
 774                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 775                 virt_dev = xhci->devs[slot_id];
 776                 if (virt_dev)
 777                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 778                                 event);
 779                 else
 780                         xhci_warn(xhci, "Stop endpoint command "
 781                                 "completion for disabled slot %u\n",
 782                                 slot_id);
 783                 return;
 784         }
 785
 786         memset(&deq_state, 0, sizeof(deq_state));
 787         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 788         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 789         ep = &xhci->devs[slot_id]->eps[ep_index];
 790
 791         if (list_empty(&ep->cancelled_td_list)) {
 792                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 793                 ep->stopped_td = NULL;
 794                 ep->stopped_trb = NULL;
 795                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 796                 return;
 797         }
 798
 799         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 800          * We have the xHCI lock, so nothing can modify this list until we drop
 801          * it.  We're also in the event handler, so we can't get re-interrupted
 802          * if another Stop Endpoint command completes
 803          */
 804         list_for_each(entry, &ep->cancelled_td_list) {
 805                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 806                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 807                                 (unsigned long long)xhci_trb_virt_to_dma(
 808                                         cur_td->start_seg, cur_td->first_trb));
 809                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 810                 if (!ep_ring) {
 811                         /* This shouldn't happen unless a driver is mucking
 812                          * with the stream ID after submission.  This will
 813                          * leave the TD on the hardware ring, and the hardware
 814                          * will try to execute it, and may access a buffer
 815                          * that has already been freed.  In the best case, the
 816                          * hardware will execute it, and the event handler will
 817                          * ignore the completion event for that TD, since it was
 818                          * removed from the td_list for that endpoint.  In
 819                          * short, don't muck with the stream ID after
 820                          * submission.
 821                          */
 822                         xhci_warn(xhci, "WARN Cancelled URB %p "
 823                                         "has invalid stream ID %u.\n",
 824                                         cur_td->urb,
 825                                         cur_td->urb->stream_id);
 826                         goto remove_finished_td;
 827                 }
 828                 /*
 829                  * If we stopped on the TD we need to cancel, then we have to
 830                  * move the xHC endpoint ring dequeue pointer past this TD.
 831                  */
 832                 if (cur_td == ep->stopped_td)
 833                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 834                                         cur_td->urb->stream_id,
 835                                         cur_td, &deq_state);
 836                 else
 837                         td_to_noop(xhci, ep_ring, cur_td, false);
 838 remove_finished_td:
 839                 /*
 840                  * The event handler won't see a completion for this TD anymore,
 841                  * so remove it from the endpoint ring's TD list.  Keep it in
 842                  * the cancelled TD list for URB completion later.
 843                  */
 844                 list_del_init(&cur_td->td_list);
 845         }
 846         last_unlinked_td = cur_td;
 847         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 848
 849         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 850         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 851                 xhci_queue_new_dequeue_state(xhci,
 852                                 slot_id, ep_index,
 853                                 ep->stopped_td->urb->stream_id,
 854                                 &deq_state);
 855                 xhci_ring_cmd_db(xhci);
 856         } else {
 857                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 858                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 859         }
 860
 861         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 862         if (!(ep->ep_state & EP_HALTED)) {
 863                 ep->stopped_td = NULL;
 864                 ep->stopped_trb = NULL;
 865         }
 866
 867         /*
 868          * Drop the lock and complete the URBs in the cancelled TD list.
 869          * New TDs to be cancelled might be added to the end of the list before
 870          * we can complete all the URBs for the TDs we already unlinked.
 871          * So stop when we've completed the URB for the last TD we unlinked.
 872          */
 873         do {
 874                 cur_td = list_entry(ep->cancelled_td_list.next,
 875                                 struct xhci_td, cancelled_td_list);
 876                 list_del_init(&cur_td->cancelled_td_list);
 877
 878                 /* Clean up the cancelled URB */
 879                 /* Doesn't matter what we pass for status, since the core will
 880                  * just overwrite it (because the URB has been unlinked).
 881                  */
 882                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 883
 884                 /* Stop processing the cancelled list if the watchdog timer is
 885                  * running.
 886                  */
 887                 if (xhci->xhc_state & XHCI_STATE_DYING)
 888                         return;
 889         } while (cur_td != last_unlinked_td);
 890
 891         /* Return to the event handler with xhci->lock re-acquired */
 892 }
 893
 894 /* Watchdog timer function for when a stop endpoint command fails to complete.
 895  * In this case, we assume the host controller is broken or dying or dead.  The
 896  * host may still be completing some other events, so we have to be careful to
 897  * let the event ring handler and the URB dequeueing/enqueueing functions know
 898  * through xhci->state.
 899  *
 900  * The timer may also fire if the host takes a very long time to respond to the
 901  * command, and the stop endpoint command completion handler cannot delete the
 902  * timer before the timer function is called.  Another endpoint cancellation may
 903  * sneak in before the timer function can grab the lock, and that may queue
 904  * another stop endpoint command and add the timer back.  So we cannot use a
 905  * simple flag to say whether there is a pending stop endpoint command for a
 906  * particular endpoint.
 907  *
 908  * Instead we use a combination of that flag and a counter for the number of
 909  * pending stop endpoint commands.  If the timer is the tail end of the last
 910  * stop endpoint command, and the endpoint's command is still pending, we assume
 911  * the host is dying.
 912  */
 913 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 914 {
 915         struct xhci_hcd *xhci;
 916         struct xhci_virt_ep *ep;
 917         struct xhci_virt_ep *temp_ep;
 918         struct xhci_ring *ring;
 919         struct xhci_td *cur_td;
 920         int ret, i, j;
 921         unsigned long flags;
 922
 923         ep = (struct xhci_virt_ep *) arg;
 924         xhci = ep->xhci;
 925
 926         spin_lock_irqsave(&xhci->lock, flags);
 927
 928         ep->stop_cmds_pending--;
 929         if (xhci->xhc_state & XHCI_STATE_DYING) {
 930                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 931                                 "xHCI as DYING, exiting.\n");
 932                 spin_unlock_irqrestore(&xhci->lock, flags);
 933                 return;
 934         }
 935         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 936                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 937                                 "exiting.\n");
 938                 spin_unlock_irqrestore(&xhci->lock, flags);
 939                 return;
 940         }
 941
 942         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 943         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 944         /* Oops, HC is dead or dying or at least not responding to the stop
 945          * endpoint command.
 946          */
 947         xhci->xhc_state |= XHCI_STATE_DYING;
 948         /* Disable interrupts from the host controller and start halting it */
 949         xhci_quiesce(xhci);
 950         spin_unlock_irqrestore(&xhci->lock, flags);
 951
 952         ret = xhci_halt(xhci);
 953
 954         spin_lock_irqsave(&xhci->lock, flags);
 955         if (ret < 0) {
 956                 /* This is bad; the host is not responding to commands and it's
 957                  * not allowing itself to be halted.  At least interrupts are
 958                  * disabled. If we call usb_hc_died(), it will attempt to
 959                  * disconnect all device drivers under this host.  Those
 960                  * disconnect() methods will wait for all URBs to be unlinked,
 961                  * so we must complete them.
 962                  */
 963                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 964                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 965                 /* We could turn all TDs on the rings to no-ops.  This won't
 966                  * help if the host has cached part of the ring, and is slow if
 967                  * we want to preserve the cycle bit.  Skip it and hope the host
 968                  * doesn't touch the memory.
 969                  */
 970         }
 971         for (i = 0; i < MAX_HC_SLOTS; i++) {
 972                 if (!xhci->devs[i])
 973                         continue;
 974                 for (j = 0; j < 31; j++) {
 975                         temp_ep = &xhci->devs[i]->eps[j];
 976                         ring = temp_ep->ring;
 977                         if (!ring)
 978                                 continue;
 979                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 980                                         "ep index %u\n", i, j);
 981                         while (!list_empty(&ring->td_list)) {
 982                                 cur_td = list_first_entry(&ring->td_list,
 983                                                 struct xhci_td,
 984                                                 td_list);
 985                                 list_del_init(&cur_td->td_list);
 986                                 if (!list_empty(&cur_td->cancelled_td_list))
 987                                         list_del_init(&cur_td->cancelled_td_list);
 988                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 989                                                 -ESHUTDOWN, "killed");
 990                         }
 991                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 992                                 cur_td = list_first_entry(
 993                                                 &temp_ep->cancelled_td_list,
 994                                                 struct xhci_td,
 995                                                 cancelled_td_list);
 996                                 list_del_init(&cur_td->cancelled_td_list);
 997                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 998                                                 -ESHUTDOWN, "killed");
 999                         }
1000                 }
1001         }
1002         spin_unlock_irqrestore(&xhci->lock, flags);
1003         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1004         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1005         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1006 }
1007
1008
1009 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1010                 struct xhci_virt_device *dev,
1011                 struct xhci_ring *ep_ring,
1012                 unsigned int ep_index)
1013 {
1014         union xhci_trb *dequeue_temp;
1015         int num_trbs_free_temp;
1016         bool revert = false;
1017
1018         num_trbs_free_temp = ep_ring->num_trbs_free;
1019         dequeue_temp = ep_ring->dequeue;
1020
1021         /* If we get two back-to-back stalls, and the first stalled transfer
1022          * ends just before a link TRB, the dequeue pointer will be left on
1023          * the link TRB by the code in the while loop.  So we have to update
1024          * the dequeue pointer one segment further, or we'll jump off
1025          * the segment into la-la-land.
1026          */
1027         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1028                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1029                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1030         }
1031
1032         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1033                 /* We have more usable TRBs */
1034                 ep_ring->num_trbs_free++;
1035                 ep_ring->dequeue++;
1036                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1037                                 ep_ring->dequeue)) {
1038                         if (ep_ring->dequeue ==
1039                                         dev->eps[ep_index].queued_deq_ptr)
1040                                 break;
1041                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1042                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1043                 }
1044                 if (ep_ring->dequeue == dequeue_temp) {
1045                         revert = true;
1046                         break;
1047                 }
1048         }
1049
1050         if (revert) {
1051                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1052                 ep_ring->num_trbs_free = num_trbs_free_temp;
1053         }
1054 }
1055
1056 /*
1057  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1058  * we need to clear the set deq pending flag in the endpoint ring state, so that
1059  * the TD queueing code can ring the doorbell again.  We also need to ring the
1060  * endpoint doorbell to restart the ring, but only if there aren't more
1061  * cancellations pending.
1062  */
1063 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1064                 struct xhci_event_cmd *event,
1065                 union xhci_trb *trb)
1066 {
1067         unsigned int slot_id;
1068         unsigned int ep_index;
1069         unsigned int stream_id;
1070         struct xhci_ring *ep_ring;
1071         struct xhci_virt_device *dev;
1072         struct xhci_ep_ctx *ep_ctx;
1073         struct xhci_slot_ctx *slot_ctx;
1074
1075         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1076         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1077         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1078         dev = xhci->devs[slot_id];
1079
1080         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1081         if (!ep_ring) {
1082                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1083                                 "freed stream ID %u\n",
1084                                 stream_id);
1085                 /* XXX: Harmless??? */
1086                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1087                 return;
1088         }
1089
1090         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1091         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1092
1093         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1094                 unsigned int ep_state;
1095                 unsigned int slot_state;
1096
1097                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1098                 case COMP_TRB_ERR:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1100                                         "of stream ID configuration\n");
1101                         break;
1102                 case COMP_CTX_STATE:
1103                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1104                                         "to incorrect slot or ep state.\n");
1105                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1106                         ep_state &= EP_STATE_MASK;
1107                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1108                         slot_state = GET_SLOT_STATE(slot_state);
1109                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1110                                         slot_state, ep_state);
1111                         break;
1112                 case COMP_EBADSLT:
1113                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1114                                         "slot %u was not enabled.\n", slot_id);
1115                         break;
1116                 default:
1117                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1118                                         "completion code of %u.\n",
1119                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1120                         break;
1121                 }
1122                 /* OK what do we do now?  The endpoint state is hosed, and we
1123                  * should never get to this point if the synchronization between
1124                  * queueing, and endpoint state are correct.  This might happen
1125                  * if the device gets disconnected after we've finished
1126                  * cancelling URBs, which might not be an error...
1127                  */
1128         } else {
1129                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1130                          le64_to_cpu(ep_ctx->deq));
1131                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1132                                          dev->eps[ep_index].queued_deq_ptr) ==
1133                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1134                         /* Update the ring's dequeue segment and dequeue pointer
1135                          * to reflect the new position.
1136                          */
1137                         update_ring_for_set_deq_completion(xhci, dev,
1138                                 ep_ring, ep_index);
1139                 } else {
1140                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1141                                         "Ptr command & xHCI internal state.\n");
1142                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1143                                         dev->eps[ep_index].queued_deq_seg,
1144                                         dev->eps[ep_index].queued_deq_ptr);
1145                 }
1146         }
1147
1148         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1149         dev->eps[ep_index].queued_deq_seg = NULL;
1150         dev->eps[ep_index].queued_deq_ptr = NULL;
1151         /* Restart any rings with pending URBs */
1152         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1153 }
1154
1155 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1156                 struct xhci_event_cmd *event,
1157                 union xhci_trb *trb)
1158 {
1159         int slot_id;
1160         unsigned int ep_index;
1161
1162         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1163         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1164         /* This command will only fail if the endpoint wasn't halted,
1165          * but we don't care.
1166          */
1167         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1168                  GET_COMP_CODE(le32_to_cpu(event->status)));
1169
1170         /* HW with the reset endpoint quirk needs to have a configure endpoint
1171          * command complete before the endpoint can be used.  Queue that here
1172          * because the HW can't handle two commands being queued in a row.
1173          */
1174         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1175                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1176                 xhci_queue_configure_endpoint(xhci,
1177                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1178                                 false);
1179                 xhci_ring_cmd_db(xhci);
1180         } else {
1181                 /* Clear our internal halted state and restart the ring(s) */
1182                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1183                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1184         }
1185 }
1186
1187 /* Complete the command and detele it from the devcie's command queue.
1188  */
1189 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1190                 struct xhci_command *command, u32 status)
1191 {
1192         command->status = status;
1193         list_del(&command->cmd_list);
1194         if (command->completion)
1195                 complete(command->completion);
1196         else
1197                 xhci_free_command(xhci, command);
1198 }
1199
1200
1201 /* Check to see if a command in the device's command queue matches this one.
1202  * Signal the completion or free the command, and return 1.  Return 0 if the
1203  * completed command isn't at the head of the command list.
1204  */
1205 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1206                 struct xhci_virt_device *virt_dev,
1207                 struct xhci_event_cmd *event)
1208 {
1209         struct xhci_command *command;
1210
1211         if (list_empty(&virt_dev->cmd_list))
1212                 return 0;
1213
1214         command = list_entry(virt_dev->cmd_list.next,
1215                         struct xhci_command, cmd_list);
1216         if (xhci->cmd_ring->dequeue != command->command_trb)
1217                 return 0;
1218
1219         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1220                         GET_COMP_CODE(le32_to_cpu(event->status)));
1221         return 1;
1222 }
1223
1224 /*
1225  * Finding the command trb need to be cancelled and modifying it to
1226  * NO OP command. And if the command is in device's command wait
1227  * list, finishing and freeing it.
1228  *
1229  * If we can't find the command trb, we think it had already been
1230  * executed.
1231  */
1232 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1233 {
1234         struct xhci_segment *cur_seg;
1235         union xhci_trb *cmd_trb;
1236         u32 cycle_state;
1237
1238         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1239                 return;
1240
1241         /* find the current segment of command ring */
1242         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1243                         xhci->cmd_ring->dequeue, &cycle_state);
1244
1245         if (!cur_seg) {
1246                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1247                                 xhci->cmd_ring->dequeue,
1248                                 (unsigned long long)
1249                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1250                                         xhci->cmd_ring->dequeue));
1251                 xhci_debug_ring(xhci, xhci->cmd_ring);
1252                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1253                 return;
1254         }
1255
1256         /* find the command trb matched by cd from command ring */
1257         for (cmd_trb = xhci->cmd_ring->dequeue;
1258                         cmd_trb != xhci->cmd_ring->enqueue;
1259                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1260                 /* If the trb is link trb, continue */
1261                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1262                         continue;
1263
1264                 if (cur_cd->cmd_trb == cmd_trb) {
1265
1266                         /* If the command in device's command list, we should
1267                          * finish it and free the command structure.
1268                          */
1269                         if (cur_cd->command)
1270                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1271                                         cur_cd->command, COMP_CMD_STOP);
1272
1273                         /* get cycle state from the origin command trb */
1274                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1275                                 & TRB_CYCLE;
1276
1277                         /* modify the command trb to NO OP command */
1278                         cmd_trb->generic.field[0] = 0;
1279                         cmd_trb->generic.field[1] = 0;
1280                         cmd_trb->generic.field[2] = 0;
1281                         cmd_trb->generic.field[3] = cpu_to_le32(
1282                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1283                         break;
1284                 }
1285         }
1286 }
1287
1288 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1289 {
1290         struct xhci_cd *cur_cd, *next_cd;
1291
1292         if (list_empty(&xhci->cancel_cmd_list))
1293                 return;
1294
1295         list_for_each_entry_safe(cur_cd, next_cd,
1296                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1297                 xhci_cmd_to_noop(xhci, cur_cd);
1298                 list_del(&cur_cd->cancel_cmd_list);
1299                 kfree(cur_cd);
1300         }
1301 }
1302
1303 /*
1304  * traversing the cancel_cmd_list. If the command descriptor according
1305  * to cmd_trb is found, the function free it and return 1, otherwise
1306  * return 0.
1307  */
1308 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1309                 union xhci_trb *cmd_trb)
1310 {
1311         struct xhci_cd *cur_cd, *next_cd;
1312
1313         if (list_empty(&xhci->cancel_cmd_list))
1314                 return 0;
1315
1316         list_for_each_entry_safe(cur_cd, next_cd,
1317                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1318                 if (cur_cd->cmd_trb == cmd_trb) {
1319                         if (cur_cd->command)
1320                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1321                                         cur_cd->command, COMP_CMD_STOP);
1322                         list_del(&cur_cd->cancel_cmd_list);
1323                         kfree(cur_cd);
1324                         return 1;
1325                 }
1326         }
1327
1328         return 0;
1329 }
1330
1331 /*
1332  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1333  * trb pointed by the command ring dequeue pointer is the trb we want to
1334  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1335  * traverse the cancel_cmd_list to trun the all of the commands according
1336  * to command descriptor to NO-OP trb.
1337  */
1338 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1339                 int cmd_trb_comp_code)
1340 {
1341         int cur_trb_is_good = 0;
1342
1343         /* Searching the cmd trb pointed by the command ring dequeue
1344          * pointer in command descriptor list. If it is found, free it.
1345          */
1346         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1347                         xhci->cmd_ring->dequeue);
1348
1349         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1350                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1351         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1352                 /* traversing the cancel_cmd_list and canceling
1353                  * the command according to command descriptor
1354                  */
1355                 xhci_cancel_cmd_in_cd_list(xhci);
1356
1357                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1358                 /*
1359                  * ring command ring doorbell again to restart the
1360                  * command ring
1361                  */
1362                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1363                         xhci_ring_cmd_db(xhci);
1364         }
1365         return cur_trb_is_good;
1366 }
1367
1368 static void handle_cmd_completion(struct xhci_hcd *xhci,
1369                 struct xhci_event_cmd *event)
1370 {
1371         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1372         u64 cmd_dma;
1373         dma_addr_t cmd_dequeue_dma;
1374         struct xhci_input_control_ctx *ctrl_ctx;
1375         struct xhci_virt_device *virt_dev;
1376         unsigned int ep_index;
1377         struct xhci_ring *ep_ring;
1378         unsigned int ep_state;
1379
1380         cmd_dma = le64_to_cpu(event->cmd_trb);
1381         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1382                         xhci->cmd_ring->dequeue);
1383         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1384         if (cmd_dequeue_dma == 0) {
1385                 xhci->error_bitmask |= 1 << 4;
1386                 return;
1387         }
1388         /* Does the DMA address match our internal dequeue pointer address? */
1389         if (cmd_dma != (u64) cmd_dequeue_dma) {
1390                 xhci->error_bitmask |= 1 << 5;
1391                 return;
1392         }
1393
1394         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1395                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1396                 /* If the return value is 0, we think the trb pointed by
1397                  * command ring dequeue pointer is a good trb. The good
1398                  * trb means we don't want to cancel the trb, but it have
1399                  * been stopped by host. So we should handle it normally.
1400                  * Otherwise, driver should invoke inc_deq() and return.
1401                  */
1402                 if (handle_stopped_cmd_ring(xhci,
1403                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1404                         inc_deq(xhci, xhci->cmd_ring);
1405                         return;
1406                 }
1407                 /* There is no command to handle if we get a stop event when the
1408                  * command ring is empty, event->cmd_trb points to the next
1409                  * unset command
1410                  */
1411                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1412                         return;
1413         }
1414
1415         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1416                 & TRB_TYPE_BITMASK) {
1417         case TRB_TYPE(TRB_ENABLE_SLOT):
1418                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1419                         xhci->slot_id = slot_id;
1420                 else
1421                         xhci->slot_id = 0;
1422                 complete(&xhci->addr_dev);
1423                 break;
1424         case TRB_TYPE(TRB_DISABLE_SLOT):
1425                 if (xhci->devs[slot_id]) {
1426                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1427                                 /* Delete default control endpoint resources */
1428                                 xhci_free_device_endpoint_resources(xhci,
1429                                                 xhci->devs[slot_id], true);
1430                         xhci_free_virt_device(xhci, slot_id);
1431                 }
1432                 break;
1433         case TRB_TYPE(TRB_CONFIG_EP):
1434                 virt_dev = xhci->devs[slot_id];
1435                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1436                         break;
1437                 /*
1438                  * Configure endpoint commands can come from the USB core
1439                  * configuration or alt setting changes, or because the HW
1440                  * needed an extra configure endpoint command after a reset
1441                  * endpoint command or streams were being configured.
1442                  * If the command was for a halted endpoint, the xHCI driver
1443                  * is not waiting on the configure endpoint command.
1444                  */
1445                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1446                                 virt_dev->in_ctx);
1447                 /* Input ctx add_flags are the endpoint index plus one */
1448                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1449                 /* A usb_set_interface() call directly after clearing a halted
1450                  * condition may race on this quirky hardware.  Not worth
1451                  * worrying about, since this is prototype hardware.  Not sure
1452                  * if this will work for streams, but streams support was
1453                  * untested on this prototype.
1454                  */
1455                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1456                                 ep_index != (unsigned int) -1 &&
1457                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1458                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1459                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1460                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1461                         if (!(ep_state & EP_HALTED))
1462                                 goto bandwidth_change;
1463                         xhci_dbg(xhci, "Completed config ep cmd - "
1464                                         "last ep index = %d, state = %d\n",
1465                                         ep_index, ep_state);
1466                         /* Clear internal halted state and restart ring(s) */
1467                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1468                                 ~EP_HALTED;
1469                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1470                         break;
1471                 }
1472 bandwidth_change:
1473                 xhci_dbg(xhci, "Completed config ep cmd\n");
1474                 xhci->devs[slot_id]->cmd_status =
1475                         GET_COMP_CODE(le32_to_cpu(event->status));
1476                 complete(&xhci->devs[slot_id]->cmd_completion);
1477                 break;
1478         case TRB_TYPE(TRB_EVAL_CONTEXT):
1479                 virt_dev = xhci->devs[slot_id];
1480                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1481                         break;
1482                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1483                 complete(&xhci->devs[slot_id]->cmd_completion);
1484                 break;
1485         case TRB_TYPE(TRB_ADDR_DEV):
1486                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1487                 complete(&xhci->addr_dev);
1488                 break;
1489         case TRB_TYPE(TRB_STOP_RING):
1490                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1491                 break;
1492         case TRB_TYPE(TRB_SET_DEQ):
1493                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1494                 break;
1495         case TRB_TYPE(TRB_CMD_NOOP):
1496                 break;
1497         case TRB_TYPE(TRB_RESET_EP):
1498                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1499                 break;
1500         case TRB_TYPE(TRB_RESET_DEV):
1501                 xhci_dbg(xhci, "Completed reset device command.\n");
1502                 slot_id = TRB_TO_SLOT_ID(
1503                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1504                 virt_dev = xhci->devs[slot_id];
1505                 if (virt_dev)
1506                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1507                 else
1508                         xhci_warn(xhci, "Reset device command completion "
1509                                         "for disabled slot %u\n", slot_id);
1510                 break;
1511         case TRB_TYPE(TRB_NEC_GET_FW):
1512                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1513                         xhci->error_bitmask |= 1 << 6;
1514                         break;
1515                 }
1516                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1517                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1518                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1519                 break;
1520         default:
1521                 /* Skip over unknown commands on the event ring */
1522                 xhci->error_bitmask |= 1 << 6;
1523                 break;
1524         }
1525         inc_deq(xhci, xhci->cmd_ring);
1526 }
1527
1528 static void handle_vendor_event(struct xhci_hcd *xhci,
1529                 union xhci_trb *event)
1530 {
1531         u32 trb_type;
1532
1533         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1534         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1535         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1536                 handle_cmd_completion(xhci, &event->event_cmd);
1537 }
1538
1539 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1540  * port registers -- USB 3.0 and USB 2.0).
1541  *
1542  * Returns a zero-based port number, which is suitable for indexing into each of
1543  * the split roothubs' port arrays and bus state arrays.
1544  * Add one to it in order to call xhci_find_slot_id_by_port.
1545  */
1546 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1547                 struct xhci_hcd *xhci, u32 port_id)
1548 {
1549         unsigned int i;
1550         unsigned int num_similar_speed_ports = 0;
1551
1552         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1553          * and usb2_ports are 0-based indexes.  Count the number of similar
1554          * speed ports, up to 1 port before this port.
1555          */
1556         for (i = 0; i < (port_id - 1); i++) {
1557                 u8 port_speed = xhci->port_array[i];
1558
1559                 /*
1560                  * Skip ports that don't have known speeds, or have duplicate
1561                  * Extended Capabilities port speed entries.
1562                  */
1563                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1564                         continue;
1565
1566                 /*
1567                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1568                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1569                  * matches the device speed, it's a similar speed port.
1570                  */
1571                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1572                         num_similar_speed_ports++;
1573         }
1574         return num_similar_speed_ports;
1575 }
1576
1577 static void handle_device_notification(struct xhci_hcd *xhci,
1578                 union xhci_trb *event)
1579 {
1580         u32 slot_id;
1581         struct usb_device *udev;
1582
1583         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1584         if (!xhci->devs[slot_id]) {
1585                 xhci_warn(xhci, "Device Notification event for "
1586                                 "unused slot %u\n", slot_id);
1587                 return;
1588         }
1589
1590         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1591                         slot_id);
1592         udev = xhci->devs[slot_id]->udev;
1593         if (udev && udev->parent)
1594                 usb_wakeup_notification(udev->parent, udev->portnum);
1595 }
1596
1597 static void handle_port_status(struct xhci_hcd *xhci,
1598                 union xhci_trb *event)
1599 {
1600         struct usb_hcd *hcd;
1601         u32 port_id;
1602         u32 temp, temp1;
1603         int max_ports;
1604         int slot_id;
1605         unsigned int faked_port_index;
1606         u8 major_revision;
1607         struct xhci_bus_state *bus_state;
1608         __le32 __iomem **port_array;
1609         bool bogus_port_status = false;
1610
1611         /* Port status change events always have a successful completion code */
1612         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1613                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1614                 xhci->error_bitmask |= 1 << 8;
1615         }
1616         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1617         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1618
1619         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1620         if ((port_id <= 0) || (port_id > max_ports)) {
1621                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1622                 inc_deq(xhci, xhci->event_ring);
1623                 return;
1624         }
1625
1626         /* Figure out which usb_hcd this port is attached to:
1627          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1628          */
1629         major_revision = xhci->port_array[port_id - 1];
1630
1631         /* Find the right roothub. */
1632         hcd = xhci_to_hcd(xhci);
1633         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1634                 hcd = xhci->shared_hcd;
1635
1636         if (major_revision == 0) {
1637                 xhci_warn(xhci, "Event for port %u not in "
1638                                 "Extended Capabilities, ignoring.\n",
1639                                 port_id);
1640                 bogus_port_status = true;
1641                 goto cleanup;
1642         }
1643         if (major_revision == DUPLICATE_ENTRY) {
1644                 xhci_warn(xhci, "Event for port %u duplicated in"
1645                                 "Extended Capabilities, ignoring.\n",
1646                                 port_id);
1647                 bogus_port_status = true;
1648                 goto cleanup;
1649         }
1650
1651         /*
1652          * Hardware port IDs reported by a Port Status Change Event include USB
1653          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1654          * resume event, but we first need to translate the hardware port ID
1655          * into the index into the ports on the correct split roothub, and the
1656          * correct bus_state structure.
1657          */
1658         bus_state = &xhci->bus_state[hcd_index(hcd)];
1659         if (hcd->speed == HCD_USB3)
1660                 port_array = xhci->usb3_ports;
1661         else
1662                 port_array = xhci->usb2_ports;
1663         /* Find the faked port hub number */
1664         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1665                         port_id);
1666
1667         temp = xhci_readl(xhci, port_array[faked_port_index]);
1668         if (hcd->state == HC_STATE_SUSPENDED) {
1669                 xhci_dbg(xhci, "resume root hub\n");
1670                 usb_hcd_resume_root_hub(hcd);
1671         }
1672
1673         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1674                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1675
1676                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1677                 if (!(temp1 & CMD_RUN)) {
1678                         xhci_warn(xhci, "xHC is not running.\n");
1679                         goto cleanup;
1680                 }
1681
1682                 if (DEV_SUPERSPEED(temp)) {
1683                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1684                         /* Set a flag to say the port signaled remote wakeup,
1685                          * so we can tell the difference between the end of
1686                          * device and host initiated resume.
1687                          */
1688                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1689                         xhci_test_and_clear_bit(xhci, port_array,
1690                                         faked_port_index, PORT_PLC);
1691                         xhci_set_link_state(xhci, port_array, faked_port_index,
1692                                                 XDEV_U0);
1693                         /* Need to wait until the next link state change
1694                          * indicates the device is actually in U0.
1695                          */
1696                         bogus_port_status = true;
1697                         goto cleanup;
1698                 } else {
1699                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1700                         bus_state->resume_done[faked_port_index] = jiffies +
1701                                 msecs_to_jiffies(20);
1702                         set_bit(faked_port_index, &bus_state->resuming_ports);
1703                         mod_timer(&hcd->rh_timer,
1704                                   bus_state->resume_done[faked_port_index]);
1705                         /* Do the rest in GetPortStatus */
1706                 }
1707         }
1708
1709         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1710                         DEV_SUPERSPEED(temp)) {
1711                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1712                 /* We've just brought the device into U0 through either the
1713                  * Resume state after a device remote wakeup, or through the
1714                  * U3Exit state after a host-initiated resume.  If it's a device
1715                  * initiated remote wake, don't pass up the link state change,
1716                  * so the roothub behavior is consistent with external
1717                  * USB 3.0 hub behavior.
1718                  */
1719                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1720                                 faked_port_index + 1);
1721                 if (slot_id && xhci->devs[slot_id])
1722                         xhci_ring_device(xhci, slot_id);
1723                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1724                         bus_state->port_remote_wakeup &=
1725                                 ~(1 << faked_port_index);
1726                         xhci_test_and_clear_bit(xhci, port_array,
1727                                         faked_port_index, PORT_PLC);
1728                         usb_wakeup_notification(hcd->self.root_hub,
1729                                         faked_port_index + 1);
1730                         bogus_port_status = true;
1731                         goto cleanup;
1732                 }
1733         }
1734
1735         if (hcd->speed != HCD_USB3)
1736                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1737                                         PORT_PLC);
1738
1739 cleanup:
1740         /* Update event ring dequeue pointer before dropping the lock */
1741         inc_deq(xhci, xhci->event_ring);
1742
1743         /* Don't make the USB core poll the roothub if we got a bad port status
1744          * change event.  Besides, at that point we can't tell which roothub
1745          * (USB 2.0 or USB 3.0) to kick.
1746          */
1747         if (bogus_port_status)
1748                 return;
1749
1750         /*
1751          * xHCI port-status-change events occur when the "or" of all the
1752          * status-change bits in the portsc register changes from 0 to 1.
1753          * New status changes won't cause an event if any other change
1754          * bits are still set.  When an event occurs, switch over to
1755          * polling to avoid losing status changes.
1756          */
1757         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1758         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1759         spin_unlock(&xhci->lock);
1760         /* Pass this up to the core */
1761         usb_hcd_poll_rh_status(hcd);
1762         spin_lock(&xhci->lock);
1763 }
1764
1765 /*
1766  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1767  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1768  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1769  * returns 0.
1770  */
1771 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1772                 union xhci_trb  *start_trb,
1773                 union xhci_trb  *end_trb,
1774                 dma_addr_t      suspect_dma)
1775 {
1776         dma_addr_t start_dma;
1777         dma_addr_t end_seg_dma;
1778         dma_addr_t end_trb_dma;
1779         struct xhci_segment *cur_seg;
1780
1781         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1782         cur_seg = start_seg;
1783
1784         do {
1785                 if (start_dma == 0)
1786                         return NULL;
1787                 /* We may get an event for a Link TRB in the middle of a TD */
1788                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1789                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1790                 /* If the end TRB isn't in this segment, this is set to 0 */
1791                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1792
1793                 if (end_trb_dma > 0) {
1794                         /* The end TRB is in this segment, so suspect should be here */
1795                         if (start_dma <= end_trb_dma) {
1796                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1797                                         return cur_seg;
1798                         } else {
1799                                 /* Case for one segment with
1800                                  * a TD wrapped around to the top
1801                                  */
1802                                 if ((suspect_dma >= start_dma &&
1803                                                         suspect_dma <= end_seg_dma) ||
1804                                                 (suspect_dma >= cur_seg->dma &&
1805                                                  suspect_dma <= end_trb_dma))
1806                                         return cur_seg;
1807                         }
1808                         return NULL;
1809                 } else {
1810                         /* Might still be somewhere in this segment */
1811                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1812                                 return cur_seg;
1813                 }
1814                 cur_seg = cur_seg->next;
1815                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1816         } while (cur_seg != start_seg);
1817
1818         return NULL;
1819 }
1820
1821 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1822                 unsigned int slot_id, unsigned int ep_index,
1823                 unsigned int stream_id,
1824                 struct xhci_td *td, union xhci_trb *event_trb)
1825 {
1826         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1827         ep->ep_state |= EP_HALTED;
1828         ep->stopped_td = td;
1829         ep->stopped_trb = event_trb;
1830         ep->stopped_stream = stream_id;
1831
1832         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1833         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1834
1835         ep->stopped_td = NULL;
1836         ep->stopped_trb = NULL;
1837         ep->stopped_stream = 0;
1838
1839         xhci_ring_cmd_db(xhci);
1840 }
1841
1842 /* Check if an error has halted the endpoint ring.  The class driver will
1843  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1844  * However, a babble and other errors also halt the endpoint ring, and the class
1845  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1846  * Ring Dequeue Pointer command manually.
1847  */
1848 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1849                 struct xhci_ep_ctx *ep_ctx,
1850                 unsigned int trb_comp_code)
1851 {
1852         /* TRB completion codes that may require a manual halt cleanup */
1853         if (trb_comp_code == COMP_TX_ERR ||
1854                         trb_comp_code == COMP_BABBLE ||
1855                         trb_comp_code == COMP_SPLIT_ERR)
1856                 /* The 0.96 spec says a babbling control endpoint
1857                  * is not halted. The 0.96 spec says it is.  Some HW
1858                  * claims to be 0.95 compliant, but it halts the control
1859                  * endpoint anyway.  Check if a babble halted the
1860                  * endpoint.
1861                  */
1862                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1863                     cpu_to_le32(EP_STATE_HALTED))
1864                         return 1;
1865
1866         return 0;
1867 }
1868
1869 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1870 {
1871         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1872                 /* Vendor defined "informational" completion code,
1873                  * treat as not-an-error.
1874                  */
1875                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1876                                 trb_comp_code);
1877                 xhci_dbg(xhci, "Treating code as success.\n");
1878                 return 1;
1879         }
1880         return 0;
1881 }
1882
1883 /*
1884  * Finish the td processing, remove the td from td list;
1885  * Return 1 if the urb can be given back.
1886  */
1887 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1888         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1889         struct xhci_virt_ep *ep, int *status, bool skip)
1890 {
1891         struct xhci_virt_device *xdev;
1892         struct xhci_ring *ep_ring;
1893         unsigned int slot_id;
1894         int ep_index;
1895         struct urb *urb = NULL;
1896         struct xhci_ep_ctx *ep_ctx;
1897         int ret = 0;
1898         struct urb_priv *urb_priv;
1899         u32 trb_comp_code;
1900
1901         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1902         xdev = xhci->devs[slot_id];
1903         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1904         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1905         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1906         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1907
1908         if (skip)
1909                 goto td_cleanup;
1910
1911         if (trb_comp_code == COMP_STOP_INVAL ||
1912                         trb_comp_code == COMP_STOP) {
1913                 /* The Endpoint Stop Command completion will take care of any
1914                  * stopped TDs.  A stopped TD may be restarted, so don't update
1915                  * the ring dequeue pointer or take this TD off any lists yet.
1916                  */
1917                 ep->stopped_td = td;
1918                 ep->stopped_trb = event_trb;
1919                 return 0;
1920         } else {
1921                 if (trb_comp_code == COMP_STALL) {
1922                         /* The transfer is completed from the driver's
1923                          * perspective, but we need to issue a set dequeue
1924                          * command for this stalled endpoint to move the dequeue
1925                          * pointer past the TD.  We can't do that here because
1926                          * the halt condition must be cleared first.  Let the
1927                          * USB class driver clear the stall later.
1928                          */
1929                         ep->stopped_td = td;
1930                         ep->stopped_trb = event_trb;
1931                         ep->stopped_stream = ep_ring->stream_id;
1932                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1933                                         ep_ctx, trb_comp_code)) {
1934                         /* Other types of errors halt the endpoint, but the
1935                          * class driver doesn't call usb_reset_endpoint() unless
1936                          * the error is -EPIPE.  Clear the halted status in the
1937                          * xHCI hardware manually.
1938                          */
1939                         xhci_cleanup_halted_endpoint(xhci,
1940                                         slot_id, ep_index, ep_ring->stream_id,
1941                                         td, event_trb);
1942                 } else {
1943                         /* Update ring dequeue pointer */
1944                         while (ep_ring->dequeue != td->last_trb)
1945                                 inc_deq(xhci, ep_ring);
1946                         inc_deq(xhci, ep_ring);
1947                 }
1948
1949 td_cleanup:
1950                 /* Clean up the endpoint's TD list */
1951                 urb = td->urb;
1952                 urb_priv = urb->hcpriv;
1953
1954                 /* Do one last check of the actual transfer length.
1955                  * If the host controller said we transferred more data than
1956                  * the buffer length, urb->actual_length will be a very big
1957                  * number (since it's unsigned).  Play it safe and say we didn't
1958                  * transfer anything.
1959                  */
1960                 if (urb->actual_length > urb->transfer_buffer_length) {
1961                         xhci_warn(xhci, "URB transfer length is wrong, "
1962                                         "xHC issue? req. len = %u, "
1963                                         "act. len = %u\n",
1964                                         urb->transfer_buffer_length,
1965                                         urb->actual_length);
1966                         urb->actual_length = 0;
1967                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1968                                 *status = -EREMOTEIO;
1969                         else
1970                                 *status = 0;
1971                 }
1972                 list_del_init(&td->td_list);
1973                 /* Was this TD slated to be cancelled but completed anyway? */
1974                 if (!list_empty(&td->cancelled_td_list))
1975                         list_del_init(&td->cancelled_td_list);
1976
1977                 urb_priv->td_cnt++;
1978                 /* Giveback the urb when all the tds are completed */
1979                 if (urb_priv->td_cnt == urb_priv->length) {
1980                         ret = 1;
1981                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1982                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1983                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1984                                         == 0) {
1985                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1986                                                 usb_amd_quirk_pll_enable();
1987                                 }
1988                         }
1989                 }
1990         }
1991
1992         return ret;
1993 }
1994
1995 /*
1996  * Process control tds, update urb status and actual_length.
1997  */
1998 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1999         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2000         struct xhci_virt_ep *ep, int *status)
2001 {
2002         struct xhci_virt_device *xdev;
2003         struct xhci_ring *ep_ring;
2004         unsigned int slot_id;
2005         int ep_index;
2006         struct xhci_ep_ctx *ep_ctx;
2007         u32 trb_comp_code;
2008
2009         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2010         xdev = xhci->devs[slot_id];
2011         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2012         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2013         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2014         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2015
2016         switch (trb_comp_code) {
2017         case COMP_SUCCESS:
2018                 if (event_trb == ep_ring->dequeue) {
2019                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2020                                         "without IOC set??\n");
2021                         *status = -ESHUTDOWN;
2022                 } else if (event_trb != td->last_trb) {
2023                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2024                                         "without IOC set??\n");
2025                         *status = -ESHUTDOWN;
2026                 } else {
2027                         *status = 0;
2028                 }
2029                 break;
2030         case COMP_SHORT_TX:
2031                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2032                         *status = -EREMOTEIO;
2033                 else
2034                         *status = 0;
2035                 break;
2036         case COMP_STOP_INVAL:
2037         case COMP_STOP:
2038                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2039         default:
2040                 if (!xhci_requires_manual_halt_cleanup(xhci,
2041                                         ep_ctx, trb_comp_code))
2042                         break;
2043                 xhci_dbg(xhci, "TRB error code %u, "
2044                                 "halted endpoint index = %u\n",
2045                                 trb_comp_code, ep_index);
2046                 /* else fall through */
2047         case COMP_STALL:
2048                 /* Did we transfer part of the data (middle) phase? */
2049                 if (event_trb != ep_ring->dequeue &&
2050                                 event_trb != td->last_trb)
2051                         td->urb->actual_length =
2052                                 td->urb->transfer_buffer_length -
2053                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2054                 else
2055                         td->urb->actual_length = 0;
2056
2057                 xhci_cleanup_halted_endpoint(xhci,
2058                         slot_id, ep_index, 0, td, event_trb);
2059                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2060         }
2061         /*
2062          * Did we transfer any data, despite the errors that might have
2063          * happened?  I.e. did we get past the setup stage?
2064          */
2065         if (event_trb != ep_ring->dequeue) {
2066                 /* The event was for the status stage */
2067                 if (event_trb == td->last_trb) {
2068                         if (td->urb->actual_length != 0) {
2069                                 /* Don't overwrite a previously set error code
2070                                  */
2071                                 if ((*status == -EINPROGRESS || *status == 0) &&
2072                                                 (td->urb->transfer_flags
2073                                                  & URB_SHORT_NOT_OK))
2074                                         /* Did we already see a short data
2075                                          * stage? */
2076                                         *status = -EREMOTEIO;
2077                         } else {
2078                                 td->urb->actual_length =
2079                                         td->urb->transfer_buffer_length;
2080                         }
2081                 } else {
2082                 /* Maybe the event was for the data stage? */
2083                         td->urb->actual_length =
2084                                 td->urb->transfer_buffer_length -
2085                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2086                         xhci_dbg(xhci, "Waiting for status "
2087                                         "stage event\n");
2088                         return 0;
2089                 }
2090         }
2091
2092         return finish_td(xhci, td, event_trb, event, ep, status, false);
2093 }
2094
2095 /*
2096  * Process isochronous tds, update urb packet status and actual_length.
2097  */
2098 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2099         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2100         struct xhci_virt_ep *ep, int *status)
2101 {
2102         struct xhci_ring *ep_ring;
2103         struct urb_priv *urb_priv;
2104         int idx;
2105         int len = 0;
2106         union xhci_trb *cur_trb;
2107         struct xhci_segment *cur_seg;
2108         struct usb_iso_packet_descriptor *frame;
2109         u32 trb_comp_code;
2110         bool skip_td = false;
2111
2112         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2113         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2114         urb_priv = td->urb->hcpriv;
2115         idx = urb_priv->td_cnt;
2116         frame = &td->urb->iso_frame_desc[idx];
2117
2118         /* handle completion code */
2119         switch (trb_comp_code) {
2120         case COMP_SUCCESS:
2121                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2122                         frame->status = 0;
2123                         break;
2124                 }
2125                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2126                         trb_comp_code = COMP_SHORT_TX;
2127         case COMP_SHORT_TX:
2128                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2129                                 -EREMOTEIO : 0;
2130                 break;
2131         case COMP_BW_OVER:
2132                 frame->status = -ECOMM;
2133                 skip_td = true;
2134                 break;
2135         case COMP_BUFF_OVER:
2136         case COMP_BABBLE:
2137                 frame->status = -EOVERFLOW;
2138                 skip_td = true;
2139                 break;
2140         case COMP_DEV_ERR:
2141         case COMP_STALL:
2142         case COMP_TX_ERR:
2143                 frame->status = -EPROTO;
2144                 skip_td = true;
2145                 break;
2146         case COMP_STOP:
2147         case COMP_STOP_INVAL:
2148                 break;
2149         default:
2150                 frame->status = -1;
2151                 break;
2152         }
2153
2154         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2155                 frame->actual_length = frame->length;
2156                 td->urb->actual_length += frame->length;
2157         } else {
2158                 for (cur_trb = ep_ring->dequeue,
2159                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2160                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2161                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2162                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2163                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2164                 }
2165                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2166                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2167
2168                 if (trb_comp_code != COMP_STOP_INVAL) {
2169                         frame->actual_length = len;
2170                         td->urb->actual_length += len;
2171                 }
2172         }
2173
2174         return finish_td(xhci, td, event_trb, event, ep, status, false);
2175 }
2176
2177 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2178                         struct xhci_transfer_event *event,
2179                         struct xhci_virt_ep *ep, int *status)
2180 {
2181         struct xhci_ring *ep_ring;
2182         struct urb_priv *urb_priv;
2183         struct usb_iso_packet_descriptor *frame;
2184         int idx;
2185
2186         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2187         urb_priv = td->urb->hcpriv;
2188         idx = urb_priv->td_cnt;
2189         frame = &td->urb->iso_frame_desc[idx];
2190
2191         /* The transfer is partly done. */
2192         frame->status = -EXDEV;
2193
2194         /* calc actual length */
2195         frame->actual_length = 0;
2196
2197         /* Update ring dequeue pointer */
2198         while (ep_ring->dequeue != td->last_trb)
2199                 inc_deq(xhci, ep_ring);
2200         inc_deq(xhci, ep_ring);
2201
2202         return finish_td(xhci, td, NULL, event, ep, status, true);
2203 }
2204
2205 /*
2206  * Process bulk and interrupt tds, update urb status and actual_length.
2207  */
2208 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2209         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2210         struct xhci_virt_ep *ep, int *status)
2211 {
2212         struct xhci_ring *ep_ring;
2213         union xhci_trb *cur_trb;
2214         struct xhci_segment *cur_seg;
2215         u32 trb_comp_code;
2216
2217         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2218         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2219
2220         switch (trb_comp_code) {
2221         case COMP_SUCCESS:
2222                 /* Double check that the HW transferred everything. */
2223                 if (event_trb != td->last_trb ||
2224                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2225                         xhci_warn(xhci, "WARN Successful completion "
2226                                         "on short TX\n");
2227                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2228                                 *status = -EREMOTEIO;
2229                         else
2230                                 *status = 0;
2231                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2232                                 trb_comp_code = COMP_SHORT_TX;
2233                 } else {
2234                         *status = 0;
2235                 }
2236                 break;
2237         case COMP_SHORT_TX:
2238                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2239                         *status = -EREMOTEIO;
2240                 else
2241                         *status = 0;
2242                 break;
2243         default:
2244                 /* Others already handled above */
2245                 break;
2246         }
2247         if (trb_comp_code == COMP_SHORT_TX)
2248                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2249                                 "%d bytes untransferred\n",
2250                                 td->urb->ep->desc.bEndpointAddress,
2251                                 td->urb->transfer_buffer_length,
2252                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2253         /* Fast path - was this the last TRB in the TD for this URB? */
2254         if (event_trb == td->last_trb) {
2255                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2256                         td->urb->actual_length =
2257                                 td->urb->transfer_buffer_length -
2258                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2259                         if (td->urb->transfer_buffer_length <
2260                                         td->urb->actual_length) {
2261                                 xhci_warn(xhci, "HC gave bad length "
2262                                                 "of %d bytes left\n",
2263                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2264                                 td->urb->actual_length = 0;
2265                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2266                                         *status = -EREMOTEIO;
2267                                 else
2268                                         *status = 0;
2269                         }
2270                         /* Don't overwrite a previously set error code */
2271                         if (*status == -EINPROGRESS) {
2272                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2273                                         *status = -EREMOTEIO;
2274                                 else
2275                                         *status = 0;
2276                         }
2277                 } else {
2278                         td->urb->actual_length =
2279                                 td->urb->transfer_buffer_length;
2280                         /* Ignore a short packet completion if the
2281                          * untransferred length was zero.
2282                          */
2283                         if (*status == -EREMOTEIO)
2284                                 *status = 0;
2285                 }
2286         } else {
2287                 /* Slow path - walk the list, starting from the dequeue
2288                  * pointer, to get the actual length transferred.
2289                  */
2290                 td->urb->actual_length = 0;
2291                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2292                                 cur_trb != event_trb;
2293                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2294                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2295                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2296                                 td->urb->actual_length +=
2297                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2298                 }
2299                 /* If the ring didn't stop on a Link or No-op TRB, add
2300                  * in the actual bytes transferred from the Normal TRB
2301                  */
2302                 if (trb_comp_code != COMP_STOP_INVAL)
2303                         td->urb->actual_length +=
2304                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2305                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2306         }
2307
2308         return finish_td(xhci, td, event_trb, event, ep, status, false);
2309 }
2310
2311 /*
2312  * If this function returns an error condition, it means it got a Transfer
2313  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2314  * At this point, the host controller is probably hosed and should be reset.
2315  */
2316 static int handle_tx_event(struct xhci_hcd *xhci,
2317                 struct xhci_transfer_event *event)
2318         __releases(&xhci->lock)
2319         __acquires(&xhci->lock)
2320 {
2321         struct xhci_virt_device *xdev;
2322         struct xhci_virt_ep *ep;
2323         struct xhci_ring *ep_ring;
2324         unsigned int slot_id;
2325         int ep_index;
2326         struct xhci_td *td = NULL;
2327         dma_addr_t event_dma;
2328         struct xhci_segment *event_seg;
2329         union xhci_trb *event_trb;
2330         struct urb *urb = NULL;
2331         int status = -EINPROGRESS;
2332         struct urb_priv *urb_priv;
2333         struct xhci_ep_ctx *ep_ctx;
2334         struct list_head *tmp;
2335         u32 trb_comp_code;
2336         int ret = 0;
2337         int td_num = 0;
2338
2339         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2340         xdev = xhci->devs[slot_id];
2341         if (!xdev) {
2342                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2343                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2344                          (unsigned long long) xhci_trb_virt_to_dma(
2345                                  xhci->event_ring->deq_seg,
2346                                  xhci->event_ring->dequeue),
2347                          lower_32_bits(le64_to_cpu(event->buffer)),
2348                          upper_32_bits(le64_to_cpu(event->buffer)),
2349                          le32_to_cpu(event->transfer_len),
2350                          le32_to_cpu(event->flags));
2351                 xhci_dbg(xhci, "Event ring:\n");
2352                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2353                 return -ENODEV;
2354         }
2355
2356         /* Endpoint ID is 1 based, our index is zero based */
2357         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2358         ep = &xdev->eps[ep_index];
2359         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2360         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2361         if (!ep_ring ||
2362             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2363             EP_STATE_DISABLED) {
2364                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2365                                 "or incorrect stream ring\n");
2366                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2367                          (unsigned long long) xhci_trb_virt_to_dma(
2368                                  xhci->event_ring->deq_seg,
2369                                  xhci->event_ring->dequeue),
2370                          lower_32_bits(le64_to_cpu(event->buffer)),
2371                          upper_32_bits(le64_to_cpu(event->buffer)),
2372                          le32_to_cpu(event->transfer_len),
2373                          le32_to_cpu(event->flags));
2374                 xhci_dbg(xhci, "Event ring:\n");
2375                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2376                 return -ENODEV;
2377         }
2378
2379         /* Count current td numbers if ep->skip is set */
2380         if (ep->skip) {
2381                 list_for_each(tmp, &ep_ring->td_list)
2382                         td_num++;
2383         }
2384
2385         event_dma = le64_to_cpu(event->buffer);
2386         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2387         /* Look for common error cases */
2388         switch (trb_comp_code) {
2389         /* Skip codes that require special handling depending on
2390          * transfer type
2391          */
2392         case COMP_SUCCESS:
2393                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2394                         break;
2395                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2396                         trb_comp_code = COMP_SHORT_TX;
2397                 else
2398                         xhci_warn_ratelimited(xhci,
2399                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2400         case COMP_SHORT_TX:
2401                 break;
2402         case COMP_STOP:
2403                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2404                 break;
2405         case COMP_STOP_INVAL:
2406                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2407                 break;
2408         case COMP_STALL:
2409                 xhci_dbg(xhci, "Stalled endpoint\n");
2410                 ep->ep_state |= EP_HALTED;
2411                 status = -EPIPE;
2412                 break;
2413         case COMP_TRB_ERR:
2414                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2415                 status = -EILSEQ;
2416                 break;
2417         case COMP_SPLIT_ERR:
2418         case COMP_TX_ERR:
2419                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2420                 status = -EPROTO;
2421                 break;
2422         case COMP_BABBLE:
2423                 xhci_dbg(xhci, "Babble error on endpoint\n");
2424                 status = -EOVERFLOW;
2425                 break;
2426         case COMP_DB_ERR:
2427                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2428                 status = -ENOSR;
2429                 break;
2430         case COMP_BW_OVER:
2431                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2432                 break;
2433         case COMP_BUFF_OVER:
2434                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2435                 break;
2436         case COMP_UNDERRUN:
2437                 /*
2438                  * When the Isoch ring is empty, the xHC will generate
2439                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2440                  * Underrun Event for OUT Isoch endpoint.
2441                  */
2442                 xhci_dbg(xhci, "underrun event on endpoint\n");
2443                 if (!list_empty(&ep_ring->td_list))
2444                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2445                                         "still with TDs queued?\n",
2446                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2447                                  ep_index);
2448                 goto cleanup;
2449         case COMP_OVERRUN:
2450                 xhci_dbg(xhci, "overrun event on endpoint\n");
2451                 if (!list_empty(&ep_ring->td_list))
2452                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2453                                         "still with TDs queued?\n",
2454                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2455                                  ep_index);
2456                 goto cleanup;
2457         case COMP_DEV_ERR:
2458                 xhci_warn(xhci, "WARN: detect an incompatible device");
2459                 status = -EPROTO;
2460                 break;
2461         case COMP_MISSED_INT:
2462                 /*
2463                  * When encounter missed service error, one or more isoc tds
2464                  * may be missed by xHC.
2465                  * Set skip flag of the ep_ring; Complete the missed tds as
2466                  * short transfer when process the ep_ring next time.
2467                  */
2468                 ep->skip = true;
2469                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2470                 goto cleanup;
2471         default:
2472                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2473                         status = 0;
2474                         break;
2475                 }
2476                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2477                                 "busted\n");
2478                 goto cleanup;
2479         }
2480
2481         do {
2482                 /* This TRB should be in the TD at the head of this ring's
2483                  * TD list.
2484                  */
2485                 if (list_empty(&ep_ring->td_list)) {
2486                         /*
2487                          * A stopped endpoint may generate an extra completion
2488                          * event if the device was suspended.  Don't print
2489                          * warnings.
2490                          */
2491                         if (!(trb_comp_code == COMP_STOP ||
2492                                                 trb_comp_code == COMP_STOP_INVAL)) {
2493                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2494                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2495                                                 ep_index);
2496                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2497                                                 (le32_to_cpu(event->flags) &
2498                                                  TRB_TYPE_BITMASK)>>10);
2499                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2500                         }
2501                         if (ep->skip) {
2502                                 ep->skip = false;
2503                                 xhci_dbg(xhci, "td_list is empty while skip "
2504                                                 "flag set. Clear skip flag.\n");
2505                         }
2506                         ret = 0;
2507                         goto cleanup;
2508                 }
2509
2510                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2511                 if (ep->skip && td_num == 0) {
2512                         ep->skip = false;
2513                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2514                                                 "Clear skip flag.\n");
2515                         ret = 0;
2516                         goto cleanup;
2517                 }
2518
2519                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2520                 if (ep->skip)
2521                         td_num--;
2522
2523                 /* Is this a TRB in the currently executing TD? */
2524                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2525                                 td->last_trb, event_dma);
2526
2527                 /*
2528                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2529                  * is not in the current TD pointed by ep_ring->dequeue because
2530                  * that the hardware dequeue pointer still at the previous TRB
2531                  * of the current TD. The previous TRB maybe a Link TD or the
2532                  * last TRB of the previous TD. The command completion handle
2533                  * will take care the rest.
2534                  */
2535                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2536                         ret = 0;
2537                         goto cleanup;
2538                 }
2539
2540                 if (!event_seg) {
2541                         if (!ep->skip ||
2542                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2543                                 /* Some host controllers give a spurious
2544                                  * successful event after a short transfer.
2545                                  * Ignore it.
2546                                  */
2547                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2548                                                 ep_ring->last_td_was_short) {
2549                                         ep_ring->last_td_was_short = false;
2550                                         ret = 0;
2551                                         goto cleanup;
2552                                 }
2553                                 /* HC is busted, give up! */
2554                                 xhci_err(xhci,
2555                                         "ERROR Transfer event TRB DMA ptr not "
2556                                         "part of current TD\n");
2557                                 return -ESHUTDOWN;
2558                         }
2559
2560                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2561                         goto cleanup;
2562                 }
2563                 if (trb_comp_code == COMP_SHORT_TX)
2564                         ep_ring->last_td_was_short = true;
2565                 else
2566                         ep_ring->last_td_was_short = false;
2567
2568                 if (ep->skip) {
2569                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2570                         ep->skip = false;
2571                 }
2572
2573                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2574                                                 sizeof(*event_trb)];
2575                 /*
2576                  * No-op TRB should not trigger interrupts.
2577                  * If event_trb is a no-op TRB, it means the
2578                  * corresponding TD has been cancelled. Just ignore
2579                  * the TD.
2580                  */
2581                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2582                         xhci_dbg(xhci,
2583                                  "event_trb is a no-op TRB. Skip it\n");
2584                         goto cleanup;
2585                 }
2586
2587                 /* Now update the urb's actual_length and give back to
2588                  * the core
2589                  */
2590                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2591                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2592                                                  &status);
2593                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2594                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2595                                                  &status);
2596                 else
2597                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2598                                                  ep, &status);
2599
2600 cleanup:
2601                 /*
2602                  * Do not update event ring dequeue pointer if ep->skip is set.
2603                  * Will roll back to continue process missed tds.
2604                  */
2605                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2606                         inc_deq(xhci, xhci->event_ring);
2607                 }
2608
2609                 if (ret) {
2610                         urb = td->urb;
2611                         urb_priv = urb->hcpriv;
2612                         /* Leave the TD around for the reset endpoint function
2613                          * to use(but only if it's not a control endpoint,
2614                          * since we already queued the Set TR dequeue pointer
2615                          * command for stalled control endpoints).
2616                          */
2617                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2618                                 (trb_comp_code != COMP_STALL &&
2619                                         trb_comp_code != COMP_BABBLE))
2620                                 xhci_urb_free_priv(xhci, urb_priv);
2621                         else
2622                                 kfree(urb_priv);
2623
2624                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2625                         if ((urb->actual_length != urb->transfer_buffer_length &&
2626                                                 (urb->transfer_flags &
2627                                                  URB_SHORT_NOT_OK)) ||
2628                                         (status != 0 &&
2629                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2630                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2631                                                 "expected = %d, status = %d\n",
2632                                                 urb, urb->actual_length,
2633                                                 urb->transfer_buffer_length,
2634                                                 status);
2635                         spin_unlock(&xhci->lock);
2636                         /* EHCI, UHCI, and OHCI always unconditionally set the
2637                          * urb->status of an isochronous endpoint to 0.
2638                          */
2639                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2640                                 status = 0;
2641                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2642                         spin_lock(&xhci->lock);
2643                 }
2644
2645         /*
2646          * If ep->skip is set, it means there are missed tds on the
2647          * endpoint ring need to take care of.
2648          * Process them as short transfer until reach the td pointed by
2649          * the event.
2650          */
2651         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2652
2653         return 0;
2654 }
2655
2656 /*
2657  * This function handles all OS-owned events on the event ring.  It may drop
2658  * xhci->lock between event processing (e.g. to pass up port status changes).
2659  * Returns >0 for "possibly more events to process" (caller should call again),
2660  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2661  */
2662 static int xhci_handle_event(struct xhci_hcd *xhci)
2663 {
2664         union xhci_trb *event;
2665         int update_ptrs = 1;
2666         int ret;
2667
2668         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2669                 xhci->error_bitmask |= 1 << 1;
2670                 return 0;
2671         }
2672
2673         event = xhci->event_ring->dequeue;
2674         /* Does the HC or OS own the TRB? */
2675         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2676             xhci->event_ring->cycle_state) {
2677                 xhci->error_bitmask |= 1 << 2;
2678                 return 0;
2679         }
2680
2681         /*
2682          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2683          * speculative reads of the event's flags/data below.
2684          */
2685         rmb();
2686         /* FIXME: Handle more event types. */
2687         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2688         case TRB_TYPE(TRB_COMPLETION):
2689                 handle_cmd_completion(xhci, &event->event_cmd);
2690                 break;
2691         case TRB_TYPE(TRB_PORT_STATUS):
2692                 handle_port_status(xhci, event);
2693                 update_ptrs = 0;
2694                 break;
2695         case TRB_TYPE(TRB_TRANSFER):
2696                 ret = handle_tx_event(xhci, &event->trans_event);
2697                 if (ret < 0)
2698                         xhci->error_bitmask |= 1 << 9;
2699                 else
2700                         update_ptrs = 0;
2701                 break;
2702         case TRB_TYPE(TRB_DEV_NOTE):
2703                 handle_device_notification(xhci, event);
2704                 break;
2705         default:
2706                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2707                     TRB_TYPE(48))
2708                         handle_vendor_event(xhci, event);
2709                 else
2710                         xhci->error_bitmask |= 1 << 3;
2711         }
2712         /* Any of the above functions may drop and re-acquire the lock, so check
2713          * to make sure a watchdog timer didn't mark the host as non-responsive.
2714          */
2715         if (xhci->xhc_state & XHCI_STATE_DYING) {
2716                 xhci_dbg(xhci, "xHCI host dying, returning from "
2717                                 "event handler.\n");
2718                 return 0;
2719         }
2720
2721         if (update_ptrs)
2722                 /* Update SW event ring dequeue pointer */
2723                 inc_deq(xhci, xhci->event_ring);
2724
2725         /* Are there more items on the event ring?  Caller will call us again to
2726          * check.
2727          */
2728         return 1;
2729 }
2730
2731 /*
2732  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2733  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2734  * indicators of an event TRB error, but we check the status *first* to be safe.
2735  */
2736 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2737 {
2738         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2739         u32 status;
2740         u64 temp_64;
2741         union xhci_trb *event_ring_deq;
2742         dma_addr_t deq;
2743
2744         spin_lock(&xhci->lock);
2745         /* Check if the xHC generated the interrupt, or the irq is shared */
2746         status = xhci_readl(xhci, &xhci->op_regs->status);
2747         if (status == 0xffffffff)
2748                 goto hw_died;
2749
2750         if (!(status & STS_EINT)) {
2751                 spin_unlock(&xhci->lock);
2752                 return IRQ_NONE;
2753         }
2754         if (status & STS_FATAL) {
2755                 xhci_warn(xhci, "WARNING: Host System Error\n");
2756                 xhci_halt(xhci);
2757 hw_died:
2758                 spin_unlock(&xhci->lock);
2759                 return -ESHUTDOWN;
2760         }
2761
2762         /*
2763          * Clear the op reg interrupt status first,
2764          * so we can receive interrupts from other MSI-X interrupters.
2765          * Write 1 to clear the interrupt status.
2766          */
2767         status |= STS_EINT;
2768         xhci_writel(xhci, status, &xhci->op_regs->status);
2769         /* FIXME when MSI-X is supported and there are multiple vectors */
2770         /* Clear the MSI-X event interrupt status */
2771
2772         if (hcd->irq) {
2773                 u32 irq_pending;
2774                 /* Acknowledge the PCI interrupt */
2775                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2776                 irq_pending |= IMAN_IP;
2777                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2778         }
2779
2780         if (xhci->xhc_state & XHCI_STATE_DYING) {
2781                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2782                                 "Shouldn't IRQs be disabled?\n");
2783                 /* Clear the event handler busy flag (RW1C);
2784                  * the event ring should be empty.
2785                  */
2786                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2787                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2788                                 &xhci->ir_set->erst_dequeue);
2789                 spin_unlock(&xhci->lock);
2790
2791                 return IRQ_HANDLED;
2792         }
2793
2794         event_ring_deq = xhci->event_ring->dequeue;
2795         /* FIXME this should be a delayed service routine
2796          * that clears the EHB.
2797          */
2798         while (xhci_handle_event(xhci) > 0) {}
2799
2800         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2801         /* If necessary, update the HW's version of the event ring deq ptr. */
2802         if (event_ring_deq != xhci->event_ring->dequeue) {
2803                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2804                                 xhci->event_ring->dequeue);
2805                 if (deq == 0)
2806                         xhci_warn(xhci, "WARN something wrong with SW event "
2807                                         "ring dequeue ptr.\n");
2808                 /* Update HC event ring dequeue pointer */
2809                 temp_64 &= ERST_PTR_MASK;
2810                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2811         }
2812
2813         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2814         temp_64 |= ERST_EHB;
2815         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2816
2817         spin_unlock(&xhci->lock);
2818
2819         return IRQ_HANDLED;
2820 }
2821
2822 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2823 {
2824         return xhci_irq(hcd);
2825 }
2826
2827 /****           Endpoint Ring Operations        ****/
2828
2829 /*
2830  * Generic function for queueing a TRB on a ring.
2831  * The caller must have checked to make sure there's room on the ring.
2832  *
2833  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2834  *                      prepare_transfer()?
2835  */
2836 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2837                 bool more_trbs_coming,
2838                 u32 field1, u32 field2, u32 field3, u32 field4)
2839 {
2840         struct xhci_generic_trb *trb;
2841
2842         trb = &ring->enqueue->generic;
2843         trb->field[0] = cpu_to_le32(field1);
2844         trb->field[1] = cpu_to_le32(field2);
2845         trb->field[2] = cpu_to_le32(field3);
2846         trb->field[3] = cpu_to_le32(field4);
2847         inc_enq(xhci, ring, more_trbs_coming);
2848 }
2849
2850 /*
2851  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2852  * FIXME allocate segments if the ring is full.
2853  */
2854 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2855                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2856 {
2857         unsigned int num_trbs_needed;
2858
2859         /* Make sure the endpoint has been added to xHC schedule */
2860         switch (ep_state) {
2861         case EP_STATE_DISABLED:
2862                 /*
2863                  * USB core changed config/interfaces without notifying us,
2864                  * or hardware is reporting the wrong state.
2865                  */
2866                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2867                 return -ENOENT;
2868         case EP_STATE_ERROR:
2869                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2870                 /* FIXME event handling code for error needs to clear it */
2871                 /* XXX not sure if this should be -ENOENT or not */
2872                 return -EINVAL;
2873         case EP_STATE_HALTED:
2874                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2875         case EP_STATE_STOPPED:
2876         case EP_STATE_RUNNING:
2877                 break;
2878         default:
2879                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2880                 /*
2881                  * FIXME issue Configure Endpoint command to try to get the HC
2882                  * back into a known state.
2883                  */
2884                 return -EINVAL;
2885         }
2886
2887         while (1) {
2888                 if (room_on_ring(xhci, ep_ring, num_trbs))
2889                         break;
2890
2891                 if (ep_ring == xhci->cmd_ring) {
2892                         xhci_err(xhci, "Do not support expand command ring\n");
2893                         return -ENOMEM;
2894                 }
2895
2896                 xhci_dbg(xhci, "ERROR no room on ep ring, "
2897                                         "try ring expansion\n");
2898                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2899                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2900                                         mem_flags)) {
2901                         xhci_err(xhci, "Ring expansion failed\n");
2902                         return -ENOMEM;
2903                 }
2904         }
2905
2906         if (enqueue_is_link_trb(ep_ring)) {
2907                 struct xhci_ring *ring = ep_ring;
2908                 union xhci_trb *next;
2909
2910                 next = ring->enqueue;
2911
2912                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2913                         /* If we're not dealing with 0.95 hardware or isoc rings
2914                          * on AMD 0.96 host, clear the chain bit.
2915                          */
2916                         if (!xhci_link_trb_quirk(xhci) &&
2917                                         !(ring->type == TYPE_ISOC &&
2918                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2919                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2920                         else
2921                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2922
2923                         wmb();
2924                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2925
2926                         /* Toggle the cycle bit after the last ring segment. */
2927                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2928                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2929                         }
2930                         ring->enq_seg = ring->enq_seg->next;
2931                         ring->enqueue = ring->enq_seg->trbs;
2932                         next = ring->enqueue;
2933                 }
2934         }
2935
2936         return 0;
2937 }
2938
2939 static int prepare_transfer(struct xhci_hcd *xhci,
2940                 struct xhci_virt_device *xdev,
2941                 unsigned int ep_index,
2942                 unsigned int stream_id,
2943                 unsigned int num_trbs,
2944                 struct urb *urb,
2945                 unsigned int td_index,
2946                 gfp_t mem_flags)
2947 {
2948         int ret;
2949         struct urb_priv *urb_priv;
2950         struct xhci_td  *td;
2951         struct xhci_ring *ep_ring;
2952         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2953
2954         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2955         if (!ep_ring) {
2956                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2957                                 stream_id);
2958                 return -EINVAL;
2959         }
2960
2961         ret = prepare_ring(xhci, ep_ring,
2962                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2963                            num_trbs, mem_flags);
2964         if (ret)
2965                 return ret;
2966
2967         urb_priv = urb->hcpriv;
2968         td = urb_priv->td[td_index];
2969
2970         INIT_LIST_HEAD(&td->td_list);
2971         INIT_LIST_HEAD(&td->cancelled_td_list);
2972
2973         if (td_index == 0) {
2974                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2975                 if (unlikely(ret))
2976                         return ret;
2977         }
2978
2979         td->urb = urb;
2980         /* Add this TD to the tail of the endpoint ring's TD list */
2981         list_add_tail(&td->td_list, &ep_ring->td_list);
2982         td->start_seg = ep_ring->enq_seg;
2983         td->first_trb = ep_ring->enqueue;
2984
2985         urb_priv->td[td_index] = td;
2986
2987         return 0;
2988 }
2989
2990 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2991 {
2992         int num_sgs, num_trbs, running_total, temp, i;
2993         struct scatterlist *sg;
2994
2995         sg = NULL;
2996         num_sgs = urb->num_mapped_sgs;
2997         temp = urb->transfer_buffer_length;
2998
2999         num_trbs = 0;
3000         for_each_sg(urb->sg, sg, num_sgs, i) {
3001                 unsigned int len = sg_dma_len(sg);
3002
3003                 /* Scatter gather list entries may cross 64KB boundaries */
3004                 running_total = TRB_MAX_BUFF_SIZE -
3005                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3006                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3007                 if (running_total != 0)
3008                         num_trbs++;
3009
3010                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3011                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3012                         num_trbs++;
3013                         running_total += TRB_MAX_BUFF_SIZE;
3014                 }
3015                 len = min_t(int, len, temp);
3016                 temp -= len;
3017                 if (temp == 0)
3018                         break;
3019         }
3020         return num_trbs;
3021 }
3022
3023 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3024 {
3025         if (num_trbs != 0)
3026                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3027                                 "TRBs, %d left\n", __func__,
3028                                 urb->ep->desc.bEndpointAddress, num_trbs);
3029         if (running_total != urb->transfer_buffer_length)
3030                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3031                                 "queued %#x (%d), asked for %#x (%d)\n",
3032                                 __func__,
3033                                 urb->ep->desc.bEndpointAddress,
3034                                 running_total, running_total,
3035                                 urb->transfer_buffer_length,
3036                                 urb->transfer_buffer_length);
3037 }
3038
3039 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3040                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3041                 struct xhci_generic_trb *start_trb)
3042 {
3043         /*
3044          * Pass all the TRBs to the hardware at once and make sure this write
3045          * isn't reordered.
3046          */
3047         wmb();
3048         if (start_cycle)
3049                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3050         else
3051                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3052         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3053 }
3054
3055 /*
3056  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3057  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3058  * (comprised of sg list entries) can take several service intervals to
3059  * transmit.
3060  */
3061 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3062                 struct urb *urb, int slot_id, unsigned int ep_index)
3063 {
3064         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3065                         xhci->devs[slot_id]->out_ctx, ep_index);
3066         int xhci_interval;
3067         int ep_interval;
3068
3069         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3070         ep_interval = urb->interval;
3071         /* Convert to microframes */
3072         if (urb->dev->speed == USB_SPEED_LOW ||
3073                         urb->dev->speed == USB_SPEED_FULL)
3074                 ep_interval *= 8;
3075         /* FIXME change this to a warning and a suggestion to use the new API
3076          * to set the polling interval (once the API is added).
3077          */
3078         if (xhci_interval != ep_interval) {
3079                 if (printk_ratelimit())
3080                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3081                                         " (%d microframe%s) than xHCI "
3082                                         "(%d microframe%s)\n",
3083                                         ep_interval,
3084                                         ep_interval == 1 ? "" : "s",
3085                                         xhci_interval,
3086                                         xhci_interval == 1 ? "" : "s");
3087                 urb->interval = xhci_interval;
3088                 /* Convert back to frames for LS/FS devices */
3089                 if (urb->dev->speed == USB_SPEED_LOW ||
3090                                 urb->dev->speed == USB_SPEED_FULL)
3091                         urb->interval /= 8;
3092         }
3093         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3094 }
3095
3096 /*
3097  * The TD size is the number of bytes remaining in the TD (including this TRB),
3098  * right shifted by 10.
3099  * It must fit in bits 21:17, so it can't be bigger than 31.
3100  */
3101 static u32 xhci_td_remainder(unsigned int remainder)
3102 {
3103         u32 max = (1 << (21 - 17 + 1)) - 1;
3104
3105         if ((remainder >> 10) >= max)
3106                 return max << 17;
3107         else
3108                 return (remainder >> 10) << 17;
3109 }
3110
3111 /*
3112  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3113  * packets remaining in the TD (*not* including this TRB).
3114  *
3115  * Total TD packet count = total_packet_count =
3116  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3117  *
3118  * Packets transferred up to and including this TRB = packets_transferred =
3119  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3120  *
3121  * TD size = total_packet_count - packets_transferred
3122  *
3123  * It must fit in bits 21:17, so it can't be bigger than 31.
3124  * The last TRB in a TD must have the TD size set to zero.
3125  */
3126 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3127                 unsigned int total_packet_count, struct urb *urb,
3128                 unsigned int num_trbs_left)
3129 {
3130         int packets_transferred;
3131
3132         /* One TRB with a zero-length data packet. */
3133         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3134                 return 0;
3135
3136         /* All the TRB queueing functions don't count the current TRB in
3137          * running_total.
3138          */
3139         packets_transferred = (running_total + trb_buff_len) /
3140                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3141
3142         if ((total_packet_count - packets_transferred) > 31)
3143                 return 31 << 17;
3144         return (total_packet_count - packets_transferred) << 17;
3145 }
3146
3147 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3148                 struct urb *urb, int slot_id, unsigned int ep_index)
3149 {
3150         struct xhci_ring *ep_ring;
3151         unsigned int num_trbs;
3152         struct urb_priv *urb_priv;
3153         struct xhci_td *td;
3154         struct scatterlist *sg;
3155         int num_sgs;
3156         int trb_buff_len, this_sg_len, running_total;
3157         unsigned int total_packet_count;
3158         bool first_trb;
3159         u64 addr;
3160         bool more_trbs_coming;
3161
3162         struct xhci_generic_trb *start_trb;
3163         int start_cycle;
3164
3165         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3166         if (!ep_ring)
3167                 return -EINVAL;
3168
3169         num_trbs = count_sg_trbs_needed(xhci, urb);
3170         num_sgs = urb->num_mapped_sgs;
3171         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3172                         usb_endpoint_maxp(&urb->ep->desc));
3173
3174         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3175                         ep_index, urb->stream_id,
3176                         num_trbs, urb, 0, mem_flags);
3177         if (trb_buff_len < 0)
3178                 return trb_buff_len;
3179
3180         urb_priv = urb->hcpriv;
3181         td = urb_priv->td[0];
3182
3183         /*
3184          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3185          * until we've finished creating all the other TRBs.  The ring's cycle
3186          * state may change as we enqueue the other TRBs, so save it too.
3187          */
3188         start_trb = &ep_ring->enqueue->generic;
3189         start_cycle = ep_ring->cycle_state;
3190
3191         running_total = 0;
3192         /*
3193          * How much data is in the first TRB?
3194          *
3195          * There are three forces at work for TRB buffer pointers and lengths:
3196          * 1. We don't want to walk off the end of this sg-list entry buffer.
3197          * 2. The transfer length that the driver requested may be smaller than
3198          *    the amount of memory allocated for this scatter-gather list.
3199          * 3. TRBs buffers can't cross 64KB boundaries.
3200          */
3201         sg = urb->sg;
3202         addr = (u64) sg_dma_address(sg);
3203         this_sg_len = sg_dma_len(sg);
3204         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3205         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3206         if (trb_buff_len > urb->transfer_buffer_length)
3207                 trb_buff_len = urb->transfer_buffer_length;
3208
3209         first_trb = true;
3210         /* Queue the first TRB, even if it's zero-length */
3211         do {
3212                 u32 field = 0;
3213                 u32 length_field = 0;
3214                 u32 remainder = 0;
3215
3216                 /* Don't change the cycle bit of the first TRB until later */
3217                 if (first_trb) {
3218                         first_trb = false;
3219                         if (start_cycle == 0)
3220                                 field |= 0x1;
3221                 } else
3222                         field |= ep_ring->cycle_state;
3223
3224                 /* Chain all the TRBs together; clear the chain bit in the last
3225                  * TRB to indicate it's the last TRB in the chain.
3226                  */
3227                 if (num_trbs > 1) {
3228                         field |= TRB_CHAIN;
3229                 } else {
3230                         /* FIXME - add check for ZERO_PACKET flag before this */
3231                         td->last_trb = ep_ring->enqueue;
3232                         field |= TRB_IOC;
3233                 }
3234
3235                 /* Only set interrupt on short packet for IN endpoints */
3236                 if (usb_urb_dir_in(urb))
3237                         field |= TRB_ISP;
3238
3239                 if (TRB_MAX_BUFF_SIZE -
3240                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3241                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3242                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3243                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3244                                         (unsigned int) addr + trb_buff_len);
3245                 }
3246
3247                 /* Set the TRB length, TD size, and interrupter fields. */
3248                 if (xhci->hci_version < 0x100) {
3249                         remainder = xhci_td_remainder(
3250                                         urb->transfer_buffer_length -
3251                                         running_total);
3252                 } else {
3253                         remainder = xhci_v1_0_td_remainder(running_total,
3254                                         trb_buff_len, total_packet_count, urb,
3255                                         num_trbs - 1);
3256                 }
3257                 length_field = TRB_LEN(trb_buff_len) |
3258                         remainder |
3259                         TRB_INTR_TARGET(0);
3260
3261                 if (num_trbs > 1)
3262                         more_trbs_coming = true;
3263                 else
3264                         more_trbs_coming = false;
3265                 queue_trb(xhci, ep_ring, more_trbs_coming,
3266                                 lower_32_bits(addr),
3267                                 upper_32_bits(addr),
3268                                 length_field,
3269                                 field | TRB_TYPE(TRB_NORMAL));
3270                 --num_trbs;
3271                 running_total += trb_buff_len;
3272
3273                 /* Calculate length for next transfer --
3274                  * Are we done queueing all the TRBs for this sg entry?
3275                  */
3276                 this_sg_len -= trb_buff_len;
3277                 if (this_sg_len == 0) {
3278                         --num_sgs;
3279                         if (num_sgs == 0)
3280                                 break;
3281                         sg = sg_next(sg);
3282                         addr = (u64) sg_dma_address(sg);
3283                         this_sg_len = sg_dma_len(sg);
3284                 } else {
3285                         addr += trb_buff_len;
3286                 }
3287
3288                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3289                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3290                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3291                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3292                         trb_buff_len =
3293                                 urb->transfer_buffer_length - running_total;
3294         } while (running_total < urb->transfer_buffer_length);
3295
3296         check_trb_math(urb, num_trbs, running_total);
3297         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3298                         start_cycle, start_trb);
3299         return 0;
3300 }
3301
3302 /* This is very similar to what ehci-q.c qtd_fill() does */
3303 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3304                 struct urb *urb, int slot_id, unsigned int ep_index)
3305 {
3306         struct xhci_ring *ep_ring;
3307         struct urb_priv *urb_priv;
3308         struct xhci_td *td;
3309         int num_trbs;
3310         struct xhci_generic_trb *start_trb;
3311         bool first_trb;
3312         bool more_trbs_coming;
3313         int start_cycle;
3314         u32 field, length_field;
3315
3316         int running_total, trb_buff_len, ret;
3317         unsigned int total_packet_count;
3318         u64 addr;
3319
3320         if (urb->num_sgs)
3321                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3322
3323         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3324         if (!ep_ring)
3325                 return -EINVAL;
3326
3327         num_trbs = 0;
3328         /* How much data is (potentially) left before the 64KB boundary? */
3329         running_total = TRB_MAX_BUFF_SIZE -
3330                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3331         running_total &= TRB_MAX_BUFF_SIZE - 1;
3332
3333         /* If there's some data on this 64KB chunk, or we have to send a
3334          * zero-length transfer, we need at least one TRB
3335          */
3336         if (running_total != 0 || urb->transfer_buffer_length == 0)
3337                 num_trbs++;
3338         /* How many more 64KB chunks to transfer, how many more TRBs? */
3339         while (running_total < urb->transfer_buffer_length) {
3340                 num_trbs++;
3341                 running_total += TRB_MAX_BUFF_SIZE;
3342         }
3343         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3344
3345         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3346                         ep_index, urb->stream_id,
3347                         num_trbs, urb, 0, mem_flags);
3348         if (ret < 0)
3349                 return ret;
3350
3351         urb_priv = urb->hcpriv;
3352         td = urb_priv->td[0];
3353
3354         /*
3355          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3356          * until we've finished creating all the other TRBs.  The ring's cycle
3357          * state may change as we enqueue the other TRBs, so save it too.
3358          */
3359         start_trb = &ep_ring->enqueue->generic;
3360         start_cycle = ep_ring->cycle_state;
3361
3362         running_total = 0;
3363         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3364                         usb_endpoint_maxp(&urb->ep->desc));
3365         /* How much data is in the first TRB? */
3366         addr = (u64) urb->transfer_dma;
3367         trb_buff_len = TRB_MAX_BUFF_SIZE -
3368                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3369         if (trb_buff_len > urb->transfer_buffer_length)
3370                 trb_buff_len = urb->transfer_buffer_length;
3371
3372         first_trb = true;
3373
3374         /* Queue the first TRB, even if it's zero-length */
3375         do {
3376                 u32 remainder = 0;
3377                 field = 0;
3378
3379                 /* Don't change the cycle bit of the first TRB until later */
3380                 if (first_trb) {
3381                         first_trb = false;
3382                         if (start_cycle == 0)
3383                                 field |= 0x1;
3384                 } else
3385                         field |= ep_ring->cycle_state;
3386
3387                 /* Chain all the TRBs together; clear the chain bit in the last
3388                  * TRB to indicate it's the last TRB in the chain.
3389                  */
3390                 if (num_trbs > 1) {
3391                         field |= TRB_CHAIN;
3392                 } else {
3393                         /* FIXME - add check for ZERO_PACKET flag before this */
3394                         td->last_trb = ep_ring->enqueue;
3395                         field |= TRB_IOC;
3396                 }
3397
3398                 /* Only set interrupt on short packet for IN endpoints */
3399                 if (usb_urb_dir_in(urb))
3400                         field |= TRB_ISP;
3401
3402                 /* Set the TRB length, TD size, and interrupter fields. */
3403                 if (xhci->hci_version < 0x100) {
3404                         remainder = xhci_td_remainder(
3405                                         urb->transfer_buffer_length -
3406                                         running_total);
3407                 } else {
3408                         remainder = xhci_v1_0_td_remainder(running_total,
3409                                         trb_buff_len, total_packet_count, urb,
3410                                         num_trbs - 1);
3411                 }
3412                 length_field = TRB_LEN(trb_buff_len) |
3413                         remainder |
3414                         TRB_INTR_TARGET(0);
3415
3416                 if (num_trbs > 1)
3417                         more_trbs_coming = true;
3418                 else
3419                         more_trbs_coming = false;
3420                 queue_trb(xhci, ep_ring, more_trbs_coming,
3421                                 lower_32_bits(addr),
3422                                 upper_32_bits(addr),
3423                                 length_field,
3424                                 field | TRB_TYPE(TRB_NORMAL));
3425                 --num_trbs;
3426                 running_total += trb_buff_len;
3427
3428                 /* Calculate length for next transfer */
3429                 addr += trb_buff_len;
3430                 trb_buff_len = urb->transfer_buffer_length - running_total;
3431                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3432                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3433         } while (running_total < urb->transfer_buffer_length);
3434
3435         check_trb_math(urb, num_trbs, running_total);
3436         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3437                         start_cycle, start_trb);
3438         return 0;
3439 }
3440
3441 /* Caller must have locked xhci->lock */
3442 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3443                 struct urb *urb, int slot_id, unsigned int ep_index)
3444 {
3445         struct xhci_ring *ep_ring;
3446         int num_trbs;
3447         int ret;
3448         struct usb_ctrlrequest *setup;
3449         struct xhci_generic_trb *start_trb;
3450         int start_cycle;
3451         u32 field, length_field;
3452         struct urb_priv *urb_priv;
3453         struct xhci_td *td;
3454
3455         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3456         if (!ep_ring)
3457                 return -EINVAL;
3458
3459         /*
3460          * Need to copy setup packet into setup TRB, so we can't use the setup
3461          * DMA address.
3462          */
3463         if (!urb->setup_packet)
3464                 return -EINVAL;
3465
3466         /* 1 TRB for setup, 1 for status */
3467         num_trbs = 2;
3468         /*
3469          * Don't need to check if we need additional event data and normal TRBs,
3470          * since data in control transfers will never get bigger than 16MB
3471          * XXX: can we get a buffer that crosses 64KB boundaries?
3472          */
3473         if (urb->transfer_buffer_length > 0)
3474                 num_trbs++;
3475         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3476                         ep_index, urb->stream_id,
3477                         num_trbs, urb, 0, mem_flags);
3478         if (ret < 0)
3479                 return ret;
3480
3481         urb_priv = urb->hcpriv;
3482         td = urb_priv->td[0];
3483
3484         /*
3485          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3486          * until we've finished creating all the other TRBs.  The ring's cycle
3487          * state may change as we enqueue the other TRBs, so save it too.
3488          */
3489         start_trb = &ep_ring->enqueue->generic;
3490         start_cycle = ep_ring->cycle_state;
3491
3492         /* Queue setup TRB - see section 6.4.1.2.1 */
3493         /* FIXME better way to translate setup_packet into two u32 fields? */
3494         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3495         field = 0;
3496         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3497         if (start_cycle == 0)
3498                 field |= 0x1;
3499
3500         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3501         if (xhci->hci_version == 0x100) {
3502                 if (urb->transfer_buffer_length > 0) {
3503                         if (setup->bRequestType & USB_DIR_IN)
3504                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3505                         else
3506                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3507                 }
3508         }
3509
3510         queue_trb(xhci, ep_ring, true,
3511                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3512                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3513                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3514                   /* Immediate data in pointer */
3515                   field);
3516
3517         /* If there's data, queue data TRBs */
3518         /* Only set interrupt on short packet for IN endpoints */
3519         if (usb_urb_dir_in(urb))
3520                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3521         else
3522                 field = TRB_TYPE(TRB_DATA);
3523
3524         length_field = TRB_LEN(urb->transfer_buffer_length) |
3525                 xhci_td_remainder(urb->transfer_buffer_length) |
3526                 TRB_INTR_TARGET(0);
3527         if (urb->transfer_buffer_length > 0) {
3528                 if (setup->bRequestType & USB_DIR_IN)
3529                         field |= TRB_DIR_IN;
3530                 queue_trb(xhci, ep_ring, true,
3531                                 lower_32_bits(urb->transfer_dma),
3532                                 upper_32_bits(urb->transfer_dma),
3533                                 length_field,
3534                                 field | ep_ring->cycle_state);
3535         }
3536
3537         /* Save the DMA address of the last TRB in the TD */
3538         td->last_trb = ep_ring->enqueue;
3539
3540         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3541         /* If the device sent data, the status stage is an OUT transfer */
3542         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3543                 field = 0;
3544         else
3545                 field = TRB_DIR_IN;
3546         queue_trb(xhci, ep_ring, false,
3547                         0,
3548                         0,
3549                         TRB_INTR_TARGET(0),
3550                         /* Event on completion */
3551                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3552
3553         giveback_first_trb(xhci, slot_id, ep_index, 0,
3554                         start_cycle, start_trb);
3555         return 0;
3556 }
3557
3558 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3559                 struct urb *urb, int i)
3560 {
3561         int num_trbs = 0;
3562         u64 addr, td_len;
3563
3564         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3565         td_len = urb->iso_frame_desc[i].length;
3566
3567         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3568                         TRB_MAX_BUFF_SIZE);
3569         if (num_trbs == 0)
3570                 num_trbs++;
3571
3572         return num_trbs;
3573 }
3574
3575 /*
3576  * The transfer burst count field of the isochronous TRB defines the number of
3577  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3578  * devices can burst up to bMaxBurst number of packets per service interval.
3579  * This field is zero based, meaning a value of zero in the field means one
3580  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3581  * zero.  Only xHCI 1.0 host controllers support this field.
3582  */
3583 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3584                 struct usb_device *udev,
3585                 struct urb *urb, unsigned int total_packet_count)
3586 {
3587         unsigned int max_burst;
3588
3589         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3590                 return 0;
3591
3592         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3593         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3594 }
3595
3596 /*
3597  * Returns the number of packets in the last "burst" of packets.  This field is
3598  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3599  * the last burst packet count is equal to the total number of packets in the
3600  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3601  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3602  * contain 1 to (bMaxBurst + 1) packets.
3603  */
3604 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3605                 struct usb_device *udev,
3606                 struct urb *urb, unsigned int total_packet_count)
3607 {
3608         unsigned int max_burst;
3609         unsigned int residue;
3610
3611         if (xhci->hci_version < 0x100)
3612                 return 0;
3613
3614         switch (udev->speed) {
3615         case USB_SPEED_SUPER:
3616                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3617                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3618                 residue = total_packet_count % (max_burst + 1);
3619                 /* If residue is zero, the last burst contains (max_burst + 1)
3620                  * number of packets, but the TLBPC field is zero-based.
3621                  */
3622                 if (residue == 0)
3623                         return max_burst;
3624                 return residue - 1;
3625         default:
3626                 if (total_packet_count == 0)
3627                         return 0;
3628                 return total_packet_count - 1;
3629         }
3630 }
3631
3632 /* This is for isoc transfer */
3633 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3634                 struct urb *urb, int slot_id, unsigned int ep_index)
3635 {
3636         struct xhci_ring *ep_ring;
3637         struct urb_priv *urb_priv;
3638         struct xhci_td *td;
3639         int num_tds, trbs_per_td;
3640         struct xhci_generic_trb *start_trb;
3641         bool first_trb;
3642         int start_cycle;
3643         u32 field, length_field;
3644         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3645         u64 start_addr, addr;
3646         int i, j;
3647         bool more_trbs_coming;
3648
3649         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3650
3651         num_tds = urb->number_of_packets;
3652         if (num_tds < 1) {
3653                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3654                 return -EINVAL;
3655         }
3656
3657         start_addr = (u64) urb->transfer_dma;
3658         start_trb = &ep_ring->enqueue->generic;
3659         start_cycle = ep_ring->cycle_state;
3660
3661         urb_priv = urb->hcpriv;
3662         /* Queue the first TRB, even if it's zero-length */
3663         for (i = 0; i < num_tds; i++) {
3664                 unsigned int total_packet_count;
3665                 unsigned int burst_count;
3666                 unsigned int residue;
3667
3668                 first_trb = true;
3669                 running_total = 0;
3670                 addr = start_addr + urb->iso_frame_desc[i].offset;
3671                 td_len = urb->iso_frame_desc[i].length;
3672                 td_remain_len = td_len;
3673                 total_packet_count = DIV_ROUND_UP(td_len,
3674                                 GET_MAX_PACKET(
3675                                         usb_endpoint_maxp(&urb->ep->desc)));
3676                 /* A zero-length transfer still involves at least one packet. */
3677                 if (total_packet_count == 0)
3678                         total_packet_count++;
3679                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3680                                 total_packet_count);
3681                 residue = xhci_get_last_burst_packet_count(xhci,
3682                                 urb->dev, urb, total_packet_count);
3683
3684                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3685
3686                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3687                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3688                 if (ret < 0) {
3689                         if (i == 0)
3690                                 return ret;
3691                         goto cleanup;
3692                 }
3693
3694                 td = urb_priv->td[i];
3695                 for (j = 0; j < trbs_per_td; j++) {
3696                         u32 remainder = 0;
3697                         field = 0;
3698
3699                         if (first_trb) {
3700                                 field = TRB_TBC(burst_count) |
3701                                         TRB_TLBPC(residue);
3702                                 /* Queue the isoc TRB */
3703                                 field |= TRB_TYPE(TRB_ISOC);
3704                                 /* Assume URB_ISO_ASAP is set */
3705                                 field |= TRB_SIA;
3706                                 if (i == 0) {
3707                                         if (start_cycle == 0)
3708                                                 field |= 0x1;
3709                                 } else
3710                                         field |= ep_ring->cycle_state;
3711                                 first_trb = false;
3712                         } else {
3713                                 /* Queue other normal TRBs */
3714                                 field |= TRB_TYPE(TRB_NORMAL);
3715                                 field |= ep_ring->cycle_state;
3716                         }
3717
3718                         /* Only set interrupt on short packet for IN EPs */
3719                         if (usb_urb_dir_in(urb))
3720                                 field |= TRB_ISP;
3721
3722                         /* Chain all the TRBs together; clear the chain bit in
3723                          * the last TRB to indicate it's the last TRB in the
3724                          * chain.
3725                          */
3726                         if (j < trbs_per_td - 1) {
3727                                 field |= TRB_CHAIN;
3728                                 more_trbs_coming = true;
3729                         } else {
3730                                 td->last_trb = ep_ring->enqueue;
3731                                 field |= TRB_IOC;
3732                                 if (xhci->hci_version == 0x100 &&
3733                                                 !(xhci->quirks &
3734                                                         XHCI_AVOID_BEI)) {
3735                                         /* Set BEI bit except for the last td */
3736                                         if (i < num_tds - 1)
3737                                                 field |= TRB_BEI;
3738                                 }
3739                                 more_trbs_coming = false;
3740                         }
3741
3742                         /* Calculate TRB length */
3743                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3744                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3745                         if (trb_buff_len > td_remain_len)
3746                                 trb_buff_len = td_remain_len;
3747
3748                         /* Set the TRB length, TD size, & interrupter fields. */
3749                         if (xhci->hci_version < 0x100) {
3750                                 remainder = xhci_td_remainder(
3751                                                 td_len - running_total);
3752                         } else {
3753                                 remainder = xhci_v1_0_td_remainder(
3754                                                 running_total, trb_buff_len,
3755                                                 total_packet_count, urb,
3756                                                 (trbs_per_td - j - 1));
3757                         }
3758                         length_field = TRB_LEN(trb_buff_len) |
3759                                 remainder |
3760                                 TRB_INTR_TARGET(0);
3761
3762                         queue_trb(xhci, ep_ring, more_trbs_coming,
3763                                 lower_32_bits(addr),
3764                                 upper_32_bits(addr),
3765                                 length_field,
3766                                 field);
3767                         running_total += trb_buff_len;
3768
3769                         addr += trb_buff_len;
3770                         td_remain_len -= trb_buff_len;
3771                 }
3772
3773                 /* Check TD length */
3774                 if (running_total != td_len) {
3775                         xhci_err(xhci, "ISOC TD length unmatch\n");
3776                         ret = -EINVAL;
3777                         goto cleanup;
3778                 }
3779         }
3780
3781         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3782                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3783                         usb_amd_quirk_pll_disable();
3784         }
3785         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3786
3787         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3788                         start_cycle, start_trb);
3789         return 0;
3790 cleanup:
3791         /* Clean up a partially enqueued isoc transfer. */
3792
3793         for (i--; i >= 0; i--)
3794                 list_del_init(&urb_priv->td[i]->td_list);
3795
3796         /* Use the first TD as a temporary variable to turn the TDs we've queued
3797          * into No-ops with a software-owned cycle bit. That way the hardware
3798          * won't accidentally start executing bogus TDs when we partially
3799          * overwrite them.  td->first_trb and td->start_seg are already set.
3800          */
3801         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3802         /* Every TRB except the first & last will have its cycle bit flipped. */
3803         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3804
3805         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3806         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3807         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3808         ep_ring->cycle_state = start_cycle;
3809         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3810         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3811         return ret;
3812 }
3813
3814 /*
3815  * Check transfer ring to guarantee there is enough room for the urb.
3816  * Update ISO URB start_frame and interval.
3817  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3818  * update the urb->start_frame by now.
3819  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3820  */
3821 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3822                 struct urb *urb, int slot_id, unsigned int ep_index)
3823 {
3824         struct xhci_virt_device *xdev;
3825         struct xhci_ring *ep_ring;
3826         struct xhci_ep_ctx *ep_ctx;
3827         int start_frame;
3828         int xhci_interval;
3829         int ep_interval;
3830         int num_tds, num_trbs, i;
3831         int ret;
3832
3833         xdev = xhci->devs[slot_id];
3834         ep_ring = xdev->eps[ep_index].ring;
3835         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3836
3837         num_trbs = 0;
3838         num_tds = urb->number_of_packets;
3839         for (i = 0; i < num_tds; i++)
3840                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3841
3842         /* Check the ring to guarantee there is enough room for the whole urb.
3843          * Do not insert any td of the urb to the ring if the check failed.
3844          */
3845         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3846                            num_trbs, mem_flags);
3847         if (ret)
3848                 return ret;
3849
3850         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3851         start_frame &= 0x3fff;
3852
3853         urb->start_frame = start_frame;
3854         if (urb->dev->speed == USB_SPEED_LOW ||
3855                         urb->dev->speed == USB_SPEED_FULL)
3856                 urb->start_frame >>= 3;
3857
3858         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3859         ep_interval = urb->interval;
3860         /* Convert to microframes */
3861         if (urb->dev->speed == USB_SPEED_LOW ||
3862                         urb->dev->speed == USB_SPEED_FULL)
3863                 ep_interval *= 8;
3864         /* FIXME change this to a warning and a suggestion to use the new API
3865          * to set the polling interval (once the API is added).
3866          */
3867         if (xhci_interval != ep_interval) {
3868                 if (printk_ratelimit())
3869                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3870                                         " (%d microframe%s) than xHCI "
3871                                         "(%d microframe%s)\n",
3872                                         ep_interval,
3873                                         ep_interval == 1 ? "" : "s",
3874                                         xhci_interval,
3875                                         xhci_interval == 1 ? "" : "s");
3876                 urb->interval = xhci_interval;
3877                 /* Convert back to frames for LS/FS devices */
3878                 if (urb->dev->speed == USB_SPEED_LOW ||
3879                                 urb->dev->speed == USB_SPEED_FULL)
3880                         urb->interval /= 8;
3881         }
3882         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3883
3884         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3885 }
3886
3887 /****           Command Ring Operations         ****/
3888
3889 /* Generic function for queueing a command TRB on the command ring.
3890  * Check to make sure there's room on the command ring for one command TRB.
3891  * Also check that there's room reserved for commands that must not fail.
3892  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3893  * then only check for the number of reserved spots.
3894  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3895  * because the command event handler may want to resubmit a failed command.
3896  */
3897 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3898                 u32 field3, u32 field4, bool command_must_succeed)
3899 {
3900         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3901         int ret;
3902
3903         if (!command_must_succeed)
3904                 reserved_trbs++;
3905
3906         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3907                         reserved_trbs, GFP_ATOMIC);
3908         if (ret < 0) {
3909                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3910                 if (command_must_succeed)
3911                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3912                                         "unfailable commands failed.\n");
3913                 return ret;
3914         }
3915         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3916                         field4 | xhci->cmd_ring->cycle_state);
3917         return 0;
3918 }
3919
3920 /* Queue a slot enable or disable request on the command ring */
3921 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3922 {
3923         return queue_command(xhci, 0, 0, 0,
3924                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3925 }
3926
3927 /* Queue an address device command TRB */
3928 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3929                 u32 slot_id)
3930 {
3931         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3932                         upper_32_bits(in_ctx_ptr), 0,
3933                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3934                         false);
3935 }
3936
3937 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3938                 u32 field1, u32 field2, u32 field3, u32 field4)
3939 {
3940         return queue_command(xhci, field1, field2, field3, field4, false);
3941 }
3942
3943 /* Queue a reset device command TRB */
3944 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3945 {
3946         return queue_command(xhci, 0, 0, 0,
3947                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3948                         false);
3949 }
3950
3951 /* Queue a configure endpoint command TRB */
3952 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3953                 u32 slot_id, bool command_must_succeed)
3954 {
3955         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3956                         upper_32_bits(in_ctx_ptr), 0,
3957                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3958                         command_must_succeed);
3959 }
3960
3961 /* Queue an evaluate context command TRB */
3962 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3963                 u32 slot_id, bool command_must_succeed)
3964 {
3965         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3966                         upper_32_bits(in_ctx_ptr), 0,
3967                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3968                         command_must_succeed);
3969 }
3970
3971 /*
3972  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3973  * activity on an endpoint that is about to be suspended.
3974  */
3975 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3976                 unsigned int ep_index, int suspend)
3977 {
3978         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3979         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3980         u32 type = TRB_TYPE(TRB_STOP_RING);
3981         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3982
3983         return queue_command(xhci, 0, 0, 0,
3984                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3985 }
3986
3987 /* Set Transfer Ring Dequeue Pointer command.
3988  * This should not be used for endpoints that have streams enabled.
3989  */
3990 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3991                 unsigned int ep_index, unsigned int stream_id,
3992                 struct xhci_segment *deq_seg,
3993                 union xhci_trb *deq_ptr, u32 cycle_state)
3994 {
3995         dma_addr_t addr;
3996         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3997         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3998         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3999         u32 type = TRB_TYPE(TRB_SET_DEQ);
4000         struct xhci_virt_ep *ep;
4001
4002         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4003         if (addr == 0) {
4004                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4005                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4006                                 deq_seg, deq_ptr);
4007                 return 0;
4008         }
4009         ep = &xhci->devs[slot_id]->eps[ep_index];
4010         if ((ep->ep_state & SET_DEQ_PENDING)) {
4011                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4012                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4013                 return 0;
4014         }
4015         ep->queued_deq_seg = deq_seg;
4016         ep->queued_deq_ptr = deq_ptr;
4017         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4018                         upper_32_bits(addr), trb_stream_id,
4019                         trb_slot_id | trb_ep_index | type, false);
4020 }
4021
4022 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4023                 unsigned int ep_index)
4024 {
4025         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4026         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4027         u32 type = TRB_TYPE(TRB_RESET_EP);
4028
4029         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4030                         false);
4031 }