2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset > TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state ^= 1;
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 xhci_err(xhci, "Stopped the command ring failed, "
306 "maybe the host is dead\n");
307 xhci->xhc_state |= XHCI_STATE_DYING;
316 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
317 unsigned int slot_id,
318 unsigned int ep_index,
319 unsigned int stream_id)
321 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
323 unsigned int ep_state = ep->ep_state;
325 /* Don't ring the doorbell for this endpoint if there are pending
326 * cancellations because we don't want to interrupt processing.
327 * We don't want to restart any stream rings if there's a set dequeue
328 * pointer command pending because the device can choose to start any
329 * stream once the endpoint is on the HW schedule.
331 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
332 (ep_state & EP_HALTED))
334 writel(DB_VALUE(ep_index, stream_id), db_addr);
335 /* The CPU has better things to do at this point than wait for a
336 * write-posting flush. It'll get there soon enough.
340 /* Ring the doorbell for any rings with pending URBs */
341 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
342 unsigned int slot_id,
343 unsigned int ep_index)
345 unsigned int stream_id;
346 struct xhci_virt_ep *ep;
348 ep = &xhci->devs[slot_id]->eps[ep_index];
350 /* A ring has pending URBs if its TD list is not empty */
351 if (!(ep->ep_state & EP_HAS_STREAMS)) {
352 if (ep->ring && !(list_empty(&ep->ring->td_list)))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
357 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
359 struct xhci_stream_info *stream_info = ep->stream_info;
360 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
361 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
366 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
367 unsigned int slot_id, unsigned int ep_index,
368 unsigned int stream_id)
370 struct xhci_virt_ep *ep;
372 ep = &xhci->devs[slot_id]->eps[ep_index];
373 /* Common case: no streams */
374 if (!(ep->ep_state & EP_HAS_STREAMS))
377 if (stream_id == 0) {
379 "WARN: Slot ID %u, ep index %u has streams, "
380 "but URB has no stream ID.\n",
385 if (stream_id < ep->stream_info->num_streams)
386 return ep->stream_info->stream_rings[stream_id];
389 "WARN: Slot ID %u, ep index %u has "
390 "stream IDs 1 to %u allocated, "
391 "but stream ID %u is requested.\n",
393 ep->stream_info->num_streams - 1,
398 /* Get the right ring for the given URB.
399 * If the endpoint supports streams, boundary check the URB's stream ID.
400 * If the endpoint doesn't support streams, return the singular endpoint ring.
402 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
405 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
406 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
410 * Move the xHC's endpoint ring dequeue pointer past cur_td.
411 * Record the new state of the xHC's endpoint ring dequeue segment,
412 * dequeue pointer, and new consumer cycle state in state.
413 * Update our internal representation of the ring's dequeue pointer.
415 * We do this in three jumps:
416 * - First we update our new ring state to be the same as when the xHC stopped.
417 * - Then we traverse the ring to find the segment that contains
418 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
419 * any link TRBs with the toggle cycle bit set.
420 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
421 * if we've moved it past a link TRB with the toggle cycle bit set.
423 * Some of the uses of xhci_generic_trb are grotty, but if they're done
424 * with correct __le32 accesses they should work fine. Only users of this are
427 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
428 unsigned int slot_id, unsigned int ep_index,
429 unsigned int stream_id, struct xhci_td *cur_td,
430 struct xhci_dequeue_state *state)
432 struct xhci_virt_device *dev = xhci->devs[slot_id];
433 struct xhci_virt_ep *ep = &dev->eps[ep_index];
434 struct xhci_ring *ep_ring;
435 struct xhci_segment *new_seg;
436 union xhci_trb *new_deq;
439 bool cycle_found = false;
440 bool td_last_trb_found = false;
442 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
443 ep_index, stream_id);
445 xhci_warn(xhci, "WARN can't find new dequeue state "
446 "for invalid stream ID %u.\n",
451 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
452 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
453 "Finding endpoint context");
454 /* 4.6.9 the css flag is written to the stream context for streams */
455 if (ep->ep_state & EP_HAS_STREAMS) {
456 struct xhci_stream_ctx *ctx =
457 &ep->stream_info->stream_ctx_array[stream_id];
458 hw_dequeue = le64_to_cpu(ctx->stream_ring);
460 struct xhci_ep_ctx *ep_ctx
461 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
462 hw_dequeue = le64_to_cpu(ep_ctx->deq);
465 new_seg = ep_ring->deq_seg;
466 new_deq = ep_ring->dequeue;
467 state->new_cycle_state = hw_dequeue & 0x1;
470 * We want to find the pointer, segment and cycle state of the new trb
471 * (the one after current TD's last_trb). We know the cycle state at
472 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
476 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
477 == (dma_addr_t)(hw_dequeue & ~0xf)) {
479 if (td_last_trb_found)
482 if (new_deq == cur_td->last_trb)
483 td_last_trb_found = true;
486 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
487 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
488 state->new_cycle_state ^= 0x1;
490 next_trb(xhci, ep_ring, &new_seg, &new_deq);
492 /* Search wrapped around, bail out */
493 if (new_deq == ep->ring->dequeue) {
494 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
495 state->new_deq_seg = NULL;
496 state->new_deq_ptr = NULL;
500 } while (!cycle_found || !td_last_trb_found);
502 state->new_deq_seg = new_seg;
503 state->new_deq_ptr = new_deq;
505 /* Don't update the ring cycle state for the producer (us). */
506 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
507 "Cycle state = 0x%x", state->new_cycle_state);
509 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
510 "New dequeue segment = %p (virtual)",
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
514 "New dequeue pointer = 0x%llx (DMA)",
515 (unsigned long long) addr);
518 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
519 * (The last TRB actually points to the ring enqueue pointer, which is not part
520 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
522 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
523 struct xhci_td *cur_td, bool flip_cycle)
525 struct xhci_segment *cur_seg;
526 union xhci_trb *cur_trb;
528 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
530 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
531 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
532 /* Unchain any chained Link TRBs, but
533 * leave the pointers intact.
535 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
536 /* Flip the cycle bit (link TRBs can't be the first
540 cur_trb->generic.field[3] ^=
541 cpu_to_le32(TRB_CYCLE);
542 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
543 "Cancel (unchain) link TRB");
544 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
545 "Address = %p (0x%llx dma); "
546 "in seg %p (0x%llx dma)",
548 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
550 (unsigned long long)cur_seg->dma);
552 cur_trb->generic.field[0] = 0;
553 cur_trb->generic.field[1] = 0;
554 cur_trb->generic.field[2] = 0;
555 /* Preserve only the cycle bit of this TRB */
556 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
557 /* Flip the cycle bit except on the first or last TRB */
558 if (flip_cycle && cur_trb != cur_td->first_trb &&
559 cur_trb != cur_td->last_trb)
560 cur_trb->generic.field[3] ^=
561 cpu_to_le32(TRB_CYCLE);
562 cur_trb->generic.field[3] |= cpu_to_le32(
563 TRB_TYPE(TRB_TR_NOOP));
564 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
565 "TRB to noop at offset 0x%llx",
567 xhci_trb_virt_to_dma(cur_seg, cur_trb));
569 if (cur_trb == cur_td->last_trb)
574 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
575 struct xhci_virt_ep *ep)
577 ep->ep_state &= ~EP_HALT_PENDING;
578 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
579 * timer is running on another CPU, we don't decrement stop_cmds_pending
580 * (since we didn't successfully stop the watchdog timer).
582 if (del_timer(&ep->stop_cmd_timer))
583 ep->stop_cmds_pending--;
586 /* Must be called with xhci->lock held in interrupt context */
587 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
588 struct xhci_td *cur_td, int status)
592 struct urb_priv *urb_priv;
595 urb_priv = urb->hcpriv;
597 hcd = bus_to_hcd(urb->dev->bus);
599 /* Only giveback urb when this is the last td in urb */
600 if (urb_priv->td_cnt == urb_priv->length) {
601 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
602 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
603 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
604 if (xhci->quirks & XHCI_AMD_PLL_FIX)
605 usb_amd_quirk_pll_enable();
608 usb_hcd_unlink_urb_from_ep(hcd, urb);
610 spin_unlock(&xhci->lock);
611 usb_hcd_giveback_urb(hcd, urb, status);
612 xhci_urb_free_priv(urb_priv);
613 spin_lock(&xhci->lock);
618 * When we get a command completion for a Stop Endpoint Command, we need to
619 * unlink any cancelled TDs from the ring. There are two ways to do that:
621 * 1. If the HW was in the middle of processing the TD that needs to be
622 * cancelled, then we must move the ring's dequeue pointer past the last TRB
623 * in the TD with a Set Dequeue Pointer Command.
624 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
625 * bit cleared) so that the HW will skip over them.
627 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
628 union xhci_trb *trb, struct xhci_event_cmd *event)
630 unsigned int ep_index;
631 struct xhci_ring *ep_ring;
632 struct xhci_virt_ep *ep;
633 struct list_head *entry;
634 struct xhci_td *cur_td = NULL;
635 struct xhci_td *last_unlinked_td;
637 struct xhci_dequeue_state deq_state;
639 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
640 if (!xhci->devs[slot_id])
641 xhci_warn(xhci, "Stop endpoint command "
642 "completion for disabled slot %u\n",
647 memset(&deq_state, 0, sizeof(deq_state));
648 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
649 ep = &xhci->devs[slot_id]->eps[ep_index];
651 if (list_empty(&ep->cancelled_td_list)) {
652 xhci_stop_watchdog_timer_in_irq(xhci, ep);
653 ep->stopped_td = NULL;
654 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
658 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
659 * We have the xHCI lock, so nothing can modify this list until we drop
660 * it. We're also in the event handler, so we can't get re-interrupted
661 * if another Stop Endpoint command completes
663 list_for_each(entry, &ep->cancelled_td_list) {
664 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
665 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
666 "Removing canceled TD starting at 0x%llx (dma).",
667 (unsigned long long)xhci_trb_virt_to_dma(
668 cur_td->start_seg, cur_td->first_trb));
669 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
671 /* This shouldn't happen unless a driver is mucking
672 * with the stream ID after submission. This will
673 * leave the TD on the hardware ring, and the hardware
674 * will try to execute it, and may access a buffer
675 * that has already been freed. In the best case, the
676 * hardware will execute it, and the event handler will
677 * ignore the completion event for that TD, since it was
678 * removed from the td_list for that endpoint. In
679 * short, don't muck with the stream ID after
682 xhci_warn(xhci, "WARN Cancelled URB %p "
683 "has invalid stream ID %u.\n",
685 cur_td->urb->stream_id);
686 goto remove_finished_td;
689 * If we stopped on the TD we need to cancel, then we have to
690 * move the xHC endpoint ring dequeue pointer past this TD.
692 if (cur_td == ep->stopped_td)
693 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
694 cur_td->urb->stream_id,
697 td_to_noop(xhci, ep_ring, cur_td, false);
700 * The event handler won't see a completion for this TD anymore,
701 * so remove it from the endpoint ring's TD list. Keep it in
702 * the cancelled TD list for URB completion later.
704 list_del_init(&cur_td->td_list);
706 last_unlinked_td = cur_td;
707 xhci_stop_watchdog_timer_in_irq(xhci, ep);
709 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
710 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
711 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
712 ep->stopped_td->urb->stream_id, &deq_state);
713 xhci_ring_cmd_db(xhci);
715 /* Otherwise ring the doorbell(s) to restart queued transfers */
716 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
719 ep->stopped_td = NULL;
722 * Drop the lock and complete the URBs in the cancelled TD list.
723 * New TDs to be cancelled might be added to the end of the list before
724 * we can complete all the URBs for the TDs we already unlinked.
725 * So stop when we've completed the URB for the last TD we unlinked.
728 cur_td = list_entry(ep->cancelled_td_list.next,
729 struct xhci_td, cancelled_td_list);
730 list_del_init(&cur_td->cancelled_td_list);
732 /* Clean up the cancelled URB */
733 /* Doesn't matter what we pass for status, since the core will
734 * just overwrite it (because the URB has been unlinked).
736 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
738 /* Stop processing the cancelled list if the watchdog timer is
741 if (xhci->xhc_state & XHCI_STATE_DYING)
743 } while (cur_td != last_unlinked_td);
745 /* Return to the event handler with xhci->lock re-acquired */
748 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
750 struct xhci_td *cur_td;
752 while (!list_empty(&ring->td_list)) {
753 cur_td = list_first_entry(&ring->td_list,
754 struct xhci_td, td_list);
755 list_del_init(&cur_td->td_list);
756 if (!list_empty(&cur_td->cancelled_td_list))
757 list_del_init(&cur_td->cancelled_td_list);
758 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
762 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
763 int slot_id, int ep_index)
765 struct xhci_td *cur_td;
766 struct xhci_virt_ep *ep;
767 struct xhci_ring *ring;
769 ep = &xhci->devs[slot_id]->eps[ep_index];
770 if ((ep->ep_state & EP_HAS_STREAMS) ||
771 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
774 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
776 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
777 "Killing URBs for slot ID %u, ep index %u, stream %u",
778 slot_id, ep_index, stream_id + 1);
779 xhci_kill_ring_urbs(xhci,
780 ep->stream_info->stream_rings[stream_id]);
786 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
787 "Killing URBs for slot ID %u, ep index %u",
789 xhci_kill_ring_urbs(xhci, ring);
791 while (!list_empty(&ep->cancelled_td_list)) {
792 cur_td = list_first_entry(&ep->cancelled_td_list,
793 struct xhci_td, cancelled_td_list);
794 list_del_init(&cur_td->cancelled_td_list);
795 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
799 /* Watchdog timer function for when a stop endpoint command fails to complete.
800 * In this case, we assume the host controller is broken or dying or dead. The
801 * host may still be completing some other events, so we have to be careful to
802 * let the event ring handler and the URB dequeueing/enqueueing functions know
803 * through xhci->state.
805 * The timer may also fire if the host takes a very long time to respond to the
806 * command, and the stop endpoint command completion handler cannot delete the
807 * timer before the timer function is called. Another endpoint cancellation may
808 * sneak in before the timer function can grab the lock, and that may queue
809 * another stop endpoint command and add the timer back. So we cannot use a
810 * simple flag to say whether there is a pending stop endpoint command for a
811 * particular endpoint.
813 * Instead we use a combination of that flag and a counter for the number of
814 * pending stop endpoint commands. If the timer is the tail end of the last
815 * stop endpoint command, and the endpoint's command is still pending, we assume
818 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
820 struct xhci_hcd *xhci;
821 struct xhci_virt_ep *ep;
825 ep = (struct xhci_virt_ep *) arg;
828 spin_lock_irqsave(&xhci->lock, flags);
830 ep->stop_cmds_pending--;
831 if (xhci->xhc_state & XHCI_STATE_DYING) {
832 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
833 "Stop EP timer ran, but another timer marked "
834 "xHCI as DYING, exiting.");
835 spin_unlock_irqrestore(&xhci->lock, flags);
838 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
839 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
840 "Stop EP timer ran, but no command pending, "
842 spin_unlock_irqrestore(&xhci->lock, flags);
846 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
847 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
848 /* Oops, HC is dead or dying or at least not responding to the stop
851 xhci->xhc_state |= XHCI_STATE_DYING;
852 /* Disable interrupts from the host controller and start halting it */
854 spin_unlock_irqrestore(&xhci->lock, flags);
856 ret = xhci_halt(xhci);
858 spin_lock_irqsave(&xhci->lock, flags);
860 /* This is bad; the host is not responding to commands and it's
861 * not allowing itself to be halted. At least interrupts are
862 * disabled. If we call usb_hc_died(), it will attempt to
863 * disconnect all device drivers under this host. Those
864 * disconnect() methods will wait for all URBs to be unlinked,
865 * so we must complete them.
867 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
868 xhci_warn(xhci, "Completing active URBs anyway.\n");
869 /* We could turn all TDs on the rings to no-ops. This won't
870 * help if the host has cached part of the ring, and is slow if
871 * we want to preserve the cycle bit. Skip it and hope the host
872 * doesn't touch the memory.
875 for (i = 0; i < MAX_HC_SLOTS; i++) {
878 for (j = 0; j < 31; j++)
879 xhci_kill_endpoint_urbs(xhci, i, j);
881 spin_unlock_irqrestore(&xhci->lock, flags);
882 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
883 "Calling usb_hc_died()");
884 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
885 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
886 "xHCI host controller is dead.");
890 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
891 struct xhci_virt_device *dev,
892 struct xhci_ring *ep_ring,
893 unsigned int ep_index)
895 union xhci_trb *dequeue_temp;
896 int num_trbs_free_temp;
899 num_trbs_free_temp = ep_ring->num_trbs_free;
900 dequeue_temp = ep_ring->dequeue;
902 /* If we get two back-to-back stalls, and the first stalled transfer
903 * ends just before a link TRB, the dequeue pointer will be left on
904 * the link TRB by the code in the while loop. So we have to update
905 * the dequeue pointer one segment further, or we'll jump off
906 * the segment into la-la-land.
908 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
909 ep_ring->deq_seg = ep_ring->deq_seg->next;
910 ep_ring->dequeue = ep_ring->deq_seg->trbs;
913 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
914 /* We have more usable TRBs */
915 ep_ring->num_trbs_free++;
917 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
919 if (ep_ring->dequeue ==
920 dev->eps[ep_index].queued_deq_ptr)
922 ep_ring->deq_seg = ep_ring->deq_seg->next;
923 ep_ring->dequeue = ep_ring->deq_seg->trbs;
925 if (ep_ring->dequeue == dequeue_temp) {
932 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
933 ep_ring->num_trbs_free = num_trbs_free_temp;
938 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
939 * we need to clear the set deq pending flag in the endpoint ring state, so that
940 * the TD queueing code can ring the doorbell again. We also need to ring the
941 * endpoint doorbell to restart the ring, but only if there aren't more
942 * cancellations pending.
944 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
945 union xhci_trb *trb, u32 cmd_comp_code)
947 unsigned int ep_index;
948 unsigned int stream_id;
949 struct xhci_ring *ep_ring;
950 struct xhci_virt_device *dev;
951 struct xhci_virt_ep *ep;
952 struct xhci_ep_ctx *ep_ctx;
953 struct xhci_slot_ctx *slot_ctx;
955 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
956 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
957 dev = xhci->devs[slot_id];
958 ep = &dev->eps[ep_index];
960 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
962 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
964 /* XXX: Harmless??? */
968 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
969 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
971 if (cmd_comp_code != COMP_SUCCESS) {
972 unsigned int ep_state;
973 unsigned int slot_state;
975 switch (cmd_comp_code) {
977 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
980 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
981 ep_state = le32_to_cpu(ep_ctx->ep_info);
982 ep_state &= EP_STATE_MASK;
983 slot_state = le32_to_cpu(slot_ctx->dev_state);
984 slot_state = GET_SLOT_STATE(slot_state);
985 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
986 "Slot state = %u, EP state = %u",
987 slot_state, ep_state);
990 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
994 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
998 /* OK what do we do now? The endpoint state is hosed, and we
999 * should never get to this point if the synchronization between
1000 * queueing, and endpoint state are correct. This might happen
1001 * if the device gets disconnected after we've finished
1002 * cancelling URBs, which might not be an error...
1006 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1007 if (ep->ep_state & EP_HAS_STREAMS) {
1008 struct xhci_stream_ctx *ctx =
1009 &ep->stream_info->stream_ctx_array[stream_id];
1010 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1012 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1014 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1015 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1016 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1017 ep->queued_deq_ptr) == deq) {
1018 /* Update the ring's dequeue segment and dequeue pointer
1019 * to reflect the new position.
1021 update_ring_for_set_deq_completion(xhci, dev,
1024 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1025 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1026 ep->queued_deq_seg, ep->queued_deq_ptr);
1031 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1032 dev->eps[ep_index].queued_deq_seg = NULL;
1033 dev->eps[ep_index].queued_deq_ptr = NULL;
1034 /* Restart any rings with pending URBs */
1035 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1038 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1039 union xhci_trb *trb, u32 cmd_comp_code)
1041 unsigned int ep_index;
1043 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1044 /* This command will only fail if the endpoint wasn't halted,
1045 * but we don't care.
1047 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1048 "Ignoring reset ep completion code of %u", cmd_comp_code);
1050 /* HW with the reset endpoint quirk needs to have a configure endpoint
1051 * command complete before the endpoint can be used. Queue that here
1052 * because the HW can't handle two commands being queued in a row.
1054 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1055 struct xhci_command *command;
1056 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1058 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1061 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1062 "Queueing configure endpoint command");
1063 xhci_queue_configure_endpoint(xhci, command,
1064 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1066 xhci_ring_cmd_db(xhci);
1068 /* Clear our internal halted state */
1069 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1073 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1076 if (cmd_comp_code == COMP_SUCCESS)
1077 xhci->slot_id = slot_id;
1082 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1084 struct xhci_virt_device *virt_dev;
1086 virt_dev = xhci->devs[slot_id];
1089 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1090 /* Delete default control endpoint resources */
1091 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1092 xhci_free_virt_device(xhci, slot_id);
1095 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1096 struct xhci_event_cmd *event, u32 cmd_comp_code)
1098 struct xhci_virt_device *virt_dev;
1099 struct xhci_input_control_ctx *ctrl_ctx;
1100 unsigned int ep_index;
1101 unsigned int ep_state;
1102 u32 add_flags, drop_flags;
1105 * Configure endpoint commands can come from the USB core
1106 * configuration or alt setting changes, or because the HW
1107 * needed an extra configure endpoint command after a reset
1108 * endpoint command or streams were being configured.
1109 * If the command was for a halted endpoint, the xHCI driver
1110 * is not waiting on the configure endpoint command.
1112 virt_dev = xhci->devs[slot_id];
1113 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1115 xhci_warn(xhci, "Could not get input context, bad type.\n");
1119 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1120 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1121 /* Input ctx add_flags are the endpoint index plus one */
1122 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1124 /* A usb_set_interface() call directly after clearing a halted
1125 * condition may race on this quirky hardware. Not worth
1126 * worrying about, since this is prototype hardware. Not sure
1127 * if this will work for streams, but streams support was
1128 * untested on this prototype.
1130 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1131 ep_index != (unsigned int) -1 &&
1132 add_flags - SLOT_FLAG == drop_flags) {
1133 ep_state = virt_dev->eps[ep_index].ep_state;
1134 if (!(ep_state & EP_HALTED))
1136 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1137 "Completed config ep cmd - "
1138 "last ep index = %d, state = %d",
1139 ep_index, ep_state);
1140 /* Clear internal halted state and restart ring(s) */
1141 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1148 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1149 struct xhci_event_cmd *event)
1151 xhci_dbg(xhci, "Completed reset device command.\n");
1152 if (!xhci->devs[slot_id])
1153 xhci_warn(xhci, "Reset device command completion "
1154 "for disabled slot %u\n", slot_id);
1157 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1158 struct xhci_event_cmd *event)
1160 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1161 xhci->error_bitmask |= 1 << 6;
1164 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1165 "NEC firmware version %2x.%02x",
1166 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1167 NEC_FW_MINOR(le32_to_cpu(event->status)));
1170 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1172 list_del(&cmd->cmd_list);
1174 if (cmd->completion) {
1175 cmd->status = status;
1176 complete(cmd->completion);
1182 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1184 struct xhci_command *cur_cmd, *tmp_cmd;
1185 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1186 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1190 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1191 * If there are other commands waiting then restart the ring and kick the timer.
1192 * This must be called with command ring stopped and xhci->lock held.
1194 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1195 struct xhci_command *cur_cmd)
1197 struct xhci_command *i_cmd, *tmp_cmd;
1200 /* Turn all aborted commands in list to no-ops, then restart */
1201 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1204 if (i_cmd->status != COMP_CMD_ABORT)
1207 i_cmd->status = COMP_CMD_STOP;
1209 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1210 i_cmd->command_trb);
1211 /* get cycle state from the original cmd trb */
1212 cycle_state = le32_to_cpu(
1213 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1214 /* modify the command trb to no-op command */
1215 i_cmd->command_trb->generic.field[0] = 0;
1216 i_cmd->command_trb->generic.field[1] = 0;
1217 i_cmd->command_trb->generic.field[2] = 0;
1218 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1219 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1222 * caller waiting for completion is called when command
1223 * completion event is received for these no-op commands
1227 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1229 /* ring command ring doorbell to restart the command ring */
1230 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1231 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1232 xhci->current_cmd = cur_cmd;
1233 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1234 xhci_ring_cmd_db(xhci);
1240 void xhci_handle_command_timeout(unsigned long data)
1242 struct xhci_hcd *xhci;
1244 unsigned long flags;
1246 struct xhci_command *cur_cmd = NULL;
1247 xhci = (struct xhci_hcd *) data;
1249 /* mark this command to be cancelled */
1250 spin_lock_irqsave(&xhci->lock, flags);
1251 if (xhci->current_cmd) {
1252 cur_cmd = xhci->current_cmd;
1253 cur_cmd->status = COMP_CMD_ABORT;
1257 /* Make sure command ring is running before aborting it */
1258 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1259 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1260 (hw_ring_state & CMD_RING_RUNNING)) {
1262 spin_unlock_irqrestore(&xhci->lock, flags);
1263 xhci_dbg(xhci, "Command timeout\n");
1264 ret = xhci_abort_cmd_ring(xhci);
1265 if (unlikely(ret == -ESHUTDOWN)) {
1266 xhci_err(xhci, "Abort command ring failed\n");
1267 xhci_cleanup_command_queue(xhci);
1268 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1269 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1273 /* command timeout on stopped ring, ring can't be aborted */
1274 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1275 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1276 spin_unlock_irqrestore(&xhci->lock, flags);
1280 static void handle_cmd_completion(struct xhci_hcd *xhci,
1281 struct xhci_event_cmd *event)
1283 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1285 dma_addr_t cmd_dequeue_dma;
1287 union xhci_trb *cmd_trb;
1288 struct xhci_command *cmd;
1291 cmd_dma = le64_to_cpu(event->cmd_trb);
1292 cmd_trb = xhci->cmd_ring->dequeue;
1293 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1295 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1296 if (cmd_dequeue_dma == 0) {
1297 xhci->error_bitmask |= 1 << 4;
1300 /* Does the DMA address match our internal dequeue pointer address? */
1301 if (cmd_dma != (u64) cmd_dequeue_dma) {
1302 xhci->error_bitmask |= 1 << 5;
1306 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1308 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1310 "Command completion event does not match command\n");
1314 del_timer(&xhci->cmd_timer);
1316 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1318 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1320 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1321 if (cmd_comp_code == COMP_CMD_STOP) {
1322 xhci_handle_stopped_cmd_ring(xhci, cmd);
1326 * Host aborted the command ring, check if the current command was
1327 * supposed to be aborted, otherwise continue normally.
1328 * The command ring is stopped now, but the xHC will issue a Command
1329 * Ring Stopped event which will cause us to restart it.
1331 if (cmd_comp_code == COMP_CMD_ABORT) {
1332 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1333 if (cmd->status == COMP_CMD_ABORT)
1337 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1339 case TRB_ENABLE_SLOT:
1340 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1342 case TRB_DISABLE_SLOT:
1343 xhci_handle_cmd_disable_slot(xhci, slot_id);
1346 if (!cmd->completion)
1347 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1350 case TRB_EVAL_CONTEXT:
1355 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1356 le32_to_cpu(cmd_trb->generic.field[3])));
1357 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1360 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1361 le32_to_cpu(cmd_trb->generic.field[3])));
1362 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1365 /* Is this an aborted command turned to NO-OP? */
1366 if (cmd->status == COMP_CMD_STOP)
1367 cmd_comp_code = COMP_CMD_STOP;
1370 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1371 le32_to_cpu(cmd_trb->generic.field[3])));
1372 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1375 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1376 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1378 slot_id = TRB_TO_SLOT_ID(
1379 le32_to_cpu(cmd_trb->generic.field[3]));
1380 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1382 case TRB_NEC_GET_FW:
1383 xhci_handle_cmd_nec_get_fw(xhci, event);
1386 /* Skip over unknown commands on the event ring */
1387 xhci->error_bitmask |= 1 << 6;
1391 /* restart timer if this wasn't the last command */
1392 if (cmd->cmd_list.next != &xhci->cmd_list) {
1393 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1394 struct xhci_command, cmd_list);
1395 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1399 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1401 inc_deq(xhci, xhci->cmd_ring);
1404 static void handle_vendor_event(struct xhci_hcd *xhci,
1405 union xhci_trb *event)
1409 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1410 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1411 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1412 handle_cmd_completion(xhci, &event->event_cmd);
1415 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1416 * port registers -- USB 3.0 and USB 2.0).
1418 * Returns a zero-based port number, which is suitable for indexing into each of
1419 * the split roothubs' port arrays and bus state arrays.
1420 * Add one to it in order to call xhci_find_slot_id_by_port.
1422 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1423 struct xhci_hcd *xhci, u32 port_id)
1426 unsigned int num_similar_speed_ports = 0;
1428 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1429 * and usb2_ports are 0-based indexes. Count the number of similar
1430 * speed ports, up to 1 port before this port.
1432 for (i = 0; i < (port_id - 1); i++) {
1433 u8 port_speed = xhci->port_array[i];
1436 * Skip ports that don't have known speeds, or have duplicate
1437 * Extended Capabilities port speed entries.
1439 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1443 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1444 * 1.1 ports are under the USB 2.0 hub. If the port speed
1445 * matches the device speed, it's a similar speed port.
1447 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1448 num_similar_speed_ports++;
1450 return num_similar_speed_ports;
1453 static void handle_device_notification(struct xhci_hcd *xhci,
1454 union xhci_trb *event)
1457 struct usb_device *udev;
1459 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1460 if (!xhci->devs[slot_id]) {
1461 xhci_warn(xhci, "Device Notification event for "
1462 "unused slot %u\n", slot_id);
1466 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1468 udev = xhci->devs[slot_id]->udev;
1469 if (udev && udev->parent)
1470 usb_wakeup_notification(udev->parent, udev->portnum);
1473 static void handle_port_status(struct xhci_hcd *xhci,
1474 union xhci_trb *event)
1476 struct usb_hcd *hcd;
1481 unsigned int faked_port_index;
1483 struct xhci_bus_state *bus_state;
1484 __le32 __iomem **port_array;
1485 bool bogus_port_status = false;
1487 /* Port status change events always have a successful completion code */
1488 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1489 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1490 xhci->error_bitmask |= 1 << 8;
1492 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1493 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1495 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1496 if ((port_id <= 0) || (port_id > max_ports)) {
1497 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1498 inc_deq(xhci, xhci->event_ring);
1502 /* Figure out which usb_hcd this port is attached to:
1503 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1505 major_revision = xhci->port_array[port_id - 1];
1507 /* Find the right roothub. */
1508 hcd = xhci_to_hcd(xhci);
1509 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1510 hcd = xhci->shared_hcd;
1512 if (major_revision == 0) {
1513 xhci_warn(xhci, "Event for port %u not in "
1514 "Extended Capabilities, ignoring.\n",
1516 bogus_port_status = true;
1519 if (major_revision == DUPLICATE_ENTRY) {
1520 xhci_warn(xhci, "Event for port %u duplicated in"
1521 "Extended Capabilities, ignoring.\n",
1523 bogus_port_status = true;
1528 * Hardware port IDs reported by a Port Status Change Event include USB
1529 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1530 * resume event, but we first need to translate the hardware port ID
1531 * into the index into the ports on the correct split roothub, and the
1532 * correct bus_state structure.
1534 bus_state = &xhci->bus_state[hcd_index(hcd)];
1535 if (hcd->speed == HCD_USB3)
1536 port_array = xhci->usb3_ports;
1538 port_array = xhci->usb2_ports;
1539 /* Find the faked port hub number */
1540 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1543 temp = readl(port_array[faked_port_index]);
1544 if (hcd->state == HC_STATE_SUSPENDED) {
1545 xhci_dbg(xhci, "resume root hub\n");
1546 usb_hcd_resume_root_hub(hcd);
1549 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1550 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1552 temp1 = readl(&xhci->op_regs->command);
1553 if (!(temp1 & CMD_RUN)) {
1554 xhci_warn(xhci, "xHC is not running.\n");
1558 if (DEV_SUPERSPEED(temp)) {
1559 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1560 /* Set a flag to say the port signaled remote wakeup,
1561 * so we can tell the difference between the end of
1562 * device and host initiated resume.
1564 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1565 xhci_test_and_clear_bit(xhci, port_array,
1566 faked_port_index, PORT_PLC);
1567 xhci_set_link_state(xhci, port_array, faked_port_index,
1569 /* Need to wait until the next link state change
1570 * indicates the device is actually in U0.
1572 bogus_port_status = true;
1575 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1576 bus_state->resume_done[faked_port_index] = jiffies +
1577 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1578 set_bit(faked_port_index, &bus_state->resuming_ports);
1579 mod_timer(&hcd->rh_timer,
1580 bus_state->resume_done[faked_port_index]);
1581 /* Do the rest in GetPortStatus */
1585 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1586 DEV_SUPERSPEED(temp)) {
1587 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1588 /* We've just brought the device into U0 through either the
1589 * Resume state after a device remote wakeup, or through the
1590 * U3Exit state after a host-initiated resume. If it's a device
1591 * initiated remote wake, don't pass up the link state change,
1592 * so the roothub behavior is consistent with external
1593 * USB 3.0 hub behavior.
1595 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1596 faked_port_index + 1);
1597 if (slot_id && xhci->devs[slot_id])
1598 xhci_ring_device(xhci, slot_id);
1599 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1600 bus_state->port_remote_wakeup &=
1601 ~(1 << faked_port_index);
1602 xhci_test_and_clear_bit(xhci, port_array,
1603 faked_port_index, PORT_PLC);
1604 usb_wakeup_notification(hcd->self.root_hub,
1605 faked_port_index + 1);
1606 bogus_port_status = true;
1612 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1613 * RExit to a disconnect state). If so, let the the driver know it's
1614 * out of the RExit state.
1616 if (!DEV_SUPERSPEED(temp) &&
1617 test_and_clear_bit(faked_port_index,
1618 &bus_state->rexit_ports)) {
1619 complete(&bus_state->rexit_done[faked_port_index]);
1620 bogus_port_status = true;
1624 if (hcd->speed != HCD_USB3)
1625 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1629 /* Update event ring dequeue pointer before dropping the lock */
1630 inc_deq(xhci, xhci->event_ring);
1632 /* Don't make the USB core poll the roothub if we got a bad port status
1633 * change event. Besides, at that point we can't tell which roothub
1634 * (USB 2.0 or USB 3.0) to kick.
1636 if (bogus_port_status)
1640 * xHCI port-status-change events occur when the "or" of all the
1641 * status-change bits in the portsc register changes from 0 to 1.
1642 * New status changes won't cause an event if any other change
1643 * bits are still set. When an event occurs, switch over to
1644 * polling to avoid losing status changes.
1646 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1647 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1648 spin_unlock(&xhci->lock);
1649 /* Pass this up to the core */
1650 usb_hcd_poll_rh_status(hcd);
1651 spin_lock(&xhci->lock);
1655 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1656 * at end_trb, which may be in another segment. If the suspect DMA address is a
1657 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1660 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1661 struct xhci_segment *start_seg,
1662 union xhci_trb *start_trb,
1663 union xhci_trb *end_trb,
1664 dma_addr_t suspect_dma,
1667 dma_addr_t start_dma;
1668 dma_addr_t end_seg_dma;
1669 dma_addr_t end_trb_dma;
1670 struct xhci_segment *cur_seg;
1672 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1673 cur_seg = start_seg;
1678 /* We may get an event for a Link TRB in the middle of a TD */
1679 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1680 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1681 /* If the end TRB isn't in this segment, this is set to 0 */
1682 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1686 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1687 (unsigned long long)suspect_dma,
1688 (unsigned long long)start_dma,
1689 (unsigned long long)end_trb_dma,
1690 (unsigned long long)cur_seg->dma,
1691 (unsigned long long)end_seg_dma);
1693 if (end_trb_dma > 0) {
1694 /* The end TRB is in this segment, so suspect should be here */
1695 if (start_dma <= end_trb_dma) {
1696 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1699 /* Case for one segment with
1700 * a TD wrapped around to the top
1702 if ((suspect_dma >= start_dma &&
1703 suspect_dma <= end_seg_dma) ||
1704 (suspect_dma >= cur_seg->dma &&
1705 suspect_dma <= end_trb_dma))
1710 /* Might still be somewhere in this segment */
1711 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1714 cur_seg = cur_seg->next;
1715 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1716 } while (cur_seg != start_seg);
1721 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1722 unsigned int slot_id, unsigned int ep_index,
1723 unsigned int stream_id,
1724 struct xhci_td *td, union xhci_trb *event_trb)
1726 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1727 struct xhci_command *command;
1728 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1732 ep->ep_state |= EP_HALTED;
1733 ep->stopped_stream = stream_id;
1735 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1736 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1738 ep->stopped_stream = 0;
1740 xhci_ring_cmd_db(xhci);
1743 /* Check if an error has halted the endpoint ring. The class driver will
1744 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1745 * However, a babble and other errors also halt the endpoint ring, and the class
1746 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1747 * Ring Dequeue Pointer command manually.
1749 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1750 struct xhci_ep_ctx *ep_ctx,
1751 unsigned int trb_comp_code)
1753 /* TRB completion codes that may require a manual halt cleanup */
1754 if (trb_comp_code == COMP_TX_ERR ||
1755 trb_comp_code == COMP_BABBLE ||
1756 trb_comp_code == COMP_SPLIT_ERR)
1757 /* The 0.96 spec says a babbling control endpoint
1758 * is not halted. The 0.96 spec says it is. Some HW
1759 * claims to be 0.95 compliant, but it halts the control
1760 * endpoint anyway. Check if a babble halted the
1763 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1764 cpu_to_le32(EP_STATE_HALTED))
1770 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1772 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1773 /* Vendor defined "informational" completion code,
1774 * treat as not-an-error.
1776 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1778 xhci_dbg(xhci, "Treating code as success.\n");
1785 * Finish the td processing, remove the td from td list;
1786 * Return 1 if the urb can be given back.
1788 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1789 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1790 struct xhci_virt_ep *ep, int *status, bool skip)
1792 struct xhci_virt_device *xdev;
1793 struct xhci_ring *ep_ring;
1794 unsigned int slot_id;
1796 struct urb *urb = NULL;
1797 struct xhci_ep_ctx *ep_ctx;
1799 struct urb_priv *urb_priv;
1802 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1803 xdev = xhci->devs[slot_id];
1804 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1805 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1806 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1807 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1812 if (trb_comp_code == COMP_STOP_INVAL || trb_comp_code == COMP_STOP) {
1813 /* The Endpoint Stop Command completion will take care of any
1814 * stopped TDs. A stopped TD may be restarted, so don't update
1815 * the ring dequeue pointer or take this TD off any lists yet.
1817 ep->stopped_td = td;
1820 if (trb_comp_code == COMP_STALL ||
1821 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1823 /* Issue a reset endpoint command to clear the host side
1824 * halt, followed by a set dequeue command to move the
1825 * dequeue pointer past the TD.
1826 * The class driver clears the device side halt later.
1828 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1829 ep_ring->stream_id, td, event_trb);
1831 /* Update ring dequeue pointer */
1832 while (ep_ring->dequeue != td->last_trb)
1833 inc_deq(xhci, ep_ring);
1834 inc_deq(xhci, ep_ring);
1838 /* Clean up the endpoint's TD list */
1840 urb_priv = urb->hcpriv;
1842 /* Do one last check of the actual transfer length.
1843 * If the host controller said we transferred more data than the buffer
1844 * length, urb->actual_length will be a very big number (since it's
1845 * unsigned). Play it safe and say we didn't transfer anything.
1847 if (urb->actual_length > urb->transfer_buffer_length) {
1848 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1849 urb->transfer_buffer_length,
1850 urb->actual_length);
1851 urb->actual_length = 0;
1852 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1853 *status = -EREMOTEIO;
1857 list_del_init(&td->td_list);
1858 /* Was this TD slated to be cancelled but completed anyway? */
1859 if (!list_empty(&td->cancelled_td_list))
1860 list_del_init(&td->cancelled_td_list);
1863 /* Giveback the urb when all the tds are completed */
1864 if (urb_priv->td_cnt == urb_priv->length) {
1866 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1867 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1868 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1869 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1870 usb_amd_quirk_pll_enable();
1879 * Process control tds, update urb status and actual_length.
1881 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1882 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1883 struct xhci_virt_ep *ep, int *status)
1885 struct xhci_virt_device *xdev;
1886 struct xhci_ring *ep_ring;
1887 unsigned int slot_id;
1889 struct xhci_ep_ctx *ep_ctx;
1892 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1893 xdev = xhci->devs[slot_id];
1894 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1895 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1896 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1897 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1899 switch (trb_comp_code) {
1901 if (event_trb == ep_ring->dequeue) {
1902 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1903 "without IOC set??\n");
1904 *status = -ESHUTDOWN;
1905 } else if (event_trb != td->last_trb) {
1906 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1907 "without IOC set??\n");
1908 *status = -ESHUTDOWN;
1914 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1915 *status = -EREMOTEIO;
1919 case COMP_STOP_INVAL:
1921 return finish_td(xhci, td, event_trb, event, ep, status, false);
1923 if (!xhci_requires_manual_halt_cleanup(xhci,
1924 ep_ctx, trb_comp_code))
1926 xhci_dbg(xhci, "TRB error code %u, "
1927 "halted endpoint index = %u\n",
1928 trb_comp_code, ep_index);
1929 /* else fall through */
1931 /* Did we transfer part of the data (middle) phase? */
1932 if (event_trb != ep_ring->dequeue &&
1933 event_trb != td->last_trb)
1934 td->urb->actual_length =
1935 td->urb->transfer_buffer_length -
1936 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1938 td->urb->actual_length = 0;
1940 return finish_td(xhci, td, event_trb, event, ep, status, false);
1943 * Did we transfer any data, despite the errors that might have
1944 * happened? I.e. did we get past the setup stage?
1946 if (event_trb != ep_ring->dequeue) {
1947 /* The event was for the status stage */
1948 if (event_trb == td->last_trb) {
1949 if (td->urb_length_set) {
1950 /* Don't overwrite a previously set error code
1952 if ((*status == -EINPROGRESS || *status == 0) &&
1953 (td->urb->transfer_flags
1954 & URB_SHORT_NOT_OK))
1955 /* Did we already see a short data
1957 *status = -EREMOTEIO;
1959 td->urb->actual_length =
1960 td->urb->transfer_buffer_length;
1964 * Maybe the event was for the data stage? If so, update
1965 * already the actual_length of the URB and flag it as
1966 * set, so that it is not overwritten in the event for
1969 td->urb_length_set = true;
1970 td->urb->actual_length =
1971 td->urb->transfer_buffer_length -
1972 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1973 xhci_dbg(xhci, "Waiting for status "
1979 return finish_td(xhci, td, event_trb, event, ep, status, false);
1983 * Process isochronous tds, update urb packet status and actual_length.
1985 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1986 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1987 struct xhci_virt_ep *ep, int *status)
1989 struct xhci_ring *ep_ring;
1990 struct urb_priv *urb_priv;
1993 union xhci_trb *cur_trb;
1994 struct xhci_segment *cur_seg;
1995 struct usb_iso_packet_descriptor *frame;
1997 bool skip_td = false;
1999 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2000 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2001 urb_priv = td->urb->hcpriv;
2002 idx = urb_priv->td_cnt;
2003 frame = &td->urb->iso_frame_desc[idx];
2005 /* handle completion code */
2006 switch (trb_comp_code) {
2008 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2012 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2013 trb_comp_code = COMP_SHORT_TX;
2015 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2019 frame->status = -ECOMM;
2022 case COMP_BUFF_OVER:
2024 frame->status = -EOVERFLOW;
2030 frame->status = -EPROTO;
2034 case COMP_STOP_INVAL:
2041 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2042 frame->actual_length = frame->length;
2043 td->urb->actual_length += frame->length;
2045 for (cur_trb = ep_ring->dequeue,
2046 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2047 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2048 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2049 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2050 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2052 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2053 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2055 if (trb_comp_code != COMP_STOP_INVAL) {
2056 frame->actual_length = len;
2057 td->urb->actual_length += len;
2061 return finish_td(xhci, td, event_trb, event, ep, status, false);
2064 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2065 struct xhci_transfer_event *event,
2066 struct xhci_virt_ep *ep, int *status)
2068 struct xhci_ring *ep_ring;
2069 struct urb_priv *urb_priv;
2070 struct usb_iso_packet_descriptor *frame;
2073 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2074 urb_priv = td->urb->hcpriv;
2075 idx = urb_priv->td_cnt;
2076 frame = &td->urb->iso_frame_desc[idx];
2078 /* The transfer is partly done. */
2079 frame->status = -EXDEV;
2081 /* calc actual length */
2082 frame->actual_length = 0;
2084 /* Update ring dequeue pointer */
2085 while (ep_ring->dequeue != td->last_trb)
2086 inc_deq(xhci, ep_ring);
2087 inc_deq(xhci, ep_ring);
2089 return finish_td(xhci, td, NULL, event, ep, status, true);
2093 * Process bulk and interrupt tds, update urb status and actual_length.
2095 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2096 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2097 struct xhci_virt_ep *ep, int *status)
2099 struct xhci_ring *ep_ring;
2100 union xhci_trb *cur_trb;
2101 struct xhci_segment *cur_seg;
2104 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2105 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2107 switch (trb_comp_code) {
2109 /* Double check that the HW transferred everything. */
2110 if (event_trb != td->last_trb ||
2111 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2112 xhci_warn(xhci, "WARN Successful completion "
2114 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2115 *status = -EREMOTEIO;
2118 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2119 trb_comp_code = COMP_SHORT_TX;
2125 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2126 *status = -EREMOTEIO;
2131 /* Others already handled above */
2134 if (trb_comp_code == COMP_SHORT_TX)
2135 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2136 "%d bytes untransferred\n",
2137 td->urb->ep->desc.bEndpointAddress,
2138 td->urb->transfer_buffer_length,
2139 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2140 /* Fast path - was this the last TRB in the TD for this URB? */
2141 if (event_trb == td->last_trb) {
2142 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2143 td->urb->actual_length =
2144 td->urb->transfer_buffer_length -
2145 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2146 if (td->urb->transfer_buffer_length <
2147 td->urb->actual_length) {
2148 xhci_warn(xhci, "HC gave bad length "
2149 "of %d bytes left\n",
2150 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2151 td->urb->actual_length = 0;
2152 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2153 *status = -EREMOTEIO;
2157 /* Don't overwrite a previously set error code */
2158 if (*status == -EINPROGRESS) {
2159 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2160 *status = -EREMOTEIO;
2165 td->urb->actual_length =
2166 td->urb->transfer_buffer_length;
2167 /* Ignore a short packet completion if the
2168 * untransferred length was zero.
2170 if (*status == -EREMOTEIO)
2174 /* Slow path - walk the list, starting from the dequeue
2175 * pointer, to get the actual length transferred.
2177 td->urb->actual_length = 0;
2178 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2179 cur_trb != event_trb;
2180 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2181 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2182 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2183 td->urb->actual_length +=
2184 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2186 /* If the ring didn't stop on a Link or No-op TRB, add
2187 * in the actual bytes transferred from the Normal TRB
2189 if (trb_comp_code != COMP_STOP_INVAL)
2190 td->urb->actual_length +=
2191 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2192 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2195 return finish_td(xhci, td, event_trb, event, ep, status, false);
2199 * If this function returns an error condition, it means it got a Transfer
2200 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2201 * At this point, the host controller is probably hosed and should be reset.
2203 static int handle_tx_event(struct xhci_hcd *xhci,
2204 struct xhci_transfer_event *event)
2205 __releases(&xhci->lock)
2206 __acquires(&xhci->lock)
2208 struct xhci_virt_device *xdev;
2209 struct xhci_virt_ep *ep;
2210 struct xhci_ring *ep_ring;
2211 unsigned int slot_id;
2213 struct xhci_td *td = NULL;
2214 dma_addr_t event_dma;
2215 struct xhci_segment *event_seg;
2216 union xhci_trb *event_trb;
2217 struct urb *urb = NULL;
2218 int status = -EINPROGRESS;
2219 struct urb_priv *urb_priv;
2220 struct xhci_ep_ctx *ep_ctx;
2221 struct list_head *tmp;
2226 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2227 xdev = xhci->devs[slot_id];
2229 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2230 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2231 (unsigned long long) xhci_trb_virt_to_dma(
2232 xhci->event_ring->deq_seg,
2233 xhci->event_ring->dequeue),
2234 lower_32_bits(le64_to_cpu(event->buffer)),
2235 upper_32_bits(le64_to_cpu(event->buffer)),
2236 le32_to_cpu(event->transfer_len),
2237 le32_to_cpu(event->flags));
2238 xhci_dbg(xhci, "Event ring:\n");
2239 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2243 /* Endpoint ID is 1 based, our index is zero based */
2244 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2245 ep = &xdev->eps[ep_index];
2246 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2247 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2249 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2250 EP_STATE_DISABLED) {
2251 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2252 "or incorrect stream ring\n");
2253 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2254 (unsigned long long) xhci_trb_virt_to_dma(
2255 xhci->event_ring->deq_seg,
2256 xhci->event_ring->dequeue),
2257 lower_32_bits(le64_to_cpu(event->buffer)),
2258 upper_32_bits(le64_to_cpu(event->buffer)),
2259 le32_to_cpu(event->transfer_len),
2260 le32_to_cpu(event->flags));
2261 xhci_dbg(xhci, "Event ring:\n");
2262 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2266 /* Count current td numbers if ep->skip is set */
2268 list_for_each(tmp, &ep_ring->td_list)
2272 event_dma = le64_to_cpu(event->buffer);
2273 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2274 /* Look for common error cases */
2275 switch (trb_comp_code) {
2276 /* Skip codes that require special handling depending on
2280 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2282 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2283 trb_comp_code = COMP_SHORT_TX;
2285 xhci_warn_ratelimited(xhci,
2286 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2290 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2292 case COMP_STOP_INVAL:
2293 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2296 xhci_dbg(xhci, "Stalled endpoint\n");
2297 ep->ep_state |= EP_HALTED;
2301 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2304 case COMP_SPLIT_ERR:
2306 xhci_dbg(xhci, "Transfer error on endpoint\n");
2310 xhci_dbg(xhci, "Babble error on endpoint\n");
2311 status = -EOVERFLOW;
2314 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2318 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2320 case COMP_BUFF_OVER:
2321 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2325 * When the Isoch ring is empty, the xHC will generate
2326 * a Ring Overrun Event for IN Isoch endpoint or Ring
2327 * Underrun Event for OUT Isoch endpoint.
2329 xhci_dbg(xhci, "underrun event on endpoint\n");
2330 if (!list_empty(&ep_ring->td_list))
2331 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2332 "still with TDs queued?\n",
2333 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2337 xhci_dbg(xhci, "overrun event on endpoint\n");
2338 if (!list_empty(&ep_ring->td_list))
2339 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2340 "still with TDs queued?\n",
2341 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2345 xhci_warn(xhci, "WARN: detect an incompatible device");
2348 case COMP_MISSED_INT:
2350 * When encounter missed service error, one or more isoc tds
2351 * may be missed by xHC.
2352 * Set skip flag of the ep_ring; Complete the missed tds as
2353 * short transfer when process the ep_ring next time.
2356 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2359 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2363 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2369 /* This TRB should be in the TD at the head of this ring's
2372 if (list_empty(&ep_ring->td_list)) {
2374 * A stopped endpoint may generate an extra completion
2375 * event if the device was suspended. Don't print
2378 if (!(trb_comp_code == COMP_STOP ||
2379 trb_comp_code == COMP_STOP_INVAL)) {
2380 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2381 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2383 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2384 (le32_to_cpu(event->flags) &
2385 TRB_TYPE_BITMASK)>>10);
2386 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2390 xhci_dbg(xhci, "td_list is empty while skip "
2391 "flag set. Clear skip flag.\n");
2397 /* We've skipped all the TDs on the ep ring when ep->skip set */
2398 if (ep->skip && td_num == 0) {
2400 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2401 "Clear skip flag.\n");
2406 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2410 /* Is this a TRB in the currently executing TD? */
2411 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2412 td->last_trb, event_dma, false);
2415 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2416 * is not in the current TD pointed by ep_ring->dequeue because
2417 * that the hardware dequeue pointer still at the previous TRB
2418 * of the current TD. The previous TRB maybe a Link TD or the
2419 * last TRB of the previous TD. The command completion handle
2420 * will take care the rest.
2422 if (!event_seg && (trb_comp_code == COMP_STOP ||
2423 trb_comp_code == COMP_STOP_INVAL)) {
2430 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2431 /* Some host controllers give a spurious
2432 * successful event after a short transfer.
2435 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2436 ep_ring->last_td_was_short) {
2437 ep_ring->last_td_was_short = false;
2441 /* HC is busted, give up! */
2443 "ERROR Transfer event TRB DMA ptr not "
2444 "part of current TD ep_index %d "
2445 "comp_code %u\n", ep_index,
2447 trb_in_td(xhci, ep_ring->deq_seg,
2448 ep_ring->dequeue, td->last_trb,
2453 ret = skip_isoc_td(xhci, td, event, ep, &status);
2456 if (trb_comp_code == COMP_SHORT_TX)
2457 ep_ring->last_td_was_short = true;
2459 ep_ring->last_td_was_short = false;
2462 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2466 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2467 sizeof(*event_trb)];
2469 * No-op TRB should not trigger interrupts.
2470 * If event_trb is a no-op TRB, it means the
2471 * corresponding TD has been cancelled. Just ignore
2474 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2476 "event_trb is a no-op TRB. Skip it\n");
2480 /* Now update the urb's actual_length and give back to
2483 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2484 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2486 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2487 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2490 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2495 * Do not update event ring dequeue pointer if ep->skip is set.
2496 * Will roll back to continue process missed tds.
2498 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2499 inc_deq(xhci, xhci->event_ring);
2504 urb_priv = urb->hcpriv;
2506 xhci_urb_free_priv(urb_priv);
2508 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2509 if ((urb->actual_length != urb->transfer_buffer_length &&
2510 (urb->transfer_flags &
2511 URB_SHORT_NOT_OK)) ||
2513 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2514 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2515 "expected = %d, status = %d\n",
2516 urb, urb->actual_length,
2517 urb->transfer_buffer_length,
2519 spin_unlock(&xhci->lock);
2520 /* EHCI, UHCI, and OHCI always unconditionally set the
2521 * urb->status of an isochronous endpoint to 0.
2523 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2525 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2526 spin_lock(&xhci->lock);
2530 * If ep->skip is set, it means there are missed tds on the
2531 * endpoint ring need to take care of.
2532 * Process them as short transfer until reach the td pointed by
2535 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2541 * This function handles all OS-owned events on the event ring. It may drop
2542 * xhci->lock between event processing (e.g. to pass up port status changes).
2543 * Returns >0 for "possibly more events to process" (caller should call again),
2544 * otherwise 0 if done. In future, <0 returns should indicate error code.
2546 static int xhci_handle_event(struct xhci_hcd *xhci)
2548 union xhci_trb *event;
2549 int update_ptrs = 1;
2552 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2553 xhci->error_bitmask |= 1 << 1;
2557 event = xhci->event_ring->dequeue;
2558 /* Does the HC or OS own the TRB? */
2559 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2560 xhci->event_ring->cycle_state) {
2561 xhci->error_bitmask |= 1 << 2;
2566 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2567 * speculative reads of the event's flags/data below.
2570 /* FIXME: Handle more event types. */
2571 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2572 case TRB_TYPE(TRB_COMPLETION):
2573 handle_cmd_completion(xhci, &event->event_cmd);
2575 case TRB_TYPE(TRB_PORT_STATUS):
2576 handle_port_status(xhci, event);
2579 case TRB_TYPE(TRB_TRANSFER):
2580 ret = handle_tx_event(xhci, &event->trans_event);
2582 xhci->error_bitmask |= 1 << 9;
2586 case TRB_TYPE(TRB_DEV_NOTE):
2587 handle_device_notification(xhci, event);
2590 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2592 handle_vendor_event(xhci, event);
2594 xhci->error_bitmask |= 1 << 3;
2596 /* Any of the above functions may drop and re-acquire the lock, so check
2597 * to make sure a watchdog timer didn't mark the host as non-responsive.
2599 if (xhci->xhc_state & XHCI_STATE_DYING) {
2600 xhci_dbg(xhci, "xHCI host dying, returning from "
2601 "event handler.\n");
2606 /* Update SW event ring dequeue pointer */
2607 inc_deq(xhci, xhci->event_ring);
2609 /* Are there more items on the event ring? Caller will call us again to
2616 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2617 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2618 * indicators of an event TRB error, but we check the status *first* to be safe.
2620 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2622 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2625 union xhci_trb *event_ring_deq;
2628 spin_lock(&xhci->lock);
2629 /* Check if the xHC generated the interrupt, or the irq is shared */
2630 status = readl(&xhci->op_regs->status);
2631 if (status == 0xffffffff)
2634 if (!(status & STS_EINT)) {
2635 spin_unlock(&xhci->lock);
2638 if (status & STS_FATAL) {
2639 xhci_warn(xhci, "WARNING: Host System Error\n");
2642 spin_unlock(&xhci->lock);
2647 * Clear the op reg interrupt status first,
2648 * so we can receive interrupts from other MSI-X interrupters.
2649 * Write 1 to clear the interrupt status.
2652 writel(status, &xhci->op_regs->status);
2653 /* FIXME when MSI-X is supported and there are multiple vectors */
2654 /* Clear the MSI-X event interrupt status */
2658 /* Acknowledge the PCI interrupt */
2659 irq_pending = readl(&xhci->ir_set->irq_pending);
2660 irq_pending |= IMAN_IP;
2661 writel(irq_pending, &xhci->ir_set->irq_pending);
2664 if (xhci->xhc_state & XHCI_STATE_DYING) {
2665 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2666 "Shouldn't IRQs be disabled?\n");
2667 /* Clear the event handler busy flag (RW1C);
2668 * the event ring should be empty.
2670 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2671 xhci_write_64(xhci, temp_64 | ERST_EHB,
2672 &xhci->ir_set->erst_dequeue);
2673 spin_unlock(&xhci->lock);
2678 event_ring_deq = xhci->event_ring->dequeue;
2679 /* FIXME this should be a delayed service routine
2680 * that clears the EHB.
2682 while (xhci_handle_event(xhci) > 0) {}
2684 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2685 /* If necessary, update the HW's version of the event ring deq ptr. */
2686 if (event_ring_deq != xhci->event_ring->dequeue) {
2687 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2688 xhci->event_ring->dequeue);
2690 xhci_warn(xhci, "WARN something wrong with SW event "
2691 "ring dequeue ptr.\n");
2692 /* Update HC event ring dequeue pointer */
2693 temp_64 &= ERST_PTR_MASK;
2694 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2697 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2698 temp_64 |= ERST_EHB;
2699 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2701 spin_unlock(&xhci->lock);
2706 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2708 return xhci_irq(hcd);
2711 /**** Endpoint Ring Operations ****/
2714 * Generic function for queueing a TRB on a ring.
2715 * The caller must have checked to make sure there's room on the ring.
2717 * @more_trbs_coming: Will you enqueue more TRBs before calling
2718 * prepare_transfer()?
2720 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2721 bool more_trbs_coming,
2722 u32 field1, u32 field2, u32 field3, u32 field4)
2724 struct xhci_generic_trb *trb;
2726 trb = &ring->enqueue->generic;
2727 trb->field[0] = cpu_to_le32(field1);
2728 trb->field[1] = cpu_to_le32(field2);
2729 trb->field[2] = cpu_to_le32(field3);
2730 trb->field[3] = cpu_to_le32(field4);
2731 inc_enq(xhci, ring, more_trbs_coming);
2735 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2736 * FIXME allocate segments if the ring is full.
2738 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2739 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2741 unsigned int num_trbs_needed;
2743 /* Make sure the endpoint has been added to xHC schedule */
2745 case EP_STATE_DISABLED:
2747 * USB core changed config/interfaces without notifying us,
2748 * or hardware is reporting the wrong state.
2750 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2752 case EP_STATE_ERROR:
2753 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2754 /* FIXME event handling code for error needs to clear it */
2755 /* XXX not sure if this should be -ENOENT or not */
2757 case EP_STATE_HALTED:
2758 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2759 case EP_STATE_STOPPED:
2760 case EP_STATE_RUNNING:
2763 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2765 * FIXME issue Configure Endpoint command to try to get the HC
2766 * back into a known state.
2772 if (room_on_ring(xhci, ep_ring, num_trbs))
2775 if (ep_ring == xhci->cmd_ring) {
2776 xhci_err(xhci, "Do not support expand command ring\n");
2780 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2781 "ERROR no room on ep ring, try ring expansion");
2782 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2783 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2785 xhci_err(xhci, "Ring expansion failed\n");
2790 if (enqueue_is_link_trb(ep_ring)) {
2791 struct xhci_ring *ring = ep_ring;
2792 union xhci_trb *next;
2794 next = ring->enqueue;
2796 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2797 /* If we're not dealing with 0.95 hardware or isoc rings
2798 * on AMD 0.96 host, clear the chain bit.
2800 if (!xhci_link_trb_quirk(xhci) &&
2801 !(ring->type == TYPE_ISOC &&
2802 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2803 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2805 next->link.control |= cpu_to_le32(TRB_CHAIN);
2808 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2810 /* Toggle the cycle bit after the last ring segment. */
2811 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2812 ring->cycle_state ^= 1;
2814 ring->enq_seg = ring->enq_seg->next;
2815 ring->enqueue = ring->enq_seg->trbs;
2816 next = ring->enqueue;
2823 static int prepare_transfer(struct xhci_hcd *xhci,
2824 struct xhci_virt_device *xdev,
2825 unsigned int ep_index,
2826 unsigned int stream_id,
2827 unsigned int num_trbs,
2829 unsigned int td_index,
2833 struct urb_priv *urb_priv;
2835 struct xhci_ring *ep_ring;
2836 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2838 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2840 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2845 ret = prepare_ring(xhci, ep_ring,
2846 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2847 num_trbs, mem_flags);
2851 urb_priv = urb->hcpriv;
2852 td = urb_priv->td[td_index];
2854 INIT_LIST_HEAD(&td->td_list);
2855 INIT_LIST_HEAD(&td->cancelled_td_list);
2857 if (td_index == 0) {
2858 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2864 /* Add this TD to the tail of the endpoint ring's TD list */
2865 list_add_tail(&td->td_list, &ep_ring->td_list);
2866 td->start_seg = ep_ring->enq_seg;
2867 td->first_trb = ep_ring->enqueue;
2869 urb_priv->td[td_index] = td;
2874 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2876 int num_sgs, num_trbs, running_total, temp, i;
2877 struct scatterlist *sg;
2880 num_sgs = urb->num_mapped_sgs;
2881 temp = urb->transfer_buffer_length;
2884 for_each_sg(urb->sg, sg, num_sgs, i) {
2885 unsigned int len = sg_dma_len(sg);
2887 /* Scatter gather list entries may cross 64KB boundaries */
2888 running_total = TRB_MAX_BUFF_SIZE -
2889 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2890 running_total &= TRB_MAX_BUFF_SIZE - 1;
2891 if (running_total != 0)
2894 /* How many more 64KB chunks to transfer, how many more TRBs? */
2895 while (running_total < sg_dma_len(sg) && running_total < temp) {
2897 running_total += TRB_MAX_BUFF_SIZE;
2899 len = min_t(int, len, temp);
2907 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2910 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2911 "TRBs, %d left\n", __func__,
2912 urb->ep->desc.bEndpointAddress, num_trbs);
2913 if (running_total != urb->transfer_buffer_length)
2914 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2915 "queued %#x (%d), asked for %#x (%d)\n",
2917 urb->ep->desc.bEndpointAddress,
2918 running_total, running_total,
2919 urb->transfer_buffer_length,
2920 urb->transfer_buffer_length);
2923 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2924 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2925 struct xhci_generic_trb *start_trb)
2928 * Pass all the TRBs to the hardware at once and make sure this write
2933 start_trb->field[3] |= cpu_to_le32(start_cycle);
2935 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2936 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2940 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2941 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2942 * (comprised of sg list entries) can take several service intervals to
2945 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2946 struct urb *urb, int slot_id, unsigned int ep_index)
2948 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2949 xhci->devs[slot_id]->out_ctx, ep_index);
2953 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2954 ep_interval = urb->interval;
2955 /* Convert to microframes */
2956 if (urb->dev->speed == USB_SPEED_LOW ||
2957 urb->dev->speed == USB_SPEED_FULL)
2959 /* FIXME change this to a warning and a suggestion to use the new API
2960 * to set the polling interval (once the API is added).
2962 if (xhci_interval != ep_interval) {
2963 dev_dbg_ratelimited(&urb->dev->dev,
2964 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
2965 ep_interval, ep_interval == 1 ? "" : "s",
2966 xhci_interval, xhci_interval == 1 ? "" : "s");
2967 urb->interval = xhci_interval;
2968 /* Convert back to frames for LS/FS devices */
2969 if (urb->dev->speed == USB_SPEED_LOW ||
2970 urb->dev->speed == USB_SPEED_FULL)
2973 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
2977 * The TD size is the number of bytes remaining in the TD (including this TRB),
2978 * right shifted by 10.
2979 * It must fit in bits 21:17, so it can't be bigger than 31.
2981 static u32 xhci_td_remainder(unsigned int remainder)
2983 u32 max = (1 << (21 - 17 + 1)) - 1;
2985 if ((remainder >> 10) >= max)
2988 return (remainder >> 10) << 17;
2992 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
2993 * packets remaining in the TD (*not* including this TRB).
2995 * Total TD packet count = total_packet_count =
2996 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
2998 * Packets transferred up to and including this TRB = packets_transferred =
2999 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3001 * TD size = total_packet_count - packets_transferred
3003 * It must fit in bits 21:17, so it can't be bigger than 31.
3004 * The last TRB in a TD must have the TD size set to zero.
3006 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3007 unsigned int total_packet_count, struct urb *urb,
3008 unsigned int num_trbs_left)
3010 int packets_transferred;
3012 /* One TRB with a zero-length data packet. */
3013 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3016 /* All the TRB queueing functions don't count the current TRB in
3019 packets_transferred = (running_total + trb_buff_len) /
3020 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3022 if ((total_packet_count - packets_transferred) > 31)
3024 return (total_packet_count - packets_transferred) << 17;
3027 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3028 struct urb *urb, int slot_id, unsigned int ep_index)
3030 struct xhci_ring *ep_ring;
3031 unsigned int num_trbs;
3032 struct urb_priv *urb_priv;
3034 struct scatterlist *sg;
3036 int trb_buff_len, this_sg_len, running_total;
3037 unsigned int total_packet_count;
3040 bool more_trbs_coming;
3042 struct xhci_generic_trb *start_trb;
3045 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3049 num_trbs = count_sg_trbs_needed(xhci, urb);
3050 num_sgs = urb->num_mapped_sgs;
3051 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3052 usb_endpoint_maxp(&urb->ep->desc));
3054 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3055 ep_index, urb->stream_id,
3056 num_trbs, urb, 0, mem_flags);
3057 if (trb_buff_len < 0)
3058 return trb_buff_len;
3060 urb_priv = urb->hcpriv;
3061 td = urb_priv->td[0];
3064 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3065 * until we've finished creating all the other TRBs. The ring's cycle
3066 * state may change as we enqueue the other TRBs, so save it too.
3068 start_trb = &ep_ring->enqueue->generic;
3069 start_cycle = ep_ring->cycle_state;
3073 * How much data is in the first TRB?
3075 * There are three forces at work for TRB buffer pointers and lengths:
3076 * 1. We don't want to walk off the end of this sg-list entry buffer.
3077 * 2. The transfer length that the driver requested may be smaller than
3078 * the amount of memory allocated for this scatter-gather list.
3079 * 3. TRBs buffers can't cross 64KB boundaries.
3082 addr = (u64) sg_dma_address(sg);
3083 this_sg_len = sg_dma_len(sg);
3084 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3085 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3086 if (trb_buff_len > urb->transfer_buffer_length)
3087 trb_buff_len = urb->transfer_buffer_length;
3090 /* Queue the first TRB, even if it's zero-length */
3093 u32 length_field = 0;
3096 /* Don't change the cycle bit of the first TRB until later */
3099 if (start_cycle == 0)
3102 field |= ep_ring->cycle_state;
3104 /* Chain all the TRBs together; clear the chain bit in the last
3105 * TRB to indicate it's the last TRB in the chain.
3110 /* FIXME - add check for ZERO_PACKET flag before this */
3111 td->last_trb = ep_ring->enqueue;
3115 /* Only set interrupt on short packet for IN endpoints */
3116 if (usb_urb_dir_in(urb))
3119 if (TRB_MAX_BUFF_SIZE -
3120 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3121 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3122 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3123 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3124 (unsigned int) addr + trb_buff_len);
3127 /* Set the TRB length, TD size, and interrupter fields. */
3128 if (xhci->hci_version < 0x100) {
3129 remainder = xhci_td_remainder(
3130 urb->transfer_buffer_length -
3133 remainder = xhci_v1_0_td_remainder(running_total,
3134 trb_buff_len, total_packet_count, urb,
3137 length_field = TRB_LEN(trb_buff_len) |
3142 more_trbs_coming = true;
3144 more_trbs_coming = false;
3145 queue_trb(xhci, ep_ring, more_trbs_coming,
3146 lower_32_bits(addr),
3147 upper_32_bits(addr),
3149 field | TRB_TYPE(TRB_NORMAL));
3151 running_total += trb_buff_len;
3153 /* Calculate length for next transfer --
3154 * Are we done queueing all the TRBs for this sg entry?
3156 this_sg_len -= trb_buff_len;
3157 if (this_sg_len == 0) {
3162 addr = (u64) sg_dma_address(sg);
3163 this_sg_len = sg_dma_len(sg);
3165 addr += trb_buff_len;
3168 trb_buff_len = TRB_MAX_BUFF_SIZE -
3169 (addr & (TRB_MAX_BUFF_SIZE - 1));
3170 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3171 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3173 urb->transfer_buffer_length - running_total;
3174 } while (running_total < urb->transfer_buffer_length);
3176 check_trb_math(urb, num_trbs, running_total);
3177 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3178 start_cycle, start_trb);
3182 /* This is very similar to what ehci-q.c qtd_fill() does */
3183 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3184 struct urb *urb, int slot_id, unsigned int ep_index)
3186 struct xhci_ring *ep_ring;
3187 struct urb_priv *urb_priv;
3190 struct xhci_generic_trb *start_trb;
3192 bool more_trbs_coming;
3194 u32 field, length_field;
3196 int running_total, trb_buff_len, ret;
3197 unsigned int total_packet_count;
3201 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3203 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3208 /* How much data is (potentially) left before the 64KB boundary? */
3209 running_total = TRB_MAX_BUFF_SIZE -
3210 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3211 running_total &= TRB_MAX_BUFF_SIZE - 1;
3213 /* If there's some data on this 64KB chunk, or we have to send a
3214 * zero-length transfer, we need at least one TRB
3216 if (running_total != 0 || urb->transfer_buffer_length == 0)
3218 /* How many more 64KB chunks to transfer, how many more TRBs? */
3219 while (running_total < urb->transfer_buffer_length) {
3221 running_total += TRB_MAX_BUFF_SIZE;
3223 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3225 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3226 ep_index, urb->stream_id,
3227 num_trbs, urb, 0, mem_flags);
3231 urb_priv = urb->hcpriv;
3232 td = urb_priv->td[0];
3235 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3236 * until we've finished creating all the other TRBs. The ring's cycle
3237 * state may change as we enqueue the other TRBs, so save it too.
3239 start_trb = &ep_ring->enqueue->generic;
3240 start_cycle = ep_ring->cycle_state;
3243 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3244 usb_endpoint_maxp(&urb->ep->desc));
3245 /* How much data is in the first TRB? */
3246 addr = (u64) urb->transfer_dma;
3247 trb_buff_len = TRB_MAX_BUFF_SIZE -
3248 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3249 if (trb_buff_len > urb->transfer_buffer_length)
3250 trb_buff_len = urb->transfer_buffer_length;
3254 /* Queue the first TRB, even if it's zero-length */
3259 /* Don't change the cycle bit of the first TRB until later */
3262 if (start_cycle == 0)
3265 field |= ep_ring->cycle_state;
3267 /* Chain all the TRBs together; clear the chain bit in the last
3268 * TRB to indicate it's the last TRB in the chain.
3273 /* FIXME - add check for ZERO_PACKET flag before this */
3274 td->last_trb = ep_ring->enqueue;
3278 /* Only set interrupt on short packet for IN endpoints */
3279 if (usb_urb_dir_in(urb))
3282 /* Set the TRB length, TD size, and interrupter fields. */
3283 if (xhci->hci_version < 0x100) {
3284 remainder = xhci_td_remainder(
3285 urb->transfer_buffer_length -
3288 remainder = xhci_v1_0_td_remainder(running_total,
3289 trb_buff_len, total_packet_count, urb,
3292 length_field = TRB_LEN(trb_buff_len) |
3297 more_trbs_coming = true;
3299 more_trbs_coming = false;
3300 queue_trb(xhci, ep_ring, more_trbs_coming,
3301 lower_32_bits(addr),
3302 upper_32_bits(addr),
3304 field | TRB_TYPE(TRB_NORMAL));
3306 running_total += trb_buff_len;
3308 /* Calculate length for next transfer */
3309 addr += trb_buff_len;
3310 trb_buff_len = urb->transfer_buffer_length - running_total;
3311 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3312 trb_buff_len = TRB_MAX_BUFF_SIZE;
3313 } while (running_total < urb->transfer_buffer_length);
3315 check_trb_math(urb, num_trbs, running_total);
3316 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3317 start_cycle, start_trb);
3321 /* Caller must have locked xhci->lock */
3322 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3323 struct urb *urb, int slot_id, unsigned int ep_index)
3325 struct xhci_ring *ep_ring;
3328 struct usb_ctrlrequest *setup;
3329 struct xhci_generic_trb *start_trb;
3331 u32 field, length_field;
3332 struct urb_priv *urb_priv;
3335 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3340 * Need to copy setup packet into setup TRB, so we can't use the setup
3343 if (!urb->setup_packet)
3346 /* 1 TRB for setup, 1 for status */
3349 * Don't need to check if we need additional event data and normal TRBs,
3350 * since data in control transfers will never get bigger than 16MB
3351 * XXX: can we get a buffer that crosses 64KB boundaries?
3353 if (urb->transfer_buffer_length > 0)
3355 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3356 ep_index, urb->stream_id,
3357 num_trbs, urb, 0, mem_flags);
3361 urb_priv = urb->hcpriv;
3362 td = urb_priv->td[0];
3365 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3366 * until we've finished creating all the other TRBs. The ring's cycle
3367 * state may change as we enqueue the other TRBs, so save it too.
3369 start_trb = &ep_ring->enqueue->generic;
3370 start_cycle = ep_ring->cycle_state;
3372 /* Queue setup TRB - see section 6.4.1.2.1 */
3373 /* FIXME better way to translate setup_packet into two u32 fields? */
3374 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3376 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3377 if (start_cycle == 0)
3380 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3381 if (xhci->hci_version == 0x100) {
3382 if (urb->transfer_buffer_length > 0) {
3383 if (setup->bRequestType & USB_DIR_IN)
3384 field |= TRB_TX_TYPE(TRB_DATA_IN);
3386 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3390 queue_trb(xhci, ep_ring, true,
3391 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3392 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3393 TRB_LEN(8) | TRB_INTR_TARGET(0),
3394 /* Immediate data in pointer */
3397 /* If there's data, queue data TRBs */
3398 /* Only set interrupt on short packet for IN endpoints */
3399 if (usb_urb_dir_in(urb))
3400 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3402 field = TRB_TYPE(TRB_DATA);
3404 length_field = TRB_LEN(urb->transfer_buffer_length) |
3405 xhci_td_remainder(urb->transfer_buffer_length) |
3407 if (urb->transfer_buffer_length > 0) {
3408 if (setup->bRequestType & USB_DIR_IN)
3409 field |= TRB_DIR_IN;
3410 queue_trb(xhci, ep_ring, true,
3411 lower_32_bits(urb->transfer_dma),
3412 upper_32_bits(urb->transfer_dma),
3414 field | ep_ring->cycle_state);
3417 /* Save the DMA address of the last TRB in the TD */
3418 td->last_trb = ep_ring->enqueue;
3420 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3421 /* If the device sent data, the status stage is an OUT transfer */
3422 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3426 queue_trb(xhci, ep_ring, false,
3430 /* Event on completion */
3431 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3433 giveback_first_trb(xhci, slot_id, ep_index, 0,
3434 start_cycle, start_trb);
3438 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3439 struct urb *urb, int i)
3444 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3445 td_len = urb->iso_frame_desc[i].length;
3447 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3456 * The transfer burst count field of the isochronous TRB defines the number of
3457 * bursts that are required to move all packets in this TD. Only SuperSpeed
3458 * devices can burst up to bMaxBurst number of packets per service interval.
3459 * This field is zero based, meaning a value of zero in the field means one
3460 * burst. Basically, for everything but SuperSpeed devices, this field will be
3461 * zero. Only xHCI 1.0 host controllers support this field.
3463 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3464 struct usb_device *udev,
3465 struct urb *urb, unsigned int total_packet_count)
3467 unsigned int max_burst;
3469 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3472 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3473 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3477 * Returns the number of packets in the last "burst" of packets. This field is
3478 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3479 * the last burst packet count is equal to the total number of packets in the
3480 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3481 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3482 * contain 1 to (bMaxBurst + 1) packets.
3484 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3485 struct usb_device *udev,
3486 struct urb *urb, unsigned int total_packet_count)
3488 unsigned int max_burst;
3489 unsigned int residue;
3491 if (xhci->hci_version < 0x100)
3494 switch (udev->speed) {
3495 case USB_SPEED_SUPER:
3496 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3497 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3498 residue = total_packet_count % (max_burst + 1);
3499 /* If residue is zero, the last burst contains (max_burst + 1)
3500 * number of packets, but the TLBPC field is zero-based.
3506 if (total_packet_count == 0)
3508 return total_packet_count - 1;
3512 /* This is for isoc transfer */
3513 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3514 struct urb *urb, int slot_id, unsigned int ep_index)
3516 struct xhci_ring *ep_ring;
3517 struct urb_priv *urb_priv;
3519 int num_tds, trbs_per_td;
3520 struct xhci_generic_trb *start_trb;
3523 u32 field, length_field;
3524 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3525 u64 start_addr, addr;
3527 bool more_trbs_coming;
3529 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3531 num_tds = urb->number_of_packets;
3533 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3537 start_addr = (u64) urb->transfer_dma;
3538 start_trb = &ep_ring->enqueue->generic;
3539 start_cycle = ep_ring->cycle_state;
3541 urb_priv = urb->hcpriv;
3542 /* Queue the first TRB, even if it's zero-length */
3543 for (i = 0; i < num_tds; i++) {
3544 unsigned int total_packet_count;
3545 unsigned int burst_count;
3546 unsigned int residue;
3550 addr = start_addr + urb->iso_frame_desc[i].offset;
3551 td_len = urb->iso_frame_desc[i].length;
3552 td_remain_len = td_len;
3553 total_packet_count = DIV_ROUND_UP(td_len,
3555 usb_endpoint_maxp(&urb->ep->desc)));
3556 /* A zero-length transfer still involves at least one packet. */
3557 if (total_packet_count == 0)
3558 total_packet_count++;
3559 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3560 total_packet_count);
3561 residue = xhci_get_last_burst_packet_count(xhci,
3562 urb->dev, urb, total_packet_count);
3564 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3566 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3567 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3574 td = urb_priv->td[i];
3575 for (j = 0; j < trbs_per_td; j++) {
3580 field = TRB_TBC(burst_count) |
3582 /* Queue the isoc TRB */
3583 field |= TRB_TYPE(TRB_ISOC);
3584 /* Assume URB_ISO_ASAP is set */
3587 if (start_cycle == 0)
3590 field |= ep_ring->cycle_state;
3593 /* Queue other normal TRBs */
3594 field |= TRB_TYPE(TRB_NORMAL);
3595 field |= ep_ring->cycle_state;
3598 /* Only set interrupt on short packet for IN EPs */
3599 if (usb_urb_dir_in(urb))
3602 /* Chain all the TRBs together; clear the chain bit in
3603 * the last TRB to indicate it's the last TRB in the
3606 if (j < trbs_per_td - 1) {
3608 more_trbs_coming = true;
3610 td->last_trb = ep_ring->enqueue;
3612 if (xhci->hci_version == 0x100 &&
3615 /* Set BEI bit except for the last td */
3616 if (i < num_tds - 1)
3619 more_trbs_coming = false;
3622 /* Calculate TRB length */
3623 trb_buff_len = TRB_MAX_BUFF_SIZE -
3624 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3625 if (trb_buff_len > td_remain_len)
3626 trb_buff_len = td_remain_len;
3628 /* Set the TRB length, TD size, & interrupter fields. */
3629 if (xhci->hci_version < 0x100) {
3630 remainder = xhci_td_remainder(
3631 td_len - running_total);
3633 remainder = xhci_v1_0_td_remainder(
3634 running_total, trb_buff_len,
3635 total_packet_count, urb,
3636 (trbs_per_td - j - 1));
3638 length_field = TRB_LEN(trb_buff_len) |
3642 queue_trb(xhci, ep_ring, more_trbs_coming,
3643 lower_32_bits(addr),
3644 upper_32_bits(addr),
3647 running_total += trb_buff_len;
3649 addr += trb_buff_len;
3650 td_remain_len -= trb_buff_len;
3653 /* Check TD length */
3654 if (running_total != td_len) {
3655 xhci_err(xhci, "ISOC TD length unmatch\n");
3661 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3662 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3663 usb_amd_quirk_pll_disable();
3665 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3667 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3668 start_cycle, start_trb);
3671 /* Clean up a partially enqueued isoc transfer. */
3673 for (i--; i >= 0; i--)
3674 list_del_init(&urb_priv->td[i]->td_list);
3676 /* Use the first TD as a temporary variable to turn the TDs we've queued
3677 * into No-ops with a software-owned cycle bit. That way the hardware
3678 * won't accidentally start executing bogus TDs when we partially
3679 * overwrite them. td->first_trb and td->start_seg are already set.
3681 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3682 /* Every TRB except the first & last will have its cycle bit flipped. */
3683 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3685 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3686 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3687 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3688 ep_ring->cycle_state = start_cycle;
3689 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3690 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3695 * Check transfer ring to guarantee there is enough room for the urb.
3696 * Update ISO URB start_frame and interval.
3697 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3698 * update the urb->start_frame by now.
3699 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3701 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3702 struct urb *urb, int slot_id, unsigned int ep_index)
3704 struct xhci_virt_device *xdev;
3705 struct xhci_ring *ep_ring;
3706 struct xhci_ep_ctx *ep_ctx;
3710 int num_tds, num_trbs, i;
3713 xdev = xhci->devs[slot_id];
3714 ep_ring = xdev->eps[ep_index].ring;
3715 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3718 num_tds = urb->number_of_packets;
3719 for (i = 0; i < num_tds; i++)
3720 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3722 /* Check the ring to guarantee there is enough room for the whole urb.
3723 * Do not insert any td of the urb to the ring if the check failed.
3725 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3726 num_trbs, mem_flags);
3730 start_frame = readl(&xhci->run_regs->microframe_index);
3731 start_frame &= 0x3fff;
3733 urb->start_frame = start_frame;
3734 if (urb->dev->speed == USB_SPEED_LOW ||
3735 urb->dev->speed == USB_SPEED_FULL)
3736 urb->start_frame >>= 3;
3738 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3739 ep_interval = urb->interval;
3740 /* Convert to microframes */
3741 if (urb->dev->speed == USB_SPEED_LOW ||
3742 urb->dev->speed == USB_SPEED_FULL)
3744 /* FIXME change this to a warning and a suggestion to use the new API
3745 * to set the polling interval (once the API is added).
3747 if (xhci_interval != ep_interval) {
3748 dev_dbg_ratelimited(&urb->dev->dev,
3749 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3750 ep_interval, ep_interval == 1 ? "" : "s",
3751 xhci_interval, xhci_interval == 1 ? "" : "s");
3752 urb->interval = xhci_interval;
3753 /* Convert back to frames for LS/FS devices */
3754 if (urb->dev->speed == USB_SPEED_LOW ||
3755 urb->dev->speed == USB_SPEED_FULL)
3758 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3760 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3763 /**** Command Ring Operations ****/
3765 /* Generic function for queueing a command TRB on the command ring.
3766 * Check to make sure there's room on the command ring for one command TRB.
3767 * Also check that there's room reserved for commands that must not fail.
3768 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3769 * then only check for the number of reserved spots.
3770 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3771 * because the command event handler may want to resubmit a failed command.
3773 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3774 u32 field1, u32 field2,
3775 u32 field3, u32 field4, bool command_must_succeed)
3777 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3779 if (xhci->xhc_state & XHCI_STATE_DYING)
3782 if (!command_must_succeed)
3785 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3786 reserved_trbs, GFP_ATOMIC);
3788 xhci_err(xhci, "ERR: No room for command on command ring\n");
3789 if (command_must_succeed)
3790 xhci_err(xhci, "ERR: Reserved TRB counting for "
3791 "unfailable commands failed.\n");
3795 cmd->command_trb = xhci->cmd_ring->enqueue;
3796 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3798 /* if there are no other commands queued we start the timeout timer */
3799 if (xhci->cmd_list.next == &cmd->cmd_list &&
3800 !timer_pending(&xhci->cmd_timer)) {
3801 xhci->current_cmd = cmd;
3802 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3805 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3806 field4 | xhci->cmd_ring->cycle_state);
3810 /* Queue a slot enable or disable request on the command ring */
3811 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3812 u32 trb_type, u32 slot_id)
3814 return queue_command(xhci, cmd, 0, 0, 0,
3815 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3818 /* Queue an address device command TRB */
3819 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3820 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3822 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3823 upper_32_bits(in_ctx_ptr), 0,
3824 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3825 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3828 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3829 u32 field1, u32 field2, u32 field3, u32 field4)
3831 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3834 /* Queue a reset device command TRB */
3835 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3838 return queue_command(xhci, cmd, 0, 0, 0,
3839 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3843 /* Queue a configure endpoint command TRB */
3844 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3845 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3846 u32 slot_id, bool command_must_succeed)
3848 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3849 upper_32_bits(in_ctx_ptr), 0,
3850 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3851 command_must_succeed);
3854 /* Queue an evaluate context command TRB */
3855 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3856 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3858 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3859 upper_32_bits(in_ctx_ptr), 0,
3860 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3861 command_must_succeed);
3865 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3866 * activity on an endpoint that is about to be suspended.
3868 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3869 int slot_id, unsigned int ep_index, int suspend)
3871 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3872 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3873 u32 type = TRB_TYPE(TRB_STOP_RING);
3874 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3876 return queue_command(xhci, cmd, 0, 0, 0,
3877 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3880 /* Set Transfer Ring Dequeue Pointer command */
3881 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3882 unsigned int slot_id, unsigned int ep_index,
3883 unsigned int stream_id,
3884 struct xhci_dequeue_state *deq_state)
3887 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3888 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3889 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3891 u32 type = TRB_TYPE(TRB_SET_DEQ);
3892 struct xhci_virt_ep *ep;
3893 struct xhci_command *cmd;
3896 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
3897 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3898 deq_state->new_deq_seg,
3899 (unsigned long long)deq_state->new_deq_seg->dma,
3900 deq_state->new_deq_ptr,
3901 (unsigned long long)xhci_trb_virt_to_dma(
3902 deq_state->new_deq_seg, deq_state->new_deq_ptr),
3903 deq_state->new_cycle_state);
3905 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3906 deq_state->new_deq_ptr);
3908 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3909 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3910 deq_state->new_deq_seg, deq_state->new_deq_ptr);
3913 ep = &xhci->devs[slot_id]->eps[ep_index];
3914 if ((ep->ep_state & SET_DEQ_PENDING)) {
3915 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3916 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3920 /* This function gets called from contexts where it cannot sleep */
3921 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
3923 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
3927 ep->queued_deq_seg = deq_state->new_deq_seg;
3928 ep->queued_deq_ptr = deq_state->new_deq_ptr;
3930 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3931 ret = queue_command(xhci, cmd,
3932 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
3933 upper_32_bits(addr), trb_stream_id,
3934 trb_slot_id | trb_ep_index | type, false);
3936 xhci_free_command(xhci, cmd);
3940 /* Stop the TD queueing code from ringing the doorbell until
3941 * this command completes. The HC won't set the dequeue pointer
3942 * if the ring is running, and ringing the doorbell starts the
3945 ep->ep_state |= SET_DEQ_PENDING;
3948 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3949 int slot_id, unsigned int ep_index)
3951 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3952 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3953 u32 type = TRB_TYPE(TRB_RESET_EP);
3955 return queue_command(xhci, cmd, 0, 0, 0,
3956 trb_slot_id | trb_ep_index | type, false);