2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset > TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 xhci_err(xhci, "Stopped the command ring failed, "
306 "maybe the host is dead\n");
307 xhci->xhc_state |= XHCI_STATE_DYING;
316 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
317 unsigned int slot_id,
318 unsigned int ep_index,
319 unsigned int stream_id)
321 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
322 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
323 unsigned int ep_state = ep->ep_state;
325 /* Don't ring the doorbell for this endpoint if there are pending
326 * cancellations because we don't want to interrupt processing.
327 * We don't want to restart any stream rings if there's a set dequeue
328 * pointer command pending because the device can choose to start any
329 * stream once the endpoint is on the HW schedule.
331 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
332 (ep_state & EP_HALTED))
334 writel(DB_VALUE(ep_index, stream_id), db_addr);
335 /* The CPU has better things to do at this point than wait for a
336 * write-posting flush. It'll get there soon enough.
340 /* Ring the doorbell for any rings with pending URBs */
341 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
342 unsigned int slot_id,
343 unsigned int ep_index)
345 unsigned int stream_id;
346 struct xhci_virt_ep *ep;
348 ep = &xhci->devs[slot_id]->eps[ep_index];
350 /* A ring has pending URBs if its TD list is not empty */
351 if (!(ep->ep_state & EP_HAS_STREAMS)) {
352 if (ep->ring && !(list_empty(&ep->ring->td_list)))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
357 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
359 struct xhci_stream_info *stream_info = ep->stream_info;
360 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
361 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
366 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
367 unsigned int slot_id, unsigned int ep_index,
368 unsigned int stream_id)
370 struct xhci_virt_ep *ep;
372 ep = &xhci->devs[slot_id]->eps[ep_index];
373 /* Common case: no streams */
374 if (!(ep->ep_state & EP_HAS_STREAMS))
377 if (stream_id == 0) {
379 "WARN: Slot ID %u, ep index %u has streams, "
380 "but URB has no stream ID.\n",
385 if (stream_id < ep->stream_info->num_streams)
386 return ep->stream_info->stream_rings[stream_id];
389 "WARN: Slot ID %u, ep index %u has "
390 "stream IDs 1 to %u allocated, "
391 "but stream ID %u is requested.\n",
393 ep->stream_info->num_streams - 1,
398 /* Get the right ring for the given URB.
399 * If the endpoint supports streams, boundary check the URB's stream ID.
400 * If the endpoint doesn't support streams, return the singular endpoint ring.
402 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
405 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
406 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
410 * Move the xHC's endpoint ring dequeue pointer past cur_td.
411 * Record the new state of the xHC's endpoint ring dequeue segment,
412 * dequeue pointer, and new consumer cycle state in state.
413 * Update our internal representation of the ring's dequeue pointer.
415 * We do this in three jumps:
416 * - First we update our new ring state to be the same as when the xHC stopped.
417 * - Then we traverse the ring to find the segment that contains
418 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
419 * any link TRBs with the toggle cycle bit set.
420 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
421 * if we've moved it past a link TRB with the toggle cycle bit set.
423 * Some of the uses of xhci_generic_trb are grotty, but if they're done
424 * with correct __le32 accesses they should work fine. Only users of this are
427 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
428 unsigned int slot_id, unsigned int ep_index,
429 unsigned int stream_id, struct xhci_td *cur_td,
430 struct xhci_dequeue_state *state)
432 struct xhci_virt_device *dev = xhci->devs[slot_id];
433 struct xhci_virt_ep *ep = &dev->eps[ep_index];
434 struct xhci_ring *ep_ring;
435 struct xhci_segment *new_seg;
436 union xhci_trb *new_deq;
439 bool cycle_found = false;
440 bool td_last_trb_found = false;
442 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
443 ep_index, stream_id);
445 xhci_warn(xhci, "WARN can't find new dequeue state "
446 "for invalid stream ID %u.\n",
451 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
452 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
453 "Finding endpoint context");
454 /* 4.6.9 the css flag is written to the stream context for streams */
455 if (ep->ep_state & EP_HAS_STREAMS) {
456 struct xhci_stream_ctx *ctx =
457 &ep->stream_info->stream_ctx_array[stream_id];
458 hw_dequeue = le64_to_cpu(ctx->stream_ring);
460 struct xhci_ep_ctx *ep_ctx
461 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
462 hw_dequeue = le64_to_cpu(ep_ctx->deq);
465 new_seg = ep_ring->deq_seg;
466 new_deq = ep_ring->dequeue;
467 state->new_cycle_state = hw_dequeue & 0x1;
470 * We want to find the pointer, segment and cycle state of the new trb
471 * (the one after current TD's last_trb). We know the cycle state at
472 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
476 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
477 == (dma_addr_t)(hw_dequeue & ~0xf)) {
479 if (td_last_trb_found)
482 if (new_deq == cur_td->last_trb)
483 td_last_trb_found = true;
486 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
487 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
488 state->new_cycle_state ^= 0x1;
490 next_trb(xhci, ep_ring, &new_seg, &new_deq);
492 /* Search wrapped around, bail out */
493 if (new_deq == ep->ring->dequeue) {
494 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
495 state->new_deq_seg = NULL;
496 state->new_deq_ptr = NULL;
500 } while (!cycle_found || !td_last_trb_found);
502 state->new_deq_seg = new_seg;
503 state->new_deq_ptr = new_deq;
505 /* Don't update the ring cycle state for the producer (us). */
506 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
507 "Cycle state = 0x%x", state->new_cycle_state);
509 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
510 "New dequeue segment = %p (virtual)",
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
514 "New dequeue pointer = 0x%llx (DMA)",
515 (unsigned long long) addr);
518 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
519 * (The last TRB actually points to the ring enqueue pointer, which is not part
520 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
522 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
523 struct xhci_td *cur_td, bool flip_cycle)
525 struct xhci_segment *cur_seg;
526 union xhci_trb *cur_trb;
528 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
530 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
531 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
532 /* Unchain any chained Link TRBs, but
533 * leave the pointers intact.
535 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
536 /* Flip the cycle bit (link TRBs can't be the first
540 cur_trb->generic.field[3] ^=
541 cpu_to_le32(TRB_CYCLE);
542 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
543 "Cancel (unchain) link TRB");
544 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
545 "Address = %p (0x%llx dma); "
546 "in seg %p (0x%llx dma)",
548 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
550 (unsigned long long)cur_seg->dma);
552 cur_trb->generic.field[0] = 0;
553 cur_trb->generic.field[1] = 0;
554 cur_trb->generic.field[2] = 0;
555 /* Preserve only the cycle bit of this TRB */
556 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
557 /* Flip the cycle bit except on the first or last TRB */
558 if (flip_cycle && cur_trb != cur_td->first_trb &&
559 cur_trb != cur_td->last_trb)
560 cur_trb->generic.field[3] ^=
561 cpu_to_le32(TRB_CYCLE);
562 cur_trb->generic.field[3] |= cpu_to_le32(
563 TRB_TYPE(TRB_TR_NOOP));
564 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
565 "TRB to noop at offset 0x%llx",
567 xhci_trb_virt_to_dma(cur_seg, cur_trb));
569 if (cur_trb == cur_td->last_trb)
574 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
575 struct xhci_virt_ep *ep)
577 ep->ep_state &= ~EP_HALT_PENDING;
578 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
579 * timer is running on another CPU, we don't decrement stop_cmds_pending
580 * (since we didn't successfully stop the watchdog timer).
582 if (del_timer(&ep->stop_cmd_timer))
583 ep->stop_cmds_pending--;
586 /* Must be called with xhci->lock held in interrupt context */
587 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
588 struct xhci_td *cur_td, int status)
592 struct urb_priv *urb_priv;
595 urb_priv = urb->hcpriv;
597 hcd = bus_to_hcd(urb->dev->bus);
599 /* Only giveback urb when this is the last td in urb */
600 if (urb_priv->td_cnt == urb_priv->length) {
601 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
602 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
603 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
604 if (xhci->quirks & XHCI_AMD_PLL_FIX)
605 usb_amd_quirk_pll_enable();
608 usb_hcd_unlink_urb_from_ep(hcd, urb);
610 spin_unlock(&xhci->lock);
611 usb_hcd_giveback_urb(hcd, urb, status);
612 xhci_urb_free_priv(xhci, urb_priv);
613 spin_lock(&xhci->lock);
618 * When we get a command completion for a Stop Endpoint Command, we need to
619 * unlink any cancelled TDs from the ring. There are two ways to do that:
621 * 1. If the HW was in the middle of processing the TD that needs to be
622 * cancelled, then we must move the ring's dequeue pointer past the last TRB
623 * in the TD with a Set Dequeue Pointer Command.
624 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
625 * bit cleared) so that the HW will skip over them.
627 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
628 union xhci_trb *trb, struct xhci_event_cmd *event)
630 unsigned int ep_index;
631 struct xhci_ring *ep_ring;
632 struct xhci_virt_ep *ep;
633 struct list_head *entry;
634 struct xhci_td *cur_td = NULL;
635 struct xhci_td *last_unlinked_td;
637 struct xhci_dequeue_state deq_state;
639 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
640 if (!xhci->devs[slot_id])
641 xhci_warn(xhci, "Stop endpoint command "
642 "completion for disabled slot %u\n",
647 memset(&deq_state, 0, sizeof(deq_state));
648 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
649 ep = &xhci->devs[slot_id]->eps[ep_index];
651 if (list_empty(&ep->cancelled_td_list)) {
652 xhci_stop_watchdog_timer_in_irq(xhci, ep);
653 ep->stopped_td = NULL;
654 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
658 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
659 * We have the xHCI lock, so nothing can modify this list until we drop
660 * it. We're also in the event handler, so we can't get re-interrupted
661 * if another Stop Endpoint command completes
663 list_for_each(entry, &ep->cancelled_td_list) {
664 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
665 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
666 "Removing canceled TD starting at 0x%llx (dma).",
667 (unsigned long long)xhci_trb_virt_to_dma(
668 cur_td->start_seg, cur_td->first_trb));
669 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
671 /* This shouldn't happen unless a driver is mucking
672 * with the stream ID after submission. This will
673 * leave the TD on the hardware ring, and the hardware
674 * will try to execute it, and may access a buffer
675 * that has already been freed. In the best case, the
676 * hardware will execute it, and the event handler will
677 * ignore the completion event for that TD, since it was
678 * removed from the td_list for that endpoint. In
679 * short, don't muck with the stream ID after
682 xhci_warn(xhci, "WARN Cancelled URB %p "
683 "has invalid stream ID %u.\n",
685 cur_td->urb->stream_id);
686 goto remove_finished_td;
689 * If we stopped on the TD we need to cancel, then we have to
690 * move the xHC endpoint ring dequeue pointer past this TD.
692 if (cur_td == ep->stopped_td)
693 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
694 cur_td->urb->stream_id,
697 td_to_noop(xhci, ep_ring, cur_td, false);
700 * The event handler won't see a completion for this TD anymore,
701 * so remove it from the endpoint ring's TD list. Keep it in
702 * the cancelled TD list for URB completion later.
704 list_del_init(&cur_td->td_list);
706 last_unlinked_td = cur_td;
707 xhci_stop_watchdog_timer_in_irq(xhci, ep);
709 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
710 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
711 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
712 ep->stopped_td->urb->stream_id, &deq_state);
713 xhci_ring_cmd_db(xhci);
715 /* Otherwise ring the doorbell(s) to restart queued transfers */
716 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
719 /* Clear stopped_td if endpoint is not halted */
720 if (!(ep->ep_state & EP_HALTED))
721 ep->stopped_td = NULL;
724 * Drop the lock and complete the URBs in the cancelled TD list.
725 * New TDs to be cancelled might be added to the end of the list before
726 * we can complete all the URBs for the TDs we already unlinked.
727 * So stop when we've completed the URB for the last TD we unlinked.
730 cur_td = list_entry(ep->cancelled_td_list.next,
731 struct xhci_td, cancelled_td_list);
732 list_del_init(&cur_td->cancelled_td_list);
734 /* Clean up the cancelled URB */
735 /* Doesn't matter what we pass for status, since the core will
736 * just overwrite it (because the URB has been unlinked).
738 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
740 /* Stop processing the cancelled list if the watchdog timer is
743 if (xhci->xhc_state & XHCI_STATE_DYING)
745 } while (cur_td != last_unlinked_td);
747 /* Return to the event handler with xhci->lock re-acquired */
750 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
752 struct xhci_td *cur_td;
754 while (!list_empty(&ring->td_list)) {
755 cur_td = list_first_entry(&ring->td_list,
756 struct xhci_td, td_list);
757 list_del_init(&cur_td->td_list);
758 if (!list_empty(&cur_td->cancelled_td_list))
759 list_del_init(&cur_td->cancelled_td_list);
760 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
764 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
765 int slot_id, int ep_index)
767 struct xhci_td *cur_td;
768 struct xhci_virt_ep *ep;
769 struct xhci_ring *ring;
771 ep = &xhci->devs[slot_id]->eps[ep_index];
772 if ((ep->ep_state & EP_HAS_STREAMS) ||
773 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
776 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
778 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
779 "Killing URBs for slot ID %u, ep index %u, stream %u",
780 slot_id, ep_index, stream_id + 1);
781 xhci_kill_ring_urbs(xhci,
782 ep->stream_info->stream_rings[stream_id]);
788 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
789 "Killing URBs for slot ID %u, ep index %u",
791 xhci_kill_ring_urbs(xhci, ring);
793 while (!list_empty(&ep->cancelled_td_list)) {
794 cur_td = list_first_entry(&ep->cancelled_td_list,
795 struct xhci_td, cancelled_td_list);
796 list_del_init(&cur_td->cancelled_td_list);
797 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
801 /* Watchdog timer function for when a stop endpoint command fails to complete.
802 * In this case, we assume the host controller is broken or dying or dead. The
803 * host may still be completing some other events, so we have to be careful to
804 * let the event ring handler and the URB dequeueing/enqueueing functions know
805 * through xhci->state.
807 * The timer may also fire if the host takes a very long time to respond to the
808 * command, and the stop endpoint command completion handler cannot delete the
809 * timer before the timer function is called. Another endpoint cancellation may
810 * sneak in before the timer function can grab the lock, and that may queue
811 * another stop endpoint command and add the timer back. So we cannot use a
812 * simple flag to say whether there is a pending stop endpoint command for a
813 * particular endpoint.
815 * Instead we use a combination of that flag and a counter for the number of
816 * pending stop endpoint commands. If the timer is the tail end of the last
817 * stop endpoint command, and the endpoint's command is still pending, we assume
820 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
822 struct xhci_hcd *xhci;
823 struct xhci_virt_ep *ep;
827 ep = (struct xhci_virt_ep *) arg;
830 spin_lock_irqsave(&xhci->lock, flags);
832 ep->stop_cmds_pending--;
833 if (xhci->xhc_state & XHCI_STATE_DYING) {
834 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
835 "Stop EP timer ran, but another timer marked "
836 "xHCI as DYING, exiting.");
837 spin_unlock_irqrestore(&xhci->lock, flags);
840 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
841 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
842 "Stop EP timer ran, but no command pending, "
844 spin_unlock_irqrestore(&xhci->lock, flags);
848 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
849 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
850 /* Oops, HC is dead or dying or at least not responding to the stop
853 xhci->xhc_state |= XHCI_STATE_DYING;
854 /* Disable interrupts from the host controller and start halting it */
856 spin_unlock_irqrestore(&xhci->lock, flags);
858 ret = xhci_halt(xhci);
860 spin_lock_irqsave(&xhci->lock, flags);
862 /* This is bad; the host is not responding to commands and it's
863 * not allowing itself to be halted. At least interrupts are
864 * disabled. If we call usb_hc_died(), it will attempt to
865 * disconnect all device drivers under this host. Those
866 * disconnect() methods will wait for all URBs to be unlinked,
867 * so we must complete them.
869 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
870 xhci_warn(xhci, "Completing active URBs anyway.\n");
871 /* We could turn all TDs on the rings to no-ops. This won't
872 * help if the host has cached part of the ring, and is slow if
873 * we want to preserve the cycle bit. Skip it and hope the host
874 * doesn't touch the memory.
877 for (i = 0; i < MAX_HC_SLOTS; i++) {
880 for (j = 0; j < 31; j++)
881 xhci_kill_endpoint_urbs(xhci, i, j);
883 spin_unlock_irqrestore(&xhci->lock, flags);
884 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
885 "Calling usb_hc_died()");
886 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
887 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
888 "xHCI host controller is dead.");
892 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
893 struct xhci_virt_device *dev,
894 struct xhci_ring *ep_ring,
895 unsigned int ep_index)
897 union xhci_trb *dequeue_temp;
898 int num_trbs_free_temp;
901 num_trbs_free_temp = ep_ring->num_trbs_free;
902 dequeue_temp = ep_ring->dequeue;
904 /* If we get two back-to-back stalls, and the first stalled transfer
905 * ends just before a link TRB, the dequeue pointer will be left on
906 * the link TRB by the code in the while loop. So we have to update
907 * the dequeue pointer one segment further, or we'll jump off
908 * the segment into la-la-land.
910 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
911 ep_ring->deq_seg = ep_ring->deq_seg->next;
912 ep_ring->dequeue = ep_ring->deq_seg->trbs;
915 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
916 /* We have more usable TRBs */
917 ep_ring->num_trbs_free++;
919 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
921 if (ep_ring->dequeue ==
922 dev->eps[ep_index].queued_deq_ptr)
924 ep_ring->deq_seg = ep_ring->deq_seg->next;
925 ep_ring->dequeue = ep_ring->deq_seg->trbs;
927 if (ep_ring->dequeue == dequeue_temp) {
934 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
935 ep_ring->num_trbs_free = num_trbs_free_temp;
940 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
941 * we need to clear the set deq pending flag in the endpoint ring state, so that
942 * the TD queueing code can ring the doorbell again. We also need to ring the
943 * endpoint doorbell to restart the ring, but only if there aren't more
944 * cancellations pending.
946 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
947 union xhci_trb *trb, u32 cmd_comp_code)
949 unsigned int ep_index;
950 unsigned int stream_id;
951 struct xhci_ring *ep_ring;
952 struct xhci_virt_device *dev;
953 struct xhci_virt_ep *ep;
954 struct xhci_ep_ctx *ep_ctx;
955 struct xhci_slot_ctx *slot_ctx;
957 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
958 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
959 dev = xhci->devs[slot_id];
960 ep = &dev->eps[ep_index];
962 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
964 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
966 /* XXX: Harmless??? */
970 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
971 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
973 if (cmd_comp_code != COMP_SUCCESS) {
974 unsigned int ep_state;
975 unsigned int slot_state;
977 switch (cmd_comp_code) {
979 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
982 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
983 ep_state = le32_to_cpu(ep_ctx->ep_info);
984 ep_state &= EP_STATE_MASK;
985 slot_state = le32_to_cpu(slot_ctx->dev_state);
986 slot_state = GET_SLOT_STATE(slot_state);
987 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
988 "Slot state = %u, EP state = %u",
989 slot_state, ep_state);
992 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
996 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1000 /* OK what do we do now? The endpoint state is hosed, and we
1001 * should never get to this point if the synchronization between
1002 * queueing, and endpoint state are correct. This might happen
1003 * if the device gets disconnected after we've finished
1004 * cancelling URBs, which might not be an error...
1008 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1009 if (ep->ep_state & EP_HAS_STREAMS) {
1010 struct xhci_stream_ctx *ctx =
1011 &ep->stream_info->stream_ctx_array[stream_id];
1012 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1014 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1016 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1017 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1018 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1019 ep->queued_deq_ptr) == deq) {
1020 /* Update the ring's dequeue segment and dequeue pointer
1021 * to reflect the new position.
1023 update_ring_for_set_deq_completion(xhci, dev,
1026 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1027 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1028 ep->queued_deq_seg, ep->queued_deq_ptr);
1033 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1034 dev->eps[ep_index].queued_deq_seg = NULL;
1035 dev->eps[ep_index].queued_deq_ptr = NULL;
1036 /* Restart any rings with pending URBs */
1037 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1040 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1041 union xhci_trb *trb, u32 cmd_comp_code)
1043 unsigned int ep_index;
1045 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1046 /* This command will only fail if the endpoint wasn't halted,
1047 * but we don't care.
1049 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1050 "Ignoring reset ep completion code of %u", cmd_comp_code);
1052 /* HW with the reset endpoint quirk needs to have a configure endpoint
1053 * command complete before the endpoint can be used. Queue that here
1054 * because the HW can't handle two commands being queued in a row.
1056 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1057 struct xhci_command *command;
1058 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1060 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1063 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1064 "Queueing configure endpoint command");
1065 xhci_queue_configure_endpoint(xhci, command,
1066 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1068 xhci_ring_cmd_db(xhci);
1070 /* Clear our internal halted state and restart the ring(s) */
1071 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1072 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1076 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1079 if (cmd_comp_code == COMP_SUCCESS)
1080 xhci->slot_id = slot_id;
1085 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1087 struct xhci_virt_device *virt_dev;
1089 virt_dev = xhci->devs[slot_id];
1092 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1093 /* Delete default control endpoint resources */
1094 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1095 xhci_free_virt_device(xhci, slot_id);
1098 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1099 struct xhci_event_cmd *event, u32 cmd_comp_code)
1101 struct xhci_virt_device *virt_dev;
1102 struct xhci_input_control_ctx *ctrl_ctx;
1103 unsigned int ep_index;
1104 unsigned int ep_state;
1105 u32 add_flags, drop_flags;
1108 * Configure endpoint commands can come from the USB core
1109 * configuration or alt setting changes, or because the HW
1110 * needed an extra configure endpoint command after a reset
1111 * endpoint command or streams were being configured.
1112 * If the command was for a halted endpoint, the xHCI driver
1113 * is not waiting on the configure endpoint command.
1115 virt_dev = xhci->devs[slot_id];
1116 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1118 xhci_warn(xhci, "Could not get input context, bad type.\n");
1122 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1123 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1124 /* Input ctx add_flags are the endpoint index plus one */
1125 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1127 /* A usb_set_interface() call directly after clearing a halted
1128 * condition may race on this quirky hardware. Not worth
1129 * worrying about, since this is prototype hardware. Not sure
1130 * if this will work for streams, but streams support was
1131 * untested on this prototype.
1133 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1134 ep_index != (unsigned int) -1 &&
1135 add_flags - SLOT_FLAG == drop_flags) {
1136 ep_state = virt_dev->eps[ep_index].ep_state;
1137 if (!(ep_state & EP_HALTED))
1139 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1140 "Completed config ep cmd - "
1141 "last ep index = %d, state = %d",
1142 ep_index, ep_state);
1143 /* Clear internal halted state and restart ring(s) */
1144 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1145 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1151 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1152 struct xhci_event_cmd *event)
1154 xhci_dbg(xhci, "Completed reset device command.\n");
1155 if (!xhci->devs[slot_id])
1156 xhci_warn(xhci, "Reset device command completion "
1157 "for disabled slot %u\n", slot_id);
1160 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1161 struct xhci_event_cmd *event)
1163 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1164 xhci->error_bitmask |= 1 << 6;
1167 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1168 "NEC firmware version %2x.%02x",
1169 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1170 NEC_FW_MINOR(le32_to_cpu(event->status)));
1173 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1175 list_del(&cmd->cmd_list);
1177 if (cmd->completion) {
1178 cmd->status = status;
1179 complete(cmd->completion);
1185 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1187 struct xhci_command *cur_cmd, *tmp_cmd;
1188 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1189 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1193 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1194 * If there are other commands waiting then restart the ring and kick the timer.
1195 * This must be called with command ring stopped and xhci->lock held.
1197 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1198 struct xhci_command *cur_cmd)
1200 struct xhci_command *i_cmd, *tmp_cmd;
1203 /* Turn all aborted commands in list to no-ops, then restart */
1204 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1207 if (i_cmd->status != COMP_CMD_ABORT)
1210 i_cmd->status = COMP_CMD_STOP;
1212 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1213 i_cmd->command_trb);
1214 /* get cycle state from the original cmd trb */
1215 cycle_state = le32_to_cpu(
1216 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1217 /* modify the command trb to no-op command */
1218 i_cmd->command_trb->generic.field[0] = 0;
1219 i_cmd->command_trb->generic.field[1] = 0;
1220 i_cmd->command_trb->generic.field[2] = 0;
1221 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1222 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1225 * caller waiting for completion is called when command
1226 * completion event is received for these no-op commands
1230 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1232 /* ring command ring doorbell to restart the command ring */
1233 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1234 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1235 xhci->current_cmd = cur_cmd;
1236 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1237 xhci_ring_cmd_db(xhci);
1243 void xhci_handle_command_timeout(unsigned long data)
1245 struct xhci_hcd *xhci;
1247 unsigned long flags;
1249 struct xhci_command *cur_cmd = NULL;
1250 xhci = (struct xhci_hcd *) data;
1252 /* mark this command to be cancelled */
1253 spin_lock_irqsave(&xhci->lock, flags);
1254 if (xhci->current_cmd) {
1255 cur_cmd = xhci->current_cmd;
1256 cur_cmd->status = COMP_CMD_ABORT;
1260 /* Make sure command ring is running before aborting it */
1261 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1262 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1263 (hw_ring_state & CMD_RING_RUNNING)) {
1265 spin_unlock_irqrestore(&xhci->lock, flags);
1266 xhci_dbg(xhci, "Command timeout\n");
1267 ret = xhci_abort_cmd_ring(xhci);
1268 if (unlikely(ret == -ESHUTDOWN)) {
1269 xhci_err(xhci, "Abort command ring failed\n");
1270 xhci_cleanup_command_queue(xhci);
1271 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1272 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1276 /* command timeout on stopped ring, ring can't be aborted */
1277 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1278 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1279 spin_unlock_irqrestore(&xhci->lock, flags);
1283 static void handle_cmd_completion(struct xhci_hcd *xhci,
1284 struct xhci_event_cmd *event)
1286 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1288 dma_addr_t cmd_dequeue_dma;
1290 union xhci_trb *cmd_trb;
1291 struct xhci_command *cmd;
1294 cmd_dma = le64_to_cpu(event->cmd_trb);
1295 cmd_trb = xhci->cmd_ring->dequeue;
1296 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1298 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1299 if (cmd_dequeue_dma == 0) {
1300 xhci->error_bitmask |= 1 << 4;
1303 /* Does the DMA address match our internal dequeue pointer address? */
1304 if (cmd_dma != (u64) cmd_dequeue_dma) {
1305 xhci->error_bitmask |= 1 << 5;
1309 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1311 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1313 "Command completion event does not match command\n");
1317 del_timer(&xhci->cmd_timer);
1319 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1321 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1323 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1324 if (cmd_comp_code == COMP_CMD_STOP) {
1325 xhci_handle_stopped_cmd_ring(xhci, cmd);
1329 * Host aborted the command ring, check if the current command was
1330 * supposed to be aborted, otherwise continue normally.
1331 * The command ring is stopped now, but the xHC will issue a Command
1332 * Ring Stopped event which will cause us to restart it.
1334 if (cmd_comp_code == COMP_CMD_ABORT) {
1335 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1336 if (cmd->status == COMP_CMD_ABORT)
1340 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1342 case TRB_ENABLE_SLOT:
1343 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1345 case TRB_DISABLE_SLOT:
1346 xhci_handle_cmd_disable_slot(xhci, slot_id);
1349 if (!cmd->completion)
1350 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1353 case TRB_EVAL_CONTEXT:
1358 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1359 le32_to_cpu(cmd_trb->generic.field[3])));
1360 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1363 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1364 le32_to_cpu(cmd_trb->generic.field[3])));
1365 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1368 /* Is this an aborted command turned to NO-OP? */
1369 if (cmd->status == COMP_CMD_STOP)
1370 cmd_comp_code = COMP_CMD_STOP;
1373 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1374 le32_to_cpu(cmd_trb->generic.field[3])));
1375 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1378 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1379 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1381 slot_id = TRB_TO_SLOT_ID(
1382 le32_to_cpu(cmd_trb->generic.field[3]));
1383 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1385 case TRB_NEC_GET_FW:
1386 xhci_handle_cmd_nec_get_fw(xhci, event);
1389 /* Skip over unknown commands on the event ring */
1390 xhci->error_bitmask |= 1 << 6;
1394 /* restart timer if this wasn't the last command */
1395 if (cmd->cmd_list.next != &xhci->cmd_list) {
1396 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1397 struct xhci_command, cmd_list);
1398 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1402 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1404 inc_deq(xhci, xhci->cmd_ring);
1407 static void handle_vendor_event(struct xhci_hcd *xhci,
1408 union xhci_trb *event)
1412 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1413 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1414 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1415 handle_cmd_completion(xhci, &event->event_cmd);
1418 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1419 * port registers -- USB 3.0 and USB 2.0).
1421 * Returns a zero-based port number, which is suitable for indexing into each of
1422 * the split roothubs' port arrays and bus state arrays.
1423 * Add one to it in order to call xhci_find_slot_id_by_port.
1425 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1426 struct xhci_hcd *xhci, u32 port_id)
1429 unsigned int num_similar_speed_ports = 0;
1431 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1432 * and usb2_ports are 0-based indexes. Count the number of similar
1433 * speed ports, up to 1 port before this port.
1435 for (i = 0; i < (port_id - 1); i++) {
1436 u8 port_speed = xhci->port_array[i];
1439 * Skip ports that don't have known speeds, or have duplicate
1440 * Extended Capabilities port speed entries.
1442 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1446 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1447 * 1.1 ports are under the USB 2.0 hub. If the port speed
1448 * matches the device speed, it's a similar speed port.
1450 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1451 num_similar_speed_ports++;
1453 return num_similar_speed_ports;
1456 static void handle_device_notification(struct xhci_hcd *xhci,
1457 union xhci_trb *event)
1460 struct usb_device *udev;
1462 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1463 if (!xhci->devs[slot_id]) {
1464 xhci_warn(xhci, "Device Notification event for "
1465 "unused slot %u\n", slot_id);
1469 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1471 udev = xhci->devs[slot_id]->udev;
1472 if (udev && udev->parent)
1473 usb_wakeup_notification(udev->parent, udev->portnum);
1476 static void handle_port_status(struct xhci_hcd *xhci,
1477 union xhci_trb *event)
1479 struct usb_hcd *hcd;
1484 unsigned int faked_port_index;
1486 struct xhci_bus_state *bus_state;
1487 __le32 __iomem **port_array;
1488 bool bogus_port_status = false;
1490 /* Port status change events always have a successful completion code */
1491 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1492 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1493 xhci->error_bitmask |= 1 << 8;
1495 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1496 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1498 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1499 if ((port_id <= 0) || (port_id > max_ports)) {
1500 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1501 inc_deq(xhci, xhci->event_ring);
1505 /* Figure out which usb_hcd this port is attached to:
1506 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1508 major_revision = xhci->port_array[port_id - 1];
1510 /* Find the right roothub. */
1511 hcd = xhci_to_hcd(xhci);
1512 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1513 hcd = xhci->shared_hcd;
1515 if (major_revision == 0) {
1516 xhci_warn(xhci, "Event for port %u not in "
1517 "Extended Capabilities, ignoring.\n",
1519 bogus_port_status = true;
1522 if (major_revision == DUPLICATE_ENTRY) {
1523 xhci_warn(xhci, "Event for port %u duplicated in"
1524 "Extended Capabilities, ignoring.\n",
1526 bogus_port_status = true;
1531 * Hardware port IDs reported by a Port Status Change Event include USB
1532 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1533 * resume event, but we first need to translate the hardware port ID
1534 * into the index into the ports on the correct split roothub, and the
1535 * correct bus_state structure.
1537 bus_state = &xhci->bus_state[hcd_index(hcd)];
1538 if (hcd->speed == HCD_USB3)
1539 port_array = xhci->usb3_ports;
1541 port_array = xhci->usb2_ports;
1542 /* Find the faked port hub number */
1543 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1546 temp = readl(port_array[faked_port_index]);
1547 if (hcd->state == HC_STATE_SUSPENDED) {
1548 xhci_dbg(xhci, "resume root hub\n");
1549 usb_hcd_resume_root_hub(hcd);
1552 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1553 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1555 temp1 = readl(&xhci->op_regs->command);
1556 if (!(temp1 & CMD_RUN)) {
1557 xhci_warn(xhci, "xHC is not running.\n");
1561 if (DEV_SUPERSPEED(temp)) {
1562 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1563 /* Set a flag to say the port signaled remote wakeup,
1564 * so we can tell the difference between the end of
1565 * device and host initiated resume.
1567 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1568 xhci_test_and_clear_bit(xhci, port_array,
1569 faked_port_index, PORT_PLC);
1570 xhci_set_link_state(xhci, port_array, faked_port_index,
1572 /* Need to wait until the next link state change
1573 * indicates the device is actually in U0.
1575 bogus_port_status = true;
1578 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1579 bus_state->resume_done[faked_port_index] = jiffies +
1580 msecs_to_jiffies(20);
1581 set_bit(faked_port_index, &bus_state->resuming_ports);
1582 mod_timer(&hcd->rh_timer,
1583 bus_state->resume_done[faked_port_index]);
1584 /* Do the rest in GetPortStatus */
1588 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1589 DEV_SUPERSPEED(temp)) {
1590 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1591 /* We've just brought the device into U0 through either the
1592 * Resume state after a device remote wakeup, or through the
1593 * U3Exit state after a host-initiated resume. If it's a device
1594 * initiated remote wake, don't pass up the link state change,
1595 * so the roothub behavior is consistent with external
1596 * USB 3.0 hub behavior.
1598 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1599 faked_port_index + 1);
1600 if (slot_id && xhci->devs[slot_id])
1601 xhci_ring_device(xhci, slot_id);
1602 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1603 bus_state->port_remote_wakeup &=
1604 ~(1 << faked_port_index);
1605 xhci_test_and_clear_bit(xhci, port_array,
1606 faked_port_index, PORT_PLC);
1607 usb_wakeup_notification(hcd->self.root_hub,
1608 faked_port_index + 1);
1609 bogus_port_status = true;
1615 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1616 * RExit to a disconnect state). If so, let the the driver know it's
1617 * out of the RExit state.
1619 if (!DEV_SUPERSPEED(temp) &&
1620 test_and_clear_bit(faked_port_index,
1621 &bus_state->rexit_ports)) {
1622 complete(&bus_state->rexit_done[faked_port_index]);
1623 bogus_port_status = true;
1627 if (hcd->speed != HCD_USB3)
1628 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1632 /* Update event ring dequeue pointer before dropping the lock */
1633 inc_deq(xhci, xhci->event_ring);
1635 /* Don't make the USB core poll the roothub if we got a bad port status
1636 * change event. Besides, at that point we can't tell which roothub
1637 * (USB 2.0 or USB 3.0) to kick.
1639 if (bogus_port_status)
1643 * xHCI port-status-change events occur when the "or" of all the
1644 * status-change bits in the portsc register changes from 0 to 1.
1645 * New status changes won't cause an event if any other change
1646 * bits are still set. When an event occurs, switch over to
1647 * polling to avoid losing status changes.
1649 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1650 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1651 spin_unlock(&xhci->lock);
1652 /* Pass this up to the core */
1653 usb_hcd_poll_rh_status(hcd);
1654 spin_lock(&xhci->lock);
1658 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1659 * at end_trb, which may be in another segment. If the suspect DMA address is a
1660 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1663 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1664 struct xhci_segment *start_seg,
1665 union xhci_trb *start_trb,
1666 union xhci_trb *end_trb,
1667 dma_addr_t suspect_dma,
1670 dma_addr_t start_dma;
1671 dma_addr_t end_seg_dma;
1672 dma_addr_t end_trb_dma;
1673 struct xhci_segment *cur_seg;
1675 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1676 cur_seg = start_seg;
1681 /* We may get an event for a Link TRB in the middle of a TD */
1682 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1683 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1684 /* If the end TRB isn't in this segment, this is set to 0 */
1685 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1689 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1690 (unsigned long long)suspect_dma,
1691 (unsigned long long)start_dma,
1692 (unsigned long long)end_trb_dma,
1693 (unsigned long long)cur_seg->dma,
1694 (unsigned long long)end_seg_dma);
1696 if (end_trb_dma > 0) {
1697 /* The end TRB is in this segment, so suspect should be here */
1698 if (start_dma <= end_trb_dma) {
1699 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1702 /* Case for one segment with
1703 * a TD wrapped around to the top
1705 if ((suspect_dma >= start_dma &&
1706 suspect_dma <= end_seg_dma) ||
1707 (suspect_dma >= cur_seg->dma &&
1708 suspect_dma <= end_trb_dma))
1713 /* Might still be somewhere in this segment */
1714 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1717 cur_seg = cur_seg->next;
1718 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1719 } while (cur_seg != start_seg);
1724 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1725 unsigned int slot_id, unsigned int ep_index,
1726 unsigned int stream_id,
1727 struct xhci_td *td, union xhci_trb *event_trb)
1729 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1730 struct xhci_command *command;
1731 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1735 ep->ep_state |= EP_HALTED;
1736 ep->stopped_td = td;
1737 ep->stopped_stream = stream_id;
1739 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1740 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1742 ep->stopped_td = NULL;
1743 ep->stopped_stream = 0;
1745 xhci_ring_cmd_db(xhci);
1748 /* Check if an error has halted the endpoint ring. The class driver will
1749 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1750 * However, a babble and other errors also halt the endpoint ring, and the class
1751 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1752 * Ring Dequeue Pointer command manually.
1754 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1755 struct xhci_ep_ctx *ep_ctx,
1756 unsigned int trb_comp_code)
1758 /* TRB completion codes that may require a manual halt cleanup */
1759 if (trb_comp_code == COMP_TX_ERR ||
1760 trb_comp_code == COMP_BABBLE ||
1761 trb_comp_code == COMP_SPLIT_ERR)
1762 /* The 0.96 spec says a babbling control endpoint
1763 * is not halted. The 0.96 spec says it is. Some HW
1764 * claims to be 0.95 compliant, but it halts the control
1765 * endpoint anyway. Check if a babble halted the
1768 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1769 cpu_to_le32(EP_STATE_HALTED))
1775 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1777 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1778 /* Vendor defined "informational" completion code,
1779 * treat as not-an-error.
1781 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1783 xhci_dbg(xhci, "Treating code as success.\n");
1790 * Finish the td processing, remove the td from td list;
1791 * Return 1 if the urb can be given back.
1793 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1794 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1795 struct xhci_virt_ep *ep, int *status, bool skip)
1797 struct xhci_virt_device *xdev;
1798 struct xhci_ring *ep_ring;
1799 unsigned int slot_id;
1801 struct urb *urb = NULL;
1802 struct xhci_ep_ctx *ep_ctx;
1804 struct urb_priv *urb_priv;
1807 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1808 xdev = xhci->devs[slot_id];
1809 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1810 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1811 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1812 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1817 if (trb_comp_code == COMP_STOP_INVAL ||
1818 trb_comp_code == COMP_STOP) {
1819 /* The Endpoint Stop Command completion will take care of any
1820 * stopped TDs. A stopped TD may be restarted, so don't update
1821 * the ring dequeue pointer or take this TD off any lists yet.
1823 ep->stopped_td = td;
1826 if (trb_comp_code == COMP_STALL) {
1827 /* The transfer is completed from the driver's
1828 * perspective, but we need to issue a set dequeue
1829 * command for this stalled endpoint to move the dequeue
1830 * pointer past the TD. We can't do that here because
1831 * the halt condition must be cleared first. Let the
1832 * USB class driver clear the stall later.
1834 ep->stopped_td = td;
1835 ep->stopped_stream = ep_ring->stream_id;
1836 } else if (xhci_requires_manual_halt_cleanup(xhci,
1837 ep_ctx, trb_comp_code)) {
1838 /* Other types of errors halt the endpoint, but the
1839 * class driver doesn't call usb_reset_endpoint() unless
1840 * the error is -EPIPE. Clear the halted status in the
1841 * xHCI hardware manually.
1843 xhci_cleanup_halted_endpoint(xhci,
1844 slot_id, ep_index, ep_ring->stream_id,
1847 /* Update ring dequeue pointer */
1848 while (ep_ring->dequeue != td->last_trb)
1849 inc_deq(xhci, ep_ring);
1850 inc_deq(xhci, ep_ring);
1854 /* Clean up the endpoint's TD list */
1856 urb_priv = urb->hcpriv;
1858 /* Do one last check of the actual transfer length.
1859 * If the host controller said we transferred more data than
1860 * the buffer length, urb->actual_length will be a very big
1861 * number (since it's unsigned). Play it safe and say we didn't
1862 * transfer anything.
1864 if (urb->actual_length > urb->transfer_buffer_length) {
1865 xhci_warn(xhci, "URB transfer length is wrong, "
1866 "xHC issue? req. len = %u, "
1868 urb->transfer_buffer_length,
1869 urb->actual_length);
1870 urb->actual_length = 0;
1871 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1872 *status = -EREMOTEIO;
1876 list_del_init(&td->td_list);
1877 /* Was this TD slated to be cancelled but completed anyway? */
1878 if (!list_empty(&td->cancelled_td_list))
1879 list_del_init(&td->cancelled_td_list);
1882 /* Giveback the urb when all the tds are completed */
1883 if (urb_priv->td_cnt == urb_priv->length) {
1885 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1886 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1887 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1889 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1890 usb_amd_quirk_pll_enable();
1900 * Process control tds, update urb status and actual_length.
1902 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1903 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1904 struct xhci_virt_ep *ep, int *status)
1906 struct xhci_virt_device *xdev;
1907 struct xhci_ring *ep_ring;
1908 unsigned int slot_id;
1910 struct xhci_ep_ctx *ep_ctx;
1913 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1914 xdev = xhci->devs[slot_id];
1915 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1916 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1917 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1918 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1920 switch (trb_comp_code) {
1922 if (event_trb == ep_ring->dequeue) {
1923 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1924 "without IOC set??\n");
1925 *status = -ESHUTDOWN;
1926 } else if (event_trb != td->last_trb) {
1927 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1928 "without IOC set??\n");
1929 *status = -ESHUTDOWN;
1935 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1936 *status = -EREMOTEIO;
1940 case COMP_STOP_INVAL:
1942 return finish_td(xhci, td, event_trb, event, ep, status, false);
1944 if (!xhci_requires_manual_halt_cleanup(xhci,
1945 ep_ctx, trb_comp_code))
1947 xhci_dbg(xhci, "TRB error code %u, "
1948 "halted endpoint index = %u\n",
1949 trb_comp_code, ep_index);
1950 /* else fall through */
1952 /* Did we transfer part of the data (middle) phase? */
1953 if (event_trb != ep_ring->dequeue &&
1954 event_trb != td->last_trb)
1955 td->urb->actual_length =
1956 td->urb->transfer_buffer_length -
1957 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1959 td->urb->actual_length = 0;
1961 xhci_cleanup_halted_endpoint(xhci,
1962 slot_id, ep_index, 0, td, event_trb);
1963 return finish_td(xhci, td, event_trb, event, ep, status, true);
1966 * Did we transfer any data, despite the errors that might have
1967 * happened? I.e. did we get past the setup stage?
1969 if (event_trb != ep_ring->dequeue) {
1970 /* The event was for the status stage */
1971 if (event_trb == td->last_trb) {
1972 if (td->urb->actual_length != 0) {
1973 /* Don't overwrite a previously set error code
1975 if ((*status == -EINPROGRESS || *status == 0) &&
1976 (td->urb->transfer_flags
1977 & URB_SHORT_NOT_OK))
1978 /* Did we already see a short data
1980 *status = -EREMOTEIO;
1982 td->urb->actual_length =
1983 td->urb->transfer_buffer_length;
1986 /* Maybe the event was for the data stage? */
1987 td->urb->actual_length =
1988 td->urb->transfer_buffer_length -
1989 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1990 xhci_dbg(xhci, "Waiting for status "
1996 return finish_td(xhci, td, event_trb, event, ep, status, false);
2000 * Process isochronous tds, update urb packet status and actual_length.
2002 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2003 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2004 struct xhci_virt_ep *ep, int *status)
2006 struct xhci_ring *ep_ring;
2007 struct urb_priv *urb_priv;
2010 union xhci_trb *cur_trb;
2011 struct xhci_segment *cur_seg;
2012 struct usb_iso_packet_descriptor *frame;
2014 bool skip_td = false;
2016 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2017 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2018 urb_priv = td->urb->hcpriv;
2019 idx = urb_priv->td_cnt;
2020 frame = &td->urb->iso_frame_desc[idx];
2022 /* handle completion code */
2023 switch (trb_comp_code) {
2025 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2029 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2030 trb_comp_code = COMP_SHORT_TX;
2032 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2036 frame->status = -ECOMM;
2039 case COMP_BUFF_OVER:
2041 frame->status = -EOVERFLOW;
2047 frame->status = -EPROTO;
2051 case COMP_STOP_INVAL:
2058 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2059 frame->actual_length = frame->length;
2060 td->urb->actual_length += frame->length;
2062 for (cur_trb = ep_ring->dequeue,
2063 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2064 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2065 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2066 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2067 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2069 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2070 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2072 if (trb_comp_code != COMP_STOP_INVAL) {
2073 frame->actual_length = len;
2074 td->urb->actual_length += len;
2078 return finish_td(xhci, td, event_trb, event, ep, status, false);
2081 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2082 struct xhci_transfer_event *event,
2083 struct xhci_virt_ep *ep, int *status)
2085 struct xhci_ring *ep_ring;
2086 struct urb_priv *urb_priv;
2087 struct usb_iso_packet_descriptor *frame;
2090 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2091 urb_priv = td->urb->hcpriv;
2092 idx = urb_priv->td_cnt;
2093 frame = &td->urb->iso_frame_desc[idx];
2095 /* The transfer is partly done. */
2096 frame->status = -EXDEV;
2098 /* calc actual length */
2099 frame->actual_length = 0;
2101 /* Update ring dequeue pointer */
2102 while (ep_ring->dequeue != td->last_trb)
2103 inc_deq(xhci, ep_ring);
2104 inc_deq(xhci, ep_ring);
2106 return finish_td(xhci, td, NULL, event, ep, status, true);
2110 * Process bulk and interrupt tds, update urb status and actual_length.
2112 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2113 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2114 struct xhci_virt_ep *ep, int *status)
2116 struct xhci_ring *ep_ring;
2117 union xhci_trb *cur_trb;
2118 struct xhci_segment *cur_seg;
2121 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2122 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2124 switch (trb_comp_code) {
2126 /* Double check that the HW transferred everything. */
2127 if (event_trb != td->last_trb ||
2128 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2129 xhci_warn(xhci, "WARN Successful completion "
2131 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2132 *status = -EREMOTEIO;
2135 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2136 trb_comp_code = COMP_SHORT_TX;
2142 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2143 *status = -EREMOTEIO;
2148 /* Others already handled above */
2151 if (trb_comp_code == COMP_SHORT_TX)
2152 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2153 "%d bytes untransferred\n",
2154 td->urb->ep->desc.bEndpointAddress,
2155 td->urb->transfer_buffer_length,
2156 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2157 /* Fast path - was this the last TRB in the TD for this URB? */
2158 if (event_trb == td->last_trb) {
2159 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2160 td->urb->actual_length =
2161 td->urb->transfer_buffer_length -
2162 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2163 if (td->urb->transfer_buffer_length <
2164 td->urb->actual_length) {
2165 xhci_warn(xhci, "HC gave bad length "
2166 "of %d bytes left\n",
2167 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2168 td->urb->actual_length = 0;
2169 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2170 *status = -EREMOTEIO;
2174 /* Don't overwrite a previously set error code */
2175 if (*status == -EINPROGRESS) {
2176 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2177 *status = -EREMOTEIO;
2182 td->urb->actual_length =
2183 td->urb->transfer_buffer_length;
2184 /* Ignore a short packet completion if the
2185 * untransferred length was zero.
2187 if (*status == -EREMOTEIO)
2191 /* Slow path - walk the list, starting from the dequeue
2192 * pointer, to get the actual length transferred.
2194 td->urb->actual_length = 0;
2195 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2196 cur_trb != event_trb;
2197 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2198 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2199 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2200 td->urb->actual_length +=
2201 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2203 /* If the ring didn't stop on a Link or No-op TRB, add
2204 * in the actual bytes transferred from the Normal TRB
2206 if (trb_comp_code != COMP_STOP_INVAL)
2207 td->urb->actual_length +=
2208 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2209 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2212 return finish_td(xhci, td, event_trb, event, ep, status, false);
2216 * If this function returns an error condition, it means it got a Transfer
2217 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2218 * At this point, the host controller is probably hosed and should be reset.
2220 static int handle_tx_event(struct xhci_hcd *xhci,
2221 struct xhci_transfer_event *event)
2222 __releases(&xhci->lock)
2223 __acquires(&xhci->lock)
2225 struct xhci_virt_device *xdev;
2226 struct xhci_virt_ep *ep;
2227 struct xhci_ring *ep_ring;
2228 unsigned int slot_id;
2230 struct xhci_td *td = NULL;
2231 dma_addr_t event_dma;
2232 struct xhci_segment *event_seg;
2233 union xhci_trb *event_trb;
2234 struct urb *urb = NULL;
2235 int status = -EINPROGRESS;
2236 struct urb_priv *urb_priv;
2237 struct xhci_ep_ctx *ep_ctx;
2238 struct list_head *tmp;
2243 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2244 xdev = xhci->devs[slot_id];
2246 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2247 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2248 (unsigned long long) xhci_trb_virt_to_dma(
2249 xhci->event_ring->deq_seg,
2250 xhci->event_ring->dequeue),
2251 lower_32_bits(le64_to_cpu(event->buffer)),
2252 upper_32_bits(le64_to_cpu(event->buffer)),
2253 le32_to_cpu(event->transfer_len),
2254 le32_to_cpu(event->flags));
2255 xhci_dbg(xhci, "Event ring:\n");
2256 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2260 /* Endpoint ID is 1 based, our index is zero based */
2261 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2262 ep = &xdev->eps[ep_index];
2263 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2264 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2266 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2267 EP_STATE_DISABLED) {
2268 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2269 "or incorrect stream ring\n");
2270 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2271 (unsigned long long) xhci_trb_virt_to_dma(
2272 xhci->event_ring->deq_seg,
2273 xhci->event_ring->dequeue),
2274 lower_32_bits(le64_to_cpu(event->buffer)),
2275 upper_32_bits(le64_to_cpu(event->buffer)),
2276 le32_to_cpu(event->transfer_len),
2277 le32_to_cpu(event->flags));
2278 xhci_dbg(xhci, "Event ring:\n");
2279 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2283 /* Count current td numbers if ep->skip is set */
2285 list_for_each(tmp, &ep_ring->td_list)
2289 event_dma = le64_to_cpu(event->buffer);
2290 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2291 /* Look for common error cases */
2292 switch (trb_comp_code) {
2293 /* Skip codes that require special handling depending on
2297 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2299 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2300 trb_comp_code = COMP_SHORT_TX;
2302 xhci_warn_ratelimited(xhci,
2303 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2307 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2309 case COMP_STOP_INVAL:
2310 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2313 xhci_dbg(xhci, "Stalled endpoint\n");
2314 ep->ep_state |= EP_HALTED;
2318 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2321 case COMP_SPLIT_ERR:
2323 xhci_dbg(xhci, "Transfer error on endpoint\n");
2327 xhci_dbg(xhci, "Babble error on endpoint\n");
2328 status = -EOVERFLOW;
2331 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2335 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2337 case COMP_BUFF_OVER:
2338 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2342 * When the Isoch ring is empty, the xHC will generate
2343 * a Ring Overrun Event for IN Isoch endpoint or Ring
2344 * Underrun Event for OUT Isoch endpoint.
2346 xhci_dbg(xhci, "underrun event on endpoint\n");
2347 if (!list_empty(&ep_ring->td_list))
2348 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2349 "still with TDs queued?\n",
2350 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2354 xhci_dbg(xhci, "overrun event on endpoint\n");
2355 if (!list_empty(&ep_ring->td_list))
2356 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2357 "still with TDs queued?\n",
2358 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2362 xhci_warn(xhci, "WARN: detect an incompatible device");
2365 case COMP_MISSED_INT:
2367 * When encounter missed service error, one or more isoc tds
2368 * may be missed by xHC.
2369 * Set skip flag of the ep_ring; Complete the missed tds as
2370 * short transfer when process the ep_ring next time.
2373 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2376 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2380 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2386 /* This TRB should be in the TD at the head of this ring's
2389 if (list_empty(&ep_ring->td_list)) {
2391 * A stopped endpoint may generate an extra completion
2392 * event if the device was suspended. Don't print
2395 if (!(trb_comp_code == COMP_STOP ||
2396 trb_comp_code == COMP_STOP_INVAL)) {
2397 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2398 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2400 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2401 (le32_to_cpu(event->flags) &
2402 TRB_TYPE_BITMASK)>>10);
2403 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2407 xhci_dbg(xhci, "td_list is empty while skip "
2408 "flag set. Clear skip flag.\n");
2414 /* We've skipped all the TDs on the ep ring when ep->skip set */
2415 if (ep->skip && td_num == 0) {
2417 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2418 "Clear skip flag.\n");
2423 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2427 /* Is this a TRB in the currently executing TD? */
2428 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2429 td->last_trb, event_dma, false);
2432 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2433 * is not in the current TD pointed by ep_ring->dequeue because
2434 * that the hardware dequeue pointer still at the previous TRB
2435 * of the current TD. The previous TRB maybe a Link TD or the
2436 * last TRB of the previous TD. The command completion handle
2437 * will take care the rest.
2439 if (!event_seg && (trb_comp_code == COMP_STOP ||
2440 trb_comp_code == COMP_STOP_INVAL)) {
2447 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2448 /* Some host controllers give a spurious
2449 * successful event after a short transfer.
2452 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2453 ep_ring->last_td_was_short) {
2454 ep_ring->last_td_was_short = false;
2458 /* HC is busted, give up! */
2460 "ERROR Transfer event TRB DMA ptr not "
2461 "part of current TD ep_index %d "
2462 "comp_code %u\n", ep_index,
2464 trb_in_td(xhci, ep_ring->deq_seg,
2465 ep_ring->dequeue, td->last_trb,
2470 ret = skip_isoc_td(xhci, td, event, ep, &status);
2473 if (trb_comp_code == COMP_SHORT_TX)
2474 ep_ring->last_td_was_short = true;
2476 ep_ring->last_td_was_short = false;
2479 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2483 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2484 sizeof(*event_trb)];
2486 * No-op TRB should not trigger interrupts.
2487 * If event_trb is a no-op TRB, it means the
2488 * corresponding TD has been cancelled. Just ignore
2491 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2493 "event_trb is a no-op TRB. Skip it\n");
2497 /* Now update the urb's actual_length and give back to
2500 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2501 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2503 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2504 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2507 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2512 * Do not update event ring dequeue pointer if ep->skip is set.
2513 * Will roll back to continue process missed tds.
2515 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2516 inc_deq(xhci, xhci->event_ring);
2521 urb_priv = urb->hcpriv;
2522 /* Leave the TD around for the reset endpoint function
2523 * to use(but only if it's not a control endpoint,
2524 * since we already queued the Set TR dequeue pointer
2525 * command for stalled control endpoints).
2527 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2528 (trb_comp_code != COMP_STALL &&
2529 trb_comp_code != COMP_BABBLE))
2530 xhci_urb_free_priv(xhci, urb_priv);
2534 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2535 if ((urb->actual_length != urb->transfer_buffer_length &&
2536 (urb->transfer_flags &
2537 URB_SHORT_NOT_OK)) ||
2539 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2540 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2541 "expected = %d, status = %d\n",
2542 urb, urb->actual_length,
2543 urb->transfer_buffer_length,
2545 spin_unlock(&xhci->lock);
2546 /* EHCI, UHCI, and OHCI always unconditionally set the
2547 * urb->status of an isochronous endpoint to 0.
2549 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2551 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2552 spin_lock(&xhci->lock);
2556 * If ep->skip is set, it means there are missed tds on the
2557 * endpoint ring need to take care of.
2558 * Process them as short transfer until reach the td pointed by
2561 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2567 * This function handles all OS-owned events on the event ring. It may drop
2568 * xhci->lock between event processing (e.g. to pass up port status changes).
2569 * Returns >0 for "possibly more events to process" (caller should call again),
2570 * otherwise 0 if done. In future, <0 returns should indicate error code.
2572 static int xhci_handle_event(struct xhci_hcd *xhci)
2574 union xhci_trb *event;
2575 int update_ptrs = 1;
2578 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2579 xhci->error_bitmask |= 1 << 1;
2583 event = xhci->event_ring->dequeue;
2584 /* Does the HC or OS own the TRB? */
2585 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2586 xhci->event_ring->cycle_state) {
2587 xhci->error_bitmask |= 1 << 2;
2592 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2593 * speculative reads of the event's flags/data below.
2596 /* FIXME: Handle more event types. */
2597 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2598 case TRB_TYPE(TRB_COMPLETION):
2599 handle_cmd_completion(xhci, &event->event_cmd);
2601 case TRB_TYPE(TRB_PORT_STATUS):
2602 handle_port_status(xhci, event);
2605 case TRB_TYPE(TRB_TRANSFER):
2606 ret = handle_tx_event(xhci, &event->trans_event);
2608 xhci->error_bitmask |= 1 << 9;
2612 case TRB_TYPE(TRB_DEV_NOTE):
2613 handle_device_notification(xhci, event);
2616 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2618 handle_vendor_event(xhci, event);
2620 xhci->error_bitmask |= 1 << 3;
2622 /* Any of the above functions may drop and re-acquire the lock, so check
2623 * to make sure a watchdog timer didn't mark the host as non-responsive.
2625 if (xhci->xhc_state & XHCI_STATE_DYING) {
2626 xhci_dbg(xhci, "xHCI host dying, returning from "
2627 "event handler.\n");
2632 /* Update SW event ring dequeue pointer */
2633 inc_deq(xhci, xhci->event_ring);
2635 /* Are there more items on the event ring? Caller will call us again to
2642 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2643 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2644 * indicators of an event TRB error, but we check the status *first* to be safe.
2646 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2648 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2651 union xhci_trb *event_ring_deq;
2654 spin_lock(&xhci->lock);
2655 /* Check if the xHC generated the interrupt, or the irq is shared */
2656 status = readl(&xhci->op_regs->status);
2657 if (status == 0xffffffff)
2660 if (!(status & STS_EINT)) {
2661 spin_unlock(&xhci->lock);
2664 if (status & STS_FATAL) {
2665 xhci_warn(xhci, "WARNING: Host System Error\n");
2668 spin_unlock(&xhci->lock);
2673 * Clear the op reg interrupt status first,
2674 * so we can receive interrupts from other MSI-X interrupters.
2675 * Write 1 to clear the interrupt status.
2678 writel(status, &xhci->op_regs->status);
2679 /* FIXME when MSI-X is supported and there are multiple vectors */
2680 /* Clear the MSI-X event interrupt status */
2684 /* Acknowledge the PCI interrupt */
2685 irq_pending = readl(&xhci->ir_set->irq_pending);
2686 irq_pending |= IMAN_IP;
2687 writel(irq_pending, &xhci->ir_set->irq_pending);
2690 if (xhci->xhc_state & XHCI_STATE_DYING) {
2691 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2692 "Shouldn't IRQs be disabled?\n");
2693 /* Clear the event handler busy flag (RW1C);
2694 * the event ring should be empty.
2696 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2697 xhci_write_64(xhci, temp_64 | ERST_EHB,
2698 &xhci->ir_set->erst_dequeue);
2699 spin_unlock(&xhci->lock);
2704 event_ring_deq = xhci->event_ring->dequeue;
2705 /* FIXME this should be a delayed service routine
2706 * that clears the EHB.
2708 while (xhci_handle_event(xhci) > 0) {}
2710 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2711 /* If necessary, update the HW's version of the event ring deq ptr. */
2712 if (event_ring_deq != xhci->event_ring->dequeue) {
2713 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2714 xhci->event_ring->dequeue);
2716 xhci_warn(xhci, "WARN something wrong with SW event "
2717 "ring dequeue ptr.\n");
2718 /* Update HC event ring dequeue pointer */
2719 temp_64 &= ERST_PTR_MASK;
2720 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2723 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2724 temp_64 |= ERST_EHB;
2725 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2727 spin_unlock(&xhci->lock);
2732 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2734 return xhci_irq(hcd);
2737 /**** Endpoint Ring Operations ****/
2740 * Generic function for queueing a TRB on a ring.
2741 * The caller must have checked to make sure there's room on the ring.
2743 * @more_trbs_coming: Will you enqueue more TRBs before calling
2744 * prepare_transfer()?
2746 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2747 bool more_trbs_coming,
2748 u32 field1, u32 field2, u32 field3, u32 field4)
2750 struct xhci_generic_trb *trb;
2752 trb = &ring->enqueue->generic;
2753 trb->field[0] = cpu_to_le32(field1);
2754 trb->field[1] = cpu_to_le32(field2);
2755 trb->field[2] = cpu_to_le32(field3);
2756 trb->field[3] = cpu_to_le32(field4);
2757 inc_enq(xhci, ring, more_trbs_coming);
2761 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2762 * FIXME allocate segments if the ring is full.
2764 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2765 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2767 unsigned int num_trbs_needed;
2769 /* Make sure the endpoint has been added to xHC schedule */
2771 case EP_STATE_DISABLED:
2773 * USB core changed config/interfaces without notifying us,
2774 * or hardware is reporting the wrong state.
2776 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2778 case EP_STATE_ERROR:
2779 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2780 /* FIXME event handling code for error needs to clear it */
2781 /* XXX not sure if this should be -ENOENT or not */
2783 case EP_STATE_HALTED:
2784 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2785 case EP_STATE_STOPPED:
2786 case EP_STATE_RUNNING:
2789 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2791 * FIXME issue Configure Endpoint command to try to get the HC
2792 * back into a known state.
2798 if (room_on_ring(xhci, ep_ring, num_trbs))
2801 if (ep_ring == xhci->cmd_ring) {
2802 xhci_err(xhci, "Do not support expand command ring\n");
2806 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2807 "ERROR no room on ep ring, try ring expansion");
2808 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2809 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2811 xhci_err(xhci, "Ring expansion failed\n");
2816 if (enqueue_is_link_trb(ep_ring)) {
2817 struct xhci_ring *ring = ep_ring;
2818 union xhci_trb *next;
2820 next = ring->enqueue;
2822 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2823 /* If we're not dealing with 0.95 hardware or isoc rings
2824 * on AMD 0.96 host, clear the chain bit.
2826 if (!xhci_link_trb_quirk(xhci) &&
2827 !(ring->type == TYPE_ISOC &&
2828 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2829 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2831 next->link.control |= cpu_to_le32(TRB_CHAIN);
2834 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2836 /* Toggle the cycle bit after the last ring segment. */
2837 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2838 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2840 ring->enq_seg = ring->enq_seg->next;
2841 ring->enqueue = ring->enq_seg->trbs;
2842 next = ring->enqueue;
2849 static int prepare_transfer(struct xhci_hcd *xhci,
2850 struct xhci_virt_device *xdev,
2851 unsigned int ep_index,
2852 unsigned int stream_id,
2853 unsigned int num_trbs,
2855 unsigned int td_index,
2859 struct urb_priv *urb_priv;
2861 struct xhci_ring *ep_ring;
2862 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2864 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2866 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2871 ret = prepare_ring(xhci, ep_ring,
2872 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2873 num_trbs, mem_flags);
2877 urb_priv = urb->hcpriv;
2878 td = urb_priv->td[td_index];
2880 INIT_LIST_HEAD(&td->td_list);
2881 INIT_LIST_HEAD(&td->cancelled_td_list);
2883 if (td_index == 0) {
2884 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2890 /* Add this TD to the tail of the endpoint ring's TD list */
2891 list_add_tail(&td->td_list, &ep_ring->td_list);
2892 td->start_seg = ep_ring->enq_seg;
2893 td->first_trb = ep_ring->enqueue;
2895 urb_priv->td[td_index] = td;
2900 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2902 int num_sgs, num_trbs, running_total, temp, i;
2903 struct scatterlist *sg;
2906 num_sgs = urb->num_mapped_sgs;
2907 temp = urb->transfer_buffer_length;
2910 for_each_sg(urb->sg, sg, num_sgs, i) {
2911 unsigned int len = sg_dma_len(sg);
2913 /* Scatter gather list entries may cross 64KB boundaries */
2914 running_total = TRB_MAX_BUFF_SIZE -
2915 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2916 running_total &= TRB_MAX_BUFF_SIZE - 1;
2917 if (running_total != 0)
2920 /* How many more 64KB chunks to transfer, how many more TRBs? */
2921 while (running_total < sg_dma_len(sg) && running_total < temp) {
2923 running_total += TRB_MAX_BUFF_SIZE;
2925 len = min_t(int, len, temp);
2933 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2936 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2937 "TRBs, %d left\n", __func__,
2938 urb->ep->desc.bEndpointAddress, num_trbs);
2939 if (running_total != urb->transfer_buffer_length)
2940 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2941 "queued %#x (%d), asked for %#x (%d)\n",
2943 urb->ep->desc.bEndpointAddress,
2944 running_total, running_total,
2945 urb->transfer_buffer_length,
2946 urb->transfer_buffer_length);
2949 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2950 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2951 struct xhci_generic_trb *start_trb)
2954 * Pass all the TRBs to the hardware at once and make sure this write
2959 start_trb->field[3] |= cpu_to_le32(start_cycle);
2961 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2962 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2966 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2967 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2968 * (comprised of sg list entries) can take several service intervals to
2971 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2972 struct urb *urb, int slot_id, unsigned int ep_index)
2974 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2975 xhci->devs[slot_id]->out_ctx, ep_index);
2979 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2980 ep_interval = urb->interval;
2981 /* Convert to microframes */
2982 if (urb->dev->speed == USB_SPEED_LOW ||
2983 urb->dev->speed == USB_SPEED_FULL)
2985 /* FIXME change this to a warning and a suggestion to use the new API
2986 * to set the polling interval (once the API is added).
2988 if (xhci_interval != ep_interval) {
2989 dev_dbg_ratelimited(&urb->dev->dev,
2990 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
2991 ep_interval, ep_interval == 1 ? "" : "s",
2992 xhci_interval, xhci_interval == 1 ? "" : "s");
2993 urb->interval = xhci_interval;
2994 /* Convert back to frames for LS/FS devices */
2995 if (urb->dev->speed == USB_SPEED_LOW ||
2996 urb->dev->speed == USB_SPEED_FULL)
2999 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3003 * The TD size is the number of bytes remaining in the TD (including this TRB),
3004 * right shifted by 10.
3005 * It must fit in bits 21:17, so it can't be bigger than 31.
3007 static u32 xhci_td_remainder(unsigned int remainder)
3009 u32 max = (1 << (21 - 17 + 1)) - 1;
3011 if ((remainder >> 10) >= max)
3014 return (remainder >> 10) << 17;
3018 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3019 * packets remaining in the TD (*not* including this TRB).
3021 * Total TD packet count = total_packet_count =
3022 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3024 * Packets transferred up to and including this TRB = packets_transferred =
3025 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3027 * TD size = total_packet_count - packets_transferred
3029 * It must fit in bits 21:17, so it can't be bigger than 31.
3030 * The last TRB in a TD must have the TD size set to zero.
3032 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3033 unsigned int total_packet_count, struct urb *urb,
3034 unsigned int num_trbs_left)
3036 int packets_transferred;
3038 /* One TRB with a zero-length data packet. */
3039 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3042 /* All the TRB queueing functions don't count the current TRB in
3045 packets_transferred = (running_total + trb_buff_len) /
3046 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3048 if ((total_packet_count - packets_transferred) > 31)
3050 return (total_packet_count - packets_transferred) << 17;
3053 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3054 struct urb *urb, int slot_id, unsigned int ep_index)
3056 struct xhci_ring *ep_ring;
3057 unsigned int num_trbs;
3058 struct urb_priv *urb_priv;
3060 struct scatterlist *sg;
3062 int trb_buff_len, this_sg_len, running_total;
3063 unsigned int total_packet_count;
3066 bool more_trbs_coming;
3068 struct xhci_generic_trb *start_trb;
3071 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3075 num_trbs = count_sg_trbs_needed(xhci, urb);
3076 num_sgs = urb->num_mapped_sgs;
3077 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3078 usb_endpoint_maxp(&urb->ep->desc));
3080 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3081 ep_index, urb->stream_id,
3082 num_trbs, urb, 0, mem_flags);
3083 if (trb_buff_len < 0)
3084 return trb_buff_len;
3086 urb_priv = urb->hcpriv;
3087 td = urb_priv->td[0];
3090 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3091 * until we've finished creating all the other TRBs. The ring's cycle
3092 * state may change as we enqueue the other TRBs, so save it too.
3094 start_trb = &ep_ring->enqueue->generic;
3095 start_cycle = ep_ring->cycle_state;
3099 * How much data is in the first TRB?
3101 * There are three forces at work for TRB buffer pointers and lengths:
3102 * 1. We don't want to walk off the end of this sg-list entry buffer.
3103 * 2. The transfer length that the driver requested may be smaller than
3104 * the amount of memory allocated for this scatter-gather list.
3105 * 3. TRBs buffers can't cross 64KB boundaries.
3108 addr = (u64) sg_dma_address(sg);
3109 this_sg_len = sg_dma_len(sg);
3110 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3111 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3112 if (trb_buff_len > urb->transfer_buffer_length)
3113 trb_buff_len = urb->transfer_buffer_length;
3116 /* Queue the first TRB, even if it's zero-length */
3119 u32 length_field = 0;
3122 /* Don't change the cycle bit of the first TRB until later */
3125 if (start_cycle == 0)
3128 field |= ep_ring->cycle_state;
3130 /* Chain all the TRBs together; clear the chain bit in the last
3131 * TRB to indicate it's the last TRB in the chain.
3136 /* FIXME - add check for ZERO_PACKET flag before this */
3137 td->last_trb = ep_ring->enqueue;
3141 /* Only set interrupt on short packet for IN endpoints */
3142 if (usb_urb_dir_in(urb))
3145 if (TRB_MAX_BUFF_SIZE -
3146 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3147 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3148 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3149 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3150 (unsigned int) addr + trb_buff_len);
3153 /* Set the TRB length, TD size, and interrupter fields. */
3154 if (xhci->hci_version < 0x100) {
3155 remainder = xhci_td_remainder(
3156 urb->transfer_buffer_length -
3159 remainder = xhci_v1_0_td_remainder(running_total,
3160 trb_buff_len, total_packet_count, urb,
3163 length_field = TRB_LEN(trb_buff_len) |
3168 more_trbs_coming = true;
3170 more_trbs_coming = false;
3171 queue_trb(xhci, ep_ring, more_trbs_coming,
3172 lower_32_bits(addr),
3173 upper_32_bits(addr),
3175 field | TRB_TYPE(TRB_NORMAL));
3177 running_total += trb_buff_len;
3179 /* Calculate length for next transfer --
3180 * Are we done queueing all the TRBs for this sg entry?
3182 this_sg_len -= trb_buff_len;
3183 if (this_sg_len == 0) {
3188 addr = (u64) sg_dma_address(sg);
3189 this_sg_len = sg_dma_len(sg);
3191 addr += trb_buff_len;
3194 trb_buff_len = TRB_MAX_BUFF_SIZE -
3195 (addr & (TRB_MAX_BUFF_SIZE - 1));
3196 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3197 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3199 urb->transfer_buffer_length - running_total;
3200 } while (running_total < urb->transfer_buffer_length);
3202 check_trb_math(urb, num_trbs, running_total);
3203 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3204 start_cycle, start_trb);
3208 /* This is very similar to what ehci-q.c qtd_fill() does */
3209 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3210 struct urb *urb, int slot_id, unsigned int ep_index)
3212 struct xhci_ring *ep_ring;
3213 struct urb_priv *urb_priv;
3216 struct xhci_generic_trb *start_trb;
3218 bool more_trbs_coming;
3220 u32 field, length_field;
3222 int running_total, trb_buff_len, ret;
3223 unsigned int total_packet_count;
3227 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3229 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3234 /* How much data is (potentially) left before the 64KB boundary? */
3235 running_total = TRB_MAX_BUFF_SIZE -
3236 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3237 running_total &= TRB_MAX_BUFF_SIZE - 1;
3239 /* If there's some data on this 64KB chunk, or we have to send a
3240 * zero-length transfer, we need at least one TRB
3242 if (running_total != 0 || urb->transfer_buffer_length == 0)
3244 /* How many more 64KB chunks to transfer, how many more TRBs? */
3245 while (running_total < urb->transfer_buffer_length) {
3247 running_total += TRB_MAX_BUFF_SIZE;
3249 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3251 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3252 ep_index, urb->stream_id,
3253 num_trbs, urb, 0, mem_flags);
3257 urb_priv = urb->hcpriv;
3258 td = urb_priv->td[0];
3261 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3262 * until we've finished creating all the other TRBs. The ring's cycle
3263 * state may change as we enqueue the other TRBs, so save it too.
3265 start_trb = &ep_ring->enqueue->generic;
3266 start_cycle = ep_ring->cycle_state;
3269 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3270 usb_endpoint_maxp(&urb->ep->desc));
3271 /* How much data is in the first TRB? */
3272 addr = (u64) urb->transfer_dma;
3273 trb_buff_len = TRB_MAX_BUFF_SIZE -
3274 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3275 if (trb_buff_len > urb->transfer_buffer_length)
3276 trb_buff_len = urb->transfer_buffer_length;
3280 /* Queue the first TRB, even if it's zero-length */
3285 /* Don't change the cycle bit of the first TRB until later */
3288 if (start_cycle == 0)
3291 field |= ep_ring->cycle_state;
3293 /* Chain all the TRBs together; clear the chain bit in the last
3294 * TRB to indicate it's the last TRB in the chain.
3299 /* FIXME - add check for ZERO_PACKET flag before this */
3300 td->last_trb = ep_ring->enqueue;
3304 /* Only set interrupt on short packet for IN endpoints */
3305 if (usb_urb_dir_in(urb))
3308 /* Set the TRB length, TD size, and interrupter fields. */
3309 if (xhci->hci_version < 0x100) {
3310 remainder = xhci_td_remainder(
3311 urb->transfer_buffer_length -
3314 remainder = xhci_v1_0_td_remainder(running_total,
3315 trb_buff_len, total_packet_count, urb,
3318 length_field = TRB_LEN(trb_buff_len) |
3323 more_trbs_coming = true;
3325 more_trbs_coming = false;
3326 queue_trb(xhci, ep_ring, more_trbs_coming,
3327 lower_32_bits(addr),
3328 upper_32_bits(addr),
3330 field | TRB_TYPE(TRB_NORMAL));
3332 running_total += trb_buff_len;
3334 /* Calculate length for next transfer */
3335 addr += trb_buff_len;
3336 trb_buff_len = urb->transfer_buffer_length - running_total;
3337 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3338 trb_buff_len = TRB_MAX_BUFF_SIZE;
3339 } while (running_total < urb->transfer_buffer_length);
3341 check_trb_math(urb, num_trbs, running_total);
3342 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3343 start_cycle, start_trb);
3347 /* Caller must have locked xhci->lock */
3348 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3349 struct urb *urb, int slot_id, unsigned int ep_index)
3351 struct xhci_ring *ep_ring;
3354 struct usb_ctrlrequest *setup;
3355 struct xhci_generic_trb *start_trb;
3357 u32 field, length_field;
3358 struct urb_priv *urb_priv;
3361 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3366 * Need to copy setup packet into setup TRB, so we can't use the setup
3369 if (!urb->setup_packet)
3372 /* 1 TRB for setup, 1 for status */
3375 * Don't need to check if we need additional event data and normal TRBs,
3376 * since data in control transfers will never get bigger than 16MB
3377 * XXX: can we get a buffer that crosses 64KB boundaries?
3379 if (urb->transfer_buffer_length > 0)
3381 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3382 ep_index, urb->stream_id,
3383 num_trbs, urb, 0, mem_flags);
3387 urb_priv = urb->hcpriv;
3388 td = urb_priv->td[0];
3391 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3392 * until we've finished creating all the other TRBs. The ring's cycle
3393 * state may change as we enqueue the other TRBs, so save it too.
3395 start_trb = &ep_ring->enqueue->generic;
3396 start_cycle = ep_ring->cycle_state;
3398 /* Queue setup TRB - see section 6.4.1.2.1 */
3399 /* FIXME better way to translate setup_packet into two u32 fields? */
3400 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3402 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3403 if (start_cycle == 0)
3406 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3407 if (xhci->hci_version == 0x100) {
3408 if (urb->transfer_buffer_length > 0) {
3409 if (setup->bRequestType & USB_DIR_IN)
3410 field |= TRB_TX_TYPE(TRB_DATA_IN);
3412 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3416 queue_trb(xhci, ep_ring, true,
3417 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3418 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3419 TRB_LEN(8) | TRB_INTR_TARGET(0),
3420 /* Immediate data in pointer */
3423 /* If there's data, queue data TRBs */
3424 /* Only set interrupt on short packet for IN endpoints */
3425 if (usb_urb_dir_in(urb))
3426 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3428 field = TRB_TYPE(TRB_DATA);
3430 length_field = TRB_LEN(urb->transfer_buffer_length) |
3431 xhci_td_remainder(urb->transfer_buffer_length) |
3433 if (urb->transfer_buffer_length > 0) {
3434 if (setup->bRequestType & USB_DIR_IN)
3435 field |= TRB_DIR_IN;
3436 queue_trb(xhci, ep_ring, true,
3437 lower_32_bits(urb->transfer_dma),
3438 upper_32_bits(urb->transfer_dma),
3440 field | ep_ring->cycle_state);
3443 /* Save the DMA address of the last TRB in the TD */
3444 td->last_trb = ep_ring->enqueue;
3446 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3447 /* If the device sent data, the status stage is an OUT transfer */
3448 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3452 queue_trb(xhci, ep_ring, false,
3456 /* Event on completion */
3457 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3459 giveback_first_trb(xhci, slot_id, ep_index, 0,
3460 start_cycle, start_trb);
3464 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3465 struct urb *urb, int i)
3470 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3471 td_len = urb->iso_frame_desc[i].length;
3473 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3482 * The transfer burst count field of the isochronous TRB defines the number of
3483 * bursts that are required to move all packets in this TD. Only SuperSpeed
3484 * devices can burst up to bMaxBurst number of packets per service interval.
3485 * This field is zero based, meaning a value of zero in the field means one
3486 * burst. Basically, for everything but SuperSpeed devices, this field will be
3487 * zero. Only xHCI 1.0 host controllers support this field.
3489 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3490 struct usb_device *udev,
3491 struct urb *urb, unsigned int total_packet_count)
3493 unsigned int max_burst;
3495 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3498 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3499 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3503 * Returns the number of packets in the last "burst" of packets. This field is
3504 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3505 * the last burst packet count is equal to the total number of packets in the
3506 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3507 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3508 * contain 1 to (bMaxBurst + 1) packets.
3510 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3511 struct usb_device *udev,
3512 struct urb *urb, unsigned int total_packet_count)
3514 unsigned int max_burst;
3515 unsigned int residue;
3517 if (xhci->hci_version < 0x100)
3520 switch (udev->speed) {
3521 case USB_SPEED_SUPER:
3522 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3523 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3524 residue = total_packet_count % (max_burst + 1);
3525 /* If residue is zero, the last burst contains (max_burst + 1)
3526 * number of packets, but the TLBPC field is zero-based.
3532 if (total_packet_count == 0)
3534 return total_packet_count - 1;
3538 /* This is for isoc transfer */
3539 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3540 struct urb *urb, int slot_id, unsigned int ep_index)
3542 struct xhci_ring *ep_ring;
3543 struct urb_priv *urb_priv;
3545 int num_tds, trbs_per_td;
3546 struct xhci_generic_trb *start_trb;
3549 u32 field, length_field;
3550 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3551 u64 start_addr, addr;
3553 bool more_trbs_coming;
3555 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3557 num_tds = urb->number_of_packets;
3559 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3563 start_addr = (u64) urb->transfer_dma;
3564 start_trb = &ep_ring->enqueue->generic;
3565 start_cycle = ep_ring->cycle_state;
3567 urb_priv = urb->hcpriv;
3568 /* Queue the first TRB, even if it's zero-length */
3569 for (i = 0; i < num_tds; i++) {
3570 unsigned int total_packet_count;
3571 unsigned int burst_count;
3572 unsigned int residue;
3576 addr = start_addr + urb->iso_frame_desc[i].offset;
3577 td_len = urb->iso_frame_desc[i].length;
3578 td_remain_len = td_len;
3579 total_packet_count = DIV_ROUND_UP(td_len,
3581 usb_endpoint_maxp(&urb->ep->desc)));
3582 /* A zero-length transfer still involves at least one packet. */
3583 if (total_packet_count == 0)
3584 total_packet_count++;
3585 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3586 total_packet_count);
3587 residue = xhci_get_last_burst_packet_count(xhci,
3588 urb->dev, urb, total_packet_count);
3590 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3592 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3593 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3600 td = urb_priv->td[i];
3601 for (j = 0; j < trbs_per_td; j++) {
3606 field = TRB_TBC(burst_count) |
3608 /* Queue the isoc TRB */
3609 field |= TRB_TYPE(TRB_ISOC);
3610 /* Assume URB_ISO_ASAP is set */
3613 if (start_cycle == 0)
3616 field |= ep_ring->cycle_state;
3619 /* Queue other normal TRBs */
3620 field |= TRB_TYPE(TRB_NORMAL);
3621 field |= ep_ring->cycle_state;
3624 /* Only set interrupt on short packet for IN EPs */
3625 if (usb_urb_dir_in(urb))
3628 /* Chain all the TRBs together; clear the chain bit in
3629 * the last TRB to indicate it's the last TRB in the
3632 if (j < trbs_per_td - 1) {
3634 more_trbs_coming = true;
3636 td->last_trb = ep_ring->enqueue;
3638 if (xhci->hci_version == 0x100 &&
3641 /* Set BEI bit except for the last td */
3642 if (i < num_tds - 1)
3645 more_trbs_coming = false;
3648 /* Calculate TRB length */
3649 trb_buff_len = TRB_MAX_BUFF_SIZE -
3650 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3651 if (trb_buff_len > td_remain_len)
3652 trb_buff_len = td_remain_len;
3654 /* Set the TRB length, TD size, & interrupter fields. */
3655 if (xhci->hci_version < 0x100) {
3656 remainder = xhci_td_remainder(
3657 td_len - running_total);
3659 remainder = xhci_v1_0_td_remainder(
3660 running_total, trb_buff_len,
3661 total_packet_count, urb,
3662 (trbs_per_td - j - 1));
3664 length_field = TRB_LEN(trb_buff_len) |
3668 queue_trb(xhci, ep_ring, more_trbs_coming,
3669 lower_32_bits(addr),
3670 upper_32_bits(addr),
3673 running_total += trb_buff_len;
3675 addr += trb_buff_len;
3676 td_remain_len -= trb_buff_len;
3679 /* Check TD length */
3680 if (running_total != td_len) {
3681 xhci_err(xhci, "ISOC TD length unmatch\n");
3687 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3688 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3689 usb_amd_quirk_pll_disable();
3691 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3693 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3694 start_cycle, start_trb);
3697 /* Clean up a partially enqueued isoc transfer. */
3699 for (i--; i >= 0; i--)
3700 list_del_init(&urb_priv->td[i]->td_list);
3702 /* Use the first TD as a temporary variable to turn the TDs we've queued
3703 * into No-ops with a software-owned cycle bit. That way the hardware
3704 * won't accidentally start executing bogus TDs when we partially
3705 * overwrite them. td->first_trb and td->start_seg are already set.
3707 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3708 /* Every TRB except the first & last will have its cycle bit flipped. */
3709 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3711 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3712 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3713 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3714 ep_ring->cycle_state = start_cycle;
3715 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3716 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3721 * Check transfer ring to guarantee there is enough room for the urb.
3722 * Update ISO URB start_frame and interval.
3723 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3724 * update the urb->start_frame by now.
3725 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3727 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3728 struct urb *urb, int slot_id, unsigned int ep_index)
3730 struct xhci_virt_device *xdev;
3731 struct xhci_ring *ep_ring;
3732 struct xhci_ep_ctx *ep_ctx;
3736 int num_tds, num_trbs, i;
3739 xdev = xhci->devs[slot_id];
3740 ep_ring = xdev->eps[ep_index].ring;
3741 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3744 num_tds = urb->number_of_packets;
3745 for (i = 0; i < num_tds; i++)
3746 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3748 /* Check the ring to guarantee there is enough room for the whole urb.
3749 * Do not insert any td of the urb to the ring if the check failed.
3751 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3752 num_trbs, mem_flags);
3756 start_frame = readl(&xhci->run_regs->microframe_index);
3757 start_frame &= 0x3fff;
3759 urb->start_frame = start_frame;
3760 if (urb->dev->speed == USB_SPEED_LOW ||
3761 urb->dev->speed == USB_SPEED_FULL)
3762 urb->start_frame >>= 3;
3764 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3765 ep_interval = urb->interval;
3766 /* Convert to microframes */
3767 if (urb->dev->speed == USB_SPEED_LOW ||
3768 urb->dev->speed == USB_SPEED_FULL)
3770 /* FIXME change this to a warning and a suggestion to use the new API
3771 * to set the polling interval (once the API is added).
3773 if (xhci_interval != ep_interval) {
3774 dev_dbg_ratelimited(&urb->dev->dev,
3775 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3776 ep_interval, ep_interval == 1 ? "" : "s",
3777 xhci_interval, xhci_interval == 1 ? "" : "s");
3778 urb->interval = xhci_interval;
3779 /* Convert back to frames for LS/FS devices */
3780 if (urb->dev->speed == USB_SPEED_LOW ||
3781 urb->dev->speed == USB_SPEED_FULL)
3784 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3786 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3789 /**** Command Ring Operations ****/
3791 /* Generic function for queueing a command TRB on the command ring.
3792 * Check to make sure there's room on the command ring for one command TRB.
3793 * Also check that there's room reserved for commands that must not fail.
3794 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3795 * then only check for the number of reserved spots.
3796 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3797 * because the command event handler may want to resubmit a failed command.
3799 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3800 u32 field1, u32 field2,
3801 u32 field3, u32 field4, bool command_must_succeed)
3803 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3805 if (xhci->xhc_state & XHCI_STATE_DYING)
3808 if (!command_must_succeed)
3811 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3812 reserved_trbs, GFP_ATOMIC);
3814 xhci_err(xhci, "ERR: No room for command on command ring\n");
3815 if (command_must_succeed)
3816 xhci_err(xhci, "ERR: Reserved TRB counting for "
3817 "unfailable commands failed.\n");
3821 cmd->command_trb = xhci->cmd_ring->enqueue;
3822 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3824 /* if there are no other commands queued we start the timeout timer */
3825 if (xhci->cmd_list.next == &cmd->cmd_list &&
3826 !timer_pending(&xhci->cmd_timer)) {
3827 xhci->current_cmd = cmd;
3828 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3831 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3832 field4 | xhci->cmd_ring->cycle_state);
3836 /* Queue a slot enable or disable request on the command ring */
3837 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3838 u32 trb_type, u32 slot_id)
3840 return queue_command(xhci, cmd, 0, 0, 0,
3841 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3844 /* Queue an address device command TRB */
3845 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3846 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3848 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3849 upper_32_bits(in_ctx_ptr), 0,
3850 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3851 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3854 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3855 u32 field1, u32 field2, u32 field3, u32 field4)
3857 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3860 /* Queue a reset device command TRB */
3861 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3864 return queue_command(xhci, cmd, 0, 0, 0,
3865 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3869 /* Queue a configure endpoint command TRB */
3870 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3871 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3872 u32 slot_id, bool command_must_succeed)
3874 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3875 upper_32_bits(in_ctx_ptr), 0,
3876 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3877 command_must_succeed);
3880 /* Queue an evaluate context command TRB */
3881 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3882 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3884 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3885 upper_32_bits(in_ctx_ptr), 0,
3886 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3887 command_must_succeed);
3891 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3892 * activity on an endpoint that is about to be suspended.
3894 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3895 int slot_id, unsigned int ep_index, int suspend)
3897 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3898 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3899 u32 type = TRB_TYPE(TRB_STOP_RING);
3900 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3902 return queue_command(xhci, cmd, 0, 0, 0,
3903 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3906 /* Set Transfer Ring Dequeue Pointer command */
3907 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3908 unsigned int slot_id, unsigned int ep_index,
3909 unsigned int stream_id,
3910 struct xhci_dequeue_state *deq_state)
3913 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3914 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3915 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3917 u32 type = TRB_TYPE(TRB_SET_DEQ);
3918 struct xhci_virt_ep *ep;
3919 struct xhci_command *cmd;
3922 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
3923 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3924 deq_state->new_deq_seg,
3925 (unsigned long long)deq_state->new_deq_seg->dma,
3926 deq_state->new_deq_ptr,
3927 (unsigned long long)xhci_trb_virt_to_dma(
3928 deq_state->new_deq_seg, deq_state->new_deq_ptr),
3929 deq_state->new_cycle_state);
3931 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3932 deq_state->new_deq_ptr);
3934 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3935 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3936 deq_state->new_deq_seg, deq_state->new_deq_ptr);
3939 ep = &xhci->devs[slot_id]->eps[ep_index];
3940 if ((ep->ep_state & SET_DEQ_PENDING)) {
3941 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3942 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3946 /* This function gets called from contexts where it cannot sleep */
3947 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
3949 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
3953 ep->queued_deq_seg = deq_state->new_deq_seg;
3954 ep->queued_deq_ptr = deq_state->new_deq_ptr;
3956 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3957 ret = queue_command(xhci, cmd,
3958 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
3959 upper_32_bits(addr), trb_stream_id,
3960 trb_slot_id | trb_ep_index | type, false);
3962 xhci_free_command(xhci, cmd);
3966 /* Stop the TD queueing code from ringing the doorbell until
3967 * this command completes. The HC won't set the dequeue pointer
3968 * if the ring is running, and ringing the doorbell starts the
3971 ep->ep_state |= SET_DEQ_PENDING;
3974 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3975 int slot_id, unsigned int ep_index)
3977 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3978 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3979 u32 type = TRB_TYPE(TRB_RESET_EP);
3981 return queue_command(xhci, cmd, 0, 0, 0,
3982 trb_slot_id | trb_ep_index | type, false);