2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset >= TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state ^= 1;
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
285 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
288 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
290 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
295 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
296 * If there are other commands waiting then restart the ring and kick the timer.
297 * This must be called with command ring stopped and xhci->lock held.
299 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
300 struct xhci_command *cur_cmd)
302 struct xhci_command *i_cmd;
305 /* Turn all aborted commands in list to no-ops, then restart */
306 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
308 if (i_cmd->status != COMP_CMD_ABORT)
311 i_cmd->status = COMP_CMD_STOP;
313 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
315 /* get cycle state from the original cmd trb */
316 cycle_state = le32_to_cpu(
317 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
318 /* modify the command trb to no-op command */
319 i_cmd->command_trb->generic.field[0] = 0;
320 i_cmd->command_trb->generic.field[1] = 0;
321 i_cmd->command_trb->generic.field[2] = 0;
322 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
323 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
326 * caller waiting for completion is called when command
327 * completion event is received for these no-op commands
331 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
333 /* ring command ring doorbell to restart the command ring */
334 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
335 !(xhci->xhc_state & XHCI_STATE_DYING)) {
336 xhci->current_cmd = cur_cmd;
337 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
338 xhci_ring_cmd_db(xhci);
342 /* Must be called with xhci->lock held, releases and aquires lock back */
343 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
348 xhci_dbg(xhci, "Abort command ring\n");
350 reinit_completion(&xhci->cmd_ring_stop_completion);
352 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
353 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
354 &xhci->op_regs->cmd_ring);
356 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
357 * time the completion od all xHCI commands, including
358 * the Command Abort operation. If software doesn't see
359 * CRR negated in a timely manner (e.g. longer than 5
360 * seconds), then it should assume that the there are
361 * larger problems with the xHC and assert HCRST.
363 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
364 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
366 /* we are about to kill xhci, give it one more chance */
367 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
368 &xhci->op_regs->cmd_ring);
370 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
371 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
373 xhci_err(xhci, "Stopped the command ring failed, "
374 "maybe the host is dead\n");
375 xhci->xhc_state |= XHCI_STATE_DYING;
382 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
383 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
384 * but the completion event in never sent. Wait 2 secs (arbitrary
385 * number) to handle those cases after negation of CMD_RING_RUNNING.
387 spin_unlock_irqrestore(&xhci->lock, flags);
388 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
389 msecs_to_jiffies(2000));
390 spin_lock_irqsave(&xhci->lock, flags);
392 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
393 xhci_cleanup_command_queue(xhci);
395 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
401 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
402 unsigned int slot_id,
403 unsigned int ep_index,
404 unsigned int stream_id)
406 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
407 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
408 unsigned int ep_state = ep->ep_state;
410 /* Don't ring the doorbell for this endpoint if there are pending
411 * cancellations because we don't want to interrupt processing.
412 * We don't want to restart any stream rings if there's a set dequeue
413 * pointer command pending because the device can choose to start any
414 * stream once the endpoint is on the HW schedule.
416 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
417 (ep_state & EP_HALTED))
419 writel(DB_VALUE(ep_index, stream_id), db_addr);
420 /* The CPU has better things to do at this point than wait for a
421 * write-posting flush. It'll get there soon enough.
425 /* Ring the doorbell for any rings with pending URBs */
426 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
427 unsigned int slot_id,
428 unsigned int ep_index)
430 unsigned int stream_id;
431 struct xhci_virt_ep *ep;
433 ep = &xhci->devs[slot_id]->eps[ep_index];
435 /* A ring has pending URBs if its TD list is not empty */
436 if (!(ep->ep_state & EP_HAS_STREAMS)) {
437 if (ep->ring && !(list_empty(&ep->ring->td_list)))
438 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
442 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
444 struct xhci_stream_info *stream_info = ep->stream_info;
445 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
446 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
451 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
452 unsigned int slot_id, unsigned int ep_index,
453 unsigned int stream_id)
455 struct xhci_virt_ep *ep;
457 ep = &xhci->devs[slot_id]->eps[ep_index];
458 /* Common case: no streams */
459 if (!(ep->ep_state & EP_HAS_STREAMS))
462 if (stream_id == 0) {
464 "WARN: Slot ID %u, ep index %u has streams, "
465 "but URB has no stream ID.\n",
470 if (stream_id < ep->stream_info->num_streams)
471 return ep->stream_info->stream_rings[stream_id];
474 "WARN: Slot ID %u, ep index %u has "
475 "stream IDs 1 to %u allocated, "
476 "but stream ID %u is requested.\n",
478 ep->stream_info->num_streams - 1,
483 /* Get the right ring for the given URB.
484 * If the endpoint supports streams, boundary check the URB's stream ID.
485 * If the endpoint doesn't support streams, return the singular endpoint ring.
487 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
490 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
491 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
495 * Move the xHC's endpoint ring dequeue pointer past cur_td.
496 * Record the new state of the xHC's endpoint ring dequeue segment,
497 * dequeue pointer, and new consumer cycle state in state.
498 * Update our internal representation of the ring's dequeue pointer.
500 * We do this in three jumps:
501 * - First we update our new ring state to be the same as when the xHC stopped.
502 * - Then we traverse the ring to find the segment that contains
503 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
504 * any link TRBs with the toggle cycle bit set.
505 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
506 * if we've moved it past a link TRB with the toggle cycle bit set.
508 * Some of the uses of xhci_generic_trb are grotty, but if they're done
509 * with correct __le32 accesses they should work fine. Only users of this are
512 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
513 unsigned int slot_id, unsigned int ep_index,
514 unsigned int stream_id, struct xhci_td *cur_td,
515 struct xhci_dequeue_state *state)
517 struct xhci_virt_device *dev = xhci->devs[slot_id];
518 struct xhci_virt_ep *ep = &dev->eps[ep_index];
519 struct xhci_ring *ep_ring;
520 struct xhci_segment *new_seg;
521 union xhci_trb *new_deq;
524 bool cycle_found = false;
525 bool td_last_trb_found = false;
527 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
528 ep_index, stream_id);
530 xhci_warn(xhci, "WARN can't find new dequeue state "
531 "for invalid stream ID %u.\n",
536 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
537 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
538 "Finding endpoint context");
539 /* 4.6.9 the css flag is written to the stream context for streams */
540 if (ep->ep_state & EP_HAS_STREAMS) {
541 struct xhci_stream_ctx *ctx =
542 &ep->stream_info->stream_ctx_array[stream_id];
543 hw_dequeue = le64_to_cpu(ctx->stream_ring);
545 struct xhci_ep_ctx *ep_ctx
546 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
547 hw_dequeue = le64_to_cpu(ep_ctx->deq);
550 new_seg = ep_ring->deq_seg;
551 new_deq = ep_ring->dequeue;
552 state->new_cycle_state = hw_dequeue & 0x1;
555 * We want to find the pointer, segment and cycle state of the new trb
556 * (the one after current TD's last_trb). We know the cycle state at
557 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
561 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
562 == (dma_addr_t)(hw_dequeue & ~0xf)) {
564 if (td_last_trb_found)
567 if (new_deq == cur_td->last_trb)
568 td_last_trb_found = true;
571 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
572 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
573 state->new_cycle_state ^= 0x1;
575 next_trb(xhci, ep_ring, &new_seg, &new_deq);
577 /* Search wrapped around, bail out */
578 if (new_deq == ep->ring->dequeue) {
579 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
580 state->new_deq_seg = NULL;
581 state->new_deq_ptr = NULL;
585 } while (!cycle_found || !td_last_trb_found);
587 state->new_deq_seg = new_seg;
588 state->new_deq_ptr = new_deq;
590 /* Don't update the ring cycle state for the producer (us). */
591 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
592 "Cycle state = 0x%x", state->new_cycle_state);
594 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
595 "New dequeue segment = %p (virtual)",
597 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
598 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
599 "New dequeue pointer = 0x%llx (DMA)",
600 (unsigned long long) addr);
603 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
604 * (The last TRB actually points to the ring enqueue pointer, which is not part
605 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
607 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
608 struct xhci_td *cur_td, bool flip_cycle)
610 struct xhci_segment *cur_seg;
611 union xhci_trb *cur_trb;
613 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
615 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
616 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
617 /* Unchain any chained Link TRBs, but
618 * leave the pointers intact.
620 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
621 /* Flip the cycle bit (link TRBs can't be the first
625 cur_trb->generic.field[3] ^=
626 cpu_to_le32(TRB_CYCLE);
627 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
628 "Cancel (unchain) link TRB");
629 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
630 "Address = %p (0x%llx dma); "
631 "in seg %p (0x%llx dma)",
633 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
635 (unsigned long long)cur_seg->dma);
637 cur_trb->generic.field[0] = 0;
638 cur_trb->generic.field[1] = 0;
639 cur_trb->generic.field[2] = 0;
640 /* Preserve only the cycle bit of this TRB */
641 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
642 /* Flip the cycle bit except on the first or last TRB */
643 if (flip_cycle && cur_trb != cur_td->first_trb &&
644 cur_trb != cur_td->last_trb)
645 cur_trb->generic.field[3] ^=
646 cpu_to_le32(TRB_CYCLE);
647 cur_trb->generic.field[3] |= cpu_to_le32(
648 TRB_TYPE(TRB_TR_NOOP));
649 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
650 "TRB to noop at offset 0x%llx",
652 xhci_trb_virt_to_dma(cur_seg, cur_trb));
654 if (cur_trb == cur_td->last_trb)
659 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
660 struct xhci_virt_ep *ep)
662 ep->ep_state &= ~EP_HALT_PENDING;
663 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
664 * timer is running on another CPU, we don't decrement stop_cmds_pending
665 * (since we didn't successfully stop the watchdog timer).
667 if (del_timer(&ep->stop_cmd_timer))
668 ep->stop_cmds_pending--;
671 /* Must be called with xhci->lock held in interrupt context */
672 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
673 struct xhci_td *cur_td, int status)
677 struct urb_priv *urb_priv;
680 urb_priv = urb->hcpriv;
682 hcd = bus_to_hcd(urb->dev->bus);
684 /* Only giveback urb when this is the last td in urb */
685 if (urb_priv->td_cnt == urb_priv->length) {
686 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
687 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
688 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
689 if (xhci->quirks & XHCI_AMD_PLL_FIX)
690 usb_amd_quirk_pll_enable();
693 usb_hcd_unlink_urb_from_ep(hcd, urb);
695 spin_unlock(&xhci->lock);
696 usb_hcd_giveback_urb(hcd, urb, status);
697 xhci_urb_free_priv(urb_priv);
698 spin_lock(&xhci->lock);
703 * When we get a command completion for a Stop Endpoint Command, we need to
704 * unlink any cancelled TDs from the ring. There are two ways to do that:
706 * 1. If the HW was in the middle of processing the TD that needs to be
707 * cancelled, then we must move the ring's dequeue pointer past the last TRB
708 * in the TD with a Set Dequeue Pointer Command.
709 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
710 * bit cleared) so that the HW will skip over them.
712 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
713 union xhci_trb *trb, struct xhci_event_cmd *event)
715 unsigned int ep_index;
716 struct xhci_ring *ep_ring;
717 struct xhci_virt_ep *ep;
718 struct list_head *entry;
719 struct xhci_td *cur_td = NULL;
720 struct xhci_td *last_unlinked_td;
722 struct xhci_dequeue_state deq_state;
724 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
725 if (!xhci->devs[slot_id])
726 xhci_warn(xhci, "Stop endpoint command "
727 "completion for disabled slot %u\n",
732 memset(&deq_state, 0, sizeof(deq_state));
733 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
734 ep = &xhci->devs[slot_id]->eps[ep_index];
736 if (list_empty(&ep->cancelled_td_list)) {
737 xhci_stop_watchdog_timer_in_irq(xhci, ep);
738 ep->stopped_td = NULL;
739 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
743 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
744 * We have the xHCI lock, so nothing can modify this list until we drop
745 * it. We're also in the event handler, so we can't get re-interrupted
746 * if another Stop Endpoint command completes
748 list_for_each(entry, &ep->cancelled_td_list) {
749 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
750 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
751 "Removing canceled TD starting at 0x%llx (dma).",
752 (unsigned long long)xhci_trb_virt_to_dma(
753 cur_td->start_seg, cur_td->first_trb));
754 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
756 /* This shouldn't happen unless a driver is mucking
757 * with the stream ID after submission. This will
758 * leave the TD on the hardware ring, and the hardware
759 * will try to execute it, and may access a buffer
760 * that has already been freed. In the best case, the
761 * hardware will execute it, and the event handler will
762 * ignore the completion event for that TD, since it was
763 * removed from the td_list for that endpoint. In
764 * short, don't muck with the stream ID after
767 xhci_warn(xhci, "WARN Cancelled URB %p "
768 "has invalid stream ID %u.\n",
770 cur_td->urb->stream_id);
771 goto remove_finished_td;
774 * If we stopped on the TD we need to cancel, then we have to
775 * move the xHC endpoint ring dequeue pointer past this TD.
777 if (cur_td == ep->stopped_td)
778 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
779 cur_td->urb->stream_id,
782 td_to_noop(xhci, ep_ring, cur_td, false);
785 * The event handler won't see a completion for this TD anymore,
786 * so remove it from the endpoint ring's TD list. Keep it in
787 * the cancelled TD list for URB completion later.
789 list_del_init(&cur_td->td_list);
791 last_unlinked_td = cur_td;
792 xhci_stop_watchdog_timer_in_irq(xhci, ep);
794 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
795 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
796 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
797 ep->stopped_td->urb->stream_id, &deq_state);
798 xhci_ring_cmd_db(xhci);
800 /* Otherwise ring the doorbell(s) to restart queued transfers */
801 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
804 ep->stopped_td = NULL;
807 * Drop the lock and complete the URBs in the cancelled TD list.
808 * New TDs to be cancelled might be added to the end of the list before
809 * we can complete all the URBs for the TDs we already unlinked.
810 * So stop when we've completed the URB for the last TD we unlinked.
813 cur_td = list_entry(ep->cancelled_td_list.next,
814 struct xhci_td, cancelled_td_list);
815 list_del_init(&cur_td->cancelled_td_list);
817 /* Clean up the cancelled URB */
818 /* Doesn't matter what we pass for status, since the core will
819 * just overwrite it (because the URB has been unlinked).
821 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
823 /* Stop processing the cancelled list if the watchdog timer is
826 if (xhci->xhc_state & XHCI_STATE_DYING)
828 } while (cur_td != last_unlinked_td);
830 /* Return to the event handler with xhci->lock re-acquired */
833 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
835 struct xhci_td *cur_td;
837 while (!list_empty(&ring->td_list)) {
838 cur_td = list_first_entry(&ring->td_list,
839 struct xhci_td, td_list);
840 list_del_init(&cur_td->td_list);
841 if (!list_empty(&cur_td->cancelled_td_list))
842 list_del_init(&cur_td->cancelled_td_list);
843 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
847 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
848 int slot_id, int ep_index)
850 struct xhci_td *cur_td;
851 struct xhci_virt_ep *ep;
852 struct xhci_ring *ring;
854 ep = &xhci->devs[slot_id]->eps[ep_index];
855 if ((ep->ep_state & EP_HAS_STREAMS) ||
856 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
859 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
862 "Killing URBs for slot ID %u, ep index %u, stream %u",
863 slot_id, ep_index, stream_id + 1);
864 xhci_kill_ring_urbs(xhci,
865 ep->stream_info->stream_rings[stream_id]);
871 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
872 "Killing URBs for slot ID %u, ep index %u",
874 xhci_kill_ring_urbs(xhci, ring);
876 while (!list_empty(&ep->cancelled_td_list)) {
877 cur_td = list_first_entry(&ep->cancelled_td_list,
878 struct xhci_td, cancelled_td_list);
879 list_del_init(&cur_td->cancelled_td_list);
880 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
884 /* Watchdog timer function for when a stop endpoint command fails to complete.
885 * In this case, we assume the host controller is broken or dying or dead. The
886 * host may still be completing some other events, so we have to be careful to
887 * let the event ring handler and the URB dequeueing/enqueueing functions know
888 * through xhci->state.
890 * The timer may also fire if the host takes a very long time to respond to the
891 * command, and the stop endpoint command completion handler cannot delete the
892 * timer before the timer function is called. Another endpoint cancellation may
893 * sneak in before the timer function can grab the lock, and that may queue
894 * another stop endpoint command and add the timer back. So we cannot use a
895 * simple flag to say whether there is a pending stop endpoint command for a
896 * particular endpoint.
898 * Instead we use a combination of that flag and a counter for the number of
899 * pending stop endpoint commands. If the timer is the tail end of the last
900 * stop endpoint command, and the endpoint's command is still pending, we assume
903 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
905 struct xhci_hcd *xhci;
906 struct xhci_virt_ep *ep;
910 ep = (struct xhci_virt_ep *) arg;
913 spin_lock_irqsave(&xhci->lock, flags);
915 ep->stop_cmds_pending--;
916 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
917 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
918 "Stop EP timer ran, but no command pending, "
920 spin_unlock_irqrestore(&xhci->lock, flags);
924 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
925 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
926 /* Oops, HC is dead or dying or at least not responding to the stop
929 xhci->xhc_state |= XHCI_STATE_DYING;
930 /* Disable interrupts from the host controller and start halting it */
932 spin_unlock_irqrestore(&xhci->lock, flags);
934 ret = xhci_halt(xhci);
936 spin_lock_irqsave(&xhci->lock, flags);
938 /* This is bad; the host is not responding to commands and it's
939 * not allowing itself to be halted. At least interrupts are
940 * disabled. If we call usb_hc_died(), it will attempt to
941 * disconnect all device drivers under this host. Those
942 * disconnect() methods will wait for all URBs to be unlinked,
943 * so we must complete them.
945 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
946 xhci_warn(xhci, "Completing active URBs anyway.\n");
947 /* We could turn all TDs on the rings to no-ops. This won't
948 * help if the host has cached part of the ring, and is slow if
949 * we want to preserve the cycle bit. Skip it and hope the host
950 * doesn't touch the memory.
953 for (i = 0; i < MAX_HC_SLOTS; i++) {
956 for (j = 0; j < 31; j++)
957 xhci_kill_endpoint_urbs(xhci, i, j);
959 spin_unlock_irqrestore(&xhci->lock, flags);
960 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
961 "Calling usb_hc_died()");
962 usb_hc_died(xhci_to_hcd(xhci));
963 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
964 "xHCI host controller is dead.");
968 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
969 struct xhci_virt_device *dev,
970 struct xhci_ring *ep_ring,
971 unsigned int ep_index)
973 union xhci_trb *dequeue_temp;
974 int num_trbs_free_temp;
977 num_trbs_free_temp = ep_ring->num_trbs_free;
978 dequeue_temp = ep_ring->dequeue;
980 /* If we get two back-to-back stalls, and the first stalled transfer
981 * ends just before a link TRB, the dequeue pointer will be left on
982 * the link TRB by the code in the while loop. So we have to update
983 * the dequeue pointer one segment further, or we'll jump off
984 * the segment into la-la-land.
986 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
987 ep_ring->deq_seg = ep_ring->deq_seg->next;
988 ep_ring->dequeue = ep_ring->deq_seg->trbs;
991 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
992 /* We have more usable TRBs */
993 ep_ring->num_trbs_free++;
995 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
997 if (ep_ring->dequeue ==
998 dev->eps[ep_index].queued_deq_ptr)
1000 ep_ring->deq_seg = ep_ring->deq_seg->next;
1001 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1003 if (ep_ring->dequeue == dequeue_temp) {
1010 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1011 ep_ring->num_trbs_free = num_trbs_free_temp;
1016 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1017 * we need to clear the set deq pending flag in the endpoint ring state, so that
1018 * the TD queueing code can ring the doorbell again. We also need to ring the
1019 * endpoint doorbell to restart the ring, but only if there aren't more
1020 * cancellations pending.
1022 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1023 union xhci_trb *trb, u32 cmd_comp_code)
1025 unsigned int ep_index;
1026 unsigned int stream_id;
1027 struct xhci_ring *ep_ring;
1028 struct xhci_virt_device *dev;
1029 struct xhci_virt_ep *ep;
1030 struct xhci_ep_ctx *ep_ctx;
1031 struct xhci_slot_ctx *slot_ctx;
1033 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1034 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1035 dev = xhci->devs[slot_id];
1036 ep = &dev->eps[ep_index];
1038 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1040 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1042 /* XXX: Harmless??? */
1046 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1047 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1049 if (cmd_comp_code != COMP_SUCCESS) {
1050 unsigned int ep_state;
1051 unsigned int slot_state;
1053 switch (cmd_comp_code) {
1055 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1057 case COMP_CTX_STATE:
1058 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1059 ep_state = le32_to_cpu(ep_ctx->ep_info);
1060 ep_state &= EP_STATE_MASK;
1061 slot_state = le32_to_cpu(slot_ctx->dev_state);
1062 slot_state = GET_SLOT_STATE(slot_state);
1063 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1064 "Slot state = %u, EP state = %u",
1065 slot_state, ep_state);
1068 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1072 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1076 /* OK what do we do now? The endpoint state is hosed, and we
1077 * should never get to this point if the synchronization between
1078 * queueing, and endpoint state are correct. This might happen
1079 * if the device gets disconnected after we've finished
1080 * cancelling URBs, which might not be an error...
1084 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1085 if (ep->ep_state & EP_HAS_STREAMS) {
1086 struct xhci_stream_ctx *ctx =
1087 &ep->stream_info->stream_ctx_array[stream_id];
1088 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1090 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1092 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1093 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1094 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1095 ep->queued_deq_ptr) == deq) {
1096 /* Update the ring's dequeue segment and dequeue pointer
1097 * to reflect the new position.
1099 update_ring_for_set_deq_completion(xhci, dev,
1102 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1103 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1104 ep->queued_deq_seg, ep->queued_deq_ptr);
1109 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1110 dev->eps[ep_index].queued_deq_seg = NULL;
1111 dev->eps[ep_index].queued_deq_ptr = NULL;
1112 /* Restart any rings with pending URBs */
1113 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1116 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1117 union xhci_trb *trb, u32 cmd_comp_code)
1119 unsigned int ep_index;
1121 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1122 /* This command will only fail if the endpoint wasn't halted,
1123 * but we don't care.
1125 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1126 "Ignoring reset ep completion code of %u", cmd_comp_code);
1128 /* HW with the reset endpoint quirk needs to have a configure endpoint
1129 * command complete before the endpoint can be used. Queue that here
1130 * because the HW can't handle two commands being queued in a row.
1132 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1133 struct xhci_command *command;
1134 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1136 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1139 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1140 "Queueing configure endpoint command");
1141 xhci_queue_configure_endpoint(xhci, command,
1142 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1144 xhci_ring_cmd_db(xhci);
1146 /* Clear our internal halted state */
1147 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1151 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1154 if (cmd_comp_code == COMP_SUCCESS)
1155 xhci->slot_id = slot_id;
1160 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1162 struct xhci_virt_device *virt_dev;
1164 virt_dev = xhci->devs[slot_id];
1167 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1168 /* Delete default control endpoint resources */
1169 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1170 xhci_free_virt_device(xhci, slot_id);
1173 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1174 struct xhci_event_cmd *event, u32 cmd_comp_code)
1176 struct xhci_virt_device *virt_dev;
1177 struct xhci_input_control_ctx *ctrl_ctx;
1178 unsigned int ep_index;
1179 unsigned int ep_state;
1180 u32 add_flags, drop_flags;
1183 * Configure endpoint commands can come from the USB core
1184 * configuration or alt setting changes, or because the HW
1185 * needed an extra configure endpoint command after a reset
1186 * endpoint command or streams were being configured.
1187 * If the command was for a halted endpoint, the xHCI driver
1188 * is not waiting on the configure endpoint command.
1190 virt_dev = xhci->devs[slot_id];
1191 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1193 xhci_warn(xhci, "Could not get input context, bad type.\n");
1197 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1198 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1199 /* Input ctx add_flags are the endpoint index plus one */
1200 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1202 /* A usb_set_interface() call directly after clearing a halted
1203 * condition may race on this quirky hardware. Not worth
1204 * worrying about, since this is prototype hardware. Not sure
1205 * if this will work for streams, but streams support was
1206 * untested on this prototype.
1208 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1209 ep_index != (unsigned int) -1 &&
1210 add_flags - SLOT_FLAG == drop_flags) {
1211 ep_state = virt_dev->eps[ep_index].ep_state;
1212 if (!(ep_state & EP_HALTED))
1214 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1215 "Completed config ep cmd - "
1216 "last ep index = %d, state = %d",
1217 ep_index, ep_state);
1218 /* Clear internal halted state and restart ring(s) */
1219 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1220 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1226 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1227 struct xhci_event_cmd *event)
1229 xhci_dbg(xhci, "Completed reset device command.\n");
1230 if (!xhci->devs[slot_id])
1231 xhci_warn(xhci, "Reset device command completion "
1232 "for disabled slot %u\n", slot_id);
1235 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1236 struct xhci_event_cmd *event)
1238 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1239 xhci->error_bitmask |= 1 << 6;
1242 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1243 "NEC firmware version %2x.%02x",
1244 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1245 NEC_FW_MINOR(le32_to_cpu(event->status)));
1248 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1250 list_del(&cmd->cmd_list);
1252 if (cmd->completion) {
1253 cmd->status = status;
1254 complete(cmd->completion);
1260 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1262 struct xhci_command *cur_cmd, *tmp_cmd;
1263 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1264 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1267 void xhci_handle_command_timeout(struct work_struct *work)
1269 struct xhci_hcd *xhci;
1271 unsigned long flags;
1274 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1276 spin_lock_irqsave(&xhci->lock, flags);
1279 * If timeout work is pending, or current_cmd is NULL, it means we
1280 * raced with command completion. Command is handled so just return.
1282 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1283 spin_unlock_irqrestore(&xhci->lock, flags);
1286 /* mark this command to be cancelled */
1287 xhci->current_cmd->status = COMP_CMD_ABORT;
1289 /* Make sure command ring is running before aborting it */
1290 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1291 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1292 (hw_ring_state & CMD_RING_RUNNING)) {
1293 /* Prevent new doorbell, and start command abort */
1294 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1295 xhci_dbg(xhci, "Command timeout\n");
1296 ret = xhci_abort_cmd_ring(xhci, flags);
1297 if (unlikely(ret == -ESHUTDOWN)) {
1298 xhci_err(xhci, "Abort command ring failed\n");
1299 xhci_cleanup_command_queue(xhci);
1300 spin_unlock_irqrestore(&xhci->lock, flags);
1301 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1302 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1307 goto time_out_completed;
1310 /* host removed. Bail out */
1311 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1312 xhci_dbg(xhci, "host removed, ring start fail?\n");
1313 xhci_cleanup_command_queue(xhci);
1315 goto time_out_completed;
1318 /* command timeout on stopped ring, ring can't be aborted */
1319 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1320 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1323 spin_unlock_irqrestore(&xhci->lock, flags);
1327 static void handle_cmd_completion(struct xhci_hcd *xhci,
1328 struct xhci_event_cmd *event)
1330 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1332 dma_addr_t cmd_dequeue_dma;
1334 union xhci_trb *cmd_trb;
1335 struct xhci_command *cmd;
1338 cmd_dma = le64_to_cpu(event->cmd_trb);
1339 cmd_trb = xhci->cmd_ring->dequeue;
1340 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1342 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1343 if (cmd_dequeue_dma == 0) {
1344 xhci->error_bitmask |= 1 << 4;
1347 /* Does the DMA address match our internal dequeue pointer address? */
1348 if (cmd_dma != (u64) cmd_dequeue_dma) {
1349 xhci->error_bitmask |= 1 << 5;
1353 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1355 cancel_delayed_work(&xhci->cmd_timer);
1357 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1359 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1361 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1362 if (cmd_comp_code == COMP_CMD_STOP) {
1363 complete_all(&xhci->cmd_ring_stop_completion);
1367 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1369 "Command completion event does not match command\n");
1374 * Host aborted the command ring, check if the current command was
1375 * supposed to be aborted, otherwise continue normally.
1376 * The command ring is stopped now, but the xHC will issue a Command
1377 * Ring Stopped event which will cause us to restart it.
1379 if (cmd_comp_code == COMP_CMD_ABORT) {
1380 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1381 if (cmd->status == COMP_CMD_ABORT) {
1382 if (xhci->current_cmd == cmd)
1383 xhci->current_cmd = NULL;
1388 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1390 case TRB_ENABLE_SLOT:
1391 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1393 case TRB_DISABLE_SLOT:
1394 xhci_handle_cmd_disable_slot(xhci, slot_id);
1397 if (!cmd->completion)
1398 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1401 case TRB_EVAL_CONTEXT:
1406 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1407 le32_to_cpu(cmd_trb->generic.field[3])));
1408 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1411 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1412 le32_to_cpu(cmd_trb->generic.field[3])));
1413 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1416 /* Is this an aborted command turned to NO-OP? */
1417 if (cmd->status == COMP_CMD_STOP)
1418 cmd_comp_code = COMP_CMD_STOP;
1421 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1422 le32_to_cpu(cmd_trb->generic.field[3])));
1423 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1426 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1427 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1429 slot_id = TRB_TO_SLOT_ID(
1430 le32_to_cpu(cmd_trb->generic.field[3]));
1431 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1433 case TRB_NEC_GET_FW:
1434 xhci_handle_cmd_nec_get_fw(xhci, event);
1437 /* Skip over unknown commands on the event ring */
1438 xhci->error_bitmask |= 1 << 6;
1442 /* restart timer if this wasn't the last command */
1443 if (cmd->cmd_list.next != &xhci->cmd_list) {
1444 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1445 struct xhci_command, cmd_list);
1446 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1447 } else if (xhci->current_cmd == cmd) {
1448 xhci->current_cmd = NULL;
1452 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1454 inc_deq(xhci, xhci->cmd_ring);
1457 static void handle_vendor_event(struct xhci_hcd *xhci,
1458 union xhci_trb *event)
1462 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1463 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1464 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1465 handle_cmd_completion(xhci, &event->event_cmd);
1468 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1469 * port registers -- USB 3.0 and USB 2.0).
1471 * Returns a zero-based port number, which is suitable for indexing into each of
1472 * the split roothubs' port arrays and bus state arrays.
1473 * Add one to it in order to call xhci_find_slot_id_by_port.
1475 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1476 struct xhci_hcd *xhci, u32 port_id)
1479 unsigned int num_similar_speed_ports = 0;
1481 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1482 * and usb2_ports are 0-based indexes. Count the number of similar
1483 * speed ports, up to 1 port before this port.
1485 for (i = 0; i < (port_id - 1); i++) {
1486 u8 port_speed = xhci->port_array[i];
1489 * Skip ports that don't have known speeds, or have duplicate
1490 * Extended Capabilities port speed entries.
1492 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1496 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1497 * 1.1 ports are under the USB 2.0 hub. If the port speed
1498 * matches the device speed, it's a similar speed port.
1500 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1501 num_similar_speed_ports++;
1503 return num_similar_speed_ports;
1506 static void handle_device_notification(struct xhci_hcd *xhci,
1507 union xhci_trb *event)
1510 struct usb_device *udev;
1512 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1513 if (!xhci->devs[slot_id]) {
1514 xhci_warn(xhci, "Device Notification event for "
1515 "unused slot %u\n", slot_id);
1519 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1521 udev = xhci->devs[slot_id]->udev;
1522 if (udev && udev->parent)
1523 usb_wakeup_notification(udev->parent, udev->portnum);
1526 static void handle_port_status(struct xhci_hcd *xhci,
1527 union xhci_trb *event)
1529 struct usb_hcd *hcd;
1534 unsigned int faked_port_index;
1536 struct xhci_bus_state *bus_state;
1537 __le32 __iomem **port_array;
1538 bool bogus_port_status = false;
1540 /* Port status change events always have a successful completion code */
1541 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1542 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1543 xhci->error_bitmask |= 1 << 8;
1545 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1546 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1548 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1549 if ((port_id <= 0) || (port_id > max_ports)) {
1550 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1551 inc_deq(xhci, xhci->event_ring);
1555 /* Figure out which usb_hcd this port is attached to:
1556 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1558 major_revision = xhci->port_array[port_id - 1];
1560 /* Find the right roothub. */
1561 hcd = xhci_to_hcd(xhci);
1562 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1563 hcd = xhci->shared_hcd;
1565 if (major_revision == 0) {
1566 xhci_warn(xhci, "Event for port %u not in "
1567 "Extended Capabilities, ignoring.\n",
1569 bogus_port_status = true;
1572 if (major_revision == DUPLICATE_ENTRY) {
1573 xhci_warn(xhci, "Event for port %u duplicated in"
1574 "Extended Capabilities, ignoring.\n",
1576 bogus_port_status = true;
1581 * Hardware port IDs reported by a Port Status Change Event include USB
1582 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1583 * resume event, but we first need to translate the hardware port ID
1584 * into the index into the ports on the correct split roothub, and the
1585 * correct bus_state structure.
1587 bus_state = &xhci->bus_state[hcd_index(hcd)];
1588 if (hcd->speed >= HCD_USB3)
1589 port_array = xhci->usb3_ports;
1591 port_array = xhci->usb2_ports;
1592 /* Find the faked port hub number */
1593 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1596 temp = readl(port_array[faked_port_index]);
1597 if (hcd->state == HC_STATE_SUSPENDED) {
1598 xhci_dbg(xhci, "resume root hub\n");
1599 usb_hcd_resume_root_hub(hcd);
1602 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1603 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1605 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1606 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1608 temp1 = readl(&xhci->op_regs->command);
1609 if (!(temp1 & CMD_RUN)) {
1610 xhci_warn(xhci, "xHC is not running.\n");
1614 if (DEV_SUPERSPEED_ANY(temp)) {
1615 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1616 /* Set a flag to say the port signaled remote wakeup,
1617 * so we can tell the difference between the end of
1618 * device and host initiated resume.
1620 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1621 xhci_test_and_clear_bit(xhci, port_array,
1622 faked_port_index, PORT_PLC);
1623 xhci_set_link_state(xhci, port_array, faked_port_index,
1625 /* Need to wait until the next link state change
1626 * indicates the device is actually in U0.
1628 bogus_port_status = true;
1630 } else if (!test_bit(faked_port_index,
1631 &bus_state->resuming_ports)) {
1632 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1633 bus_state->resume_done[faked_port_index] = jiffies +
1634 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1635 set_bit(faked_port_index, &bus_state->resuming_ports);
1636 mod_timer(&hcd->rh_timer,
1637 bus_state->resume_done[faked_port_index]);
1638 /* Do the rest in GetPortStatus */
1642 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1643 DEV_SUPERSPEED_ANY(temp)) {
1644 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1645 /* We've just brought the device into U0 through either the
1646 * Resume state after a device remote wakeup, or through the
1647 * U3Exit state after a host-initiated resume. If it's a device
1648 * initiated remote wake, don't pass up the link state change,
1649 * so the roothub behavior is consistent with external
1650 * USB 3.0 hub behavior.
1652 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1653 faked_port_index + 1);
1654 if (slot_id && xhci->devs[slot_id])
1655 xhci_ring_device(xhci, slot_id);
1656 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1657 bus_state->port_remote_wakeup &=
1658 ~(1 << faked_port_index);
1659 xhci_test_and_clear_bit(xhci, port_array,
1660 faked_port_index, PORT_PLC);
1661 usb_wakeup_notification(hcd->self.root_hub,
1662 faked_port_index + 1);
1663 bogus_port_status = true;
1669 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1670 * RExit to a disconnect state). If so, let the the driver know it's
1671 * out of the RExit state.
1673 if (!DEV_SUPERSPEED_ANY(temp) &&
1674 test_and_clear_bit(faked_port_index,
1675 &bus_state->rexit_ports)) {
1676 complete(&bus_state->rexit_done[faked_port_index]);
1677 bogus_port_status = true;
1681 if (hcd->speed < HCD_USB3)
1682 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1686 /* Update event ring dequeue pointer before dropping the lock */
1687 inc_deq(xhci, xhci->event_ring);
1689 /* Don't make the USB core poll the roothub if we got a bad port status
1690 * change event. Besides, at that point we can't tell which roothub
1691 * (USB 2.0 or USB 3.0) to kick.
1693 if (bogus_port_status)
1697 * xHCI port-status-change events occur when the "or" of all the
1698 * status-change bits in the portsc register changes from 0 to 1.
1699 * New status changes won't cause an event if any other change
1700 * bits are still set. When an event occurs, switch over to
1701 * polling to avoid losing status changes.
1703 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1704 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1705 spin_unlock(&xhci->lock);
1706 /* Pass this up to the core */
1707 usb_hcd_poll_rh_status(hcd);
1708 spin_lock(&xhci->lock);
1712 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1713 * at end_trb, which may be in another segment. If the suspect DMA address is a
1714 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1717 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1718 struct xhci_segment *start_seg,
1719 union xhci_trb *start_trb,
1720 union xhci_trb *end_trb,
1721 dma_addr_t suspect_dma,
1724 dma_addr_t start_dma;
1725 dma_addr_t end_seg_dma;
1726 dma_addr_t end_trb_dma;
1727 struct xhci_segment *cur_seg;
1729 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1730 cur_seg = start_seg;
1735 /* We may get an event for a Link TRB in the middle of a TD */
1736 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1737 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1738 /* If the end TRB isn't in this segment, this is set to 0 */
1739 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1743 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1744 (unsigned long long)suspect_dma,
1745 (unsigned long long)start_dma,
1746 (unsigned long long)end_trb_dma,
1747 (unsigned long long)cur_seg->dma,
1748 (unsigned long long)end_seg_dma);
1750 if (end_trb_dma > 0) {
1751 /* The end TRB is in this segment, so suspect should be here */
1752 if (start_dma <= end_trb_dma) {
1753 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1756 /* Case for one segment with
1757 * a TD wrapped around to the top
1759 if ((suspect_dma >= start_dma &&
1760 suspect_dma <= end_seg_dma) ||
1761 (suspect_dma >= cur_seg->dma &&
1762 suspect_dma <= end_trb_dma))
1767 /* Might still be somewhere in this segment */
1768 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1771 cur_seg = cur_seg->next;
1772 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1773 } while (cur_seg != start_seg);
1778 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1779 unsigned int slot_id, unsigned int ep_index,
1780 unsigned int stream_id,
1781 struct xhci_td *td, union xhci_trb *event_trb)
1783 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1784 struct xhci_command *command;
1785 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1789 ep->ep_state |= EP_HALTED;
1790 ep->stopped_stream = stream_id;
1792 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1793 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1795 ep->stopped_stream = 0;
1797 xhci_ring_cmd_db(xhci);
1800 /* Check if an error has halted the endpoint ring. The class driver will
1801 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1802 * However, a babble and other errors also halt the endpoint ring, and the class
1803 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1804 * Ring Dequeue Pointer command manually.
1806 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1807 struct xhci_ep_ctx *ep_ctx,
1808 unsigned int trb_comp_code)
1810 /* TRB completion codes that may require a manual halt cleanup */
1811 if (trb_comp_code == COMP_TX_ERR ||
1812 trb_comp_code == COMP_BABBLE ||
1813 trb_comp_code == COMP_SPLIT_ERR)
1814 /* The 0.96 spec says a babbling control endpoint
1815 * is not halted. The 0.96 spec says it is. Some HW
1816 * claims to be 0.95 compliant, but it halts the control
1817 * endpoint anyway. Check if a babble halted the
1820 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1821 cpu_to_le32(EP_STATE_HALTED))
1827 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1829 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1830 /* Vendor defined "informational" completion code,
1831 * treat as not-an-error.
1833 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1835 xhci_dbg(xhci, "Treating code as success.\n");
1842 * Finish the td processing, remove the td from td list;
1843 * Return 1 if the urb can be given back.
1845 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1846 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1847 struct xhci_virt_ep *ep, int *status, bool skip)
1849 struct xhci_virt_device *xdev;
1850 struct xhci_ring *ep_ring;
1851 unsigned int slot_id;
1853 struct urb *urb = NULL;
1854 struct xhci_ep_ctx *ep_ctx;
1856 struct urb_priv *urb_priv;
1859 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1860 xdev = xhci->devs[slot_id];
1861 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1862 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1863 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1864 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1869 if (trb_comp_code == COMP_STOP_INVAL ||
1870 trb_comp_code == COMP_STOP ||
1871 trb_comp_code == COMP_STOP_SHORT) {
1872 /* The Endpoint Stop Command completion will take care of any
1873 * stopped TDs. A stopped TD may be restarted, so don't update
1874 * the ring dequeue pointer or take this TD off any lists yet.
1876 ep->stopped_td = td;
1879 if (trb_comp_code == COMP_STALL ||
1880 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1882 /* Issue a reset endpoint command to clear the host side
1883 * halt, followed by a set dequeue command to move the
1884 * dequeue pointer past the TD.
1885 * The class driver clears the device side halt later.
1887 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1888 ep_ring->stream_id, td, event_trb);
1890 /* Update ring dequeue pointer */
1891 while (ep_ring->dequeue != td->last_trb)
1892 inc_deq(xhci, ep_ring);
1893 inc_deq(xhci, ep_ring);
1897 /* Clean up the endpoint's TD list */
1899 urb_priv = urb->hcpriv;
1901 /* Do one last check of the actual transfer length.
1902 * If the host controller said we transferred more data than the buffer
1903 * length, urb->actual_length will be a very big number (since it's
1904 * unsigned). Play it safe and say we didn't transfer anything.
1906 if (urb->actual_length > urb->transfer_buffer_length) {
1907 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1908 urb->transfer_buffer_length,
1909 urb->actual_length);
1910 urb->actual_length = 0;
1911 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1912 *status = -EREMOTEIO;
1916 list_del_init(&td->td_list);
1917 /* Was this TD slated to be cancelled but completed anyway? */
1918 if (!list_empty(&td->cancelled_td_list))
1919 list_del_init(&td->cancelled_td_list);
1922 /* Giveback the urb when all the tds are completed */
1923 if (urb_priv->td_cnt == urb_priv->length) {
1925 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1926 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1927 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1928 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1929 usb_amd_quirk_pll_enable();
1938 * Process control tds, update urb status and actual_length.
1940 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1941 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1942 struct xhci_virt_ep *ep, int *status)
1944 struct xhci_virt_device *xdev;
1945 struct xhci_ring *ep_ring;
1946 unsigned int slot_id;
1948 struct xhci_ep_ctx *ep_ctx;
1951 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1952 xdev = xhci->devs[slot_id];
1953 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1954 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1955 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1956 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1958 switch (trb_comp_code) {
1960 if (event_trb == ep_ring->dequeue) {
1961 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1962 "without IOC set??\n");
1963 *status = -ESHUTDOWN;
1964 } else if (event_trb != td->last_trb) {
1965 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1966 "without IOC set??\n");
1967 *status = -ESHUTDOWN;
1973 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1974 *status = -EREMOTEIO;
1978 case COMP_STOP_SHORT:
1979 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1980 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1982 td->urb->actual_length =
1983 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1985 return finish_td(xhci, td, event_trb, event, ep, status, false);
1987 /* Did we stop at data stage? */
1988 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
1989 td->urb->actual_length =
1990 td->urb->transfer_buffer_length -
1991 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1993 case COMP_STOP_INVAL:
1994 return finish_td(xhci, td, event_trb, event, ep, status, false);
1996 if (!xhci_requires_manual_halt_cleanup(xhci,
1997 ep_ctx, trb_comp_code))
1999 xhci_dbg(xhci, "TRB error code %u, "
2000 "halted endpoint index = %u\n",
2001 trb_comp_code, ep_index);
2002 /* else fall through */
2004 /* Did we transfer part of the data (middle) phase? */
2005 if (event_trb != ep_ring->dequeue &&
2006 event_trb != td->last_trb)
2007 td->urb->actual_length =
2008 td->urb->transfer_buffer_length -
2009 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2010 else if (!td->urb_length_set)
2011 td->urb->actual_length = 0;
2013 return finish_td(xhci, td, event_trb, event, ep, status, false);
2016 * Did we transfer any data, despite the errors that might have
2017 * happened? I.e. did we get past the setup stage?
2019 if (event_trb != ep_ring->dequeue) {
2020 /* The event was for the status stage */
2021 if (event_trb == td->last_trb) {
2022 if (td->urb_length_set) {
2023 /* Don't overwrite a previously set error code
2025 if ((*status == -EINPROGRESS || *status == 0) &&
2026 (td->urb->transfer_flags
2027 & URB_SHORT_NOT_OK))
2028 /* Did we already see a short data
2030 *status = -EREMOTEIO;
2032 td->urb->actual_length =
2033 td->urb->transfer_buffer_length;
2037 * Maybe the event was for the data stage? If so, update
2038 * already the actual_length of the URB and flag it as
2039 * set, so that it is not overwritten in the event for
2042 td->urb_length_set = true;
2043 td->urb->actual_length =
2044 td->urb->transfer_buffer_length -
2045 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2046 xhci_dbg(xhci, "Waiting for status "
2052 return finish_td(xhci, td, event_trb, event, ep, status, false);
2056 * Process isochronous tds, update urb packet status and actual_length.
2058 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2059 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2060 struct xhci_virt_ep *ep, int *status)
2062 struct xhci_ring *ep_ring;
2063 struct urb_priv *urb_priv;
2066 union xhci_trb *cur_trb;
2067 struct xhci_segment *cur_seg;
2068 struct usb_iso_packet_descriptor *frame;
2070 bool skip_td = false;
2072 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2073 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2074 urb_priv = td->urb->hcpriv;
2075 idx = urb_priv->td_cnt;
2076 frame = &td->urb->iso_frame_desc[idx];
2078 /* handle completion code */
2079 switch (trb_comp_code) {
2081 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2085 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2086 trb_comp_code = COMP_SHORT_TX;
2088 case COMP_STOP_SHORT:
2090 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2094 frame->status = -ECOMM;
2097 case COMP_BUFF_OVER:
2099 frame->status = -EOVERFLOW;
2104 frame->status = -EPROTO;
2108 frame->status = -EPROTO;
2109 if (event_trb != td->last_trb)
2114 case COMP_STOP_INVAL:
2121 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2122 frame->actual_length = frame->length;
2123 td->urb->actual_length += frame->length;
2124 } else if (trb_comp_code == COMP_STOP_SHORT) {
2125 frame->actual_length =
2126 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2127 td->urb->actual_length += frame->actual_length;
2129 for (cur_trb = ep_ring->dequeue,
2130 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2131 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2132 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2133 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2134 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2136 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2137 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2139 if (trb_comp_code != COMP_STOP_INVAL) {
2140 frame->actual_length = len;
2141 td->urb->actual_length += len;
2145 return finish_td(xhci, td, event_trb, event, ep, status, false);
2148 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2149 struct xhci_transfer_event *event,
2150 struct xhci_virt_ep *ep, int *status)
2152 struct xhci_ring *ep_ring;
2153 struct urb_priv *urb_priv;
2154 struct usb_iso_packet_descriptor *frame;
2157 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2158 urb_priv = td->urb->hcpriv;
2159 idx = urb_priv->td_cnt;
2160 frame = &td->urb->iso_frame_desc[idx];
2162 /* The transfer is partly done. */
2163 frame->status = -EXDEV;
2165 /* calc actual length */
2166 frame->actual_length = 0;
2168 /* Update ring dequeue pointer */
2169 while (ep_ring->dequeue != td->last_trb)
2170 inc_deq(xhci, ep_ring);
2171 inc_deq(xhci, ep_ring);
2173 return finish_td(xhci, td, NULL, event, ep, status, true);
2177 * Process bulk and interrupt tds, update urb status and actual_length.
2179 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2180 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2181 struct xhci_virt_ep *ep, int *status)
2183 struct xhci_ring *ep_ring;
2184 union xhci_trb *cur_trb;
2185 struct xhci_segment *cur_seg;
2188 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2189 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2191 switch (trb_comp_code) {
2193 /* Double check that the HW transferred everything. */
2194 if (event_trb != td->last_trb ||
2195 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2196 xhci_warn(xhci, "WARN Successful completion "
2198 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2199 *status = -EREMOTEIO;
2202 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2203 trb_comp_code = COMP_SHORT_TX;
2208 case COMP_STOP_SHORT:
2210 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2211 *status = -EREMOTEIO;
2216 /* Others already handled above */
2219 if (trb_comp_code == COMP_SHORT_TX)
2220 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2221 "%d bytes untransferred\n",
2222 td->urb->ep->desc.bEndpointAddress,
2223 td->urb->transfer_buffer_length,
2224 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2225 /* Stopped - short packet completion */
2226 if (trb_comp_code == COMP_STOP_SHORT) {
2227 td->urb->actual_length =
2228 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2230 if (td->urb->transfer_buffer_length <
2231 td->urb->actual_length) {
2232 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2233 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2234 td->urb->actual_length = 0;
2235 /* status will be set by usb core for canceled urbs */
2237 /* Fast path - was this the last TRB in the TD for this URB? */
2238 } else if (event_trb == td->last_trb) {
2239 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2240 td->urb->actual_length =
2241 td->urb->transfer_buffer_length -
2242 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2243 if (td->urb->transfer_buffer_length <
2244 td->urb->actual_length) {
2245 xhci_warn(xhci, "HC gave bad length "
2246 "of %d bytes left\n",
2247 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2248 td->urb->actual_length = 0;
2249 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2250 *status = -EREMOTEIO;
2254 /* Don't overwrite a previously set error code */
2255 if (*status == -EINPROGRESS) {
2256 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2257 *status = -EREMOTEIO;
2262 td->urb->actual_length =
2263 td->urb->transfer_buffer_length;
2264 /* Ignore a short packet completion if the
2265 * untransferred length was zero.
2267 if (*status == -EREMOTEIO)
2271 /* Slow path - walk the list, starting from the dequeue
2272 * pointer, to get the actual length transferred.
2274 td->urb->actual_length = 0;
2275 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2276 cur_trb != event_trb;
2277 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2278 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2279 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2280 td->urb->actual_length +=
2281 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2283 /* If the ring didn't stop on a Link or No-op TRB, add
2284 * in the actual bytes transferred from the Normal TRB
2286 if (trb_comp_code != COMP_STOP_INVAL)
2287 td->urb->actual_length +=
2288 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2289 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2292 return finish_td(xhci, td, event_trb, event, ep, status, false);
2296 * If this function returns an error condition, it means it got a Transfer
2297 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2298 * At this point, the host controller is probably hosed and should be reset.
2300 static int handle_tx_event(struct xhci_hcd *xhci,
2301 struct xhci_transfer_event *event)
2302 __releases(&xhci->lock)
2303 __acquires(&xhci->lock)
2305 struct xhci_virt_device *xdev;
2306 struct xhci_virt_ep *ep;
2307 struct xhci_ring *ep_ring;
2308 unsigned int slot_id;
2310 struct xhci_td *td = NULL;
2311 dma_addr_t event_dma;
2312 struct xhci_segment *event_seg;
2313 union xhci_trb *event_trb;
2314 struct urb *urb = NULL;
2315 int status = -EINPROGRESS;
2316 struct urb_priv *urb_priv;
2317 struct xhci_ep_ctx *ep_ctx;
2318 struct list_head *tmp;
2322 bool handling_skipped_tds = false;
2324 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2325 xdev = xhci->devs[slot_id];
2327 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2328 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2329 (unsigned long long) xhci_trb_virt_to_dma(
2330 xhci->event_ring->deq_seg,
2331 xhci->event_ring->dequeue),
2332 lower_32_bits(le64_to_cpu(event->buffer)),
2333 upper_32_bits(le64_to_cpu(event->buffer)),
2334 le32_to_cpu(event->transfer_len),
2335 le32_to_cpu(event->flags));
2336 xhci_dbg(xhci, "Event ring:\n");
2337 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2341 /* Endpoint ID is 1 based, our index is zero based */
2342 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2343 ep = &xdev->eps[ep_index];
2344 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2345 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2347 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2348 EP_STATE_DISABLED) {
2349 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2350 "or incorrect stream ring\n");
2351 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2352 (unsigned long long) xhci_trb_virt_to_dma(
2353 xhci->event_ring->deq_seg,
2354 xhci->event_ring->dequeue),
2355 lower_32_bits(le64_to_cpu(event->buffer)),
2356 upper_32_bits(le64_to_cpu(event->buffer)),
2357 le32_to_cpu(event->transfer_len),
2358 le32_to_cpu(event->flags));
2359 xhci_dbg(xhci, "Event ring:\n");
2360 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2364 /* Count current td numbers if ep->skip is set */
2366 list_for_each(tmp, &ep_ring->td_list)
2370 event_dma = le64_to_cpu(event->buffer);
2371 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2372 /* Look for common error cases */
2373 switch (trb_comp_code) {
2374 /* Skip codes that require special handling depending on
2378 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2380 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2381 trb_comp_code = COMP_SHORT_TX;
2383 xhci_warn_ratelimited(xhci,
2384 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2388 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2390 case COMP_STOP_INVAL:
2391 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2393 case COMP_STOP_SHORT:
2394 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2397 xhci_dbg(xhci, "Stalled endpoint\n");
2398 ep->ep_state |= EP_HALTED;
2402 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2405 case COMP_SPLIT_ERR:
2407 xhci_dbg(xhci, "Transfer error on endpoint\n");
2411 xhci_dbg(xhci, "Babble error on endpoint\n");
2412 status = -EOVERFLOW;
2415 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2419 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2421 case COMP_BUFF_OVER:
2422 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2426 * When the Isoch ring is empty, the xHC will generate
2427 * a Ring Overrun Event for IN Isoch endpoint or Ring
2428 * Underrun Event for OUT Isoch endpoint.
2430 xhci_dbg(xhci, "underrun event on endpoint\n");
2431 if (!list_empty(&ep_ring->td_list))
2432 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2433 "still with TDs queued?\n",
2434 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2438 xhci_dbg(xhci, "overrun event on endpoint\n");
2439 if (!list_empty(&ep_ring->td_list))
2440 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2441 "still with TDs queued?\n",
2442 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2446 xhci_warn(xhci, "WARN: detect an incompatible device");
2449 case COMP_MISSED_INT:
2451 * When encounter missed service error, one or more isoc tds
2452 * may be missed by xHC.
2453 * Set skip flag of the ep_ring; Complete the missed tds as
2454 * short transfer when process the ep_ring next time.
2457 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2461 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2464 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2468 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2474 /* This TRB should be in the TD at the head of this ring's
2477 if (list_empty(&ep_ring->td_list)) {
2479 * A stopped endpoint may generate an extra completion
2480 * event if the device was suspended. Don't print
2483 if (!(trb_comp_code == COMP_STOP ||
2484 trb_comp_code == COMP_STOP_INVAL)) {
2485 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2486 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2488 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2489 (le32_to_cpu(event->flags) &
2490 TRB_TYPE_BITMASK)>>10);
2491 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2495 xhci_dbg(xhci, "td_list is empty while skip "
2496 "flag set. Clear skip flag.\n");
2502 /* We've skipped all the TDs on the ep ring when ep->skip set */
2503 if (ep->skip && td_num == 0) {
2505 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2506 "Clear skip flag.\n");
2511 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2515 /* Is this a TRB in the currently executing TD? */
2516 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2517 td->last_trb, event_dma, false);
2520 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2521 * is not in the current TD pointed by ep_ring->dequeue because
2522 * that the hardware dequeue pointer still at the previous TRB
2523 * of the current TD. The previous TRB maybe a Link TD or the
2524 * last TRB of the previous TD. The command completion handle
2525 * will take care the rest.
2527 if (!event_seg && (trb_comp_code == COMP_STOP ||
2528 trb_comp_code == COMP_STOP_INVAL)) {
2535 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2536 /* Some host controllers give a spurious
2537 * successful event after a short transfer.
2540 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2541 ep_ring->last_td_was_short) {
2542 ep_ring->last_td_was_short = false;
2546 /* HC is busted, give up! */
2548 "ERROR Transfer event TRB DMA ptr not "
2549 "part of current TD ep_index %d "
2550 "comp_code %u\n", ep_index,
2552 trb_in_td(xhci, ep_ring->deq_seg,
2553 ep_ring->dequeue, td->last_trb,
2558 ret = skip_isoc_td(xhci, td, event, ep, &status);
2561 if (trb_comp_code == COMP_SHORT_TX)
2562 ep_ring->last_td_was_short = true;
2564 ep_ring->last_td_was_short = false;
2567 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2571 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2572 sizeof(*event_trb)];
2574 * No-op TRB should not trigger interrupts.
2575 * If event_trb is a no-op TRB, it means the
2576 * corresponding TD has been cancelled. Just ignore
2579 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2581 "event_trb is a no-op TRB. Skip it\n");
2585 /* Now update the urb's actual_length and give back to
2588 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2589 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2591 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2592 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2595 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2601 handling_skipped_tds = ep->skip &&
2602 trb_comp_code != COMP_MISSED_INT &&
2603 trb_comp_code != COMP_PING_ERR;
2606 * Do not update event ring dequeue pointer if we're in a loop
2607 * processing missed tds.
2609 if (!handling_skipped_tds)
2610 inc_deq(xhci, xhci->event_ring);
2614 urb_priv = urb->hcpriv;
2616 xhci_urb_free_priv(urb_priv);
2618 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2619 if ((urb->actual_length != urb->transfer_buffer_length &&
2620 (urb->transfer_flags &
2621 URB_SHORT_NOT_OK)) ||
2623 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2624 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2625 "expected = %d, status = %d\n",
2626 urb, urb->actual_length,
2627 urb->transfer_buffer_length,
2629 spin_unlock(&xhci->lock);
2630 /* EHCI, UHCI, and OHCI always unconditionally set the
2631 * urb->status of an isochronous endpoint to 0.
2633 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2635 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2636 spin_lock(&xhci->lock);
2640 * If ep->skip is set, it means there are missed tds on the
2641 * endpoint ring need to take care of.
2642 * Process them as short transfer until reach the td pointed by
2645 } while (handling_skipped_tds);
2651 * This function handles all OS-owned events on the event ring. It may drop
2652 * xhci->lock between event processing (e.g. to pass up port status changes).
2653 * Returns >0 for "possibly more events to process" (caller should call again),
2654 * otherwise 0 if done. In future, <0 returns should indicate error code.
2656 static int xhci_handle_event(struct xhci_hcd *xhci)
2658 union xhci_trb *event;
2659 int update_ptrs = 1;
2662 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2663 xhci->error_bitmask |= 1 << 1;
2667 event = xhci->event_ring->dequeue;
2668 /* Does the HC or OS own the TRB? */
2669 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2670 xhci->event_ring->cycle_state) {
2671 xhci->error_bitmask |= 1 << 2;
2676 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2677 * speculative reads of the event's flags/data below.
2680 /* FIXME: Handle more event types. */
2681 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2682 case TRB_TYPE(TRB_COMPLETION):
2683 handle_cmd_completion(xhci, &event->event_cmd);
2685 case TRB_TYPE(TRB_PORT_STATUS):
2686 handle_port_status(xhci, event);
2689 case TRB_TYPE(TRB_TRANSFER):
2690 ret = handle_tx_event(xhci, &event->trans_event);
2692 xhci->error_bitmask |= 1 << 9;
2696 case TRB_TYPE(TRB_DEV_NOTE):
2697 handle_device_notification(xhci, event);
2700 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2702 handle_vendor_event(xhci, event);
2704 xhci->error_bitmask |= 1 << 3;
2706 /* Any of the above functions may drop and re-acquire the lock, so check
2707 * to make sure a watchdog timer didn't mark the host as non-responsive.
2709 if (xhci->xhc_state & XHCI_STATE_DYING) {
2710 xhci_dbg(xhci, "xHCI host dying, returning from "
2711 "event handler.\n");
2716 /* Update SW event ring dequeue pointer */
2717 inc_deq(xhci, xhci->event_ring);
2719 /* Are there more items on the event ring? Caller will call us again to
2726 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2727 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2728 * indicators of an event TRB error, but we check the status *first* to be safe.
2730 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2732 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2735 union xhci_trb *event_ring_deq;
2738 spin_lock(&xhci->lock);
2739 /* Check if the xHC generated the interrupt, or the irq is shared */
2740 status = readl(&xhci->op_regs->status);
2741 if (status == 0xffffffff)
2744 if (!(status & STS_EINT)) {
2745 spin_unlock(&xhci->lock);
2748 if (status & STS_FATAL) {
2749 xhci_warn(xhci, "WARNING: Host System Error\n");
2752 spin_unlock(&xhci->lock);
2757 * Clear the op reg interrupt status first,
2758 * so we can receive interrupts from other MSI-X interrupters.
2759 * Write 1 to clear the interrupt status.
2762 writel(status, &xhci->op_regs->status);
2763 /* FIXME when MSI-X is supported and there are multiple vectors */
2764 /* Clear the MSI-X event interrupt status */
2768 /* Acknowledge the PCI interrupt */
2769 irq_pending = readl(&xhci->ir_set->irq_pending);
2770 irq_pending |= IMAN_IP;
2771 writel(irq_pending, &xhci->ir_set->irq_pending);
2774 if (xhci->xhc_state & XHCI_STATE_DYING ||
2775 xhci->xhc_state & XHCI_STATE_HALTED) {
2776 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2777 "Shouldn't IRQs be disabled?\n");
2778 /* Clear the event handler busy flag (RW1C);
2779 * the event ring should be empty.
2781 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2782 xhci_write_64(xhci, temp_64 | ERST_EHB,
2783 &xhci->ir_set->erst_dequeue);
2784 spin_unlock(&xhci->lock);
2789 event_ring_deq = xhci->event_ring->dequeue;
2790 /* FIXME this should be a delayed service routine
2791 * that clears the EHB.
2793 while (xhci_handle_event(xhci) > 0) {}
2795 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2796 /* If necessary, update the HW's version of the event ring deq ptr. */
2797 if (event_ring_deq != xhci->event_ring->dequeue) {
2798 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2799 xhci->event_ring->dequeue);
2801 xhci_warn(xhci, "WARN something wrong with SW event "
2802 "ring dequeue ptr.\n");
2803 /* Update HC event ring dequeue pointer */
2804 temp_64 &= ERST_PTR_MASK;
2805 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2808 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2809 temp_64 |= ERST_EHB;
2810 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2812 spin_unlock(&xhci->lock);
2817 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2819 return xhci_irq(hcd);
2822 /**** Endpoint Ring Operations ****/
2825 * Generic function for queueing a TRB on a ring.
2826 * The caller must have checked to make sure there's room on the ring.
2828 * @more_trbs_coming: Will you enqueue more TRBs before calling
2829 * prepare_transfer()?
2831 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2832 bool more_trbs_coming,
2833 u32 field1, u32 field2, u32 field3, u32 field4)
2835 struct xhci_generic_trb *trb;
2837 trb = &ring->enqueue->generic;
2838 trb->field[0] = cpu_to_le32(field1);
2839 trb->field[1] = cpu_to_le32(field2);
2840 trb->field[2] = cpu_to_le32(field3);
2841 trb->field[3] = cpu_to_le32(field4);
2842 inc_enq(xhci, ring, more_trbs_coming);
2846 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2847 * FIXME allocate segments if the ring is full.
2849 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2850 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2852 unsigned int num_trbs_needed;
2854 /* Make sure the endpoint has been added to xHC schedule */
2856 case EP_STATE_DISABLED:
2858 * USB core changed config/interfaces without notifying us,
2859 * or hardware is reporting the wrong state.
2861 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2863 case EP_STATE_ERROR:
2864 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2865 /* FIXME event handling code for error needs to clear it */
2866 /* XXX not sure if this should be -ENOENT or not */
2868 case EP_STATE_HALTED:
2869 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2870 case EP_STATE_STOPPED:
2871 case EP_STATE_RUNNING:
2874 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2876 * FIXME issue Configure Endpoint command to try to get the HC
2877 * back into a known state.
2883 if (room_on_ring(xhci, ep_ring, num_trbs))
2886 if (ep_ring == xhci->cmd_ring) {
2887 xhci_err(xhci, "Do not support expand command ring\n");
2891 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2892 "ERROR no room on ep ring, try ring expansion");
2893 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2894 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2896 xhci_err(xhci, "Ring expansion failed\n");
2901 if (enqueue_is_link_trb(ep_ring)) {
2902 struct xhci_ring *ring = ep_ring;
2903 union xhci_trb *next;
2905 next = ring->enqueue;
2907 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2908 /* If we're not dealing with 0.95 hardware or isoc rings
2909 * on AMD 0.96 host, clear the chain bit.
2911 if (!xhci_link_trb_quirk(xhci) &&
2912 !(ring->type == TYPE_ISOC &&
2913 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2914 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2916 next->link.control |= cpu_to_le32(TRB_CHAIN);
2919 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2921 /* Toggle the cycle bit after the last ring segment. */
2922 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2923 ring->cycle_state ^= 1;
2925 ring->enq_seg = ring->enq_seg->next;
2926 ring->enqueue = ring->enq_seg->trbs;
2927 next = ring->enqueue;
2934 static int prepare_transfer(struct xhci_hcd *xhci,
2935 struct xhci_virt_device *xdev,
2936 unsigned int ep_index,
2937 unsigned int stream_id,
2938 unsigned int num_trbs,
2940 unsigned int td_index,
2944 struct urb_priv *urb_priv;
2946 struct xhci_ring *ep_ring;
2947 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2949 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2951 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2956 ret = prepare_ring(xhci, ep_ring,
2957 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2958 num_trbs, mem_flags);
2962 urb_priv = urb->hcpriv;
2963 td = urb_priv->td[td_index];
2965 INIT_LIST_HEAD(&td->td_list);
2966 INIT_LIST_HEAD(&td->cancelled_td_list);
2968 if (td_index == 0) {
2969 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2975 /* Add this TD to the tail of the endpoint ring's TD list */
2976 list_add_tail(&td->td_list, &ep_ring->td_list);
2977 td->start_seg = ep_ring->enq_seg;
2978 td->first_trb = ep_ring->enqueue;
2980 urb_priv->td[td_index] = td;
2985 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2987 int num_sgs, num_trbs, running_total, temp, i;
2988 struct scatterlist *sg;
2991 num_sgs = urb->num_mapped_sgs;
2992 temp = urb->transfer_buffer_length;
2995 for_each_sg(urb->sg, sg, num_sgs, i) {
2996 unsigned int len = sg_dma_len(sg);
2998 /* Scatter gather list entries may cross 64KB boundaries */
2999 running_total = TRB_MAX_BUFF_SIZE -
3000 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3001 running_total &= TRB_MAX_BUFF_SIZE - 1;
3002 if (running_total != 0)
3005 /* How many more 64KB chunks to transfer, how many more TRBs? */
3006 while (running_total < sg_dma_len(sg) && running_total < temp) {
3008 running_total += TRB_MAX_BUFF_SIZE;
3010 len = min_t(int, len, temp);
3018 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3021 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3022 "TRBs, %d left\n", __func__,
3023 urb->ep->desc.bEndpointAddress, num_trbs);
3024 if (running_total != urb->transfer_buffer_length)
3025 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3026 "queued %#x (%d), asked for %#x (%d)\n",
3028 urb->ep->desc.bEndpointAddress,
3029 running_total, running_total,
3030 urb->transfer_buffer_length,
3031 urb->transfer_buffer_length);
3034 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3035 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3036 struct xhci_generic_trb *start_trb)
3039 * Pass all the TRBs to the hardware at once and make sure this write
3044 start_trb->field[3] |= cpu_to_le32(start_cycle);
3046 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3047 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3051 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3052 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3053 * (comprised of sg list entries) can take several service intervals to
3056 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3057 struct urb *urb, int slot_id, unsigned int ep_index)
3059 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3060 xhci->devs[slot_id]->out_ctx, ep_index);
3064 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3065 ep_interval = urb->interval;
3066 /* Convert to microframes */
3067 if (urb->dev->speed == USB_SPEED_LOW ||
3068 urb->dev->speed == USB_SPEED_FULL)
3070 /* FIXME change this to a warning and a suggestion to use the new API
3071 * to set the polling interval (once the API is added).
3073 if (xhci_interval != ep_interval) {
3074 dev_dbg_ratelimited(&urb->dev->dev,
3075 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3076 ep_interval, ep_interval == 1 ? "" : "s",
3077 xhci_interval, xhci_interval == 1 ? "" : "s");
3078 urb->interval = xhci_interval;
3079 /* Convert back to frames for LS/FS devices */
3080 if (urb->dev->speed == USB_SPEED_LOW ||
3081 urb->dev->speed == USB_SPEED_FULL)
3084 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3088 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3089 * packets remaining in the TD (*not* including this TRB).
3091 * Total TD packet count = total_packet_count =
3092 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3094 * Packets transferred up to and including this TRB = packets_transferred =
3095 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3097 * TD size = total_packet_count - packets_transferred
3099 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3100 * including this TRB, right shifted by 10
3102 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3103 * This is taken care of in the TRB_TD_SIZE() macro
3105 * The last TRB in a TD must have the TD size set to zero.
3107 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3108 int trb_buff_len, unsigned int td_total_len,
3109 struct urb *urb, unsigned int num_trbs_left)
3111 u32 maxp, total_packet_count;
3113 if (xhci->hci_version < 0x100)
3114 return ((td_total_len - transferred) >> 10);
3116 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3117 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3119 /* One TRB with a zero-length data packet. */
3120 if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
3121 trb_buff_len == td_total_len)
3124 /* Queueing functions don't count the current TRB into transferred */
3125 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3129 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3130 struct urb *urb, int slot_id, unsigned int ep_index)
3132 struct xhci_ring *ep_ring;
3133 unsigned int num_trbs;
3134 struct urb_priv *urb_priv;
3136 struct scatterlist *sg;
3138 int trb_buff_len, this_sg_len, running_total, ret;
3139 unsigned int total_packet_count;
3140 bool zero_length_needed;
3144 bool more_trbs_coming;
3146 struct xhci_generic_trb *start_trb;
3149 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3153 num_trbs = count_sg_trbs_needed(xhci, urb);
3154 num_sgs = urb->num_mapped_sgs;
3155 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3156 usb_endpoint_maxp(&urb->ep->desc));
3158 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3159 ep_index, urb->stream_id,
3160 num_trbs, urb, 0, mem_flags);
3164 urb_priv = urb->hcpriv;
3166 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3167 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3168 urb_priv->length == 2;
3169 if (zero_length_needed) {
3171 xhci_dbg(xhci, "Creating zero length td.\n");
3172 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3173 ep_index, urb->stream_id,
3174 1, urb, 1, mem_flags);
3179 td = urb_priv->td[0];
3182 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3183 * until we've finished creating all the other TRBs. The ring's cycle
3184 * state may change as we enqueue the other TRBs, so save it too.
3186 start_trb = &ep_ring->enqueue->generic;
3187 start_cycle = ep_ring->cycle_state;
3191 * How much data is in the first TRB?
3193 * There are three forces at work for TRB buffer pointers and lengths:
3194 * 1. We don't want to walk off the end of this sg-list entry buffer.
3195 * 2. The transfer length that the driver requested may be smaller than
3196 * the amount of memory allocated for this scatter-gather list.
3197 * 3. TRBs buffers can't cross 64KB boundaries.
3200 addr = (u64) sg_dma_address(sg);
3201 this_sg_len = sg_dma_len(sg);
3202 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3203 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3204 if (trb_buff_len > urb->transfer_buffer_length)
3205 trb_buff_len = urb->transfer_buffer_length;
3208 last_trb_num = zero_length_needed ? 2 : 1;
3209 /* Queue the first TRB, even if it's zero-length */
3212 u32 length_field = 0;
3215 /* Don't change the cycle bit of the first TRB until later */
3218 if (start_cycle == 0)
3221 field |= ep_ring->cycle_state;
3223 /* Chain all the TRBs together; clear the chain bit in the last
3224 * TRB to indicate it's the last TRB in the chain.
3226 if (num_trbs > last_trb_num) {
3228 } else if (num_trbs == last_trb_num) {
3229 td->last_trb = ep_ring->enqueue;
3231 } else if (zero_length_needed && num_trbs == 1) {
3233 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3237 /* Only set interrupt on short packet for IN endpoints */
3238 if (usb_urb_dir_in(urb))
3241 if (TRB_MAX_BUFF_SIZE -
3242 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3243 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3244 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3245 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3246 (unsigned int) addr + trb_buff_len);
3249 /* Set the TRB length, TD size, and interrupter fields. */
3250 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3251 urb->transfer_buffer_length,
3254 length_field = TRB_LEN(trb_buff_len) |
3255 TRB_TD_SIZE(remainder) |
3259 more_trbs_coming = true;
3261 more_trbs_coming = false;
3262 queue_trb(xhci, ep_ring, more_trbs_coming,
3263 lower_32_bits(addr),
3264 upper_32_bits(addr),
3266 field | TRB_TYPE(TRB_NORMAL));
3268 running_total += trb_buff_len;
3270 /* Calculate length for next transfer --
3271 * Are we done queueing all the TRBs for this sg entry?
3273 this_sg_len -= trb_buff_len;
3274 if (this_sg_len == 0) {
3279 addr = (u64) sg_dma_address(sg);
3280 this_sg_len = sg_dma_len(sg);
3282 addr += trb_buff_len;
3285 trb_buff_len = TRB_MAX_BUFF_SIZE -
3286 (addr & (TRB_MAX_BUFF_SIZE - 1));
3287 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3288 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3290 urb->transfer_buffer_length - running_total;
3291 } while (num_trbs > 0);
3293 check_trb_math(urb, num_trbs, running_total);
3294 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3295 start_cycle, start_trb);
3299 /* This is very similar to what ehci-q.c qtd_fill() does */
3300 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3301 struct urb *urb, int slot_id, unsigned int ep_index)
3303 struct xhci_ring *ep_ring;
3304 struct urb_priv *urb_priv;
3307 struct xhci_generic_trb *start_trb;
3310 bool more_trbs_coming;
3311 bool zero_length_needed;
3313 u32 field, length_field;
3315 int running_total, trb_buff_len, ret;
3316 unsigned int total_packet_count;
3320 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3322 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3327 /* How much data is (potentially) left before the 64KB boundary? */
3328 running_total = TRB_MAX_BUFF_SIZE -
3329 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3330 running_total &= TRB_MAX_BUFF_SIZE - 1;
3332 /* If there's some data on this 64KB chunk, or we have to send a
3333 * zero-length transfer, we need at least one TRB
3335 if (running_total != 0 || urb->transfer_buffer_length == 0)
3337 /* How many more 64KB chunks to transfer, how many more TRBs? */
3338 while (running_total < urb->transfer_buffer_length) {
3340 running_total += TRB_MAX_BUFF_SIZE;
3343 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3344 ep_index, urb->stream_id,
3345 num_trbs, urb, 0, mem_flags);
3349 urb_priv = urb->hcpriv;
3351 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3352 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3353 urb_priv->length == 2;
3354 if (zero_length_needed) {
3356 xhci_dbg(xhci, "Creating zero length td.\n");
3357 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3358 ep_index, urb->stream_id,
3359 1, urb, 1, mem_flags);
3364 td = urb_priv->td[0];
3367 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3368 * until we've finished creating all the other TRBs. The ring's cycle
3369 * state may change as we enqueue the other TRBs, so save it too.
3371 start_trb = &ep_ring->enqueue->generic;
3372 start_cycle = ep_ring->cycle_state;
3375 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3376 usb_endpoint_maxp(&urb->ep->desc));
3377 /* How much data is in the first TRB? */
3378 addr = (u64) urb->transfer_dma;
3379 trb_buff_len = TRB_MAX_BUFF_SIZE -
3380 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3381 if (trb_buff_len > urb->transfer_buffer_length)
3382 trb_buff_len = urb->transfer_buffer_length;
3385 last_trb_num = zero_length_needed ? 2 : 1;
3386 /* Queue the first TRB, even if it's zero-length */
3391 /* Don't change the cycle bit of the first TRB until later */
3394 if (start_cycle == 0)
3397 field |= ep_ring->cycle_state;
3399 /* Chain all the TRBs together; clear the chain bit in the last
3400 * TRB to indicate it's the last TRB in the chain.
3402 if (num_trbs > last_trb_num) {
3404 } else if (num_trbs == last_trb_num) {
3405 td->last_trb = ep_ring->enqueue;
3407 } else if (zero_length_needed && num_trbs == 1) {
3409 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3413 /* Only set interrupt on short packet for IN endpoints */
3414 if (usb_urb_dir_in(urb))
3417 /* Set the TRB length, TD size, and interrupter fields. */
3418 remainder = xhci_td_remainder(xhci, running_total, trb_buff_len,
3419 urb->transfer_buffer_length,
3422 length_field = TRB_LEN(trb_buff_len) |
3423 TRB_TD_SIZE(remainder) |
3427 more_trbs_coming = true;
3429 more_trbs_coming = false;
3430 queue_trb(xhci, ep_ring, more_trbs_coming,
3431 lower_32_bits(addr),
3432 upper_32_bits(addr),
3434 field | TRB_TYPE(TRB_NORMAL));
3436 running_total += trb_buff_len;
3438 /* Calculate length for next transfer */
3439 addr += trb_buff_len;
3440 trb_buff_len = urb->transfer_buffer_length - running_total;
3441 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3442 trb_buff_len = TRB_MAX_BUFF_SIZE;
3443 } while (num_trbs > 0);
3445 check_trb_math(urb, num_trbs, running_total);
3446 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3447 start_cycle, start_trb);
3451 /* Caller must have locked xhci->lock */
3452 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3453 struct urb *urb, int slot_id, unsigned int ep_index)
3455 struct xhci_ring *ep_ring;
3458 struct usb_ctrlrequest *setup;
3459 struct xhci_generic_trb *start_trb;
3461 u32 field, length_field, remainder;
3462 struct urb_priv *urb_priv;
3465 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3470 * Need to copy setup packet into setup TRB, so we can't use the setup
3473 if (!urb->setup_packet)
3476 /* 1 TRB for setup, 1 for status */
3479 * Don't need to check if we need additional event data and normal TRBs,
3480 * since data in control transfers will never get bigger than 16MB
3481 * XXX: can we get a buffer that crosses 64KB boundaries?
3483 if (urb->transfer_buffer_length > 0)
3485 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3486 ep_index, urb->stream_id,
3487 num_trbs, urb, 0, mem_flags);
3491 urb_priv = urb->hcpriv;
3492 td = urb_priv->td[0];
3495 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3496 * until we've finished creating all the other TRBs. The ring's cycle
3497 * state may change as we enqueue the other TRBs, so save it too.
3499 start_trb = &ep_ring->enqueue->generic;
3500 start_cycle = ep_ring->cycle_state;
3502 /* Queue setup TRB - see section 6.4.1.2.1 */
3503 /* FIXME better way to translate setup_packet into two u32 fields? */
3504 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3506 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3507 if (start_cycle == 0)
3510 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3511 if (xhci->hci_version >= 0x100) {
3512 if (urb->transfer_buffer_length > 0) {
3513 if (setup->bRequestType & USB_DIR_IN)
3514 field |= TRB_TX_TYPE(TRB_DATA_IN);
3516 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3520 queue_trb(xhci, ep_ring, true,
3521 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3522 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3523 TRB_LEN(8) | TRB_INTR_TARGET(0),
3524 /* Immediate data in pointer */
3527 /* If there's data, queue data TRBs */
3528 /* Only set interrupt on short packet for IN endpoints */
3529 if (usb_urb_dir_in(urb))
3530 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3532 field = TRB_TYPE(TRB_DATA);
3534 remainder = xhci_td_remainder(xhci, 0,
3535 urb->transfer_buffer_length,
3536 urb->transfer_buffer_length,
3539 length_field = TRB_LEN(urb->transfer_buffer_length) |
3540 TRB_TD_SIZE(remainder) |
3543 if (urb->transfer_buffer_length > 0) {
3544 if (setup->bRequestType & USB_DIR_IN)
3545 field |= TRB_DIR_IN;
3546 queue_trb(xhci, ep_ring, true,
3547 lower_32_bits(urb->transfer_dma),
3548 upper_32_bits(urb->transfer_dma),
3550 field | ep_ring->cycle_state);
3553 /* Save the DMA address of the last TRB in the TD */
3554 td->last_trb = ep_ring->enqueue;
3556 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3557 /* If the device sent data, the status stage is an OUT transfer */
3558 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3562 queue_trb(xhci, ep_ring, false,
3566 /* Event on completion */
3567 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3569 giveback_first_trb(xhci, slot_id, ep_index, 0,
3570 start_cycle, start_trb);
3574 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3575 struct urb *urb, int i)
3580 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3581 td_len = urb->iso_frame_desc[i].length;
3583 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3592 * The transfer burst count field of the isochronous TRB defines the number of
3593 * bursts that are required to move all packets in this TD. Only SuperSpeed
3594 * devices can burst up to bMaxBurst number of packets per service interval.
3595 * This field is zero based, meaning a value of zero in the field means one
3596 * burst. Basically, for everything but SuperSpeed devices, this field will be
3597 * zero. Only xHCI 1.0 host controllers support this field.
3599 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3600 struct usb_device *udev,
3601 struct urb *urb, unsigned int total_packet_count)
3603 unsigned int max_burst;
3605 if (xhci->hci_version < 0x100 || udev->speed < USB_SPEED_SUPER)
3608 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3609 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3613 * Returns the number of packets in the last "burst" of packets. This field is
3614 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3615 * the last burst packet count is equal to the total number of packets in the
3616 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3617 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3618 * contain 1 to (bMaxBurst + 1) packets.
3620 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3621 struct usb_device *udev,
3622 struct urb *urb, unsigned int total_packet_count)
3624 unsigned int max_burst;
3625 unsigned int residue;
3627 if (xhci->hci_version < 0x100)
3630 switch (udev->speed) {
3631 case USB_SPEED_SUPER_PLUS:
3632 case USB_SPEED_SUPER:
3633 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3634 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3635 residue = total_packet_count % (max_burst + 1);
3636 /* If residue is zero, the last burst contains (max_burst + 1)
3637 * number of packets, but the TLBPC field is zero-based.
3643 if (total_packet_count == 0)
3645 return total_packet_count - 1;
3650 * Calculates Frame ID field of the isochronous TRB identifies the
3651 * target frame that the Interval associated with this Isochronous
3652 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3654 * Returns actual frame id on success, negative value on error.
3656 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3657 struct urb *urb, int index)
3659 int start_frame, ist, ret = 0;
3660 int start_frame_id, end_frame_id, current_frame_id;
3662 if (urb->dev->speed == USB_SPEED_LOW ||
3663 urb->dev->speed == USB_SPEED_FULL)
3664 start_frame = urb->start_frame + index * urb->interval;
3666 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3668 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3670 * If bit [3] of IST is cleared to '0', software can add a TRB no
3671 * later than IST[2:0] Microframes before that TRB is scheduled to
3673 * If bit [3] of IST is set to '1', software can add a TRB no later
3674 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3676 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3677 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3680 /* Software shall not schedule an Isoch TD with a Frame ID value that
3681 * is less than the Start Frame ID or greater than the End Frame ID,
3684 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3685 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3687 * Both the End Frame ID and Start Frame ID values are calculated
3688 * in microframes. When software determines the valid Frame ID value;
3689 * The End Frame ID value should be rounded down to the nearest Frame
3690 * boundary, and the Start Frame ID value should be rounded up to the
3691 * nearest Frame boundary.
3693 current_frame_id = readl(&xhci->run_regs->microframe_index);
3694 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3695 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3697 start_frame &= 0x7ff;
3698 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3699 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3701 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3702 __func__, index, readl(&xhci->run_regs->microframe_index),
3703 start_frame_id, end_frame_id, start_frame);
3705 if (start_frame_id < end_frame_id) {
3706 if (start_frame > end_frame_id ||
3707 start_frame < start_frame_id)
3709 } else if (start_frame_id > end_frame_id) {
3710 if ((start_frame > end_frame_id &&
3711 start_frame < start_frame_id))
3718 if (ret == -EINVAL || start_frame == start_frame_id) {
3719 start_frame = start_frame_id + 1;
3720 if (urb->dev->speed == USB_SPEED_LOW ||
3721 urb->dev->speed == USB_SPEED_FULL)
3722 urb->start_frame = start_frame;
3724 urb->start_frame = start_frame << 3;
3730 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3731 start_frame, current_frame_id, index,
3732 start_frame_id, end_frame_id);
3733 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3740 /* This is for isoc transfer */
3741 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3742 struct urb *urb, int slot_id, unsigned int ep_index)
3744 struct xhci_ring *ep_ring;
3745 struct urb_priv *urb_priv;
3747 int num_tds, trbs_per_td;
3748 struct xhci_generic_trb *start_trb;
3751 u32 field, length_field;
3752 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3753 u64 start_addr, addr;
3755 bool more_trbs_coming;
3756 struct xhci_virt_ep *xep;
3758 xep = &xhci->devs[slot_id]->eps[ep_index];
3759 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3761 num_tds = urb->number_of_packets;
3763 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3767 start_addr = (u64) urb->transfer_dma;
3768 start_trb = &ep_ring->enqueue->generic;
3769 start_cycle = ep_ring->cycle_state;
3771 urb_priv = urb->hcpriv;
3772 /* Queue the first TRB, even if it's zero-length */
3773 for (i = 0; i < num_tds; i++) {
3774 unsigned int total_packet_count;
3775 unsigned int burst_count;
3776 unsigned int residue;
3780 addr = start_addr + urb->iso_frame_desc[i].offset;
3781 td_len = urb->iso_frame_desc[i].length;
3782 td_remain_len = td_len;
3783 total_packet_count = DIV_ROUND_UP(td_len,
3785 usb_endpoint_maxp(&urb->ep->desc)));
3786 /* A zero-length transfer still involves at least one packet. */
3787 if (total_packet_count == 0)
3788 total_packet_count++;
3789 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3790 total_packet_count);
3791 residue = xhci_get_last_burst_packet_count(xhci,
3792 urb->dev, urb, total_packet_count);
3794 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3796 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3797 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3804 td = urb_priv->td[i];
3805 for (j = 0; j < trbs_per_td; j++) {
3811 field = TRB_TBC(burst_count) |
3813 /* Queue the isoc TRB */
3814 field |= TRB_TYPE(TRB_ISOC);
3816 /* Calculate Frame ID and SIA fields */
3817 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3818 HCC_CFC(xhci->hcc_params)) {
3819 frame_id = xhci_get_isoc_frame_id(xhci,
3823 field |= TRB_FRAME_ID(frame_id);
3830 if (start_cycle == 0)
3833 field |= ep_ring->cycle_state;
3836 /* Queue other normal TRBs */
3837 field |= TRB_TYPE(TRB_NORMAL);
3838 field |= ep_ring->cycle_state;
3841 /* Only set interrupt on short packet for IN EPs */
3842 if (usb_urb_dir_in(urb))
3845 /* Chain all the TRBs together; clear the chain bit in
3846 * the last TRB to indicate it's the last TRB in the
3849 if (j < trbs_per_td - 1) {
3851 more_trbs_coming = true;
3853 td->last_trb = ep_ring->enqueue;
3855 if (xhci->hci_version == 0x100 &&
3858 /* Set BEI bit except for the last td */
3859 if (i < num_tds - 1)
3862 more_trbs_coming = false;
3865 /* Calculate TRB length */
3866 trb_buff_len = TRB_MAX_BUFF_SIZE -
3867 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3868 if (trb_buff_len > td_remain_len)
3869 trb_buff_len = td_remain_len;
3871 /* Set the TRB length, TD size, & interrupter fields. */
3872 remainder = xhci_td_remainder(xhci, running_total,
3873 trb_buff_len, td_len,
3874 urb, trbs_per_td - j - 1);
3876 length_field = TRB_LEN(trb_buff_len) |
3877 TRB_TD_SIZE(remainder) |
3880 queue_trb(xhci, ep_ring, more_trbs_coming,
3881 lower_32_bits(addr),
3882 upper_32_bits(addr),
3885 running_total += trb_buff_len;
3887 addr += trb_buff_len;
3888 td_remain_len -= trb_buff_len;
3891 /* Check TD length */
3892 if (running_total != td_len) {
3893 xhci_err(xhci, "ISOC TD length unmatch\n");
3899 /* store the next frame id */
3900 if (HCC_CFC(xhci->hcc_params))
3901 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3903 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3904 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3905 usb_amd_quirk_pll_disable();
3907 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3909 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3910 start_cycle, start_trb);
3913 /* Clean up a partially enqueued isoc transfer. */
3915 for (i--; i >= 0; i--)
3916 list_del_init(&urb_priv->td[i]->td_list);
3918 /* Use the first TD as a temporary variable to turn the TDs we've queued
3919 * into No-ops with a software-owned cycle bit. That way the hardware
3920 * won't accidentally start executing bogus TDs when we partially
3921 * overwrite them. td->first_trb and td->start_seg are already set.
3923 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3924 /* Every TRB except the first & last will have its cycle bit flipped. */
3925 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3927 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3928 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3929 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3930 ep_ring->cycle_state = start_cycle;
3931 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3932 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3937 * Check transfer ring to guarantee there is enough room for the urb.
3938 * Update ISO URB start_frame and interval.
3939 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3940 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3941 * Contiguous Frame ID is not supported by HC.
3943 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3944 struct urb *urb, int slot_id, unsigned int ep_index)
3946 struct xhci_virt_device *xdev;
3947 struct xhci_ring *ep_ring;
3948 struct xhci_ep_ctx *ep_ctx;
3952 int num_tds, num_trbs, i;
3954 struct xhci_virt_ep *xep;
3957 xdev = xhci->devs[slot_id];
3958 xep = &xhci->devs[slot_id]->eps[ep_index];
3959 ep_ring = xdev->eps[ep_index].ring;
3960 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3963 num_tds = urb->number_of_packets;
3964 for (i = 0; i < num_tds; i++)
3965 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3967 /* Check the ring to guarantee there is enough room for the whole urb.
3968 * Do not insert any td of the urb to the ring if the check failed.
3970 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3971 num_trbs, mem_flags);
3976 * Check interval value. This should be done before we start to
3977 * calculate the start frame value.
3979 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3980 ep_interval = urb->interval;
3981 /* Convert to microframes */
3982 if (urb->dev->speed == USB_SPEED_LOW ||
3983 urb->dev->speed == USB_SPEED_FULL)
3985 /* FIXME change this to a warning and a suggestion to use the new API
3986 * to set the polling interval (once the API is added).
3988 if (xhci_interval != ep_interval) {
3989 dev_dbg_ratelimited(&urb->dev->dev,
3990 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3991 ep_interval, ep_interval == 1 ? "" : "s",
3992 xhci_interval, xhci_interval == 1 ? "" : "s");
3993 urb->interval = xhci_interval;
3994 /* Convert back to frames for LS/FS devices */
3995 if (urb->dev->speed == USB_SPEED_LOW ||
3996 urb->dev->speed == USB_SPEED_FULL)
4000 /* Calculate the start frame and put it in urb->start_frame. */
4001 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4002 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
4004 urb->start_frame = xep->next_frame_id;
4005 goto skip_start_over;
4009 start_frame = readl(&xhci->run_regs->microframe_index);
4010 start_frame &= 0x3fff;
4012 * Round up to the next frame and consider the time before trb really
4013 * gets scheduled by hardare.
4015 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4016 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4018 start_frame += ist + XHCI_CFC_DELAY;
4019 start_frame = roundup(start_frame, 8);
4022 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4023 * is greate than 8 microframes.
4025 if (urb->dev->speed == USB_SPEED_LOW ||
4026 urb->dev->speed == USB_SPEED_FULL) {
4027 start_frame = roundup(start_frame, urb->interval << 3);
4028 urb->start_frame = start_frame >> 3;
4030 start_frame = roundup(start_frame, urb->interval);
4031 urb->start_frame = start_frame;
4035 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4037 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4040 /**** Command Ring Operations ****/
4042 /* Generic function for queueing a command TRB on the command ring.
4043 * Check to make sure there's room on the command ring for one command TRB.
4044 * Also check that there's room reserved for commands that must not fail.
4045 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4046 * then only check for the number of reserved spots.
4047 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4048 * because the command event handler may want to resubmit a failed command.
4050 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4051 u32 field1, u32 field2,
4052 u32 field3, u32 field4, bool command_must_succeed)
4054 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4057 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4058 (xhci->xhc_state & XHCI_STATE_HALTED) ||
4059 (xhci->xhc_state & XHCI_STATE_REMOVING)) {
4060 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4064 if (!command_must_succeed)
4067 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4068 reserved_trbs, GFP_ATOMIC);
4070 xhci_err(xhci, "ERR: No room for command on command ring\n");
4071 if (command_must_succeed)
4072 xhci_err(xhci, "ERR: Reserved TRB counting for "
4073 "unfailable commands failed.\n");
4077 cmd->command_trb = xhci->cmd_ring->enqueue;
4078 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4080 /* if there are no other commands queued we start the timeout timer */
4081 if (xhci->cmd_list.next == &cmd->cmd_list &&
4082 !delayed_work_pending(&xhci->cmd_timer)) {
4083 xhci->current_cmd = cmd;
4084 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4087 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4088 field4 | xhci->cmd_ring->cycle_state);
4092 /* Queue a slot enable or disable request on the command ring */
4093 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4094 u32 trb_type, u32 slot_id)
4096 return queue_command(xhci, cmd, 0, 0, 0,
4097 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4100 /* Queue an address device command TRB */
4101 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4102 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4104 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4105 upper_32_bits(in_ctx_ptr), 0,
4106 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4107 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4110 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4111 u32 field1, u32 field2, u32 field3, u32 field4)
4113 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4116 /* Queue a reset device command TRB */
4117 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4120 return queue_command(xhci, cmd, 0, 0, 0,
4121 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4125 /* Queue a configure endpoint command TRB */
4126 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4127 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4128 u32 slot_id, bool command_must_succeed)
4130 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4131 upper_32_bits(in_ctx_ptr), 0,
4132 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4133 command_must_succeed);
4136 /* Queue an evaluate context command TRB */
4137 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4138 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4140 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4141 upper_32_bits(in_ctx_ptr), 0,
4142 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4143 command_must_succeed);
4147 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4148 * activity on an endpoint that is about to be suspended.
4150 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4151 int slot_id, unsigned int ep_index, int suspend)
4153 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4154 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4155 u32 type = TRB_TYPE(TRB_STOP_RING);
4156 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4158 return queue_command(xhci, cmd, 0, 0, 0,
4159 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4162 /* Set Transfer Ring Dequeue Pointer command */
4163 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4164 unsigned int slot_id, unsigned int ep_index,
4165 unsigned int stream_id,
4166 struct xhci_dequeue_state *deq_state)
4169 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4170 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4171 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4173 u32 type = TRB_TYPE(TRB_SET_DEQ);
4174 struct xhci_virt_ep *ep;
4175 struct xhci_command *cmd;
4178 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4179 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4180 deq_state->new_deq_seg,
4181 (unsigned long long)deq_state->new_deq_seg->dma,
4182 deq_state->new_deq_ptr,
4183 (unsigned long long)xhci_trb_virt_to_dma(
4184 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4185 deq_state->new_cycle_state);
4187 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4188 deq_state->new_deq_ptr);
4190 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4191 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4192 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4195 ep = &xhci->devs[slot_id]->eps[ep_index];
4196 if ((ep->ep_state & SET_DEQ_PENDING)) {
4197 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4198 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4202 /* This function gets called from contexts where it cannot sleep */
4203 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4205 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4209 ep->queued_deq_seg = deq_state->new_deq_seg;
4210 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4212 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4213 ret = queue_command(xhci, cmd,
4214 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4215 upper_32_bits(addr), trb_stream_id,
4216 trb_slot_id | trb_ep_index | type, false);
4218 xhci_free_command(xhci, cmd);
4222 /* Stop the TD queueing code from ringing the doorbell until
4223 * this command completes. The HC won't set the dequeue pointer
4224 * if the ring is running, and ringing the doorbell starts the
4227 ep->ep_state |= SET_DEQ_PENDING;
4230 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4231 int slot_id, unsigned int ep_index)
4233 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4234 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4235 u32 type = TRB_TYPE(TRB_RESET_EP);
4237 return queue_command(xhci, cmd, 0, 0, 0,
4238 trb_slot_id | trb_ep_index | type, false);