drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.  This was
 176  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 177  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 178  */
 179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 180 {
 181         u32 chain;
 182         union xhci_trb *next;
 183         unsigned long long addr;
 184
 185         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 186         next = ++(ring->enqueue);
 187
 188         ring->enq_updates++;
 189         /* Update the dequeue pointer further if that was a link TRB or we're at
 190          * the end of an event ring segment (which doesn't have link TRBS)
 191          */
 192         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 193                 if (!consumer) {
 194                         if (ring != xhci->event_ring) {
 195                                 /* If we're not dealing with 0.95 hardware,
 196                                  * carry over the chain bit of the previous TRB
 197                                  * (which may mean the chain bit is cleared).
 198                                  */
 199                                 if (!xhci_link_trb_quirk(xhci)) {
 200                                         next->link.control &= ~TRB_CHAIN;
 201                                         next->link.control |= chain;
 202                                 }
 203                                 /* Give this link TRB to the hardware */
 204                                 wmb();
 205                                 if (next->link.control & TRB_CYCLE)
 206                                         next->link.control &= (u32) ~TRB_CYCLE;
 207                                 else
 208                                         next->link.control |= (u32) TRB_CYCLE;
 209                         }
 210                         /* Toggle the cycle bit after the last ring segment. */
 211                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 212                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 213                                 if (!in_interrupt())
 214                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 215                                                         ring,
 216                                                         (unsigned int) ring->cycle_state);
 217                         }
 218                 }
 219                 ring->enq_seg = ring->enq_seg->next;
 220                 ring->enqueue = ring->enq_seg->trbs;
 221                 next = ring->enqueue;
 222         }
 223         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 224         if (ring == xhci->event_ring)
 225                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 226         else if (ring == xhci->cmd_ring)
 227                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 228         else
 229                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 230 }
 231
 232 /*
 233  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 234  * above.
 235  * FIXME: this would be simpler and faster if we just kept track of the number
 236  * of free TRBs in a ring.
 237  */
 238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 239                 unsigned int num_trbs)
 240 {
 241         int i;
 242         union xhci_trb *enq = ring->enqueue;
 243         struct xhci_segment *enq_seg = ring->enq_seg;
 244         struct xhci_segment *cur_seg;
 245         unsigned int left_on_ring;
 246
 247         /* Check if ring is empty */
 248         if (enq == ring->dequeue) {
 249                 /* Can't use link trbs */
 250                 left_on_ring = TRBS_PER_SEGMENT - 1;
 251                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 252                                 cur_seg = cur_seg->next)
 253                         left_on_ring += TRBS_PER_SEGMENT - 1;
 254
 255                 /* Always need one TRB free in the ring. */
 256                 left_on_ring -= 1;
 257                 if (num_trbs > left_on_ring) {
 258                         xhci_warn(xhci, "Not enough room on ring; "
 259                                         "need %u TRBs, %u TRBs left\n",
 260                                         num_trbs, left_on_ring);
 261                         return 0;
 262                 }
 263                 return 1;
 264         }
 265         /* Make sure there's an extra empty TRB available */
 266         for (i = 0; i <= num_trbs; ++i) {
 267                 if (enq == ring->dequeue)
 268                         return 0;
 269                 enq++;
 270                 while (last_trb(xhci, ring, enq_seg, enq)) {
 271                         enq_seg = enq_seg->next;
 272                         enq = enq_seg->trbs;
 273                 }
 274         }
 275         return 1;
 276 }
 277
 278 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 279 {
 280         u64 temp;
 281         dma_addr_t deq;
 282
 283         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 284                         xhci->event_ring->dequeue);
 285         if (deq == 0 && !in_interrupt())
 286                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 287                                 "dequeue ptr.\n");
 288         /* Update HC event ring dequeue pointer */
 289         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 290         temp &= ERST_PTR_MASK;
 291         /* Don't clear the EHB bit (which is RW1C) because
 292          * there might be more events to service.
 293          */
 294         temp &= ~ERST_EHB;
 295         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 296         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 297                         &xhci->ir_set->erst_dequeue);
 298 }
 299
 300 /* Ring the host controller doorbell after placing a command on the ring */
 301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 302 {
 303         u32 temp;
 304
 305         xhci_dbg(xhci, "// Ding dong!\n");
 306         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 307         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 308         /* Flush PCI posted writes */
 309         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 310 }
 311
 312 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 313                 unsigned int slot_id,
 314                 unsigned int ep_index)
 315 {
 316         struct xhci_virt_ep *ep;
 317         unsigned int ep_state;
 318         u32 field;
 319         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 320
 321         ep = &xhci->devs[slot_id]->eps[ep_index];
 322         ep_state = ep->ep_state;
 323         /* Don't ring the doorbell for this endpoint if there are pending
 324          * cancellations because the we don't want to interrupt processing.
 325          */
 326         if (!ep->cancels_pending && !(ep_state & SET_DEQ_PENDING)
 327                         && !(ep_state & EP_HALTED)) {
 328                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 329                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 330                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 331                  * isn't time-critical and we shouldn't make the CPU wait for
 332                  * the flush.
 333                  */
 334                 xhci_readl(xhci, db_addr);
 335         }
 336 }
 337
 338 /*
 339  * Find the segment that trb is in.  Start searching in start_seg.
 340  * If we must move past a segment that has a link TRB with a toggle cycle state
 341  * bit set, then we will toggle the value pointed at by cycle_state.
 342  */
 343 static struct xhci_segment *find_trb_seg(
 344                 struct xhci_segment *start_seg,
 345                 union xhci_trb  *trb, int *cycle_state)
 346 {
 347         struct xhci_segment *cur_seg = start_seg;
 348         struct xhci_generic_trb *generic_trb;
 349
 350         while (cur_seg->trbs > trb ||
 351                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 352                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 353                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 354                                 TRB_TYPE(TRB_LINK) &&
 355                                 (generic_trb->field[3] & LINK_TOGGLE))
 356                         *cycle_state = ~(*cycle_state) & 0x1;
 357                 cur_seg = cur_seg->next;
 358                 if (cur_seg == start_seg)
 359                         /* Looped over the entire list.  Oops! */
 360                         return 0;
 361         }
 362         return cur_seg;
 363 }
 364
 365 /*
 366  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 367  * Record the new state of the xHC's endpoint ring dequeue segment,
 368  * dequeue pointer, and new consumer cycle state in state.
 369  * Update our internal representation of the ring's dequeue pointer.
 370  *
 371  * We do this in three jumps:
 372  *  - First we update our new ring state to be the same as when the xHC stopped.
 373  *  - Then we traverse the ring to find the segment that contains
 374  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 375  *    any link TRBs with the toggle cycle bit set.
 376  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 377  *    if we've moved it past a link TRB with the toggle cycle bit set.
 378  */
 379 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 380                 unsigned int slot_id, unsigned int ep_index,
 381                 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
 382 {
 383         struct xhci_virt_device *dev = xhci->devs[slot_id];
 384         struct xhci_ring *ep_ring = dev->eps[ep_index].ring;
 385         struct xhci_generic_trb *trb;
 386         struct xhci_ep_ctx *ep_ctx;
 387         dma_addr_t addr;
 388
 389         state->new_cycle_state = 0;
 390         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 391         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 392                         dev->eps[ep_index].stopped_trb,
 393                         &state->new_cycle_state);
 394         if (!state->new_deq_seg) {
 395                 WARN_ON(1);
 396                 return;
 397         }
 398
 399         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 400         xhci_dbg(xhci, "Finding endpoint context\n");
 401         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 402         state->new_cycle_state = 0x1 & ep_ctx->deq;
 403
 404         state->new_deq_ptr = cur_td->last_trb;
 405         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 406         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 407                         state->new_deq_ptr,
 408                         &state->new_cycle_state);
 409         if (!state->new_deq_seg) {
 410                 WARN_ON(1);
 411                 return;
 412         }
 413
 414         trb = &state->new_deq_ptr->generic;
 415         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 416                                 (trb->field[3] & LINK_TOGGLE))
 417                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 418         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 419
 420         /*
 421          * If there is only one segment in a ring, find_trb_seg()'s while loop
 422          * will not run, and it will return before it has a chance to see if it
 423          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 424          * ended just before the link TRB on a one-segment ring, or if the TD
 425          * wrapped around the top of the ring, because it doesn't have the TD in
 426          * question.  Look for the one-segment case where stalled TRB's address
 427          * is greater than the new dequeue pointer address.
 428          */
 429         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 430                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 431                 state->new_cycle_state ^= 0x1;
 432         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 433
 434         /* Don't update the ring cycle state for the producer (us). */
 435         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 436                         state->new_deq_seg);
 437         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 438         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 439                         (unsigned long long) addr);
 440         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 441         ep_ring->dequeue = state->new_deq_ptr;
 442         ep_ring->deq_seg = state->new_deq_seg;
 443 }
 444
 445 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 446                 struct xhci_td *cur_td)
 447 {
 448         struct xhci_segment *cur_seg;
 449         union xhci_trb *cur_trb;
 450
 451         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 452                         true;
 453                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 454                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 455                                 TRB_TYPE(TRB_LINK)) {
 456                         /* Unchain any chained Link TRBs, but
 457                          * leave the pointers intact.
 458                          */
 459                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 460                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 461                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 462                                         "in seg %p (0x%llx dma)\n",
 463                                         cur_trb,
 464                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 465                                         cur_seg,
 466                                         (unsigned long long)cur_seg->dma);
 467                 } else {
 468                         cur_trb->generic.field[0] = 0;
 469                         cur_trb->generic.field[1] = 0;
 470                         cur_trb->generic.field[2] = 0;
 471                         /* Preserve only the cycle bit of this TRB */
 472                         cur_trb->generic.field[3] &= TRB_CYCLE;
 473                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 474                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 475                                         "in seg %p (0x%llx dma)\n",
 476                                         cur_trb,
 477                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 478                                         cur_seg,
 479                                         (unsigned long long)cur_seg->dma);
 480                 }
 481                 if (cur_trb == cur_td->last_trb)
 482                         break;
 483         }
 484 }
 485
 486 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 487                 unsigned int ep_index, struct xhci_segment *deq_seg,
 488                 union xhci_trb *deq_ptr, u32 cycle_state);
 489
 490 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 491                 unsigned int slot_id, unsigned int ep_index,
 492                 struct xhci_dequeue_state *deq_state)
 493 {
 494         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 495
 496         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 497                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 498                         deq_state->new_deq_seg,
 499                         (unsigned long long)deq_state->new_deq_seg->dma,
 500                         deq_state->new_deq_ptr,
 501                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 502                         deq_state->new_cycle_state);
 503         queue_set_tr_deq(xhci, slot_id, ep_index,
 504                         deq_state->new_deq_seg,
 505                         deq_state->new_deq_ptr,
 506                         (u32) deq_state->new_cycle_state);
 507         /* Stop the TD queueing code from ringing the doorbell until
 508          * this command completes.  The HC won't set the dequeue pointer
 509          * if the ring is running, and ringing the doorbell starts the
 510          * ring running.
 511          */
 512         ep->ep_state |= SET_DEQ_PENDING;
 513 }
 514
 515 /*
 516  * When we get a command completion for a Stop Endpoint Command, we need to
 517  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 518  *
 519  *  1. If the HW was in the middle of processing the TD that needs to be
 520  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 521  *     in the TD with a Set Dequeue Pointer Command.
 522  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 523  *     bit cleared) so that the HW will skip over them.
 524  */
 525 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 526                 union xhci_trb *trb)
 527 {
 528         unsigned int slot_id;
 529         unsigned int ep_index;
 530         struct xhci_ring *ep_ring;
 531         struct xhci_virt_ep *ep;
 532         struct list_head *entry;
 533         struct xhci_td *cur_td = 0;
 534         struct xhci_td *last_unlinked_td;
 535
 536         struct xhci_dequeue_state deq_state;
 537 #ifdef CONFIG_USB_HCD_STAT
 538         ktime_t stop_time = ktime_get();
 539 #endif
 540
 541         memset(&deq_state, 0, sizeof(deq_state));
 542         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 543         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 544         ep = &xhci->devs[slot_id]->eps[ep_index];
 545         ep_ring = ep->ring;
 546
 547         if (list_empty(&ep->cancelled_td_list))
 548                 return;
 549
 550         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 551          * We have the xHCI lock, so nothing can modify this list until we drop
 552          * it.  We're also in the event handler, so we can't get re-interrupted
 553          * if another Stop Endpoint command completes
 554          */
 555         list_for_each(entry, &ep->cancelled_td_list) {
 556                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 557                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 558                                 cur_td->first_trb,
 559                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 560                 /*
 561                  * If we stopped on the TD we need to cancel, then we have to
 562                  * move the xHC endpoint ring dequeue pointer past this TD.
 563                  */
 564                 if (cur_td == ep->stopped_td)
 565                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 566                                         &deq_state);
 567                 else
 568                         td_to_noop(xhci, ep_ring, cur_td);
 569                 /*
 570                  * The event handler won't see a completion for this TD anymore,
 571                  * so remove it from the endpoint ring's TD list.  Keep it in
 572                  * the cancelled TD list for URB completion later.
 573                  */
 574                 list_del(&cur_td->td_list);
 575                 ep->cancels_pending--;
 576         }
 577         last_unlinked_td = cur_td;
 578
 579         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 580         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 581                 xhci_queue_new_dequeue_state(xhci,
 582                                 slot_id, ep_index, &deq_state);
 583                 xhci_ring_cmd_db(xhci);
 584         } else {
 585                 /* Otherwise just ring the doorbell to restart the ring */
 586                 ring_ep_doorbell(xhci, slot_id, ep_index);
 587         }
 588         ep->stopped_td = NULL;
 589         ep->stopped_trb = NULL;
 590
 591         /*
 592          * Drop the lock and complete the URBs in the cancelled TD list.
 593          * New TDs to be cancelled might be added to the end of the list before
 594          * we can complete all the URBs for the TDs we already unlinked.
 595          * So stop when we've completed the URB for the last TD we unlinked.
 596          */
 597         do {
 598                 cur_td = list_entry(ep->cancelled_td_list.next,
 599                                 struct xhci_td, cancelled_td_list);
 600                 list_del(&cur_td->cancelled_td_list);
 601
 602                 /* Clean up the cancelled URB */
 603 #ifdef CONFIG_USB_HCD_STAT
 604                 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
 605                                 ktime_sub(stop_time, cur_td->start_time));
 606 #endif
 607                 cur_td->urb->hcpriv = NULL;
 608                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
 609
 610                 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
 611                 spin_unlock(&xhci->lock);
 612                 /* Doesn't matter what we pass for status, since the core will
 613                  * just overwrite it (because the URB has been unlinked).
 614                  */
 615                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
 616                 kfree(cur_td);
 617
 618                 spin_lock(&xhci->lock);
 619         } while (cur_td != last_unlinked_td);
 620
 621         /* Return to the event handler with xhci->lock re-acquired */
 622 }
 623
 624 /*
 625  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 626  * we need to clear the set deq pending flag in the endpoint ring state, so that
 627  * the TD queueing code can ring the doorbell again.  We also need to ring the
 628  * endpoint doorbell to restart the ring, but only if there aren't more
 629  * cancellations pending.
 630  */
 631 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 632                 struct xhci_event_cmd *event,
 633                 union xhci_trb *trb)
 634 {
 635         unsigned int slot_id;
 636         unsigned int ep_index;
 637         struct xhci_ring *ep_ring;
 638         struct xhci_virt_device *dev;
 639         struct xhci_ep_ctx *ep_ctx;
 640         struct xhci_slot_ctx *slot_ctx;
 641
 642         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 643         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 644         dev = xhci->devs[slot_id];
 645         ep_ring = dev->eps[ep_index].ring;
 646         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 647         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 648
 649         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 650                 unsigned int ep_state;
 651                 unsigned int slot_state;
 652
 653                 switch (GET_COMP_CODE(event->status)) {
 654                 case COMP_TRB_ERR:
 655                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 656                                         "of stream ID configuration\n");
 657                         break;
 658                 case COMP_CTX_STATE:
 659                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 660                                         "to incorrect slot or ep state.\n");
 661                         ep_state = ep_ctx->ep_info;
 662                         ep_state &= EP_STATE_MASK;
 663                         slot_state = slot_ctx->dev_state;
 664                         slot_state = GET_SLOT_STATE(slot_state);
 665                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 666                                         slot_state, ep_state);
 667                         break;
 668                 case COMP_EBADSLT:
 669                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 670                                         "slot %u was not enabled.\n", slot_id);
 671                         break;
 672                 default:
 673                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 674                                         "completion code of %u.\n",
 675                                         GET_COMP_CODE(event->status));
 676                         break;
 677                 }
 678                 /* OK what do we do now?  The endpoint state is hosed, and we
 679                  * should never get to this point if the synchronization between
 680                  * queueing, and endpoint state are correct.  This might happen
 681                  * if the device gets disconnected after we've finished
 682                  * cancelling URBs, which might not be an error...
 683                  */
 684         } else {
 685                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 686                                 ep_ctx->deq);
 687         }
 688
 689         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 690         ring_ep_doorbell(xhci, slot_id, ep_index);
 691 }
 692
 693 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 694                 struct xhci_event_cmd *event,
 695                 union xhci_trb *trb)
 696 {
 697         int slot_id;
 698         unsigned int ep_index;
 699         struct xhci_ring *ep_ring;
 700
 701         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 702         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 703         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 704         /* This command will only fail if the endpoint wasn't halted,
 705          * but we don't care.
 706          */
 707         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 708                         (unsigned int) GET_COMP_CODE(event->status));
 709
 710         /* HW with the reset endpoint quirk needs to have a configure endpoint
 711          * command complete before the endpoint can be used.  Queue that here
 712          * because the HW can't handle two commands being queued in a row.
 713          */
 714         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 715                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 716                 xhci_queue_configure_endpoint(xhci,
 717                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 718                                 false);
 719                 xhci_ring_cmd_db(xhci);
 720         } else {
 721                 /* Clear our internal halted state and restart the ring */
 722                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 723                 ring_ep_doorbell(xhci, slot_id, ep_index);
 724         }
 725 }
 726
 727 /* Check to see if a command in the device's command queue matches this one.
 728  * Signal the completion or free the command, and return 1.  Return 0 if the
 729  * completed command isn't at the head of the command list.
 730  */
 731 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
 732                 struct xhci_virt_device *virt_dev,
 733                 struct xhci_event_cmd *event)
 734 {
 735         struct xhci_command *command;
 736
 737         if (list_empty(&virt_dev->cmd_list))
 738                 return 0;
 739
 740         command = list_entry(virt_dev->cmd_list.next,
 741                         struct xhci_command, cmd_list);
 742         if (xhci->cmd_ring->dequeue != command->command_trb)
 743                 return 0;
 744
 745         command->status =
 746                 GET_COMP_CODE(event->status);
 747         list_del(&command->cmd_list);
 748         if (command->completion)
 749                 complete(command->completion);
 750         else
 751                 xhci_free_command(xhci, command);
 752         return 1;
 753 }
 754
 755 static void handle_cmd_completion(struct xhci_hcd *xhci,
 756                 struct xhci_event_cmd *event)
 757 {
 758         int slot_id = TRB_TO_SLOT_ID(event->flags);
 759         u64 cmd_dma;
 760         dma_addr_t cmd_dequeue_dma;
 761         struct xhci_input_control_ctx *ctrl_ctx;
 762         struct xhci_virt_device *virt_dev;
 763         unsigned int ep_index;
 764         struct xhci_ring *ep_ring;
 765         unsigned int ep_state;
 766
 767         cmd_dma = event->cmd_trb;
 768         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 769                         xhci->cmd_ring->dequeue);
 770         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 771         if (cmd_dequeue_dma == 0) {
 772                 xhci->error_bitmask |= 1 << 4;
 773                 return;
 774         }
 775         /* Does the DMA address match our internal dequeue pointer address? */
 776         if (cmd_dma != (u64) cmd_dequeue_dma) {
 777                 xhci->error_bitmask |= 1 << 5;
 778                 return;
 779         }
 780         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 781         case TRB_TYPE(TRB_ENABLE_SLOT):
 782                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 783                         xhci->slot_id = slot_id;
 784                 else
 785                         xhci->slot_id = 0;
 786                 complete(&xhci->addr_dev);
 787                 break;
 788         case TRB_TYPE(TRB_DISABLE_SLOT):
 789                 if (xhci->devs[slot_id])
 790                         xhci_free_virt_device(xhci, slot_id);
 791                 break;
 792         case TRB_TYPE(TRB_CONFIG_EP):
 793                 virt_dev = xhci->devs[slot_id];
 794                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 795                         break;
 796                 /*
 797                  * Configure endpoint commands can come from the USB core
 798                  * configuration or alt setting changes, or because the HW
 799                  * needed an extra configure endpoint command after a reset
 800                  * endpoint command.  In the latter case, the xHCI driver is
 801                  * not waiting on the configure endpoint command.
 802                  */
 803                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
 804                                 virt_dev->in_ctx);
 805                 /* Input ctx add_flags are the endpoint index plus one */
 806                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
 807                 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
 808                 if (!ep_ring) {
 809                         /* This must have been an initial configure endpoint */
 810                         xhci->devs[slot_id]->cmd_status =
 811                                 GET_COMP_CODE(event->status);
 812                         complete(&xhci->devs[slot_id]->cmd_completion);
 813                         break;
 814                 }
 815                 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
 816                 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
 817                                 "state = %d\n", ep_index, ep_state);
 818                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
 819                                 ep_state & EP_HALTED) {
 820                         /* Clear our internal halted state and restart ring */
 821                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
 822                                 ~EP_HALTED;
 823                         ring_ep_doorbell(xhci, slot_id, ep_index);
 824                 } else {
 825                         xhci->devs[slot_id]->cmd_status =
 826                                 GET_COMP_CODE(event->status);
 827                         complete(&xhci->devs[slot_id]->cmd_completion);
 828                 }
 829                 break;
 830         case TRB_TYPE(TRB_EVAL_CONTEXT):
 831                 virt_dev = xhci->devs[slot_id];
 832                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
 833                         break;
 834                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 835                 complete(&xhci->devs[slot_id]->cmd_completion);
 836                 break;
 837         case TRB_TYPE(TRB_ADDR_DEV):
 838                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 839                 complete(&xhci->addr_dev);
 840                 break;
 841         case TRB_TYPE(TRB_STOP_RING):
 842                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 843                 break;
 844         case TRB_TYPE(TRB_SET_DEQ):
 845                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 846                 break;
 847         case TRB_TYPE(TRB_CMD_NOOP):
 848                 ++xhci->noops_handled;
 849                 break;
 850         case TRB_TYPE(TRB_RESET_EP):
 851                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 852                 break;
 853         default:
 854                 /* Skip over unknown commands on the event ring */
 855                 xhci->error_bitmask |= 1 << 6;
 856                 break;
 857         }
 858         inc_deq(xhci, xhci->cmd_ring, false);
 859 }
 860
 861 static void handle_port_status(struct xhci_hcd *xhci,
 862                 union xhci_trb *event)
 863 {
 864         u32 port_id;
 865
 866         /* Port status change events always have a successful completion code */
 867         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 868                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 869                 xhci->error_bitmask |= 1 << 8;
 870         }
 871         /* FIXME: core doesn't care about all port link state changes yet */
 872         port_id = GET_PORT_ID(event->generic.field[0]);
 873         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 874
 875         /* Update event ring dequeue pointer before dropping the lock */
 876         inc_deq(xhci, xhci->event_ring, true);
 877         xhci_set_hc_event_deq(xhci);
 878
 879         spin_unlock(&xhci->lock);
 880         /* Pass this up to the core */
 881         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 882         spin_lock(&xhci->lock);
 883 }
 884
 885 /*
 886  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 887  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 888  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 889  * returns 0.
 890  */
 891 static struct xhci_segment *trb_in_td(
 892                 struct xhci_segment *start_seg,
 893                 union xhci_trb  *start_trb,
 894                 union xhci_trb  *end_trb,
 895                 dma_addr_t      suspect_dma)
 896 {
 897         dma_addr_t start_dma;
 898         dma_addr_t end_seg_dma;
 899         dma_addr_t end_trb_dma;
 900         struct xhci_segment *cur_seg;
 901
 902         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
 903         cur_seg = start_seg;
 904
 905         do {
 906                 if (start_dma == 0)
 907                         return 0;
 908                 /* We may get an event for a Link TRB in the middle of a TD */
 909                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
 910                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
 911                 /* If the end TRB isn't in this segment, this is set to 0 */
 912                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 913
 914                 if (end_trb_dma > 0) {
 915                         /* The end TRB is in this segment, so suspect should be here */
 916                         if (start_dma <= end_trb_dma) {
 917                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
 918                                         return cur_seg;
 919                         } else {
 920                                 /* Case for one segment with
 921                                  * a TD wrapped around to the top
 922                                  */
 923                                 if ((suspect_dma >= start_dma &&
 924                                                         suspect_dma <= end_seg_dma) ||
 925                                                 (suspect_dma >= cur_seg->dma &&
 926                                                  suspect_dma <= end_trb_dma))
 927                                         return cur_seg;
 928                         }
 929                         return 0;
 930                 } else {
 931                         /* Might still be somewhere in this segment */
 932                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
 933                                 return cur_seg;
 934                 }
 935                 cur_seg = cur_seg->next;
 936                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
 937         } while (cur_seg != start_seg);
 938
 939         return 0;
 940 }
 941
 942 /*
 943  * If this function returns an error condition, it means it got a Transfer
 944  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
 945  * At this point, the host controller is probably hosed and should be reset.
 946  */
 947 static int handle_tx_event(struct xhci_hcd *xhci,
 948                 struct xhci_transfer_event *event)
 949 {
 950         struct xhci_virt_device *xdev;
 951         struct xhci_virt_ep *ep;
 952         struct xhci_ring *ep_ring;
 953         unsigned int slot_id;
 954         int ep_index;
 955         struct xhci_td *td = 0;
 956         dma_addr_t event_dma;
 957         struct xhci_segment *event_seg;
 958         union xhci_trb *event_trb;
 959         struct urb *urb = 0;
 960         int status = -EINPROGRESS;
 961         struct xhci_ep_ctx *ep_ctx;
 962         u32 trb_comp_code;
 963
 964         xhci_dbg(xhci, "In %s\n", __func__);
 965         slot_id = TRB_TO_SLOT_ID(event->flags);
 966         xdev = xhci->devs[slot_id];
 967         if (!xdev) {
 968                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 969                 return -ENODEV;
 970         }
 971
 972         /* Endpoint ID is 1 based, our index is zero based */
 973         ep_index = TRB_TO_EP_ID(event->flags) - 1;
 974         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
 975         ep = &xdev->eps[ep_index];
 976         ep_ring = ep->ring;
 977         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
 978         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
 979                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
 980                 return -ENODEV;
 981         }
 982
 983         event_dma = event->buffer;
 984         /* This TRB should be in the TD at the head of this ring's TD list */
 985         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
 986         if (list_empty(&ep_ring->td_list)) {
 987                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
 988                                 TRB_TO_SLOT_ID(event->flags), ep_index);
 989                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 990                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 991                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
 992                 urb = NULL;
 993                 goto cleanup;
 994         }
 995         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
 996         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
 997
 998         /* Is this a TRB in the currently executing TD? */
 999         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
1000         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1001                         td->last_trb, event_dma);
1002         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
1003         if (!event_seg) {
1004                 /* HC is busted, give up! */
1005                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1006                 return -ESHUTDOWN;
1007         }
1008         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
1009         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1010                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1011         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
1012                         lower_32_bits(event->buffer));
1013         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
1014                         upper_32_bits(event->buffer));
1015         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
1016                         (unsigned int) event->transfer_len);
1017         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
1018                         (unsigned int) event->flags);
1019
1020         /* Look for common error cases */
1021         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1022         switch (trb_comp_code) {
1023         /* Skip codes that require special handling depending on
1024          * transfer type
1025          */
1026         case COMP_SUCCESS:
1027         case COMP_SHORT_TX:
1028                 break;
1029         case COMP_STOP:
1030                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1031                 break;
1032         case COMP_STOP_INVAL:
1033                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1034                 break;
1035         case COMP_STALL:
1036                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1037                 ep->ep_state |= EP_HALTED;
1038                 status = -EPIPE;
1039                 break;
1040         case COMP_TRB_ERR:
1041                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1042                 status = -EILSEQ;
1043                 break;
1044         case COMP_TX_ERR:
1045                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1046                 status = -EPROTO;
1047                 break;
1048         case COMP_BABBLE:
1049                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1050                 status = -EOVERFLOW;
1051                 break;
1052         case COMP_DB_ERR:
1053                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1054                 status = -ENOSR;
1055                 break;
1056         default:
1057                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
1058                 urb = NULL;
1059                 goto cleanup;
1060         }
1061         /* Now update the urb's actual_length and give back to the core */
1062         /* Was this a control transfer? */
1063         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
1064                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1065                 switch (trb_comp_code) {
1066                 case COMP_SUCCESS:
1067                         if (event_trb == ep_ring->dequeue) {
1068                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
1069                                 status = -ESHUTDOWN;
1070                         } else if (event_trb != td->last_trb) {
1071                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
1072                                 status = -ESHUTDOWN;
1073                         } else {
1074                                 xhci_dbg(xhci, "Successful control transfer!\n");
1075                                 status = 0;
1076                         }
1077                         break;
1078                 case COMP_SHORT_TX:
1079                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
1080                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1081                                 status = -EREMOTEIO;
1082                         else
1083                                 status = 0;
1084                         break;
1085                 case COMP_BABBLE:
1086                         /* The 0.96 spec says a babbling control endpoint
1087                          * is not halted. The 0.96 spec says it is.  Some HW
1088                          * claims to be 0.95 compliant, but it halts the control
1089                          * endpoint anyway.  Check if a babble halted the
1090                          * endpoint.
1091                          */
1092                         if (ep_ctx->ep_info != EP_STATE_HALTED)
1093                                 break;
1094                         /* else fall through */
1095                 case COMP_STALL:
1096                         /* Did we transfer part of the data (middle) phase? */
1097                         if (event_trb != ep_ring->dequeue &&
1098                                         event_trb != td->last_trb)
1099                                 td->urb->actual_length =
1100                                         td->urb->transfer_buffer_length
1101                                         - TRB_LEN(event->transfer_len);
1102                         else
1103                                 td->urb->actual_length = 0;
1104
1105                         ep->stopped_td = td;
1106                         ep->stopped_trb = event_trb;
1107
1108                         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1109                         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1110
1111                         ep->stopped_td = NULL;
1112                         ep->stopped_trb = NULL;
1113
1114                         xhci_ring_cmd_db(xhci);
1115                         goto td_cleanup;
1116                 default:
1117                         /* Others already handled above */
1118                         break;
1119                 }
1120                 /*
1121                  * Did we transfer any data, despite the errors that might have
1122                  * happened?  I.e. did we get past the setup stage?
1123                  */
1124                 if (event_trb != ep_ring->dequeue) {
1125                         /* The event was for the status stage */
1126                         if (event_trb == td->last_trb) {
1127                                 if (td->urb->actual_length != 0) {
1128                                         /* Don't overwrite a previously set error code */
1129                                         if ((status == -EINPROGRESS ||
1130                                                                 status == 0) &&
1131                                                         (td->urb->transfer_flags
1132                                                          & URB_SHORT_NOT_OK))
1133                                                 /* Did we already see a short data stage? */
1134                                                 status = -EREMOTEIO;
1135                                 } else {
1136                                         td->urb->actual_length =
1137                                                 td->urb->transfer_buffer_length;
1138                                 }
1139                         } else {
1140                         /* Maybe the event was for the data stage? */
1141                                 if (trb_comp_code != COMP_STOP_INVAL) {
1142                                         /* We didn't stop on a link TRB in the middle */
1143                                         td->urb->actual_length =
1144                                                 td->urb->transfer_buffer_length -
1145                                                 TRB_LEN(event->transfer_len);
1146                                         xhci_dbg(xhci, "Waiting for status stage event\n");
1147                                         urb = NULL;
1148                                         goto cleanup;
1149                                 }
1150                         }
1151                 }
1152         } else {
1153                 switch (trb_comp_code) {
1154                 case COMP_SUCCESS:
1155                         /* Double check that the HW transferred everything. */
1156                         if (event_trb != td->last_trb) {
1157                                 xhci_warn(xhci, "WARN Successful completion "
1158                                                 "on short TX\n");
1159                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1160                                         status = -EREMOTEIO;
1161                                 else
1162                                         status = 0;
1163                         } else {
1164                                 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1165                                         xhci_dbg(xhci, "Successful bulk "
1166                                                         "transfer!\n");
1167                                 else
1168                                         xhci_dbg(xhci, "Successful interrupt "
1169                                                         "transfer!\n");
1170                                 status = 0;
1171                         }
1172                         break;
1173                 case COMP_SHORT_TX:
1174                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1175                                 status = -EREMOTEIO;
1176                         else
1177                                 status = 0;
1178                         break;
1179                 default:
1180                         /* Others already handled above */
1181                         break;
1182                 }
1183                 dev_dbg(&td->urb->dev->dev,
1184                                 "ep %#x - asked for %d bytes, "
1185                                 "%d bytes untransferred\n",
1186                                 td->urb->ep->desc.bEndpointAddress,
1187                                 td->urb->transfer_buffer_length,
1188                                 TRB_LEN(event->transfer_len));
1189                 /* Fast path - was this the last TRB in the TD for this URB? */
1190                 if (event_trb == td->last_trb) {
1191                         if (TRB_LEN(event->transfer_len) != 0) {
1192                                 td->urb->actual_length =
1193                                         td->urb->transfer_buffer_length -
1194                                         TRB_LEN(event->transfer_len);
1195                                 if (td->urb->transfer_buffer_length <
1196                                                 td->urb->actual_length) {
1197                                         xhci_warn(xhci, "HC gave bad length "
1198                                                         "of %d bytes left\n",
1199                                                         TRB_LEN(event->transfer_len));
1200                                         td->urb->actual_length = 0;
1201                                         if (td->urb->transfer_flags &
1202                                                         URB_SHORT_NOT_OK)
1203                                                 status = -EREMOTEIO;
1204                                         else
1205                                                 status = 0;
1206                                 }
1207                                 /* Don't overwrite a previously set error code */
1208                                 if (status == -EINPROGRESS) {
1209                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1210                                                 status = -EREMOTEIO;
1211                                         else
1212                                                 status = 0;
1213                                 }
1214                         } else {
1215                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1216                                 /* Ignore a short packet completion if the
1217                                  * untransferred length was zero.
1218                                  */
1219                                 if (status == -EREMOTEIO)
1220                                         status = 0;
1221                         }
1222                 } else {
1223                         /* Slow path - walk the list, starting from the dequeue
1224                          * pointer, to get the actual length transferred.
1225                          */
1226                         union xhci_trb *cur_trb;
1227                         struct xhci_segment *cur_seg;
1228
1229                         td->urb->actual_length = 0;
1230                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1231                                         cur_trb != event_trb;
1232                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1233                                 if ((cur_trb->generic.field[3] &
1234                                  TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1235                                     (cur_trb->generic.field[3] &
1236                                  TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1237                                         td->urb->actual_length +=
1238                                                 TRB_LEN(cur_trb->generic.field[2]);
1239                         }
1240                         /* If the ring didn't stop on a Link or No-op TRB, add
1241                          * in the actual bytes transferred from the Normal TRB
1242                          */
1243                         if (trb_comp_code != COMP_STOP_INVAL)
1244                                 td->urb->actual_length +=
1245                                         TRB_LEN(cur_trb->generic.field[2]) -
1246                                         TRB_LEN(event->transfer_len);
1247                 }
1248         }
1249         if (trb_comp_code == COMP_STOP_INVAL ||
1250                         trb_comp_code == COMP_STOP) {
1251                 /* The Endpoint Stop Command completion will take care of any
1252                  * stopped TDs.  A stopped TD may be restarted, so don't update
1253                  * the ring dequeue pointer or take this TD off any lists yet.
1254                  */
1255                 ep->stopped_td = td;
1256                 ep->stopped_trb = event_trb;
1257         } else {
1258                 if (trb_comp_code == COMP_STALL ||
1259                                 trb_comp_code == COMP_BABBLE) {
1260                         /* The transfer is completed from the driver's
1261                          * perspective, but we need to issue a set dequeue
1262                          * command for this stalled endpoint to move the dequeue
1263                          * pointer past the TD.  We can't do that here because
1264                          * the halt condition must be cleared first.
1265                          */
1266                         ep->stopped_td = td;
1267                         ep->stopped_trb = event_trb;
1268                 } else {
1269                         /* Update ring dequeue pointer */
1270                         while (ep_ring->dequeue != td->last_trb)
1271                                 inc_deq(xhci, ep_ring, false);
1272                         inc_deq(xhci, ep_ring, false);
1273                 }
1274
1275 td_cleanup:
1276                 /* Clean up the endpoint's TD list */
1277                 urb = td->urb;
1278                 /* Do one last check of the actual transfer length.
1279                  * If the host controller said we transferred more data than
1280                  * the buffer length, urb->actual_length will be a very big
1281                  * number (since it's unsigned).  Play it safe and say we didn't
1282                  * transfer anything.
1283                  */
1284                 if (urb->actual_length > urb->transfer_buffer_length) {
1285                         xhci_warn(xhci, "URB transfer length is wrong, "
1286                                         "xHC issue? req. len = %u, "
1287                                         "act. len = %u\n",
1288                                         urb->transfer_buffer_length,
1289                                         urb->actual_length);
1290                         urb->actual_length = 0;
1291                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1292                                 status = -EREMOTEIO;
1293                         else
1294                                 status = 0;
1295                 }
1296                 list_del(&td->td_list);
1297                 /* Was this TD slated to be cancelled but completed anyway? */
1298                 if (!list_empty(&td->cancelled_td_list)) {
1299                         list_del(&td->cancelled_td_list);
1300                         ep->cancels_pending--;
1301                 }
1302                 /* Leave the TD around for the reset endpoint function to use
1303                  * (but only if it's not a control endpoint, since we already
1304                  * queued the Set TR dequeue pointer command for stalled
1305                  * control endpoints).
1306                  */
1307                 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1308                         (trb_comp_code != COMP_STALL &&
1309                                 trb_comp_code != COMP_BABBLE)) {
1310                         kfree(td);
1311                 }
1312                 urb->hcpriv = NULL;
1313         }
1314 cleanup:
1315         inc_deq(xhci, xhci->event_ring, true);
1316         xhci_set_hc_event_deq(xhci);
1317
1318         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1319         if (urb) {
1320                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1321                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1322                                 urb, urb->actual_length, status);
1323                 spin_unlock(&xhci->lock);
1324                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1325                 spin_lock(&xhci->lock);
1326         }
1327         return 0;
1328 }
1329
1330 /*
1331  * This function handles all OS-owned events on the event ring.  It may drop
1332  * xhci->lock between event processing (e.g. to pass up port status changes).
1333  */
1334 void xhci_handle_event(struct xhci_hcd *xhci)
1335 {
1336         union xhci_trb *event;
1337         int update_ptrs = 1;
1338         int ret;
1339
1340         xhci_dbg(xhci, "In %s\n", __func__);
1341         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1342                 xhci->error_bitmask |= 1 << 1;
1343                 return;
1344         }
1345
1346         event = xhci->event_ring->dequeue;
1347         /* Does the HC or OS own the TRB? */
1348         if ((event->event_cmd.flags & TRB_CYCLE) !=
1349                         xhci->event_ring->cycle_state) {
1350                 xhci->error_bitmask |= 1 << 2;
1351                 return;
1352         }
1353         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1354
1355         /* FIXME: Handle more event types. */
1356         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1357         case TRB_TYPE(TRB_COMPLETION):
1358                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1359                 handle_cmd_completion(xhci, &event->event_cmd);
1360                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1361                 break;
1362         case TRB_TYPE(TRB_PORT_STATUS):
1363                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1364                 handle_port_status(xhci, event);
1365                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1366                 update_ptrs = 0;
1367                 break;
1368         case TRB_TYPE(TRB_TRANSFER):
1369                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1370                 ret = handle_tx_event(xhci, &event->trans_event);
1371                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1372                 if (ret < 0)
1373                         xhci->error_bitmask |= 1 << 9;
1374                 else
1375                         update_ptrs = 0;
1376                 break;
1377         default:
1378                 xhci->error_bitmask |= 1 << 3;
1379         }
1380
1381         if (update_ptrs) {
1382                 /* Update SW and HC event ring dequeue pointer */
1383                 inc_deq(xhci, xhci->event_ring, true);
1384                 xhci_set_hc_event_deq(xhci);
1385         }
1386         /* Are there more items on the event ring? */
1387         xhci_handle_event(xhci);
1388 }
1389
1390 /****           Endpoint Ring Operations        ****/
1391
1392 /*
1393  * Generic function for queueing a TRB on a ring.
1394  * The caller must have checked to make sure there's room on the ring.
1395  */
1396 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1397                 bool consumer,
1398                 u32 field1, u32 field2, u32 field3, u32 field4)
1399 {
1400         struct xhci_generic_trb *trb;
1401
1402         trb = &ring->enqueue->generic;
1403         trb->field[0] = field1;
1404         trb->field[1] = field2;
1405         trb->field[2] = field3;
1406         trb->field[3] = field4;
1407         inc_enq(xhci, ring, consumer);
1408 }
1409
1410 /*
1411  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1412  * FIXME allocate segments if the ring is full.
1413  */
1414 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1415                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1416 {
1417         /* Make sure the endpoint has been added to xHC schedule */
1418         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1419         switch (ep_state) {
1420         case EP_STATE_DISABLED:
1421                 /*
1422                  * USB core changed config/interfaces without notifying us,
1423                  * or hardware is reporting the wrong state.
1424                  */
1425                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1426                 return -ENOENT;
1427         case EP_STATE_ERROR:
1428                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1429                 /* FIXME event handling code for error needs to clear it */
1430                 /* XXX not sure if this should be -ENOENT or not */
1431                 return -EINVAL;
1432         case EP_STATE_HALTED:
1433                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1434         case EP_STATE_STOPPED:
1435         case EP_STATE_RUNNING:
1436                 break;
1437         default:
1438                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1439                 /*
1440                  * FIXME issue Configure Endpoint command to try to get the HC
1441                  * back into a known state.
1442                  */
1443                 return -EINVAL;
1444         }
1445         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1446                 /* FIXME allocate more room */
1447                 xhci_err(xhci, "ERROR no room on ep ring\n");
1448                 return -ENOMEM;
1449         }
1450         return 0;
1451 }
1452
1453 static int prepare_transfer(struct xhci_hcd *xhci,
1454                 struct xhci_virt_device *xdev,
1455                 unsigned int ep_index,
1456                 unsigned int num_trbs,
1457                 struct urb *urb,
1458                 struct xhci_td **td,
1459                 gfp_t mem_flags)
1460 {
1461         int ret;
1462         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1463         ret = prepare_ring(xhci, xdev->eps[ep_index].ring,
1464                         ep_ctx->ep_info & EP_STATE_MASK,
1465                         num_trbs, mem_flags);
1466         if (ret)
1467                 return ret;
1468         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1469         if (!*td)
1470                 return -ENOMEM;
1471         INIT_LIST_HEAD(&(*td)->td_list);
1472         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1473
1474         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1475         if (unlikely(ret)) {
1476                 kfree(*td);
1477                 return ret;
1478         }
1479
1480         (*td)->urb = urb;
1481         urb->hcpriv = (void *) (*td);
1482         /* Add this TD to the tail of the endpoint ring's TD list */
1483         list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list);
1484         (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg;
1485         (*td)->first_trb = xdev->eps[ep_index].ring->enqueue;
1486
1487         return 0;
1488 }
1489
1490 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1491 {
1492         int num_sgs, num_trbs, running_total, temp, i;
1493         struct scatterlist *sg;
1494
1495         sg = NULL;
1496         num_sgs = urb->num_sgs;
1497         temp = urb->transfer_buffer_length;
1498
1499         xhci_dbg(xhci, "count sg list trbs: \n");
1500         num_trbs = 0;
1501         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1502                 unsigned int previous_total_trbs = num_trbs;
1503                 unsigned int len = sg_dma_len(sg);
1504
1505                 /* Scatter gather list entries may cross 64KB boundaries */
1506                 running_total = TRB_MAX_BUFF_SIZE -
1507                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
1508                 running_total &= TRB_MAX_BUFF_SIZE - 1;
1509                 if (running_total != 0)
1510                         num_trbs++;
1511
1512                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1513                 while (running_total < sg_dma_len(sg) && running_total < temp) {
1514                         num_trbs++;
1515                         running_total += TRB_MAX_BUFF_SIZE;
1516                 }
1517                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1518                                 i, (unsigned long long)sg_dma_address(sg),
1519                                 len, len, num_trbs - previous_total_trbs);
1520
1521                 len = min_t(int, len, temp);
1522                 temp -= len;
1523                 if (temp == 0)
1524                         break;
1525         }
1526         xhci_dbg(xhci, "\n");
1527         if (!in_interrupt())
1528                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1529                                 urb->ep->desc.bEndpointAddress,
1530                                 urb->transfer_buffer_length,
1531                                 num_trbs);
1532         return num_trbs;
1533 }
1534
1535 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1536 {
1537         if (num_trbs != 0)
1538                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1539                                 "TRBs, %d left\n", __func__,
1540                                 urb->ep->desc.bEndpointAddress, num_trbs);
1541         if (running_total != urb->transfer_buffer_length)
1542                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1543                                 "queued %#x (%d), asked for %#x (%d)\n",
1544                                 __func__,
1545                                 urb->ep->desc.bEndpointAddress,
1546                                 running_total, running_total,
1547                                 urb->transfer_buffer_length,
1548                                 urb->transfer_buffer_length);
1549 }
1550
1551 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1552                 unsigned int ep_index, int start_cycle,
1553                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1554 {
1555         /*
1556          * Pass all the TRBs to the hardware at once and make sure this write
1557          * isn't reordered.
1558          */
1559         wmb();
1560         start_trb->field[3] |= start_cycle;
1561         ring_ep_doorbell(xhci, slot_id, ep_index);
1562 }
1563
1564 /*
1565  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
1566  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
1567  * (comprised of sg list entries) can take several service intervals to
1568  * transmit.
1569  */
1570 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1571                 struct urb *urb, int slot_id, unsigned int ep_index)
1572 {
1573         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
1574                         xhci->devs[slot_id]->out_ctx, ep_index);
1575         int xhci_interval;
1576         int ep_interval;
1577
1578         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
1579         ep_interval = urb->interval;
1580         /* Convert to microframes */
1581         if (urb->dev->speed == USB_SPEED_LOW ||
1582                         urb->dev->speed == USB_SPEED_FULL)
1583                 ep_interval *= 8;
1584         /* FIXME change this to a warning and a suggestion to use the new API
1585          * to set the polling interval (once the API is added).
1586          */
1587         if (xhci_interval != ep_interval) {
1588                 if (!printk_ratelimit())
1589                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
1590                                         " (%d microframe%s) than xHCI "
1591                                         "(%d microframe%s)\n",
1592                                         ep_interval,
1593                                         ep_interval == 1 ? "" : "s",
1594                                         xhci_interval,
1595                                         xhci_interval == 1 ? "" : "s");
1596                 urb->interval = xhci_interval;
1597                 /* Convert back to frames for LS/FS devices */
1598                 if (urb->dev->speed == USB_SPEED_LOW ||
1599                                 urb->dev->speed == USB_SPEED_FULL)
1600                         urb->interval /= 8;
1601         }
1602         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
1603 }
1604
1605 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1606                 struct urb *urb, int slot_id, unsigned int ep_index)
1607 {
1608         struct xhci_ring *ep_ring;
1609         unsigned int num_trbs;
1610         struct xhci_td *td;
1611         struct scatterlist *sg;
1612         int num_sgs;
1613         int trb_buff_len, this_sg_len, running_total;
1614         bool first_trb;
1615         u64 addr;
1616
1617         struct xhci_generic_trb *start_trb;
1618         int start_cycle;
1619
1620         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1621         num_trbs = count_sg_trbs_needed(xhci, urb);
1622         num_sgs = urb->num_sgs;
1623
1624         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1625                         ep_index, num_trbs, urb, &td, mem_flags);
1626         if (trb_buff_len < 0)
1627                 return trb_buff_len;
1628         /*
1629          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1630          * until we've finished creating all the other TRBs.  The ring's cycle
1631          * state may change as we enqueue the other TRBs, so save it too.
1632          */
1633         start_trb = &ep_ring->enqueue->generic;
1634         start_cycle = ep_ring->cycle_state;
1635
1636         running_total = 0;
1637         /*
1638          * How much data is in the first TRB?
1639          *
1640          * There are three forces at work for TRB buffer pointers and lengths:
1641          * 1. We don't want to walk off the end of this sg-list entry buffer.
1642          * 2. The transfer length that the driver requested may be smaller than
1643          *    the amount of memory allocated for this scatter-gather list.
1644          * 3. TRBs buffers can't cross 64KB boundaries.
1645          */
1646         sg = urb->sg->sg;
1647         addr = (u64) sg_dma_address(sg);
1648         this_sg_len = sg_dma_len(sg);
1649         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
1650         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1651         if (trb_buff_len > urb->transfer_buffer_length)
1652                 trb_buff_len = urb->transfer_buffer_length;
1653         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1654                         trb_buff_len);
1655
1656         first_trb = true;
1657         /* Queue the first TRB, even if it's zero-length */
1658         do {
1659                 u32 field = 0;
1660                 u32 length_field = 0;
1661
1662                 /* Don't change the cycle bit of the first TRB until later */
1663                 if (first_trb)
1664                         first_trb = false;
1665                 else
1666                         field |= ep_ring->cycle_state;
1667
1668                 /* Chain all the TRBs together; clear the chain bit in the last
1669                  * TRB to indicate it's the last TRB in the chain.
1670                  */
1671                 if (num_trbs > 1) {
1672                         field |= TRB_CHAIN;
1673                 } else {
1674                         /* FIXME - add check for ZERO_PACKET flag before this */
1675                         td->last_trb = ep_ring->enqueue;
1676                         field |= TRB_IOC;
1677                 }
1678                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1679                                 "64KB boundary at %#x, end dma = %#x\n",
1680                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1681                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1682                                 (unsigned int) addr + trb_buff_len);
1683                 if (TRB_MAX_BUFF_SIZE -
1684                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
1685                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1686                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1687                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1688                                         (unsigned int) addr + trb_buff_len);
1689                 }
1690                 length_field = TRB_LEN(trb_buff_len) |
1691                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1692                         TRB_INTR_TARGET(0);
1693                 queue_trb(xhci, ep_ring, false,
1694                                 lower_32_bits(addr),
1695                                 upper_32_bits(addr),
1696                                 length_field,
1697                                 /* We always want to know if the TRB was short,
1698                                  * or we won't get an event when it completes.
1699                                  * (Unless we use event data TRBs, which are a
1700                                  * waste of space and HC resources.)
1701                                  */
1702                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1703                 --num_trbs;
1704                 running_total += trb_buff_len;
1705
1706                 /* Calculate length for next transfer --
1707                  * Are we done queueing all the TRBs for this sg entry?
1708                  */
1709                 this_sg_len -= trb_buff_len;
1710                 if (this_sg_len == 0) {
1711                         --num_sgs;
1712                         if (num_sgs == 0)
1713                                 break;
1714                         sg = sg_next(sg);
1715                         addr = (u64) sg_dma_address(sg);
1716                         this_sg_len = sg_dma_len(sg);
1717                 } else {
1718                         addr += trb_buff_len;
1719                 }
1720
1721                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1722                         (addr & (TRB_MAX_BUFF_SIZE - 1));
1723                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1724                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1725                         trb_buff_len =
1726                                 urb->transfer_buffer_length - running_total;
1727         } while (running_total < urb->transfer_buffer_length);
1728
1729         check_trb_math(urb, num_trbs, running_total);
1730         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1731         return 0;
1732 }
1733
1734 /* This is very similar to what ehci-q.c qtd_fill() does */
1735 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1736                 struct urb *urb, int slot_id, unsigned int ep_index)
1737 {
1738         struct xhci_ring *ep_ring;
1739         struct xhci_td *td;
1740         int num_trbs;
1741         struct xhci_generic_trb *start_trb;
1742         bool first_trb;
1743         int start_cycle;
1744         u32 field, length_field;
1745
1746         int running_total, trb_buff_len, ret;
1747         u64 addr;
1748
1749         if (urb->sg)
1750                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1751
1752         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1753
1754         num_trbs = 0;
1755         /* How much data is (potentially) left before the 64KB boundary? */
1756         running_total = TRB_MAX_BUFF_SIZE -
1757                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
1758         running_total &= TRB_MAX_BUFF_SIZE - 1;
1759
1760         /* If there's some data on this 64KB chunk, or we have to send a
1761          * zero-length transfer, we need at least one TRB
1762          */
1763         if (running_total != 0 || urb->transfer_buffer_length == 0)
1764                 num_trbs++;
1765         /* How many more 64KB chunks to transfer, how many more TRBs? */
1766         while (running_total < urb->transfer_buffer_length) {
1767                 num_trbs++;
1768                 running_total += TRB_MAX_BUFF_SIZE;
1769         }
1770         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1771
1772         if (!in_interrupt())
1773                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1774                                 urb->ep->desc.bEndpointAddress,
1775                                 urb->transfer_buffer_length,
1776                                 urb->transfer_buffer_length,
1777                                 (unsigned long long)urb->transfer_dma,
1778                                 num_trbs);
1779
1780         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1781                         num_trbs, urb, &td, mem_flags);
1782         if (ret < 0)
1783                 return ret;
1784
1785         /*
1786          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1787          * until we've finished creating all the other TRBs.  The ring's cycle
1788          * state may change as we enqueue the other TRBs, so save it too.
1789          */
1790         start_trb = &ep_ring->enqueue->generic;
1791         start_cycle = ep_ring->cycle_state;
1792
1793         running_total = 0;
1794         /* How much data is in the first TRB? */
1795         addr = (u64) urb->transfer_dma;
1796         trb_buff_len = TRB_MAX_BUFF_SIZE -
1797                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
1798         if (trb_buff_len > urb->transfer_buffer_length)
1799                 trb_buff_len = urb->transfer_buffer_length;
1800
1801         first_trb = true;
1802
1803         /* Queue the first TRB, even if it's zero-length */
1804         do {
1805                 field = 0;
1806
1807                 /* Don't change the cycle bit of the first TRB until later */
1808                 if (first_trb)
1809                         first_trb = false;
1810                 else
1811                         field |= ep_ring->cycle_state;
1812
1813                 /* Chain all the TRBs together; clear the chain bit in the last
1814                  * TRB to indicate it's the last TRB in the chain.
1815                  */
1816                 if (num_trbs > 1) {
1817                         field |= TRB_CHAIN;
1818                 } else {
1819                         /* FIXME - add check for ZERO_PACKET flag before this */
1820                         td->last_trb = ep_ring->enqueue;
1821                         field |= TRB_IOC;
1822                 }
1823                 length_field = TRB_LEN(trb_buff_len) |
1824                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1825                         TRB_INTR_TARGET(0);
1826                 queue_trb(xhci, ep_ring, false,
1827                                 lower_32_bits(addr),
1828                                 upper_32_bits(addr),
1829                                 length_field,
1830                                 /* We always want to know if the TRB was short,
1831                                  * or we won't get an event when it completes.
1832                                  * (Unless we use event data TRBs, which are a
1833                                  * waste of space and HC resources.)
1834                                  */
1835                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1836                 --num_trbs;
1837                 running_total += trb_buff_len;
1838
1839                 /* Calculate length for next transfer */
1840                 addr += trb_buff_len;
1841                 trb_buff_len = urb->transfer_buffer_length - running_total;
1842                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1843                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1844         } while (running_total < urb->transfer_buffer_length);
1845
1846         check_trb_math(urb, num_trbs, running_total);
1847         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1848         return 0;
1849 }
1850
1851 /* Caller must have locked xhci->lock */
1852 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1853                 struct urb *urb, int slot_id, unsigned int ep_index)
1854 {
1855         struct xhci_ring *ep_ring;
1856         int num_trbs;
1857         int ret;
1858         struct usb_ctrlrequest *setup;
1859         struct xhci_generic_trb *start_trb;
1860         int start_cycle;
1861         u32 field, length_field;
1862         struct xhci_td *td;
1863
1864         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1865
1866         /*
1867          * Need to copy setup packet into setup TRB, so we can't use the setup
1868          * DMA address.
1869          */
1870         if (!urb->setup_packet)
1871                 return -EINVAL;
1872
1873         if (!in_interrupt())
1874                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1875                                 slot_id, ep_index);
1876         /* 1 TRB for setup, 1 for status */
1877         num_trbs = 2;
1878         /*
1879          * Don't need to check if we need additional event data and normal TRBs,
1880          * since data in control transfers will never get bigger than 16MB
1881          * XXX: can we get a buffer that crosses 64KB boundaries?
1882          */
1883         if (urb->transfer_buffer_length > 0)
1884                 num_trbs++;
1885         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1886                         urb, &td, mem_flags);
1887         if (ret < 0)
1888                 return ret;
1889
1890         /*
1891          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1892          * until we've finished creating all the other TRBs.  The ring's cycle
1893          * state may change as we enqueue the other TRBs, so save it too.
1894          */
1895         start_trb = &ep_ring->enqueue->generic;
1896         start_cycle = ep_ring->cycle_state;
1897
1898         /* Queue setup TRB - see section 6.4.1.2.1 */
1899         /* FIXME better way to translate setup_packet into two u32 fields? */
1900         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1901         queue_trb(xhci, ep_ring, false,
1902                         /* FIXME endianness is probably going to bite my ass here. */
1903                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1904                         setup->wIndex | setup->wLength << 16,
1905                         TRB_LEN(8) | TRB_INTR_TARGET(0),
1906                         /* Immediate data in pointer */
1907                         TRB_IDT | TRB_TYPE(TRB_SETUP));
1908
1909         /* If there's data, queue data TRBs */
1910         field = 0;
1911         length_field = TRB_LEN(urb->transfer_buffer_length) |
1912                 TD_REMAINDER(urb->transfer_buffer_length) |
1913                 TRB_INTR_TARGET(0);
1914         if (urb->transfer_buffer_length > 0) {
1915                 if (setup->bRequestType & USB_DIR_IN)
1916                         field |= TRB_DIR_IN;
1917                 queue_trb(xhci, ep_ring, false,
1918                                 lower_32_bits(urb->transfer_dma),
1919                                 upper_32_bits(urb->transfer_dma),
1920                                 length_field,
1921                                 /* Event on short tx */
1922                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1923         }
1924
1925         /* Save the DMA address of the last TRB in the TD */
1926         td->last_trb = ep_ring->enqueue;
1927
1928         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1929         /* If the device sent data, the status stage is an OUT transfer */
1930         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1931                 field = 0;
1932         else
1933                 field = TRB_DIR_IN;
1934         queue_trb(xhci, ep_ring, false,
1935                         0,
1936                         0,
1937                         TRB_INTR_TARGET(0),
1938                         /* Event on completion */
1939                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1940
1941         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1942         return 0;
1943 }
1944
1945 /****           Command Ring Operations         ****/
1946
1947 /* Generic function for queueing a command TRB on the command ring.
1948  * Check to make sure there's room on the command ring for one command TRB.
1949  * Also check that there's room reserved for commands that must not fail.
1950  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
1951  * then only check for the number of reserved spots.
1952  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
1953  * because the command event handler may want to resubmit a failed command.
1954  */
1955 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
1956                 u32 field3, u32 field4, bool command_must_succeed)
1957 {
1958         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
1959         if (!command_must_succeed)
1960                 reserved_trbs++;
1961
1962         if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) {
1963                 if (!in_interrupt())
1964                         xhci_err(xhci, "ERR: No room for command on command ring\n");
1965                 if (command_must_succeed)
1966                         xhci_err(xhci, "ERR: Reserved TRB counting for "
1967                                         "unfailable commands failed.\n");
1968                 return -ENOMEM;
1969         }
1970         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1971                         field4 | xhci->cmd_ring->cycle_state);
1972         return 0;
1973 }
1974
1975 /* Queue a no-op command on the command ring */
1976 static int queue_cmd_noop(struct xhci_hcd *xhci)
1977 {
1978         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
1979 }
1980
1981 /*
1982  * Place a no-op command on the command ring to test the command and
1983  * event ring.
1984  */
1985 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1986 {
1987         if (queue_cmd_noop(xhci) < 0)
1988                 return NULL;
1989         xhci->noops_submitted++;
1990         return xhci_ring_cmd_db;
1991 }
1992
1993 /* Queue a slot enable or disable request on the command ring */
1994 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1995 {
1996         return queue_command(xhci, 0, 0, 0,
1997                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
1998 }
1999
2000 /* Queue an address device command TRB */
2001 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2002                 u32 slot_id)
2003 {
2004         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2005                         upper_32_bits(in_ctx_ptr), 0,
2006                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2007                         false);
2008 }
2009
2010 /* Queue a configure endpoint command TRB */
2011 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2012                 u32 slot_id, bool command_must_succeed)
2013 {
2014         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2015                         upper_32_bits(in_ctx_ptr), 0,
2016                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
2017                         command_must_succeed);
2018 }
2019
2020 /* Queue an evaluate context command TRB */
2021 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
2022                 u32 slot_id)
2023 {
2024         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
2025                         upper_32_bits(in_ctx_ptr), 0,
2026                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
2027                         false);
2028 }
2029
2030 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
2031                 unsigned int ep_index)
2032 {
2033         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2034         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2035         u32 type = TRB_TYPE(TRB_STOP_RING);
2036
2037         return queue_command(xhci, 0, 0, 0,
2038                         trb_slot_id | trb_ep_index | type, false);
2039 }
2040
2041 /* Set Transfer Ring Dequeue Pointer command.
2042  * This should not be used for endpoints that have streams enabled.
2043  */
2044 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
2045                 unsigned int ep_index, struct xhci_segment *deq_seg,
2046                 union xhci_trb *deq_ptr, u32 cycle_state)
2047 {
2048         dma_addr_t addr;
2049         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2050         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2051         u32 type = TRB_TYPE(TRB_SET_DEQ);
2052
2053         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
2054         if (addr == 0) {
2055                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
2056                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
2057                                 deq_seg, deq_ptr);
2058                 return 0;
2059         }
2060         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
2061                         upper_32_bits(addr), 0,
2062                         trb_slot_id | trb_ep_index | type, false);
2063 }
2064
2065 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
2066                 unsigned int ep_index)
2067 {
2068         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
2069         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
2070         u32 type = TRB_TYPE(TRB_RESET_EP);
2071
2072         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
2073                         false);
2074 }