2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
43 #define PCI_VENDOR_ID_ETRON 0x1b6f
44 #define PCI_DEVICE_ID_EJ168 0x7023
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
55 static const char hcd_name[] = "xhci_hcd";
57 static struct hc_driver __read_mostly xhci_pci_hc_driver;
59 static int xhci_pci_setup(struct usb_hcd *hcd);
61 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
62 .extra_priv_size = sizeof(struct xhci_hcd),
63 .reset = xhci_pci_setup,
66 /* called after powerup, by probe or system-pm "wakeup" */
67 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
70 * TODO: Implement finding debug ports later.
71 * TODO: see if there are any quirks that need to be added to handle
72 * new extended capabilities.
75 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
76 if (!pci_set_mwi(pdev))
77 xhci_dbg(xhci, "MWI active\n");
79 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
83 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
85 struct pci_dev *pdev = to_pci_dev(dev);
87 /* Look for vendor-specific quirks */
88 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
89 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
90 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
91 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
92 pdev->revision == 0x0) {
93 xhci->quirks |= XHCI_RESET_EP_QUIRK;
94 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
95 "QUIRK: Fresco Logic xHC needs configure"
96 " endpoint cmd after reset endpoint");
98 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
99 pdev->revision == 0x4) {
100 xhci->quirks |= XHCI_SLOW_SUSPEND;
101 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
102 "QUIRK: Fresco Logic xHC revision %u"
103 "must be suspended extra slowly",
106 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
107 xhci->quirks |= XHCI_BROKEN_STREAMS;
108 /* Fresco Logic confirms: all revisions of this chip do not
109 * support MSI, even though some of them claim to in their PCI
112 xhci->quirks |= XHCI_BROKEN_MSI;
113 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
114 "QUIRK: Fresco Logic revision %u "
115 "has broken MSI implementation",
117 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
120 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
121 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
122 xhci->quirks |= XHCI_BROKEN_STREAMS;
124 if (pdev->vendor == PCI_VENDOR_ID_NEC)
125 xhci->quirks |= XHCI_NEC_HOST;
127 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
128 xhci->quirks |= XHCI_AMD_0x96_HOST;
131 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
132 xhci->quirks |= XHCI_AMD_PLL_FIX;
134 if (pdev->vendor == PCI_VENDOR_ID_AMD)
135 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
137 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
138 xhci->quirks |= XHCI_LPM_SUPPORT;
139 xhci->quirks |= XHCI_INTEL_HOST;
140 xhci->quirks |= XHCI_AVOID_BEI;
142 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
143 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
144 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
145 xhci->limit_active_eps = 64;
146 xhci->quirks |= XHCI_SW_BW_CHECKING;
148 * PPT desktop boards DH77EB and DH77DF will power back on after
149 * a few seconds of being shutdown. The fix for this is to
150 * switch the ports from xHCI to EHCI on shutdown. We can't use
151 * DMI information to find those particular boards (since each
152 * vendor will change the board name), so we have to key off all
155 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
157 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
158 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
159 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
160 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
161 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
163 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
164 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
165 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
166 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
167 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
168 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
169 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
171 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
172 pdev->device == PCI_DEVICE_ID_EJ168) {
173 xhci->quirks |= XHCI_RESET_ON_RESUME;
174 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
175 xhci->quirks |= XHCI_BROKEN_STREAMS;
177 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
178 pdev->device == 0x0015)
179 xhci->quirks |= XHCI_RESET_ON_RESUME;
180 if (pdev->vendor == PCI_VENDOR_ID_VIA)
181 xhci->quirks |= XHCI_RESET_ON_RESUME;
183 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
184 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
185 pdev->device == 0x3432)
186 xhci->quirks |= XHCI_BROKEN_STREAMS;
188 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
189 pdev->device == 0x1042)
190 xhci->quirks |= XHCI_BROKEN_STREAMS;
192 if (xhci->quirks & XHCI_RESET_ON_RESUME)
193 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
194 "QUIRK: Resetting on resume");
198 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
200 static const u8 intel_dsm_uuid[] = {
201 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
202 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
204 union acpi_object *obj;
206 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
211 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
212 #endif /* CONFIG_ACPI */
214 /* called during probe() after chip reset completes */
215 static int xhci_pci_setup(struct usb_hcd *hcd)
217 struct xhci_hcd *xhci;
218 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
221 xhci = hcd_to_xhci(hcd);
223 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
225 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
229 if (!usb_hcd_is_primary_hcd(hcd))
232 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
234 /* Find any debug ports */
235 retval = xhci_pci_reinit(xhci, pdev);
243 * We need to register our own PCI probe function (instead of the USB core's
244 * function) in order to create a second roothub under xHCI.
246 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
249 struct xhci_hcd *xhci;
250 struct hc_driver *driver;
253 driver = (struct hc_driver *)id->driver_data;
255 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
256 pm_runtime_get_noresume(&dev->dev);
258 /* Register the USB 2.0 roothub.
259 * FIXME: USB core must know to register the USB 2.0 roothub first.
260 * This is sort of silly, because we could just set the HCD driver flags
261 * to say USB 2.0, but I'm not sure what the implications would be in
262 * the other parts of the HCD code.
264 retval = usb_hcd_pci_probe(dev, id);
269 /* USB 2.0 roothub is stored in the PCI device now. */
270 hcd = dev_get_drvdata(&dev->dev);
271 xhci = hcd_to_xhci(hcd);
272 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
274 if (!xhci->shared_hcd) {
276 goto dealloc_usb2_hcd;
279 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
283 /* Roothub already marked as USB 3.0 speed */
285 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
286 HCC_MAX_PSA(xhci->hcc_params) >= 4)
287 xhci->shared_hcd->can_do_streams = 1;
289 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
290 xhci_pme_acpi_rtd3_enable(dev);
292 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
293 pm_runtime_put_noidle(&dev->dev);
298 usb_put_hcd(xhci->shared_hcd);
300 usb_hcd_pci_remove(dev);
302 pm_runtime_put_noidle(&dev->dev);
306 static void xhci_pci_remove(struct pci_dev *dev)
308 struct xhci_hcd *xhci;
310 xhci = hcd_to_xhci(pci_get_drvdata(dev));
311 xhci->xhc_state |= XHCI_STATE_REMOVING;
312 if (xhci->shared_hcd) {
313 usb_remove_hcd(xhci->shared_hcd);
314 usb_put_hcd(xhci->shared_hcd);
317 /* Workaround for spurious wakeups at shutdown with HSW */
318 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
319 pci_set_power_state(dev, PCI_D3hot);
321 usb_hcd_pci_remove(dev);
326 * In some Intel xHCI controllers, in order to get D3 working,
327 * through a vendor specific SSIC CONFIG register at offset 0x883c,
328 * SSIC PORT need to be marked as "unused" before putting xHCI
329 * into D3. After D3 exit, the SSIC port need to be marked as "used".
330 * Without this change, xHCI might not enter D3 state.
331 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
332 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
334 static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
336 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
337 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
342 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
343 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
345 for (i = 0; i < SSIC_PORT_NUM; i++) {
346 reg = (void __iomem *) xhci->cap_regs +
348 i * SSIC_PORT_CFG2_OFFSET;
351 * Notify SSIC that SSIC profile programming
354 val = readl(reg) & ~PROG_DONE;
357 /* Mark SSIC port as unused(suspend) or used(resume) */
360 val |= SSIC_PORT_UNUSED;
362 val &= ~SSIC_PORT_UNUSED;
365 /* Notify SSIC that SSIC profile programming is done */
366 val = readl(reg) | PROG_DONE;
372 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
374 writel(val | BIT(28), reg);
378 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
380 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
381 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
384 * Systems with the TI redriver that loses port status change events
385 * need to have the registers polled during D3, so avoid D3cold.
387 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
388 pdev->no_d3cold = true;
390 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
391 xhci_pme_quirk(hcd, true);
393 return xhci_suspend(xhci, do_wakeup);
396 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
398 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
399 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
402 /* The BIOS on systems with the Intel Panther Point chipset may or may
403 * not support xHCI natively. That means that during system resume, it
404 * may switch the ports back to EHCI so that users can use their
405 * keyboard to select a kernel from GRUB after resume from hibernate.
407 * The BIOS is supposed to remember whether the OS had xHCI ports
408 * enabled before resume, and switch the ports back to xHCI when the
409 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
412 * Unconditionally switch the ports back to xHCI after a system resume.
413 * It should not matter whether the EHCI or xHCI controller is
414 * resumed first. It's enough to do the switchover in xHCI because
415 * USB core won't notice anything as the hub driver doesn't start
416 * running again until after all the devices (including both EHCI and
417 * xHCI host controllers) have been resumed.
420 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
421 usb_enable_intel_xhci_ports(pdev);
423 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
424 xhci_pme_quirk(hcd, false);
426 retval = xhci_resume(xhci, hibernated);
429 #endif /* CONFIG_PM */
431 /*-------------------------------------------------------------------------*/
433 /* PCI driver selection metadata; PCI hotplugging uses this */
434 static const struct pci_device_id pci_ids[] = { {
435 /* handle any USB 3.0 xHCI controller */
436 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
437 .driver_data = (unsigned long) &xhci_pci_hc_driver,
439 { /* end: all zeroes */ }
441 MODULE_DEVICE_TABLE(pci, pci_ids);
443 /* pci driver glue; this is a "new style" PCI driver module */
444 static struct pci_driver xhci_pci_driver = {
445 .name = (char *) hcd_name,
448 .probe = xhci_pci_probe,
449 .remove = xhci_pci_remove,
450 /* suspend and resume implemented later */
452 .shutdown = usb_hcd_pci_shutdown,
455 .pm = &usb_hcd_pci_pm_ops
460 static int __init xhci_pci_init(void)
462 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
464 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
465 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
467 return pci_register_driver(&xhci_pci_driver);
469 module_init(xhci_pci_init);
471 static void __exit xhci_pci_exit(void)
473 pci_unregister_driver(&xhci_pci_driver);
475 module_exit(xhci_pci_exit);
477 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
478 MODULE_LICENSE("GPL");