drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  38                                         unsigned int cycle_state, gfp_t flags)
  39 {
  40         struct xhci_segment *seg;
  41         dma_addr_t      dma;
  42         int             i;
  43
  44         seg = kzalloc(sizeof *seg, flags);
  45         if (!seg)
  46                 return NULL;
  47
  48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  49         if (!seg->trbs) {
  50                 kfree(seg);
  51                 return NULL;
  52         }
  53
  54         memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
  55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  56         if (cycle_state == 0) {
  57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  58                         seg->trbs[i].link.control |= TRB_CYCLE;
  59         }
  60         seg->dma = dma;
  61         seg->next = NULL;
  62
  63         return seg;
  64 }
  65
  66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  67 {
  68         if (seg->trbs) {
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         kfree(seg);
  73 }
  74
  75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  76                                 struct xhci_segment *first)
  77 {
  78         struct xhci_segment *seg;
  79
  80         seg = first->next;
  81         while (seg != first) {
  82                 struct xhci_segment *next = seg->next;
  83                 xhci_segment_free(xhci, seg);
  84                 seg = next;
  85         }
  86         xhci_segment_free(xhci, first);
  87 }
  88
  89 /*
  90  * Make the prev segment point to the next segment.
  91  *
  92  * Change the last TRB in the prev segment to be a Link TRB which points to the
  93  * DMA address of the next segment.  The caller needs to set any Link TRB
  94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95  */
  96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  97                 struct xhci_segment *next, enum xhci_ring_type type)
  98 {
  99         u32 val;
 100
 101         if (!prev || !next)
 102                 return;
 103         prev->next = next;
 104         if (type != TYPE_EVENT) {
 105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 106                         cpu_to_le64(next->dma);
 107
 108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 110                 val &= ~TRB_TYPE_BITMASK;
 111                 val |= TRB_TYPE(TRB_LINK);
 112                 /* Always set the chain bit with 0.95 hardware */
 113                 /* Set chain bit for isoc rings on AMD 0.96 host */
 114                 if (xhci_link_trb_quirk(xhci) ||
 115                                 (type == TYPE_ISOC &&
 116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 117                         val |= TRB_CHAIN;
 118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 119         }
 120 }
 121
 122 /*
 123  * Link the ring to the new segments.
 124  * Set Toggle Cycle for the new ring if needed.
 125  */
 126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
 127                 struct xhci_segment *first, struct xhci_segment *last,
 128                 unsigned int num_segs)
 129 {
 130         struct xhci_segment *next;
 131
 132         if (!ring || !first || !last)
 133                 return;
 134
 135         next = ring->enq_seg->next;
 136         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
 137         xhci_link_segments(xhci, last, next, ring->type);
 138         ring->num_segs += num_segs;
 139         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
 140
 141         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
 142                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 143                         &= ~cpu_to_le32(LINK_TOGGLE);
 144                 last->trbs[TRBS_PER_SEGMENT-1].link.control
 145                         |= cpu_to_le32(LINK_TOGGLE);
 146                 ring->last_seg = last;
 147         }
 148 }
 149
 150 /* XXX: Do we need the hcd structure in all these functions? */
 151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 152 {
 153         if (!ring)
 154                 return;
 155
 156         if (ring->first_seg)
 157                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 158
 159         kfree(ring);
 160 }
 161
 162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 163                                         unsigned int cycle_state)
 164 {
 165         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 166         ring->enqueue = ring->first_seg->trbs;
 167         ring->enq_seg = ring->first_seg;
 168         ring->dequeue = ring->enqueue;
 169         ring->deq_seg = ring->first_seg;
 170         /* The ring is initialized to 0. The producer must write 1 to the cycle
 171          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 172          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 173          *
 174          * New rings are initialized with cycle state equal to 1; if we are
 175          * handling ring expansion, set the cycle state equal to the old ring.
 176          */
 177         ring->cycle_state = cycle_state;
 178         /* Not necessary for new rings, but needed for re-initialized rings */
 179         ring->enq_updates = 0;
 180         ring->deq_updates = 0;
 181
 182         /*
 183          * Each segment has a link TRB, and leave an extra TRB for SW
 184          * accounting purpose
 185          */
 186         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 187 }
 188
 189 /* Allocate segments and link them for a ring */
 190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 191                 struct xhci_segment **first, struct xhci_segment **last,
 192                 unsigned int num_segs, unsigned int cycle_state,
 193                 enum xhci_ring_type type, gfp_t flags)
 194 {
 195         struct xhci_segment *prev;
 196
 197         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 198         if (!prev)
 199                 return -ENOMEM;
 200         num_segs--;
 201
 202         *first = prev;
 203         while (num_segs > 0) {
 204                 struct xhci_segment     *next;
 205
 206                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 207                 if (!next) {
 208                         prev = *first;
 209                         while (prev) {
 210                                 next = prev->next;
 211                                 xhci_segment_free(xhci, prev);
 212                                 prev = next;
 213                         }
 214                         return -ENOMEM;
 215                 }
 216                 xhci_link_segments(xhci, prev, next, type);
 217
 218                 prev = next;
 219                 num_segs--;
 220         }
 221         xhci_link_segments(xhci, prev, *first, type);
 222         *last = prev;
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * Create a new ring with zero or more segments.
 229  *
 230  * Link each segment together into a ring.
 231  * Set the end flag and the cycle toggle bit on the last segment.
 232  * See section 4.9.1 and figures 15 and 16.
 233  */
 234 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 235                 unsigned int num_segs, unsigned int cycle_state,
 236                 enum xhci_ring_type type, gfp_t flags)
 237 {
 238         struct xhci_ring        *ring;
 239         int ret;
 240
 241         ring = kzalloc(sizeof *(ring), flags);
 242         if (!ring)
 243                 return NULL;
 244
 245         ring->num_segs = num_segs;
 246         INIT_LIST_HEAD(&ring->td_list);
 247         ring->type = type;
 248         if (num_segs == 0)
 249                 return ring;
 250
 251         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 252                         &ring->last_seg, num_segs, cycle_state, type, flags);
 253         if (ret)
 254                 goto fail;
 255
 256         /* Only event ring does not use link TRB */
 257         if (type != TYPE_EVENT) {
 258                 /* See section 4.9.2.1 and 6.4.4.1 */
 259                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 260                         cpu_to_le32(LINK_TOGGLE);
 261         }
 262         xhci_initialize_ring_info(ring, cycle_state);
 263         return ring;
 264
 265 fail:
 266         kfree(ring);
 267         return NULL;
 268 }
 269
 270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 271                 struct xhci_virt_device *virt_dev,
 272                 unsigned int ep_index)
 273 {
 274         int rings_cached;
 275
 276         rings_cached = virt_dev->num_rings_cached;
 277         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 278                 virt_dev->ring_cache[rings_cached] =
 279                         virt_dev->eps[ep_index].ring;
 280                 virt_dev->num_rings_cached++;
 281                 xhci_dbg(xhci, "Cached old ring, "
 282                                 "%d ring%s cached\n",
 283                                 virt_dev->num_rings_cached,
 284                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 285         } else {
 286                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 287                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 288                                 "freeing ring\n",
 289                                 virt_dev->num_rings_cached);
 290         }
 291         virt_dev->eps[ep_index].ring = NULL;
 292 }
 293
 294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 295  * pointers to the beginning of the ring.
 296  */
 297 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 298                         struct xhci_ring *ring, unsigned int cycle_state,
 299                         enum xhci_ring_type type)
 300 {
 301         struct xhci_segment     *seg = ring->first_seg;
 302         int i;
 303
 304         do {
 305                 memset(seg->trbs, 0,
 306                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 307                 if (cycle_state == 0) {
 308                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 309                                 seg->trbs[i].link.control |= TRB_CYCLE;
 310                 }
 311                 /* All endpoint rings have link TRBs */
 312                 xhci_link_segments(xhci, seg, seg->next, type);
 313                 seg = seg->next;
 314         } while (seg != ring->first_seg);
 315         ring->type = type;
 316         xhci_initialize_ring_info(ring, cycle_state);
 317         /* td list should be empty since all URBs have been cancelled,
 318          * but just in case...
 319          */
 320         INIT_LIST_HEAD(&ring->td_list);
 321 }
 322
 323 /*
 324  * Expand an existing ring.
 325  * Look for a cached ring or allocate a new ring which has same segment numbers
 326  * and link the two rings.
 327  */
 328 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 329                                 unsigned int num_trbs, gfp_t flags)
 330 {
 331         struct xhci_segment     *first;
 332         struct xhci_segment     *last;
 333         unsigned int            num_segs;
 334         unsigned int            num_segs_needed;
 335         int                     ret;
 336
 337         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
 338                                 (TRBS_PER_SEGMENT - 1);
 339
 340         /* Allocate number of segments we needed, or double the ring size */
 341         num_segs = ring->num_segs > num_segs_needed ?
 342                         ring->num_segs : num_segs_needed;
 343
 344         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
 345                         num_segs, ring->cycle_state, ring->type, flags);
 346         if (ret)
 347                 return -ENOMEM;
 348
 349         xhci_link_rings(xhci, ring, first, last, num_segs);
 350         xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
 351                         ring->num_segs);
 352
 353         return 0;
 354 }
 355
 356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 357
 358 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 359                                                     int type, gfp_t flags)
 360 {
 361         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 362         if (!ctx)
 363                 return NULL;
 364
 365         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 366         ctx->type = type;
 367         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 368         if (type == XHCI_CTX_TYPE_INPUT)
 369                 ctx->size += CTX_SIZE(xhci->hcc_params);
 370
 371         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 372         if (!ctx->bytes) {
 373                 kfree(ctx);
 374                 return NULL;
 375         }
 376         memset(ctx->bytes, 0, ctx->size);
 377         return ctx;
 378 }
 379
 380 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 381                              struct xhci_container_ctx *ctx)
 382 {
 383         if (!ctx)
 384                 return;
 385         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 386         kfree(ctx);
 387 }
 388
 389 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 390                                               struct xhci_container_ctx *ctx)
 391 {
 392         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 393         return (struct xhci_input_control_ctx *)ctx->bytes;
 394 }
 395
 396 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 397                                         struct xhci_container_ctx *ctx)
 398 {
 399         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 400                 return (struct xhci_slot_ctx *)ctx->bytes;
 401
 402         return (struct xhci_slot_ctx *)
 403                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 404 }
 405
 406 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 407                                     struct xhci_container_ctx *ctx,
 408                                     unsigned int ep_index)
 409 {
 410         /* increment ep index by offset of start of ep ctx array */
 411         ep_index++;
 412         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 413                 ep_index++;
 414
 415         return (struct xhci_ep_ctx *)
 416                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 417 }
 418
 419
 420 /***************** Streams structures manipulation *************************/
 421
 422 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 423                 unsigned int num_stream_ctxs,
 424                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 425 {
 426         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 427
 428         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 429                 dma_free_coherent(&pdev->dev,
 430                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 431                                 stream_ctx, dma);
 432         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 433                 return dma_pool_free(xhci->small_streams_pool,
 434                                 stream_ctx, dma);
 435         else
 436                 return dma_pool_free(xhci->medium_streams_pool,
 437                                 stream_ctx, dma);
 438 }
 439
 440 /*
 441  * The stream context array for each endpoint with bulk streams enabled can
 442  * vary in size, based on:
 443  *  - how many streams the endpoint supports,
 444  *  - the maximum primary stream array size the host controller supports,
 445  *  - and how many streams the device driver asks for.
 446  *
 447  * The stream context array must be a power of 2, and can be as small as
 448  * 64 bytes or as large as 1MB.
 449  */
 450 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 451                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 452                 gfp_t mem_flags)
 453 {
 454         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 455
 456         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 457                 return dma_alloc_coherent(&pdev->dev,
 458                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 459                                 dma, mem_flags);
 460         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 461                 return dma_pool_alloc(xhci->small_streams_pool,
 462                                 mem_flags, dma);
 463         else
 464                 return dma_pool_alloc(xhci->medium_streams_pool,
 465                                 mem_flags, dma);
 466 }
 467
 468 struct xhci_ring *xhci_dma_to_transfer_ring(
 469                 struct xhci_virt_ep *ep,
 470                 u64 address)
 471 {
 472         if (ep->ep_state & EP_HAS_STREAMS)
 473                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 474                                 address >> TRB_SEGMENT_SHIFT);
 475         return ep->ring;
 476 }
 477
 478 /* Only use this when you know stream_info is valid */
 479 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 480 static struct xhci_ring *dma_to_stream_ring(
 481                 struct xhci_stream_info *stream_info,
 482                 u64 address)
 483 {
 484         return radix_tree_lookup(&stream_info->trb_address_map,
 485                         address >> TRB_SEGMENT_SHIFT);
 486 }
 487 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 488
 489 struct xhci_ring *xhci_stream_id_to_ring(
 490                 struct xhci_virt_device *dev,
 491                 unsigned int ep_index,
 492                 unsigned int stream_id)
 493 {
 494         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 495
 496         if (stream_id == 0)
 497                 return ep->ring;
 498         if (!ep->stream_info)
 499                 return NULL;
 500
 501         if (stream_id > ep->stream_info->num_streams)
 502                 return NULL;
 503         return ep->stream_info->stream_rings[stream_id];
 504 }
 505
 506 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 507 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 508                 unsigned int num_streams,
 509                 struct xhci_stream_info *stream_info)
 510 {
 511         u32 cur_stream;
 512         struct xhci_ring *cur_ring;
 513         u64 addr;
 514
 515         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 516                 struct xhci_ring *mapped_ring;
 517                 int trb_size = sizeof(union xhci_trb);
 518
 519                 cur_ring = stream_info->stream_rings[cur_stream];
 520                 for (addr = cur_ring->first_seg->dma;
 521                                 addr < cur_ring->first_seg->dma + TRB_SEGMENT_SIZE;
 522                                 addr += trb_size) {
 523                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 524                         if (cur_ring != mapped_ring) {
 525                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 526                                                 "didn't map to stream ID %u; "
 527                                                 "mapped to ring %p\n",
 528                                                 (unsigned long long) addr,
 529                                                 cur_stream,
 530                                                 mapped_ring);
 531                                 return -EINVAL;
 532                         }
 533                 }
 534                 /* One TRB after the end of the ring segment shouldn't return a
 535                  * pointer to the current ring (although it may be a part of a
 536                  * different ring).
 537                  */
 538                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 539                 if (mapped_ring != cur_ring) {
 540                         /* One TRB before should also fail */
 541                         addr = cur_ring->first_seg->dma - trb_size;
 542                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 543                 }
 544                 if (mapped_ring == cur_ring) {
 545                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 546                                         "mapped to valid stream ID %u; "
 547                                         "mapped ring = %p\n",
 548                                         (unsigned long long) addr,
 549                                         cur_stream,
 550                                         mapped_ring);
 551                         return -EINVAL;
 552                 }
 553         }
 554         return 0;
 555 }
 556 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 557
 558 /*
 559  * Change an endpoint's internal structure so it supports stream IDs.  The
 560  * number of requested streams includes stream 0, which cannot be used by device
 561  * drivers.
 562  *
 563  * The number of stream contexts in the stream context array may be bigger than
 564  * the number of streams the driver wants to use.  This is because the number of
 565  * stream context array entries must be a power of two.
 566  *
 567  * We need a radix tree for mapping physical addresses of TRBs to which stream
 568  * ID they belong to.  We need to do this because the host controller won't tell
 569  * us which stream ring the TRB came from.  We could store the stream ID in an
 570  * event data TRB, but that doesn't help us for the cancellation case, since the
 571  * endpoint may stop before it reaches that event data TRB.
 572  *
 573  * The radix tree maps the upper portion of the TRB DMA address to a ring
 574  * segment that has the same upper portion of DMA addresses.  For example, say I
 575  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 576  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 577  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 578  * pass the radix tree a key to get the right stream ID:
 579  *
 580  *      0x10c90fff >> 10 = 0x43243
 581  *      0x10c912c0 >> 10 = 0x43244
 582  *      0x10c91400 >> 10 = 0x43245
 583  *
 584  * Obviously, only those TRBs with DMA addresses that are within the segment
 585  * will make the radix tree return the stream ID for that ring.
 586  *
 587  * Caveats for the radix tree:
 588  *
 589  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 590  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 591  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 592  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 593  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 594  * extended systems (where the DMA address can be bigger than 32-bits),
 595  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 596  */
 597 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 598                 unsigned int num_stream_ctxs,
 599                 unsigned int num_streams, gfp_t mem_flags)
 600 {
 601         struct xhci_stream_info *stream_info;
 602         u32 cur_stream;
 603         struct xhci_ring *cur_ring;
 604         unsigned long key;
 605         u64 addr;
 606         int ret;
 607
 608         xhci_dbg(xhci, "Allocating %u streams and %u "
 609                         "stream context array entries.\n",
 610                         num_streams, num_stream_ctxs);
 611         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 612                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 613                 return NULL;
 614         }
 615         xhci->cmd_ring_reserved_trbs++;
 616
 617         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 618         if (!stream_info)
 619                 goto cleanup_trbs;
 620
 621         stream_info->num_streams = num_streams;
 622         stream_info->num_stream_ctxs = num_stream_ctxs;
 623
 624         /* Initialize the array of virtual pointers to stream rings. */
 625         stream_info->stream_rings = kzalloc(
 626                         sizeof(struct xhci_ring *)*num_streams,
 627                         mem_flags);
 628         if (!stream_info->stream_rings)
 629                 goto cleanup_info;
 630
 631         /* Initialize the array of DMA addresses for stream rings for the HW. */
 632         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 633                         num_stream_ctxs, &stream_info->ctx_array_dma,
 634                         mem_flags);
 635         if (!stream_info->stream_ctx_array)
 636                 goto cleanup_ctx;
 637         memset(stream_info->stream_ctx_array, 0,
 638                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 639
 640         /* Allocate everything needed to free the stream rings later */
 641         stream_info->free_streams_command =
 642                 xhci_alloc_command(xhci, true, true, mem_flags);
 643         if (!stream_info->free_streams_command)
 644                 goto cleanup_ctx;
 645
 646         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 647
 648         /* Allocate rings for all the streams that the driver will use,
 649          * and add their segment DMA addresses to the radix tree.
 650          * Stream 0 is reserved.
 651          */
 652         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 653                 stream_info->stream_rings[cur_stream] =
 654                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
 655                 cur_ring = stream_info->stream_rings[cur_stream];
 656                 if (!cur_ring)
 657                         goto cleanup_rings;
 658                 cur_ring->stream_id = cur_stream;
 659                 /* Set deq ptr, cycle bit, and stream context type */
 660                 addr = cur_ring->first_seg->dma |
 661                         SCT_FOR_CTX(SCT_PRI_TR) |
 662                         cur_ring->cycle_state;
 663                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 664                         cpu_to_le64(addr);
 665                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 666                                 cur_stream, (unsigned long long) addr);
 667
 668                 key = (unsigned long)
 669                         (cur_ring->first_seg->dma >> TRB_SEGMENT_SHIFT);
 670                 ret = radix_tree_insert(&stream_info->trb_address_map,
 671                                 key, cur_ring);
 672                 if (ret) {
 673                         xhci_ring_free(xhci, cur_ring);
 674                         stream_info->stream_rings[cur_stream] = NULL;
 675                         goto cleanup_rings;
 676                 }
 677         }
 678         /* Leave the other unused stream ring pointers in the stream context
 679          * array initialized to zero.  This will cause the xHC to give us an
 680          * error if the device asks for a stream ID we don't have setup (if it
 681          * was any other way, the host controller would assume the ring is
 682          * "empty" and wait forever for data to be queued to that stream ID).
 683          */
 684 #if XHCI_DEBUG
 685         /* Do a little test on the radix tree to make sure it returns the
 686          * correct values.
 687          */
 688         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 689                 goto cleanup_rings;
 690 #endif
 691
 692         return stream_info;
 693
 694 cleanup_rings:
 695         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 696                 cur_ring = stream_info->stream_rings[cur_stream];
 697                 if (cur_ring) {
 698                         addr = cur_ring->first_seg->dma;
 699                         radix_tree_delete(&stream_info->trb_address_map,
 700                                         addr >> TRB_SEGMENT_SHIFT);
 701                         xhci_ring_free(xhci, cur_ring);
 702                         stream_info->stream_rings[cur_stream] = NULL;
 703                 }
 704         }
 705         xhci_free_command(xhci, stream_info->free_streams_command);
 706 cleanup_ctx:
 707         kfree(stream_info->stream_rings);
 708 cleanup_info:
 709         kfree(stream_info);
 710 cleanup_trbs:
 711         xhci->cmd_ring_reserved_trbs--;
 712         return NULL;
 713 }
 714 /*
 715  * Sets the MaxPStreams field and the Linear Stream Array field.
 716  * Sets the dequeue pointer to the stream context array.
 717  */
 718 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 719                 struct xhci_ep_ctx *ep_ctx,
 720                 struct xhci_stream_info *stream_info)
 721 {
 722         u32 max_primary_streams;
 723         /* MaxPStreams is the number of stream context array entries, not the
 724          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 725          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 726          */
 727         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 728         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 729                         1 << (max_primary_streams + 1));
 730         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 731         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 732                                        | EP_HAS_LSA);
 733         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 734 }
 735
 736 /*
 737  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 738  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 739  * not at the beginning of the ring).
 740  */
 741 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 742                 struct xhci_ep_ctx *ep_ctx,
 743                 struct xhci_virt_ep *ep)
 744 {
 745         dma_addr_t addr;
 746         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 747         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 748         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 749 }
 750
 751 /* Frees all stream contexts associated with the endpoint,
 752  *
 753  * Caller should fix the endpoint context streams fields.
 754  */
 755 void xhci_free_stream_info(struct xhci_hcd *xhci,
 756                 struct xhci_stream_info *stream_info)
 757 {
 758         int cur_stream;
 759         struct xhci_ring *cur_ring;
 760         dma_addr_t addr;
 761
 762         if (!stream_info)
 763                 return;
 764
 765         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 766                         cur_stream++) {
 767                 cur_ring = stream_info->stream_rings[cur_stream];
 768                 if (cur_ring) {
 769                         addr = cur_ring->first_seg->dma;
 770                         radix_tree_delete(&stream_info->trb_address_map,
 771                                         addr >> TRB_SEGMENT_SHIFT);
 772                         xhci_ring_free(xhci, cur_ring);
 773                         stream_info->stream_rings[cur_stream] = NULL;
 774                 }
 775         }
 776         xhci_free_command(xhci, stream_info->free_streams_command);
 777         xhci->cmd_ring_reserved_trbs--;
 778         if (stream_info->stream_ctx_array)
 779                 xhci_free_stream_ctx(xhci,
 780                                 stream_info->num_stream_ctxs,
 781                                 stream_info->stream_ctx_array,
 782                                 stream_info->ctx_array_dma);
 783
 784         if (stream_info)
 785                 kfree(stream_info->stream_rings);
 786         kfree(stream_info);
 787 }
 788
 789
 790 /***************** Device context manipulation *************************/
 791
 792 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 793                 struct xhci_virt_ep *ep)
 794 {
 795         init_timer(&ep->stop_cmd_timer);
 796         ep->stop_cmd_timer.data = (unsigned long) ep;
 797         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 798         ep->xhci = xhci;
 799 }
 800
 801 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 802                 struct xhci_virt_device *virt_dev,
 803                 int slot_id)
 804 {
 805         struct list_head *tt_list_head;
 806         struct xhci_tt_bw_info *tt_info, *next;
 807         bool slot_found = false;
 808
 809         /* If the device never made it past the Set Address stage,
 810          * it may not have the real_port set correctly.
 811          */
 812         if (virt_dev->real_port == 0 ||
 813                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 814                 xhci_dbg(xhci, "Bad real port.\n");
 815                 return;
 816         }
 817
 818         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 819         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 820                 /* Multi-TT hubs will have more than one entry */
 821                 if (tt_info->slot_id == slot_id) {
 822                         slot_found = true;
 823                         list_del(&tt_info->tt_list);
 824                         kfree(tt_info);
 825                 } else if (slot_found) {
 826                         break;
 827                 }
 828         }
 829 }
 830
 831 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 832                 struct xhci_virt_device *virt_dev,
 833                 struct usb_device *hdev,
 834                 struct usb_tt *tt, gfp_t mem_flags)
 835 {
 836         struct xhci_tt_bw_info          *tt_info;
 837         unsigned int                    num_ports;
 838         int                             i, j;
 839
 840         if (!tt->multi)
 841                 num_ports = 1;
 842         else
 843                 num_ports = hdev->maxchild;
 844
 845         for (i = 0; i < num_ports; i++, tt_info++) {
 846                 struct xhci_interval_bw_table *bw_table;
 847
 848                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 849                 if (!tt_info)
 850                         goto free_tts;
 851                 INIT_LIST_HEAD(&tt_info->tt_list);
 852                 list_add(&tt_info->tt_list,
 853                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 854                 tt_info->slot_id = virt_dev->udev->slot_id;
 855                 if (tt->multi)
 856                         tt_info->ttport = i+1;
 857                 bw_table = &tt_info->bw_table;
 858                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 859                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 860         }
 861         return 0;
 862
 863 free_tts:
 864         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 865         return -ENOMEM;
 866 }
 867
 868
 869 /* All the xhci_tds in the ring's TD list should be freed at this point.
 870  * Should be called with xhci->lock held if there is any chance the TT lists
 871  * will be manipulated by the configure endpoint, allocate device, or update
 872  * hub functions while this function is removing the TT entries from the list.
 873  */
 874 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 875 {
 876         struct xhci_virt_device *dev;
 877         int i;
 878         int old_active_eps = 0;
 879
 880         /* Slot ID 0 is reserved */
 881         if (slot_id == 0 || !xhci->devs[slot_id])
 882                 return;
 883
 884         dev = xhci->devs[slot_id];
 885         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 886         if (!dev)
 887                 return;
 888
 889         if (dev->tt_info)
 890                 old_active_eps = dev->tt_info->active_eps;
 891
 892         for (i = 0; i < 31; ++i) {
 893                 if (dev->eps[i].ring)
 894                         xhci_ring_free(xhci, dev->eps[i].ring);
 895                 if (dev->eps[i].stream_info)
 896                         xhci_free_stream_info(xhci,
 897                                         dev->eps[i].stream_info);
 898                 /* Endpoints on the TT/root port lists should have been removed
 899                  * when usb_disable_device() was called for the device.
 900                  * We can't drop them anyway, because the udev might have gone
 901                  * away by this point, and we can't tell what speed it was.
 902                  */
 903                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 904                         xhci_warn(xhci, "Slot %u endpoint %u "
 905                                         "not removed from BW list!\n",
 906                                         slot_id, i);
 907         }
 908         /* If this is a hub, free the TT(s) from the TT list */
 909         xhci_free_tt_info(xhci, dev, slot_id);
 910         /* If necessary, update the number of active TTs on this root port */
 911         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 912
 913         if (dev->ring_cache) {
 914                 for (i = 0; i < dev->num_rings_cached; i++)
 915                         xhci_ring_free(xhci, dev->ring_cache[i]);
 916                 kfree(dev->ring_cache);
 917         }
 918
 919         if (dev->in_ctx)
 920                 xhci_free_container_ctx(xhci, dev->in_ctx);
 921         if (dev->out_ctx)
 922                 xhci_free_container_ctx(xhci, dev->out_ctx);
 923
 924         kfree(xhci->devs[slot_id]);
 925         xhci->devs[slot_id] = NULL;
 926 }
 927
 928 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 929                 struct usb_device *udev, gfp_t flags)
 930 {
 931         struct xhci_virt_device *dev;
 932         int i;
 933
 934         /* Slot ID 0 is reserved */
 935         if (slot_id == 0 || xhci->devs[slot_id]) {
 936                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 937                 return 0;
 938         }
 939
 940         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 941         if (!xhci->devs[slot_id])
 942                 return 0;
 943         dev = xhci->devs[slot_id];
 944
 945         /* Allocate the (output) device context that will be used in the HC. */
 946         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 947         if (!dev->out_ctx)
 948                 goto fail;
 949
 950         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 951                         (unsigned long long)dev->out_ctx->dma);
 952
 953         /* Allocate the (input) device context for address device command */
 954         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 955         if (!dev->in_ctx)
 956                 goto fail;
 957
 958         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 959                         (unsigned long long)dev->in_ctx->dma);
 960
 961         /* Initialize the cancellation list and watchdog timers for each ep */
 962         for (i = 0; i < 31; i++) {
 963                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 964                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 965                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 966         }
 967
 968         /* Allocate endpoint 0 ring */
 969         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
 970         if (!dev->eps[0].ring)
 971                 goto fail;
 972
 973         /* Allocate pointers to the ring cache */
 974         dev->ring_cache = kzalloc(
 975                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 976                         flags);
 977         if (!dev->ring_cache)
 978                 goto fail;
 979         dev->num_rings_cached = 0;
 980
 981         init_completion(&dev->cmd_completion);
 982         INIT_LIST_HEAD(&dev->cmd_list);
 983         dev->udev = udev;
 984
 985         /* Point to output device context in dcbaa. */
 986         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 987         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 988                  slot_id,
 989                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 990                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 991
 992         return 1;
 993 fail:
 994         xhci_free_virt_device(xhci, slot_id);
 995         return 0;
 996 }
 997
 998 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 999                 struct usb_device *udev)
1000 {
1001         struct xhci_virt_device *virt_dev;
1002         struct xhci_ep_ctx      *ep0_ctx;
1003         struct xhci_ring        *ep_ring;
1004
1005         virt_dev = xhci->devs[udev->slot_id];
1006         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1007         ep_ring = virt_dev->eps[0].ring;
1008         /*
1009          * FIXME we don't keep track of the dequeue pointer very well after a
1010          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1011          * host to our enqueue pointer.  This should only be called after a
1012          * configured device has reset, so all control transfers should have
1013          * been completed or cancelled before the reset.
1014          */
1015         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1016                                                         ep_ring->enqueue)
1017                                    | ep_ring->cycle_state);
1018 }
1019
1020 /*
1021  * The xHCI roothub may have ports of differing speeds in any order in the port
1022  * status registers.  xhci->port_array provides an array of the port speed for
1023  * each offset into the port status registers.
1024  *
1025  * The xHCI hardware wants to know the roothub port number that the USB device
1026  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1027  * know is the index of that port under either the USB 2.0 or the USB 3.0
1028  * roothub, but that doesn't give us the real index into the HW port status
1029  * registers. Call xhci_find_raw_port_number() to get real index.
1030  */
1031 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1032                 struct usb_device *udev)
1033 {
1034         struct usb_device *top_dev;
1035         struct usb_hcd *hcd;
1036
1037         if (udev->speed == USB_SPEED_SUPER)
1038                 hcd = xhci->shared_hcd;
1039         else
1040                 hcd = xhci->main_hcd;
1041
1042         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1043                         top_dev = top_dev->parent)
1044                 /* Found device below root hub */;
1045
1046         return  xhci_find_raw_port_number(hcd, top_dev->portnum);
1047 }
1048
1049 /* Setup an xHCI virtual device for a Set Address command */
1050 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1051 {
1052         struct xhci_virt_device *dev;
1053         struct xhci_ep_ctx      *ep0_ctx;
1054         struct xhci_slot_ctx    *slot_ctx;
1055         u32                     port_num;
1056         struct usb_device *top_dev;
1057
1058         dev = xhci->devs[udev->slot_id];
1059         /* Slot ID 0 is reserved */
1060         if (udev->slot_id == 0 || !dev) {
1061                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1062                                 udev->slot_id);
1063                 return -EINVAL;
1064         }
1065         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1066         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1067
1068         /* 3) Only the control endpoint is valid - one endpoint context */
1069         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1070         switch (udev->speed) {
1071         case USB_SPEED_SUPER:
1072                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1073                 break;
1074         case USB_SPEED_HIGH:
1075                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1076                 break;
1077         case USB_SPEED_FULL:
1078                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1079                 break;
1080         case USB_SPEED_LOW:
1081                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1082                 break;
1083         case USB_SPEED_WIRELESS:
1084                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1085                 return -EINVAL;
1086                 break;
1087         default:
1088                 /* Speed was set earlier, this shouldn't happen. */
1089                 BUG();
1090         }
1091         /* Find the root hub port this device is under */
1092         port_num = xhci_find_real_port_number(xhci, udev);
1093         if (!port_num)
1094                 return -EINVAL;
1095         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1096         /* Set the port number in the virtual_device to the faked port number */
1097         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1098                         top_dev = top_dev->parent)
1099                 /* Found device below root hub */;
1100         dev->fake_port = top_dev->portnum;
1101         dev->real_port = port_num;
1102         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1103         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1104
1105         /* Find the right bandwidth table that this device will be a part of.
1106          * If this is a full speed device attached directly to a root port (or a
1107          * decendent of one), it counts as a primary bandwidth domain, not a
1108          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1109          * will never be created for the HS root hub.
1110          */
1111         if (!udev->tt || !udev->tt->hub->parent) {
1112                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1113         } else {
1114                 struct xhci_root_port_bw_info *rh_bw;
1115                 struct xhci_tt_bw_info *tt_bw;
1116
1117                 rh_bw = &xhci->rh_bw[port_num - 1];
1118                 /* Find the right TT. */
1119                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1120                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1121                                 continue;
1122
1123                         if (!dev->udev->tt->multi ||
1124                                         (udev->tt->multi &&
1125                                          tt_bw->ttport == dev->udev->ttport)) {
1126                                 dev->bw_table = &tt_bw->bw_table;
1127                                 dev->tt_info = tt_bw;
1128                                 break;
1129                         }
1130                 }
1131                 if (!dev->tt_info)
1132                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1133         }
1134
1135         /* Is this a LS/FS device under an external HS hub? */
1136         if (udev->tt && udev->tt->hub->parent) {
1137                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1138                                                 (udev->ttport << 8));
1139                 if (udev->tt->multi)
1140                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1141         }
1142         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1143         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1144
1145         /* Step 4 - ring already allocated */
1146         /* Step 5 */
1147         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1148         /*
1149          * XXX: Not sure about wireless USB devices.
1150          */
1151         switch (udev->speed) {
1152         case USB_SPEED_SUPER:
1153                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1154                 break;
1155         case USB_SPEED_HIGH:
1156         /* USB core guesses at a 64-byte max packet first for FS devices */
1157         case USB_SPEED_FULL:
1158                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1159                 break;
1160         case USB_SPEED_LOW:
1161                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1162                 break;
1163         case USB_SPEED_WIRELESS:
1164                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1165                 return -EINVAL;
1166                 break;
1167         default:
1168                 /* New speed? */
1169                 BUG();
1170         }
1171         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1172         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1173
1174         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1175                                    dev->eps[0].ring->cycle_state);
1176
1177         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1178
1179         return 0;
1180 }
1181
1182 /*
1183  * Convert interval expressed as 2^(bInterval - 1) == interval into
1184  * straight exponent value 2^n == interval.
1185  *
1186  */
1187 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1188                 struct usb_host_endpoint *ep)
1189 {
1190         unsigned int interval;
1191
1192         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1193         if (interval != ep->desc.bInterval - 1)
1194                 dev_warn(&udev->dev,
1195                          "ep %#x - rounding interval to %d %sframes\n",
1196                          ep->desc.bEndpointAddress,
1197                          1 << interval,
1198                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1199
1200         if (udev->speed == USB_SPEED_FULL) {
1201                 /*
1202                  * Full speed isoc endpoints specify interval in frames,
1203                  * not microframes. We are using microframes everywhere,
1204                  * so adjust accordingly.
1205                  */
1206                 interval += 3;  /* 1 frame = 2^3 uframes */
1207         }
1208
1209         return interval;
1210 }
1211
1212 /*
1213  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1214  * microframes, rounded down to nearest power of 2.
1215  */
1216 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1217                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1218                 unsigned int min_exponent, unsigned int max_exponent)
1219 {
1220         unsigned int interval;
1221
1222         interval = fls(desc_interval) - 1;
1223         interval = clamp_val(interval, min_exponent, max_exponent);
1224         if ((1 << interval) != desc_interval)
1225                 dev_warn(&udev->dev,
1226                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1227                          ep->desc.bEndpointAddress,
1228                          1 << interval,
1229                          desc_interval);
1230
1231         return interval;
1232 }
1233
1234 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1235                 struct usb_host_endpoint *ep)
1236 {
1237         if (ep->desc.bInterval == 0)
1238                 return 0;
1239         return xhci_microframes_to_exponent(udev, ep,
1240                         ep->desc.bInterval, 0, 15);
1241 }
1242
1243
1244 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1245                 struct usb_host_endpoint *ep)
1246 {
1247         return xhci_microframes_to_exponent(udev, ep,
1248                         ep->desc.bInterval * 8, 3, 10);
1249 }
1250
1251 /* Return the polling or NAK interval.
1252  *
1253  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1254  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1255  *
1256  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1257  * is set to 0.
1258  */
1259 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1260                 struct usb_host_endpoint *ep)
1261 {
1262         unsigned int interval = 0;
1263
1264         switch (udev->speed) {
1265         case USB_SPEED_HIGH:
1266                 /* Max NAK rate */
1267                 if (usb_endpoint_xfer_control(&ep->desc) ||
1268                     usb_endpoint_xfer_bulk(&ep->desc)) {
1269                         interval = xhci_parse_microframe_interval(udev, ep);
1270                         break;
1271                 }
1272                 /* Fall through - SS and HS isoc/int have same decoding */
1273
1274         case USB_SPEED_SUPER:
1275                 if (usb_endpoint_xfer_int(&ep->desc) ||
1276                     usb_endpoint_xfer_isoc(&ep->desc)) {
1277                         interval = xhci_parse_exponent_interval(udev, ep);
1278                 }
1279                 break;
1280
1281         case USB_SPEED_FULL:
1282                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1283                         interval = xhci_parse_exponent_interval(udev, ep);
1284                         break;
1285                 }
1286                 /*
1287                  * Fall through for interrupt endpoint interval decoding
1288                  * since it uses the same rules as low speed interrupt
1289                  * endpoints.
1290                  */
1291
1292         case USB_SPEED_LOW:
1293                 if (usb_endpoint_xfer_int(&ep->desc) ||
1294                     usb_endpoint_xfer_isoc(&ep->desc)) {
1295
1296                         interval = xhci_parse_frame_interval(udev, ep);
1297                 }
1298                 break;
1299
1300         default:
1301                 BUG();
1302         }
1303         return EP_INTERVAL(interval);
1304 }
1305
1306 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1307  * High speed endpoint descriptors can define "the number of additional
1308  * transaction opportunities per microframe", but that goes in the Max Burst
1309  * endpoint context field.
1310  */
1311 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1312                 struct usb_host_endpoint *ep)
1313 {
1314         if (udev->speed != USB_SPEED_SUPER ||
1315                         !usb_endpoint_xfer_isoc(&ep->desc))
1316                 return 0;
1317         return ep->ss_ep_comp.bmAttributes;
1318 }
1319
1320 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1321                 struct usb_host_endpoint *ep)
1322 {
1323         int in;
1324         u32 type;
1325
1326         in = usb_endpoint_dir_in(&ep->desc);
1327         if (usb_endpoint_xfer_control(&ep->desc)) {
1328                 type = EP_TYPE(CTRL_EP);
1329         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1330                 if (in)
1331                         type = EP_TYPE(BULK_IN_EP);
1332                 else
1333                         type = EP_TYPE(BULK_OUT_EP);
1334         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1335                 if (in)
1336                         type = EP_TYPE(ISOC_IN_EP);
1337                 else
1338                         type = EP_TYPE(ISOC_OUT_EP);
1339         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1340                 if (in)
1341                         type = EP_TYPE(INT_IN_EP);
1342                 else
1343                         type = EP_TYPE(INT_OUT_EP);
1344         } else {
1345                 BUG();
1346         }
1347         return type;
1348 }
1349
1350 /* Return the maximum endpoint service interval time (ESIT) payload.
1351  * Basically, this is the maxpacket size, multiplied by the burst size
1352  * and mult size.
1353  */
1354 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1355                 struct usb_device *udev,
1356                 struct usb_host_endpoint *ep)
1357 {
1358         int max_burst;
1359         int max_packet;
1360
1361         /* Only applies for interrupt or isochronous endpoints */
1362         if (usb_endpoint_xfer_control(&ep->desc) ||
1363                         usb_endpoint_xfer_bulk(&ep->desc))
1364                 return 0;
1365
1366         if (udev->speed == USB_SPEED_SUPER)
1367                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1368
1369         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1370         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1371         /* A 0 in max burst means 1 transfer per ESIT */
1372         return max_packet * (max_burst + 1);
1373 }
1374
1375 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1376  * Drivers will have to call usb_alloc_streams() to do that.
1377  */
1378 int xhci_endpoint_init(struct xhci_hcd *xhci,
1379                 struct xhci_virt_device *virt_dev,
1380                 struct usb_device *udev,
1381                 struct usb_host_endpoint *ep,
1382                 gfp_t mem_flags)
1383 {
1384         unsigned int ep_index;
1385         struct xhci_ep_ctx *ep_ctx;
1386         struct xhci_ring *ep_ring;
1387         unsigned int max_packet;
1388         unsigned int max_burst;
1389         enum xhci_ring_type type;
1390         u32 max_esit_payload;
1391
1392         ep_index = xhci_get_endpoint_index(&ep->desc);
1393         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1394
1395         type = usb_endpoint_type(&ep->desc);
1396         /* Set up the endpoint ring */
1397         virt_dev->eps[ep_index].new_ring =
1398                 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1399         if (!virt_dev->eps[ep_index].new_ring) {
1400                 /* Attempt to use the ring cache */
1401                 if (virt_dev->num_rings_cached == 0)
1402                         return -ENOMEM;
1403                 virt_dev->eps[ep_index].new_ring =
1404                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1405                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1406                 virt_dev->num_rings_cached--;
1407                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1408                                         1, type);
1409         }
1410         virt_dev->eps[ep_index].skip = false;
1411         ep_ring = virt_dev->eps[ep_index].new_ring;
1412         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1413
1414         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1415                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1416
1417         /* FIXME dig Mult and streams info out of ep companion desc */
1418
1419         /* Allow 3 retries for everything but isoc;
1420          * CErr shall be set to 0 for Isoch endpoints.
1421          */
1422         if (!usb_endpoint_xfer_isoc(&ep->desc))
1423                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1424         else
1425                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1426
1427         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1428
1429         /* Set the max packet size and max burst */
1430         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1431         max_burst = 0;
1432         switch (udev->speed) {
1433         case USB_SPEED_SUPER:
1434                 /* dig out max burst from ep companion desc */
1435                 max_burst = ep->ss_ep_comp.bMaxBurst;
1436                 break;
1437         case USB_SPEED_HIGH:
1438                 /* Some devices get this wrong */
1439                 if (usb_endpoint_xfer_bulk(&ep->desc))
1440                         max_packet = 512;
1441                 /* bits 11:12 specify the number of additional transaction
1442                  * opportunities per microframe (USB 2.0, section 9.6.6)
1443                  */
1444                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1445                                 usb_endpoint_xfer_int(&ep->desc)) {
1446                         max_burst = (usb_endpoint_maxp(&ep->desc)
1447                                      & 0x1800) >> 11;
1448                 }
1449                 break;
1450         case USB_SPEED_FULL:
1451         case USB_SPEED_LOW:
1452                 break;
1453         default:
1454                 BUG();
1455         }
1456         ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
1457                         MAX_BURST(max_burst));
1458         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1459         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1460
1461         /*
1462          * XXX no idea how to calculate the average TRB buffer length for bulk
1463          * endpoints, as the driver gives us no clue how big each scatter gather
1464          * list entry (or buffer) is going to be.
1465          *
1466          * For isochronous and interrupt endpoints, we set it to the max
1467          * available, until we have new API in the USB core to allow drivers to
1468          * declare how much bandwidth they actually need.
1469          *
1470          * Normally, it would be calculated by taking the total of the buffer
1471          * lengths in the TD and then dividing by the number of TRBs in a TD,
1472          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1473          * use Event Data TRBs, and we don't chain in a link TRB on short
1474          * transfers, we're basically dividing by 1.
1475          *
1476          * xHCI 1.0 specification indicates that the Average TRB Length should
1477          * be set to 8 for control endpoints.
1478          */
1479         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1480                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1481         else
1482                 ep_ctx->tx_info |=
1483                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1484
1485         /* FIXME Debug endpoint context */
1486         return 0;
1487 }
1488
1489 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1490                 struct xhci_virt_device *virt_dev,
1491                 struct usb_host_endpoint *ep)
1492 {
1493         unsigned int ep_index;
1494         struct xhci_ep_ctx *ep_ctx;
1495
1496         ep_index = xhci_get_endpoint_index(&ep->desc);
1497         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1498
1499         ep_ctx->ep_info = 0;
1500         ep_ctx->ep_info2 = 0;
1501         ep_ctx->deq = 0;
1502         ep_ctx->tx_info = 0;
1503         /* Don't free the endpoint ring until the set interface or configuration
1504          * request succeeds.
1505          */
1506 }
1507
1508 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1509 {
1510         bw_info->ep_interval = 0;
1511         bw_info->mult = 0;
1512         bw_info->num_packets = 0;
1513         bw_info->max_packet_size = 0;
1514         bw_info->type = 0;
1515         bw_info->max_esit_payload = 0;
1516 }
1517
1518 void xhci_update_bw_info(struct xhci_hcd *xhci,
1519                 struct xhci_container_ctx *in_ctx,
1520                 struct xhci_input_control_ctx *ctrl_ctx,
1521                 struct xhci_virt_device *virt_dev)
1522 {
1523         struct xhci_bw_info *bw_info;
1524         struct xhci_ep_ctx *ep_ctx;
1525         unsigned int ep_type;
1526         int i;
1527
1528         for (i = 1; i < 31; ++i) {
1529                 bw_info = &virt_dev->eps[i].bw_info;
1530
1531                 /* We can't tell what endpoint type is being dropped, but
1532                  * unconditionally clearing the bandwidth info for non-periodic
1533                  * endpoints should be harmless because the info will never be
1534                  * set in the first place.
1535                  */
1536                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1537                         /* Dropped endpoint */
1538                         xhci_clear_endpoint_bw_info(bw_info);
1539                         continue;
1540                 }
1541
1542                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1543                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1544                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1545
1546                         /* Ignore non-periodic endpoints */
1547                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1548                                         ep_type != ISOC_IN_EP &&
1549                                         ep_type != INT_IN_EP)
1550                                 continue;
1551
1552                         /* Added or changed endpoint */
1553                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1554                                         le32_to_cpu(ep_ctx->ep_info));
1555                         /* Number of packets and mult are zero-based in the
1556                          * input context, but we want one-based for the
1557                          * interval table.
1558                          */
1559                         bw_info->mult = CTX_TO_EP_MULT(
1560                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1561                         bw_info->num_packets = CTX_TO_MAX_BURST(
1562                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1563                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1564                                         le32_to_cpu(ep_ctx->ep_info2));
1565                         bw_info->type = ep_type;
1566                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1567                                         le32_to_cpu(ep_ctx->tx_info));
1568                 }
1569         }
1570 }
1571
1572 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1573  * Useful when you want to change one particular aspect of the endpoint and then
1574  * issue a configure endpoint command.
1575  */
1576 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1577                 struct xhci_container_ctx *in_ctx,
1578                 struct xhci_container_ctx *out_ctx,
1579                 unsigned int ep_index)
1580 {
1581         struct xhci_ep_ctx *out_ep_ctx;
1582         struct xhci_ep_ctx *in_ep_ctx;
1583
1584         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1585         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1586
1587         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1588         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1589         in_ep_ctx->deq = out_ep_ctx->deq;
1590         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1591 }
1592
1593 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1594  * Useful when you want to change one particular aspect of the endpoint and then
1595  * issue a configure endpoint command.  Only the context entries field matters,
1596  * but we'll copy the whole thing anyway.
1597  */
1598 void xhci_slot_copy(struct xhci_hcd *xhci,
1599                 struct xhci_container_ctx *in_ctx,
1600                 struct xhci_container_ctx *out_ctx)
1601 {
1602         struct xhci_slot_ctx *in_slot_ctx;
1603         struct xhci_slot_ctx *out_slot_ctx;
1604
1605         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1606         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1607
1608         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1609         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1610         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1611         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1612 }
1613
1614 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1615 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1616 {
1617         int i;
1618         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1619         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1620
1621         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1622
1623         if (!num_sp)
1624                 return 0;
1625
1626         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1627         if (!xhci->scratchpad)
1628                 goto fail_sp;
1629
1630         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1631                                      num_sp * sizeof(u64),
1632                                      &xhci->scratchpad->sp_dma, flags);
1633         if (!xhci->scratchpad->sp_array)
1634                 goto fail_sp2;
1635
1636         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1637         if (!xhci->scratchpad->sp_buffers)
1638                 goto fail_sp3;
1639
1640         xhci->scratchpad->sp_dma_buffers =
1641                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1642
1643         if (!xhci->scratchpad->sp_dma_buffers)
1644                 goto fail_sp4;
1645
1646         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1647         for (i = 0; i < num_sp; i++) {
1648                 dma_addr_t dma;
1649                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1650                                 flags);
1651                 if (!buf)
1652                         goto fail_sp5;
1653
1654                 xhci->scratchpad->sp_array[i] = dma;
1655                 xhci->scratchpad->sp_buffers[i] = buf;
1656                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1657         }
1658
1659         return 0;
1660
1661  fail_sp5:
1662         for (i = i - 1; i >= 0; i--) {
1663                 dma_free_coherent(dev, xhci->page_size,
1664                                     xhci->scratchpad->sp_buffers[i],
1665                                     xhci->scratchpad->sp_dma_buffers[i]);
1666         }
1667         kfree(xhci->scratchpad->sp_dma_buffers);
1668
1669  fail_sp4:
1670         kfree(xhci->scratchpad->sp_buffers);
1671
1672  fail_sp3:
1673         dma_free_coherent(dev, num_sp * sizeof(u64),
1674                             xhci->scratchpad->sp_array,
1675                             xhci->scratchpad->sp_dma);
1676
1677  fail_sp2:
1678         kfree(xhci->scratchpad);
1679         xhci->scratchpad = NULL;
1680
1681  fail_sp:
1682         return -ENOMEM;
1683 }
1684
1685 static void scratchpad_free(struct xhci_hcd *xhci)
1686 {
1687         int num_sp;
1688         int i;
1689         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1690
1691         if (!xhci->scratchpad)
1692                 return;
1693
1694         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1695
1696         for (i = 0; i < num_sp; i++) {
1697                 dma_free_coherent(&pdev->dev, xhci->page_size,
1698                                     xhci->scratchpad->sp_buffers[i],
1699                                     xhci->scratchpad->sp_dma_buffers[i]);
1700         }
1701         kfree(xhci->scratchpad->sp_dma_buffers);
1702         kfree(xhci->scratchpad->sp_buffers);
1703         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1704                             xhci->scratchpad->sp_array,
1705                             xhci->scratchpad->sp_dma);
1706         kfree(xhci->scratchpad);
1707         xhci->scratchpad = NULL;
1708 }
1709
1710 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1711                 bool allocate_in_ctx, bool allocate_completion,
1712                 gfp_t mem_flags)
1713 {
1714         struct xhci_command *command;
1715
1716         command = kzalloc(sizeof(*command), mem_flags);
1717         if (!command)
1718                 return NULL;
1719
1720         if (allocate_in_ctx) {
1721                 command->in_ctx =
1722                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1723                                         mem_flags);
1724                 if (!command->in_ctx) {
1725                         kfree(command);
1726                         return NULL;
1727                 }
1728         }
1729
1730         if (allocate_completion) {
1731                 command->completion =
1732                         kzalloc(sizeof(struct completion), mem_flags);
1733                 if (!command->completion) {
1734                         xhci_free_container_ctx(xhci, command->in_ctx);
1735                         kfree(command);
1736                         return NULL;
1737                 }
1738                 init_completion(command->completion);
1739         }
1740
1741         command->status = 0;
1742         INIT_LIST_HEAD(&command->cmd_list);
1743         return command;
1744 }
1745
1746 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1747 {
1748         if (urb_priv) {
1749                 kfree(urb_priv->td[0]);
1750                 kfree(urb_priv);
1751         }
1752 }
1753
1754 void xhci_free_command(struct xhci_hcd *xhci,
1755                 struct xhci_command *command)
1756 {
1757         xhci_free_container_ctx(xhci,
1758                         command->in_ctx);
1759         kfree(command->completion);
1760         kfree(command);
1761 }
1762
1763 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1764 {
1765         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1766         struct dev_info *dev_info, *next;
1767         struct xhci_cd  *cur_cd, *next_cd;
1768         unsigned long   flags;
1769         int size;
1770         int i, j, num_ports;
1771
1772         /* Free the Event Ring Segment Table and the actual Event Ring */
1773         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1774         if (xhci->erst.entries)
1775                 dma_free_coherent(&pdev->dev, size,
1776                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1777         xhci->erst.entries = NULL;
1778         xhci_dbg(xhci, "Freed ERST\n");
1779         if (xhci->event_ring)
1780                 xhci_ring_free(xhci, xhci->event_ring);
1781         xhci->event_ring = NULL;
1782         xhci_dbg(xhci, "Freed event ring\n");
1783
1784         if (xhci->lpm_command)
1785                 xhci_free_command(xhci, xhci->lpm_command);
1786         xhci->cmd_ring_reserved_trbs = 0;
1787         if (xhci->cmd_ring)
1788                 xhci_ring_free(xhci, xhci->cmd_ring);
1789         xhci->cmd_ring = NULL;
1790         xhci_dbg(xhci, "Freed command ring\n");
1791         list_for_each_entry_safe(cur_cd, next_cd,
1792                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1793                 list_del(&cur_cd->cancel_cmd_list);
1794                 kfree(cur_cd);
1795         }
1796
1797         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1798         for (i = 0; i < num_ports; i++) {
1799                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1800                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1801                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1802                         while (!list_empty(ep))
1803                                 list_del_init(ep->next);
1804                 }
1805         }
1806
1807         for (i = 1; i < MAX_HC_SLOTS; ++i)
1808                 xhci_free_virt_device(xhci, i);
1809
1810         if (xhci->segment_pool)
1811                 dma_pool_destroy(xhci->segment_pool);
1812         xhci->segment_pool = NULL;
1813         xhci_dbg(xhci, "Freed segment pool\n");
1814
1815         if (xhci->device_pool)
1816                 dma_pool_destroy(xhci->device_pool);
1817         xhci->device_pool = NULL;
1818         xhci_dbg(xhci, "Freed device context pool\n");
1819
1820         if (xhci->small_streams_pool)
1821                 dma_pool_destroy(xhci->small_streams_pool);
1822         xhci->small_streams_pool = NULL;
1823         xhci_dbg(xhci, "Freed small stream array pool\n");
1824
1825         if (xhci->medium_streams_pool)
1826                 dma_pool_destroy(xhci->medium_streams_pool);
1827         xhci->medium_streams_pool = NULL;
1828         xhci_dbg(xhci, "Freed medium stream array pool\n");
1829
1830         if (xhci->dcbaa)
1831                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1832                                 xhci->dcbaa, xhci->dcbaa->dma);
1833         xhci->dcbaa = NULL;
1834
1835         scratchpad_free(xhci);
1836
1837         spin_lock_irqsave(&xhci->lock, flags);
1838         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1839                 list_del(&dev_info->list);
1840                 kfree(dev_info);
1841         }
1842         spin_unlock_irqrestore(&xhci->lock, flags);
1843
1844         if (!xhci->rh_bw)
1845                 goto no_bw;
1846
1847         for (i = 0; i < num_ports; i++) {
1848                 struct xhci_tt_bw_info *tt, *n;
1849                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1850                         list_del(&tt->tt_list);
1851                         kfree(tt);
1852                 }
1853         }
1854
1855 no_bw:
1856         xhci->num_usb2_ports = 0;
1857         xhci->num_usb3_ports = 0;
1858         xhci->num_active_eps = 0;
1859         kfree(xhci->usb2_ports);
1860         kfree(xhci->usb3_ports);
1861         kfree(xhci->port_array);
1862         kfree(xhci->rh_bw);
1863
1864         xhci->page_size = 0;
1865         xhci->page_shift = 0;
1866         xhci->bus_state[0].bus_suspended = 0;
1867         xhci->bus_state[1].bus_suspended = 0;
1868 }
1869
1870 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1871                 struct xhci_segment *input_seg,
1872                 union xhci_trb *start_trb,
1873                 union xhci_trb *end_trb,
1874                 dma_addr_t input_dma,
1875                 struct xhci_segment *result_seg,
1876                 char *test_name, int test_number)
1877 {
1878         unsigned long long start_dma;
1879         unsigned long long end_dma;
1880         struct xhci_segment *seg;
1881
1882         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1883         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1884
1885         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1886         if (seg != result_seg) {
1887                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1888                                 test_name, test_number);
1889                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1890                                 "input DMA 0x%llx\n",
1891                                 input_seg,
1892                                 (unsigned long long) input_dma);
1893                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1894                                 "ending TRB %p (0x%llx DMA)\n",
1895                                 start_trb, start_dma,
1896                                 end_trb, end_dma);
1897                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1898                                 result_seg, seg);
1899                 return -1;
1900         }
1901         return 0;
1902 }
1903
1904 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1905 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1906 {
1907         struct {
1908                 dma_addr_t              input_dma;
1909                 struct xhci_segment     *result_seg;
1910         } simple_test_vector [] = {
1911                 /* A zeroed DMA field should fail */
1912                 { 0, NULL },
1913                 /* One TRB before the ring start should fail */
1914                 { xhci->event_ring->first_seg->dma - 16, NULL },
1915                 /* One byte before the ring start should fail */
1916                 { xhci->event_ring->first_seg->dma - 1, NULL },
1917                 /* Starting TRB should succeed */
1918                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1919                 /* Ending TRB should succeed */
1920                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1921                         xhci->event_ring->first_seg },
1922                 /* One byte after the ring end should fail */
1923                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1924                 /* One TRB after the ring end should fail */
1925                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1926                 /* An address of all ones should fail */
1927                 { (dma_addr_t) (~0), NULL },
1928         };
1929         struct {
1930                 struct xhci_segment     *input_seg;
1931                 union xhci_trb          *start_trb;
1932                 union xhci_trb          *end_trb;
1933                 dma_addr_t              input_dma;
1934                 struct xhci_segment     *result_seg;
1935         } complex_test_vector [] = {
1936                 /* Test feeding a valid DMA address from a different ring */
1937                 {       .input_seg = xhci->event_ring->first_seg,
1938                         .start_trb = xhci->event_ring->first_seg->trbs,
1939                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1940                         .input_dma = xhci->cmd_ring->first_seg->dma,
1941                         .result_seg = NULL,
1942                 },
1943                 /* Test feeding a valid end TRB from a different ring */
1944                 {       .input_seg = xhci->event_ring->first_seg,
1945                         .start_trb = xhci->event_ring->first_seg->trbs,
1946                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1947                         .input_dma = xhci->cmd_ring->first_seg->dma,
1948                         .result_seg = NULL,
1949                 },
1950                 /* Test feeding a valid start and end TRB from a different ring */
1951                 {       .input_seg = xhci->event_ring->first_seg,
1952                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1953                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1954                         .input_dma = xhci->cmd_ring->first_seg->dma,
1955                         .result_seg = NULL,
1956                 },
1957                 /* TRB in this ring, but after this TD */
1958                 {       .input_seg = xhci->event_ring->first_seg,
1959                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1960                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1961                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1962                         .result_seg = NULL,
1963                 },
1964                 /* TRB in this ring, but before this TD */
1965                 {       .input_seg = xhci->event_ring->first_seg,
1966                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1967                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1968                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1969                         .result_seg = NULL,
1970                 },
1971                 /* TRB in this ring, but after this wrapped TD */
1972                 {       .input_seg = xhci->event_ring->first_seg,
1973                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1974                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1975                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1976                         .result_seg = NULL,
1977                 },
1978                 /* TRB in this ring, but before this wrapped TD */
1979                 {       .input_seg = xhci->event_ring->first_seg,
1980                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1981                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1982                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1983                         .result_seg = NULL,
1984                 },
1985                 /* TRB not in this ring, and we have a wrapped TD */
1986                 {       .input_seg = xhci->event_ring->first_seg,
1987                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1988                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1989                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1990                         .result_seg = NULL,
1991                 },
1992         };
1993
1994         unsigned int num_tests;
1995         int i, ret;
1996
1997         num_tests = ARRAY_SIZE(simple_test_vector);
1998         for (i = 0; i < num_tests; i++) {
1999                 ret = xhci_test_trb_in_td(xhci,
2000                                 xhci->event_ring->first_seg,
2001                                 xhci->event_ring->first_seg->trbs,
2002                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2003                                 simple_test_vector[i].input_dma,
2004                                 simple_test_vector[i].result_seg,
2005                                 "Simple", i);
2006                 if (ret < 0)
2007                         return ret;
2008         }
2009
2010         num_tests = ARRAY_SIZE(complex_test_vector);
2011         for (i = 0; i < num_tests; i++) {
2012                 ret = xhci_test_trb_in_td(xhci,
2013                                 complex_test_vector[i].input_seg,
2014                                 complex_test_vector[i].start_trb,
2015                                 complex_test_vector[i].end_trb,
2016                                 complex_test_vector[i].input_dma,
2017                                 complex_test_vector[i].result_seg,
2018                                 "Complex", i);
2019                 if (ret < 0)
2020                         return ret;
2021         }
2022         xhci_dbg(xhci, "TRB math tests passed.\n");
2023         return 0;
2024 }
2025
2026 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2027 {
2028         u64 temp;
2029         dma_addr_t deq;
2030
2031         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2032                         xhci->event_ring->dequeue);
2033         if (deq == 0 && !in_interrupt())
2034                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2035                                 "dequeue ptr.\n");
2036         /* Update HC event ring dequeue pointer */
2037         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2038         temp &= ERST_PTR_MASK;
2039         /* Don't clear the EHB bit (which is RW1C) because
2040          * there might be more events to service.
2041          */
2042         temp &= ~ERST_EHB;
2043         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2044                         "preserving EHB bit\n");
2045         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2046                         &xhci->ir_set->erst_dequeue);
2047 }
2048
2049 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2050                 __le32 __iomem *addr, u8 major_revision)
2051 {
2052         u32 temp, port_offset, port_count;
2053         int i;
2054
2055         if (major_revision > 0x03) {
2056                 xhci_warn(xhci, "Ignoring unknown port speed, "
2057                                 "Ext Cap %p, revision = 0x%x\n",
2058                                 addr, major_revision);
2059                 /* Ignoring port protocol we can't understand. FIXME */
2060                 return;
2061         }
2062
2063         /* Port offset and count in the third dword, see section 7.2 */
2064         temp = xhci_readl(xhci, addr + 2);
2065         port_offset = XHCI_EXT_PORT_OFF(temp);
2066         port_count = XHCI_EXT_PORT_COUNT(temp);
2067         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2068                         "count = %u, revision = 0x%x\n",
2069                         addr, port_offset, port_count, major_revision);
2070         /* Port count includes the current port offset */
2071         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2072                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2073                 return;
2074
2075         /* Check the host's USB2 LPM capability */
2076         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2077                         (temp & XHCI_L1C)) {
2078                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2079                 xhci->sw_lpm_support = 1;
2080         }
2081
2082         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2083                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2084                 xhci->sw_lpm_support = 1;
2085                 if (temp & XHCI_HLC) {
2086                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2087                         xhci->hw_lpm_support = 1;
2088                 }
2089         }
2090
2091         port_offset--;
2092         for (i = port_offset; i < (port_offset + port_count); i++) {
2093                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2094                 if (xhci->port_array[i] != 0) {
2095                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2096                                         " port %u\n", addr, i);
2097                         xhci_warn(xhci, "Port was marked as USB %u, "
2098                                         "duplicated as USB %u\n",
2099                                         xhci->port_array[i], major_revision);
2100                         /* Only adjust the roothub port counts if we haven't
2101                          * found a similar duplicate.
2102                          */
2103                         if (xhci->port_array[i] != major_revision &&
2104                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2105                                 if (xhci->port_array[i] == 0x03)
2106                                         xhci->num_usb3_ports--;
2107                                 else
2108                                         xhci->num_usb2_ports--;
2109                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2110                         }
2111                         /* FIXME: Should we disable the port? */
2112                         continue;
2113                 }
2114                 xhci->port_array[i] = major_revision;
2115                 if (major_revision == 0x03)
2116                         xhci->num_usb3_ports++;
2117                 else
2118                         xhci->num_usb2_ports++;
2119         }
2120         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2121 }
2122
2123 /*
2124  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2125  * specify what speeds each port is supposed to be.  We can't count on the port
2126  * speed bits in the PORTSC register being correct until a device is connected,
2127  * but we need to set up the two fake roothubs with the correct number of USB
2128  * 3.0 and USB 2.0 ports at host controller initialization time.
2129  */
2130 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2131 {
2132         __le32 __iomem *addr;
2133         u32 offset;
2134         unsigned int num_ports;
2135         int i, j, port_index;
2136
2137         addr = &xhci->cap_regs->hcc_params;
2138         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2139         if (offset == 0) {
2140                 xhci_err(xhci, "No Extended Capability registers, "
2141                                 "unable to set up roothub.\n");
2142                 return -ENODEV;
2143         }
2144
2145         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2146         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2147         if (!xhci->port_array)
2148                 return -ENOMEM;
2149
2150         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2151         if (!xhci->rh_bw)
2152                 return -ENOMEM;
2153         for (i = 0; i < num_ports; i++) {
2154                 struct xhci_interval_bw_table *bw_table;
2155
2156                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2157                 bw_table = &xhci->rh_bw[i].bw_table;
2158                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2159                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2160         }
2161
2162         /*
2163          * For whatever reason, the first capability offset is from the
2164          * capability register base, not from the HCCPARAMS register.
2165          * See section 5.3.6 for offset calculation.
2166          */
2167         addr = &xhci->cap_regs->hc_capbase + offset;
2168         while (1) {
2169                 u32 cap_id;
2170
2171                 cap_id = xhci_readl(xhci, addr);
2172                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2173                         xhci_add_in_port(xhci, num_ports, addr,
2174                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2175                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2176                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2177                                 == num_ports)
2178                         break;
2179                 /*
2180                  * Once you're into the Extended Capabilities, the offset is
2181                  * always relative to the register holding the offset.
2182                  */
2183                 addr += offset;
2184         }
2185
2186         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2187                 xhci_warn(xhci, "No ports on the roothubs?\n");
2188                 return -ENODEV;
2189         }
2190         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2191                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2192
2193         /* Place limits on the number of roothub ports so that the hub
2194          * descriptors aren't longer than the USB core will allocate.
2195          */
2196         if (xhci->num_usb3_ports > 15) {
2197                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2198                 xhci->num_usb3_ports = 15;
2199         }
2200         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2201                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2202                                 USB_MAXCHILDREN);
2203                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2204         }
2205
2206         /*
2207          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2208          * Not sure how the USB core will handle a hub with no ports...
2209          */
2210         if (xhci->num_usb2_ports) {
2211                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2212                                 xhci->num_usb2_ports, flags);
2213                 if (!xhci->usb2_ports)
2214                         return -ENOMEM;
2215
2216                 port_index = 0;
2217                 for (i = 0; i < num_ports; i++) {
2218                         if (xhci->port_array[i] == 0x03 ||
2219                                         xhci->port_array[i] == 0 ||
2220                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2221                                 continue;
2222
2223                         xhci->usb2_ports[port_index] =
2224                                 &xhci->op_regs->port_status_base +
2225                                 NUM_PORT_REGS*i;
2226                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2227                                         "addr = %p\n", i,
2228                                         xhci->usb2_ports[port_index]);
2229                         port_index++;
2230                         if (port_index == xhci->num_usb2_ports)
2231                                 break;
2232                 }
2233         }
2234         if (xhci->num_usb3_ports) {
2235                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2236                                 xhci->num_usb3_ports, flags);
2237                 if (!xhci->usb3_ports)
2238                         return -ENOMEM;
2239
2240                 port_index = 0;
2241                 for (i = 0; i < num_ports; i++)
2242                         if (xhci->port_array[i] == 0x03) {
2243                                 xhci->usb3_ports[port_index] =
2244                                         &xhci->op_regs->port_status_base +
2245                                         NUM_PORT_REGS*i;
2246                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2247                                                 "addr = %p\n", i,
2248                                                 xhci->usb3_ports[port_index]);
2249                                 port_index++;
2250                                 if (port_index == xhci->num_usb3_ports)
2251                                         break;
2252                         }
2253         }
2254         return 0;
2255 }
2256
2257 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2258 {
2259         dma_addr_t      dma;
2260         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2261         unsigned int    val, val2;
2262         u64             val_64;
2263         struct xhci_segment     *seg;
2264         u32 page_size, temp;
2265         int i;
2266
2267         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2268         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2269
2270         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2271         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2272         for (i = 0; i < 16; i++) {
2273                 if ((0x1 & page_size) != 0)
2274                         break;
2275                 page_size = page_size >> 1;
2276         }
2277         if (i < 16)
2278                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2279         else
2280                 xhci_warn(xhci, "WARN: no supported page size\n");
2281         /* Use 4K pages, since that's common and the minimum the HC supports */
2282         xhci->page_shift = 12;
2283         xhci->page_size = 1 << xhci->page_shift;
2284         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2285
2286         /*
2287          * Program the Number of Device Slots Enabled field in the CONFIG
2288          * register with the max value of slots the HC can handle.
2289          */
2290         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2291         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2292                         (unsigned int) val);
2293         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2294         val |= (val2 & ~HCS_SLOTS_MASK);
2295         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2296                         (unsigned int) val);
2297         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2298
2299         /*
2300          * Section 5.4.8 - doorbell array must be
2301          * "physically contiguous and 64-byte (cache line) aligned".
2302          */
2303         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2304                         GFP_KERNEL);
2305         if (!xhci->dcbaa)
2306                 goto fail;
2307         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2308         xhci->dcbaa->dma = dma;
2309         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2310                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2311         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2312
2313         /*
2314          * Initialize the ring segment pool.  The ring must be a contiguous
2315          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2316          * however, the command ring segment needs 64-byte aligned segments,
2317          * so we pick the greater alignment need.
2318          */
2319         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2320                         TRB_SEGMENT_SIZE, 64, xhci->page_size);
2321
2322         /* See Table 46 and Note on Figure 55 */
2323         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2324                         2112, 64, xhci->page_size);
2325         if (!xhci->segment_pool || !xhci->device_pool)
2326                 goto fail;
2327
2328         /* Linear stream context arrays don't have any boundary restrictions,
2329          * and only need to be 16-byte aligned.
2330          */
2331         xhci->small_streams_pool =
2332                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2333                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2334         xhci->medium_streams_pool =
2335                 dma_pool_create("xHCI 1KB stream ctx arrays",
2336                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2337         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2338          * will be allocated with dma_alloc_coherent()
2339          */
2340
2341         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2342                 goto fail;
2343
2344         /* Set up the command ring to have one segments for now. */
2345         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2346         if (!xhci->cmd_ring)
2347                 goto fail;
2348         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2349         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2350                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2351
2352         /* Set the address in the Command Ring Control register */
2353         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2354         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2355                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2356                 xhci->cmd_ring->cycle_state;
2357         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2358         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2359         xhci_dbg_cmd_ptrs(xhci);
2360
2361         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2362         if (!xhci->lpm_command)
2363                 goto fail;
2364
2365         /* Reserve one command ring TRB for disabling LPM.
2366          * Since the USB core grabs the shared usb_bus bandwidth mutex before
2367          * disabling LPM, we only need to reserve one TRB for all devices.
2368          */
2369         xhci->cmd_ring_reserved_trbs++;
2370
2371         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2372         val &= DBOFF_MASK;
2373         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2374                         " from cap regs base addr\n", val);
2375         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2376         xhci_dbg_regs(xhci);
2377         xhci_print_run_regs(xhci);
2378         /* Set ir_set to interrupt register set 0 */
2379         xhci->ir_set = &xhci->run_regs->ir_set[0];
2380
2381         /*
2382          * Event ring setup: Allocate a normal ring, but also setup
2383          * the event ring segment table (ERST).  Section 4.9.3.
2384          */
2385         xhci_dbg(xhci, "// Allocating event ring\n");
2386         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2387                                                 flags);
2388         if (!xhci->event_ring)
2389                 goto fail;
2390         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2391                 goto fail;
2392
2393         xhci->erst.entries = dma_alloc_coherent(dev,
2394                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2395                         GFP_KERNEL);
2396         if (!xhci->erst.entries)
2397                 goto fail;
2398         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2399                         (unsigned long long)dma);
2400
2401         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2402         xhci->erst.num_entries = ERST_NUM_SEGS;
2403         xhci->erst.erst_dma_addr = dma;
2404         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2405                         xhci->erst.num_entries,
2406                         xhci->erst.entries,
2407                         (unsigned long long)xhci->erst.erst_dma_addr);
2408
2409         /* set ring base address and size for each segment table entry */
2410         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2411                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2412                 entry->seg_addr = cpu_to_le64(seg->dma);
2413                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2414                 entry->rsvd = 0;
2415                 seg = seg->next;
2416         }
2417
2418         /* set ERST count with the number of entries in the segment table */
2419         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2420         val &= ERST_SIZE_MASK;
2421         val |= ERST_NUM_SEGS;
2422         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2423                         val);
2424         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2425
2426         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2427         /* set the segment table base address */
2428         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2429                         (unsigned long long)xhci->erst.erst_dma_addr);
2430         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2431         val_64 &= ERST_PTR_MASK;
2432         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2433         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2434
2435         /* Set the event ring dequeue address */
2436         xhci_set_hc_event_deq(xhci);
2437         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2438         xhci_print_ir_set(xhci, 0);
2439
2440         /*
2441          * XXX: Might need to set the Interrupter Moderation Register to
2442          * something other than the default (~1ms minimum between interrupts).
2443          * See section 5.5.1.2.
2444          */
2445         init_completion(&xhci->addr_dev);
2446         for (i = 0; i < MAX_HC_SLOTS; ++i)
2447                 xhci->devs[i] = NULL;
2448         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2449                 xhci->bus_state[0].resume_done[i] = 0;
2450                 xhci->bus_state[1].resume_done[i] = 0;
2451         }
2452
2453         if (scratchpad_alloc(xhci, flags))
2454                 goto fail;
2455         if (xhci_setup_port_arrays(xhci, flags))
2456                 goto fail;
2457
2458         /* Enable USB 3.0 device notifications for function remote wake, which
2459          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2460          * U3 (device suspend).
2461          */
2462         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2463         temp &= ~DEV_NOTE_MASK;
2464         temp |= DEV_NOTE_FWAKE;
2465         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2466
2467         return 0;
2468
2469 fail:
2470         xhci_warn(xhci, "Couldn't initialize memory\n");
2471         xhci_halt(xhci);
2472         xhci_reset(xhci);
2473         xhci_mem_cleanup(xhci);
2474         return -ENOMEM;
2475 }