2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
38 unsigned int cycle_state, gfp_t flags)
40 struct xhci_segment *seg;
44 seg = kzalloc(sizeof *seg, flags);
48 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
54 memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state == 0) {
57 for (i = 0; i < TRBS_PER_SEGMENT; i++)
58 seg->trbs[i].link.control |= TRB_CYCLE;
66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
69 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
76 struct xhci_segment *first)
78 struct xhci_segment *seg;
81 while (seg != first) {
82 struct xhci_segment *next = seg->next;
83 xhci_segment_free(xhci, seg);
86 xhci_segment_free(xhci, first);
90 * Make the prev segment point to the next segment.
92 * Change the last TRB in the prev segment to be a Link TRB which points to the
93 * DMA address of the next segment. The caller needs to set any Link TRB
94 * related flags, such as End TRB, Toggle Cycle, and no snoop.
96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
97 struct xhci_segment *next, enum xhci_ring_type type)
104 if (type != TYPE_EVENT) {
105 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
106 cpu_to_le64(next->dma);
108 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
109 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
110 val &= ~TRB_TYPE_BITMASK;
111 val |= TRB_TYPE(TRB_LINK);
112 /* Always set the chain bit with 0.95 hardware */
113 /* Set chain bit for isoc rings on AMD 0.96 host */
114 if (xhci_link_trb_quirk(xhci) ||
115 (type == TYPE_ISOC &&
116 (xhci->quirks & XHCI_AMD_0x96_HOST)))
118 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
123 * Link the ring to the new segments.
124 * Set Toggle Cycle for the new ring if needed.
126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
127 struct xhci_segment *first, struct xhci_segment *last,
128 unsigned int num_segs)
130 struct xhci_segment *next;
132 if (!ring || !first || !last)
135 next = ring->enq_seg->next;
136 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
137 xhci_link_segments(xhci, last, next, ring->type);
138 ring->num_segs += num_segs;
139 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
141 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
142 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
143 &= ~cpu_to_le32(LINK_TOGGLE);
144 last->trbs[TRBS_PER_SEGMENT-1].link.control
145 |= cpu_to_le32(LINK_TOGGLE);
146 ring->last_seg = last;
150 /* XXX: Do we need the hcd structure in all these functions? */
151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
157 xhci_free_segments_for_ring(xhci, ring->first_seg);
162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
163 unsigned int cycle_state)
165 /* The ring is empty, so the enqueue pointer == dequeue pointer */
166 ring->enqueue = ring->first_seg->trbs;
167 ring->enq_seg = ring->first_seg;
168 ring->dequeue = ring->enqueue;
169 ring->deq_seg = ring->first_seg;
170 /* The ring is initialized to 0. The producer must write 1 to the cycle
171 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
172 * compare CCS to the cycle bit to check ownership, so CCS = 1.
174 * New rings are initialized with cycle state equal to 1; if we are
175 * handling ring expansion, set the cycle state equal to the old ring.
177 ring->cycle_state = cycle_state;
178 /* Not necessary for new rings, but needed for re-initialized rings */
179 ring->enq_updates = 0;
180 ring->deq_updates = 0;
183 * Each segment has a link TRB, and leave an extra TRB for SW
186 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
189 /* Allocate segments and link them for a ring */
190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
191 struct xhci_segment **first, struct xhci_segment **last,
192 unsigned int num_segs, unsigned int cycle_state,
193 enum xhci_ring_type type, gfp_t flags)
195 struct xhci_segment *prev;
197 prev = xhci_segment_alloc(xhci, cycle_state, flags);
203 while (num_segs > 0) {
204 struct xhci_segment *next;
206 next = xhci_segment_alloc(xhci, cycle_state, flags);
211 xhci_segment_free(xhci, prev);
216 xhci_link_segments(xhci, prev, next, type);
221 xhci_link_segments(xhci, prev, *first, type);
228 * Create a new ring with zero or more segments.
230 * Link each segment together into a ring.
231 * Set the end flag and the cycle toggle bit on the last segment.
232 * See section 4.9.1 and figures 15 and 16.
234 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
235 unsigned int num_segs, unsigned int cycle_state,
236 enum xhci_ring_type type, gfp_t flags)
238 struct xhci_ring *ring;
241 ring = kzalloc(sizeof *(ring), flags);
245 ring->num_segs = num_segs;
246 INIT_LIST_HEAD(&ring->td_list);
251 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
252 &ring->last_seg, num_segs, cycle_state, type, flags);
256 /* Only event ring does not use link TRB */
257 if (type != TYPE_EVENT) {
258 /* See section 4.9.2.1 and 6.4.4.1 */
259 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
260 cpu_to_le32(LINK_TOGGLE);
262 xhci_initialize_ring_info(ring, cycle_state);
270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
271 struct xhci_virt_device *virt_dev,
272 unsigned int ep_index)
276 rings_cached = virt_dev->num_rings_cached;
277 if (rings_cached < XHCI_MAX_RINGS_CACHED) {
278 virt_dev->ring_cache[rings_cached] =
279 virt_dev->eps[ep_index].ring;
280 virt_dev->num_rings_cached++;
281 xhci_dbg(xhci, "Cached old ring, "
282 "%d ring%s cached\n",
283 virt_dev->num_rings_cached,
284 (virt_dev->num_rings_cached > 1) ? "s" : "");
286 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
287 xhci_dbg(xhci, "Ring cache full (%d rings), "
289 virt_dev->num_rings_cached);
291 virt_dev->eps[ep_index].ring = NULL;
294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
295 * pointers to the beginning of the ring.
297 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
298 struct xhci_ring *ring, unsigned int cycle_state,
299 enum xhci_ring_type type)
301 struct xhci_segment *seg = ring->first_seg;
306 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
307 if (cycle_state == 0) {
308 for (i = 0; i < TRBS_PER_SEGMENT; i++)
309 seg->trbs[i].link.control |= TRB_CYCLE;
311 /* All endpoint rings have link TRBs */
312 xhci_link_segments(xhci, seg, seg->next, type);
314 } while (seg != ring->first_seg);
316 xhci_initialize_ring_info(ring, cycle_state);
317 /* td list should be empty since all URBs have been cancelled,
318 * but just in case...
320 INIT_LIST_HEAD(&ring->td_list);
324 * Expand an existing ring.
325 * Look for a cached ring or allocate a new ring which has same segment numbers
326 * and link the two rings.
328 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
329 unsigned int num_trbs, gfp_t flags)
331 struct xhci_segment *first;
332 struct xhci_segment *last;
333 unsigned int num_segs;
334 unsigned int num_segs_needed;
337 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
338 (TRBS_PER_SEGMENT - 1);
340 /* Allocate number of segments we needed, or double the ring size */
341 num_segs = ring->num_segs > num_segs_needed ?
342 ring->num_segs : num_segs_needed;
344 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
345 num_segs, ring->cycle_state, ring->type, flags);
349 xhci_link_rings(xhci, ring, first, last, num_segs);
350 xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
358 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
359 int type, gfp_t flags)
361 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
365 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
367 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
368 if (type == XHCI_CTX_TYPE_INPUT)
369 ctx->size += CTX_SIZE(xhci->hcc_params);
371 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
376 memset(ctx->bytes, 0, ctx->size);
380 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
381 struct xhci_container_ctx *ctx)
385 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
389 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
390 struct xhci_container_ctx *ctx)
392 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
393 return (struct xhci_input_control_ctx *)ctx->bytes;
396 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
397 struct xhci_container_ctx *ctx)
399 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
400 return (struct xhci_slot_ctx *)ctx->bytes;
402 return (struct xhci_slot_ctx *)
403 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
406 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
407 struct xhci_container_ctx *ctx,
408 unsigned int ep_index)
410 /* increment ep index by offset of start of ep ctx array */
412 if (ctx->type == XHCI_CTX_TYPE_INPUT)
415 return (struct xhci_ep_ctx *)
416 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
420 /***************** Streams structures manipulation *************************/
422 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
423 unsigned int num_stream_ctxs,
424 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
426 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
428 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
429 dma_free_coherent(&pdev->dev,
430 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
432 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
433 return dma_pool_free(xhci->small_streams_pool,
436 return dma_pool_free(xhci->medium_streams_pool,
441 * The stream context array for each endpoint with bulk streams enabled can
442 * vary in size, based on:
443 * - how many streams the endpoint supports,
444 * - the maximum primary stream array size the host controller supports,
445 * - and how many streams the device driver asks for.
447 * The stream context array must be a power of 2, and can be as small as
448 * 64 bytes or as large as 1MB.
450 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
451 unsigned int num_stream_ctxs, dma_addr_t *dma,
454 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
456 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
457 return dma_alloc_coherent(&pdev->dev,
458 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
460 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
461 return dma_pool_alloc(xhci->small_streams_pool,
464 return dma_pool_alloc(xhci->medium_streams_pool,
468 struct xhci_ring *xhci_dma_to_transfer_ring(
469 struct xhci_virt_ep *ep,
472 if (ep->ep_state & EP_HAS_STREAMS)
473 return radix_tree_lookup(&ep->stream_info->trb_address_map,
474 address >> TRB_SEGMENT_SHIFT);
478 /* Only use this when you know stream_info is valid */
479 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
480 static struct xhci_ring *dma_to_stream_ring(
481 struct xhci_stream_info *stream_info,
484 return radix_tree_lookup(&stream_info->trb_address_map,
485 address >> TRB_SEGMENT_SHIFT);
487 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
489 struct xhci_ring *xhci_stream_id_to_ring(
490 struct xhci_virt_device *dev,
491 unsigned int ep_index,
492 unsigned int stream_id)
494 struct xhci_virt_ep *ep = &dev->eps[ep_index];
498 if (!ep->stream_info)
501 if (stream_id > ep->stream_info->num_streams)
503 return ep->stream_info->stream_rings[stream_id];
506 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
507 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
508 unsigned int num_streams,
509 struct xhci_stream_info *stream_info)
512 struct xhci_ring *cur_ring;
515 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
516 struct xhci_ring *mapped_ring;
517 int trb_size = sizeof(union xhci_trb);
519 cur_ring = stream_info->stream_rings[cur_stream];
520 for (addr = cur_ring->first_seg->dma;
521 addr < cur_ring->first_seg->dma + TRB_SEGMENT_SIZE;
523 mapped_ring = dma_to_stream_ring(stream_info, addr);
524 if (cur_ring != mapped_ring) {
525 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
526 "didn't map to stream ID %u; "
527 "mapped to ring %p\n",
528 (unsigned long long) addr,
534 /* One TRB after the end of the ring segment shouldn't return a
535 * pointer to the current ring (although it may be a part of a
538 mapped_ring = dma_to_stream_ring(stream_info, addr);
539 if (mapped_ring != cur_ring) {
540 /* One TRB before should also fail */
541 addr = cur_ring->first_seg->dma - trb_size;
542 mapped_ring = dma_to_stream_ring(stream_info, addr);
544 if (mapped_ring == cur_ring) {
545 xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
546 "mapped to valid stream ID %u; "
547 "mapped ring = %p\n",
548 (unsigned long long) addr,
556 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
559 * Change an endpoint's internal structure so it supports stream IDs. The
560 * number of requested streams includes stream 0, which cannot be used by device
563 * The number of stream contexts in the stream context array may be bigger than
564 * the number of streams the driver wants to use. This is because the number of
565 * stream context array entries must be a power of two.
567 * We need a radix tree for mapping physical addresses of TRBs to which stream
568 * ID they belong to. We need to do this because the host controller won't tell
569 * us which stream ring the TRB came from. We could store the stream ID in an
570 * event data TRB, but that doesn't help us for the cancellation case, since the
571 * endpoint may stop before it reaches that event data TRB.
573 * The radix tree maps the upper portion of the TRB DMA address to a ring
574 * segment that has the same upper portion of DMA addresses. For example, say I
575 * have segments of size 1KB, that are always 64-byte aligned. A segment may
576 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
577 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
578 * pass the radix tree a key to get the right stream ID:
580 * 0x10c90fff >> 10 = 0x43243
581 * 0x10c912c0 >> 10 = 0x43244
582 * 0x10c91400 >> 10 = 0x43245
584 * Obviously, only those TRBs with DMA addresses that are within the segment
585 * will make the radix tree return the stream ID for that ring.
587 * Caveats for the radix tree:
589 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
590 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
591 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
592 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
593 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
594 * extended systems (where the DMA address can be bigger than 32-bits),
595 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
597 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
598 unsigned int num_stream_ctxs,
599 unsigned int num_streams, gfp_t mem_flags)
601 struct xhci_stream_info *stream_info;
603 struct xhci_ring *cur_ring;
608 xhci_dbg(xhci, "Allocating %u streams and %u "
609 "stream context array entries.\n",
610 num_streams, num_stream_ctxs);
611 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
612 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
615 xhci->cmd_ring_reserved_trbs++;
617 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
621 stream_info->num_streams = num_streams;
622 stream_info->num_stream_ctxs = num_stream_ctxs;
624 /* Initialize the array of virtual pointers to stream rings. */
625 stream_info->stream_rings = kzalloc(
626 sizeof(struct xhci_ring *)*num_streams,
628 if (!stream_info->stream_rings)
631 /* Initialize the array of DMA addresses for stream rings for the HW. */
632 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
633 num_stream_ctxs, &stream_info->ctx_array_dma,
635 if (!stream_info->stream_ctx_array)
637 memset(stream_info->stream_ctx_array, 0,
638 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
640 /* Allocate everything needed to free the stream rings later */
641 stream_info->free_streams_command =
642 xhci_alloc_command(xhci, true, true, mem_flags);
643 if (!stream_info->free_streams_command)
646 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
648 /* Allocate rings for all the streams that the driver will use,
649 * and add their segment DMA addresses to the radix tree.
650 * Stream 0 is reserved.
652 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
653 stream_info->stream_rings[cur_stream] =
654 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
655 cur_ring = stream_info->stream_rings[cur_stream];
658 cur_ring->stream_id = cur_stream;
659 /* Set deq ptr, cycle bit, and stream context type */
660 addr = cur_ring->first_seg->dma |
661 SCT_FOR_CTX(SCT_PRI_TR) |
662 cur_ring->cycle_state;
663 stream_info->stream_ctx_array[cur_stream].stream_ring =
665 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
666 cur_stream, (unsigned long long) addr);
668 key = (unsigned long)
669 (cur_ring->first_seg->dma >> TRB_SEGMENT_SHIFT);
670 ret = radix_tree_insert(&stream_info->trb_address_map,
673 xhci_ring_free(xhci, cur_ring);
674 stream_info->stream_rings[cur_stream] = NULL;
678 /* Leave the other unused stream ring pointers in the stream context
679 * array initialized to zero. This will cause the xHC to give us an
680 * error if the device asks for a stream ID we don't have setup (if it
681 * was any other way, the host controller would assume the ring is
682 * "empty" and wait forever for data to be queued to that stream ID).
685 /* Do a little test on the radix tree to make sure it returns the
688 if (xhci_test_radix_tree(xhci, num_streams, stream_info))
695 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
696 cur_ring = stream_info->stream_rings[cur_stream];
698 addr = cur_ring->first_seg->dma;
699 radix_tree_delete(&stream_info->trb_address_map,
700 addr >> TRB_SEGMENT_SHIFT);
701 xhci_ring_free(xhci, cur_ring);
702 stream_info->stream_rings[cur_stream] = NULL;
705 xhci_free_command(xhci, stream_info->free_streams_command);
707 kfree(stream_info->stream_rings);
711 xhci->cmd_ring_reserved_trbs--;
715 * Sets the MaxPStreams field and the Linear Stream Array field.
716 * Sets the dequeue pointer to the stream context array.
718 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
719 struct xhci_ep_ctx *ep_ctx,
720 struct xhci_stream_info *stream_info)
722 u32 max_primary_streams;
723 /* MaxPStreams is the number of stream context array entries, not the
724 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
725 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
727 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
728 xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
729 1 << (max_primary_streams + 1));
730 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
731 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
733 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
737 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
738 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
739 * not at the beginning of the ring).
741 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
742 struct xhci_ep_ctx *ep_ctx,
743 struct xhci_virt_ep *ep)
746 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
747 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
748 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
751 /* Frees all stream contexts associated with the endpoint,
753 * Caller should fix the endpoint context streams fields.
755 void xhci_free_stream_info(struct xhci_hcd *xhci,
756 struct xhci_stream_info *stream_info)
759 struct xhci_ring *cur_ring;
765 for (cur_stream = 1; cur_stream < stream_info->num_streams;
767 cur_ring = stream_info->stream_rings[cur_stream];
769 addr = cur_ring->first_seg->dma;
770 radix_tree_delete(&stream_info->trb_address_map,
771 addr >> TRB_SEGMENT_SHIFT);
772 xhci_ring_free(xhci, cur_ring);
773 stream_info->stream_rings[cur_stream] = NULL;
776 xhci_free_command(xhci, stream_info->free_streams_command);
777 xhci->cmd_ring_reserved_trbs--;
778 if (stream_info->stream_ctx_array)
779 xhci_free_stream_ctx(xhci,
780 stream_info->num_stream_ctxs,
781 stream_info->stream_ctx_array,
782 stream_info->ctx_array_dma);
785 kfree(stream_info->stream_rings);
790 /***************** Device context manipulation *************************/
792 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
793 struct xhci_virt_ep *ep)
795 init_timer(&ep->stop_cmd_timer);
796 ep->stop_cmd_timer.data = (unsigned long) ep;
797 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
801 static void xhci_free_tt_info(struct xhci_hcd *xhci,
802 struct xhci_virt_device *virt_dev,
805 struct list_head *tt_list_head;
806 struct xhci_tt_bw_info *tt_info, *next;
807 bool slot_found = false;
809 /* If the device never made it past the Set Address stage,
810 * it may not have the real_port set correctly.
812 if (virt_dev->real_port == 0 ||
813 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
814 xhci_dbg(xhci, "Bad real port.\n");
818 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
819 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
820 /* Multi-TT hubs will have more than one entry */
821 if (tt_info->slot_id == slot_id) {
823 list_del(&tt_info->tt_list);
825 } else if (slot_found) {
831 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
832 struct xhci_virt_device *virt_dev,
833 struct usb_device *hdev,
834 struct usb_tt *tt, gfp_t mem_flags)
836 struct xhci_tt_bw_info *tt_info;
837 unsigned int num_ports;
843 num_ports = hdev->maxchild;
845 for (i = 0; i < num_ports; i++, tt_info++) {
846 struct xhci_interval_bw_table *bw_table;
848 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
851 INIT_LIST_HEAD(&tt_info->tt_list);
852 list_add(&tt_info->tt_list,
853 &xhci->rh_bw[virt_dev->real_port - 1].tts);
854 tt_info->slot_id = virt_dev->udev->slot_id;
856 tt_info->ttport = i+1;
857 bw_table = &tt_info->bw_table;
858 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
859 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
864 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
869 /* All the xhci_tds in the ring's TD list should be freed at this point.
870 * Should be called with xhci->lock held if there is any chance the TT lists
871 * will be manipulated by the configure endpoint, allocate device, or update
872 * hub functions while this function is removing the TT entries from the list.
874 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
876 struct xhci_virt_device *dev;
878 int old_active_eps = 0;
880 /* Slot ID 0 is reserved */
881 if (slot_id == 0 || !xhci->devs[slot_id])
884 dev = xhci->devs[slot_id];
885 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
890 old_active_eps = dev->tt_info->active_eps;
892 for (i = 0; i < 31; ++i) {
893 if (dev->eps[i].ring)
894 xhci_ring_free(xhci, dev->eps[i].ring);
895 if (dev->eps[i].stream_info)
896 xhci_free_stream_info(xhci,
897 dev->eps[i].stream_info);
898 /* Endpoints on the TT/root port lists should have been removed
899 * when usb_disable_device() was called for the device.
900 * We can't drop them anyway, because the udev might have gone
901 * away by this point, and we can't tell what speed it was.
903 if (!list_empty(&dev->eps[i].bw_endpoint_list))
904 xhci_warn(xhci, "Slot %u endpoint %u "
905 "not removed from BW list!\n",
908 /* If this is a hub, free the TT(s) from the TT list */
909 xhci_free_tt_info(xhci, dev, slot_id);
910 /* If necessary, update the number of active TTs on this root port */
911 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
913 if (dev->ring_cache) {
914 for (i = 0; i < dev->num_rings_cached; i++)
915 xhci_ring_free(xhci, dev->ring_cache[i]);
916 kfree(dev->ring_cache);
920 xhci_free_container_ctx(xhci, dev->in_ctx);
922 xhci_free_container_ctx(xhci, dev->out_ctx);
924 kfree(xhci->devs[slot_id]);
925 xhci->devs[slot_id] = NULL;
928 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
929 struct usb_device *udev, gfp_t flags)
931 struct xhci_virt_device *dev;
934 /* Slot ID 0 is reserved */
935 if (slot_id == 0 || xhci->devs[slot_id]) {
936 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
940 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
941 if (!xhci->devs[slot_id])
943 dev = xhci->devs[slot_id];
945 /* Allocate the (output) device context that will be used in the HC. */
946 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
950 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
951 (unsigned long long)dev->out_ctx->dma);
953 /* Allocate the (input) device context for address device command */
954 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
958 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
959 (unsigned long long)dev->in_ctx->dma);
961 /* Initialize the cancellation list and watchdog timers for each ep */
962 for (i = 0; i < 31; i++) {
963 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
964 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
965 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
968 /* Allocate endpoint 0 ring */
969 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
970 if (!dev->eps[0].ring)
973 /* Allocate pointers to the ring cache */
974 dev->ring_cache = kzalloc(
975 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
977 if (!dev->ring_cache)
979 dev->num_rings_cached = 0;
981 init_completion(&dev->cmd_completion);
982 INIT_LIST_HEAD(&dev->cmd_list);
985 /* Point to output device context in dcbaa. */
986 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
987 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
989 &xhci->dcbaa->dev_context_ptrs[slot_id],
990 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
994 xhci_free_virt_device(xhci, slot_id);
998 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
999 struct usb_device *udev)
1001 struct xhci_virt_device *virt_dev;
1002 struct xhci_ep_ctx *ep0_ctx;
1003 struct xhci_ring *ep_ring;
1005 virt_dev = xhci->devs[udev->slot_id];
1006 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1007 ep_ring = virt_dev->eps[0].ring;
1009 * FIXME we don't keep track of the dequeue pointer very well after a
1010 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1011 * host to our enqueue pointer. This should only be called after a
1012 * configured device has reset, so all control transfers should have
1013 * been completed or cancelled before the reset.
1015 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1017 | ep_ring->cycle_state);
1021 * The xHCI roothub may have ports of differing speeds in any order in the port
1022 * status registers. xhci->port_array provides an array of the port speed for
1023 * each offset into the port status registers.
1025 * The xHCI hardware wants to know the roothub port number that the USB device
1026 * is attached to (or the roothub port its ancestor hub is attached to). All we
1027 * know is the index of that port under either the USB 2.0 or the USB 3.0
1028 * roothub, but that doesn't give us the real index into the HW port status
1029 * registers. Call xhci_find_raw_port_number() to get real index.
1031 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1032 struct usb_device *udev)
1034 struct usb_device *top_dev;
1035 struct usb_hcd *hcd;
1037 if (udev->speed == USB_SPEED_SUPER)
1038 hcd = xhci->shared_hcd;
1040 hcd = xhci->main_hcd;
1042 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1043 top_dev = top_dev->parent)
1044 /* Found device below root hub */;
1046 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1049 /* Setup an xHCI virtual device for a Set Address command */
1050 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1052 struct xhci_virt_device *dev;
1053 struct xhci_ep_ctx *ep0_ctx;
1054 struct xhci_slot_ctx *slot_ctx;
1056 struct usb_device *top_dev;
1058 dev = xhci->devs[udev->slot_id];
1059 /* Slot ID 0 is reserved */
1060 if (udev->slot_id == 0 || !dev) {
1061 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1065 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1066 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1068 /* 3) Only the control endpoint is valid - one endpoint context */
1069 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1070 switch (udev->speed) {
1071 case USB_SPEED_SUPER:
1072 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1074 case USB_SPEED_HIGH:
1075 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1077 case USB_SPEED_FULL:
1078 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1081 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1083 case USB_SPEED_WIRELESS:
1084 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1088 /* Speed was set earlier, this shouldn't happen. */
1091 /* Find the root hub port this device is under */
1092 port_num = xhci_find_real_port_number(xhci, udev);
1095 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1096 /* Set the port number in the virtual_device to the faked port number */
1097 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1098 top_dev = top_dev->parent)
1099 /* Found device below root hub */;
1100 dev->fake_port = top_dev->portnum;
1101 dev->real_port = port_num;
1102 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1103 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1105 /* Find the right bandwidth table that this device will be a part of.
1106 * If this is a full speed device attached directly to a root port (or a
1107 * decendent of one), it counts as a primary bandwidth domain, not a
1108 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1109 * will never be created for the HS root hub.
1111 if (!udev->tt || !udev->tt->hub->parent) {
1112 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1114 struct xhci_root_port_bw_info *rh_bw;
1115 struct xhci_tt_bw_info *tt_bw;
1117 rh_bw = &xhci->rh_bw[port_num - 1];
1118 /* Find the right TT. */
1119 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1120 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1123 if (!dev->udev->tt->multi ||
1125 tt_bw->ttport == dev->udev->ttport)) {
1126 dev->bw_table = &tt_bw->bw_table;
1127 dev->tt_info = tt_bw;
1132 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1135 /* Is this a LS/FS device under an external HS hub? */
1136 if (udev->tt && udev->tt->hub->parent) {
1137 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1138 (udev->ttport << 8));
1139 if (udev->tt->multi)
1140 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1142 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1143 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1145 /* Step 4 - ring already allocated */
1147 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1149 * XXX: Not sure about wireless USB devices.
1151 switch (udev->speed) {
1152 case USB_SPEED_SUPER:
1153 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1155 case USB_SPEED_HIGH:
1156 /* USB core guesses at a 64-byte max packet first for FS devices */
1157 case USB_SPEED_FULL:
1158 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1161 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1163 case USB_SPEED_WIRELESS:
1164 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1171 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1172 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1174 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1175 dev->eps[0].ring->cycle_state);
1177 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1183 * Convert interval expressed as 2^(bInterval - 1) == interval into
1184 * straight exponent value 2^n == interval.
1187 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1188 struct usb_host_endpoint *ep)
1190 unsigned int interval;
1192 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1193 if (interval != ep->desc.bInterval - 1)
1194 dev_warn(&udev->dev,
1195 "ep %#x - rounding interval to %d %sframes\n",
1196 ep->desc.bEndpointAddress,
1198 udev->speed == USB_SPEED_FULL ? "" : "micro");
1200 if (udev->speed == USB_SPEED_FULL) {
1202 * Full speed isoc endpoints specify interval in frames,
1203 * not microframes. We are using microframes everywhere,
1204 * so adjust accordingly.
1206 interval += 3; /* 1 frame = 2^3 uframes */
1213 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1214 * microframes, rounded down to nearest power of 2.
1216 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1217 struct usb_host_endpoint *ep, unsigned int desc_interval,
1218 unsigned int min_exponent, unsigned int max_exponent)
1220 unsigned int interval;
1222 interval = fls(desc_interval) - 1;
1223 interval = clamp_val(interval, min_exponent, max_exponent);
1224 if ((1 << interval) != desc_interval)
1225 dev_warn(&udev->dev,
1226 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1227 ep->desc.bEndpointAddress,
1234 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1235 struct usb_host_endpoint *ep)
1237 if (ep->desc.bInterval == 0)
1239 return xhci_microframes_to_exponent(udev, ep,
1240 ep->desc.bInterval, 0, 15);
1244 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1245 struct usb_host_endpoint *ep)
1247 return xhci_microframes_to_exponent(udev, ep,
1248 ep->desc.bInterval * 8, 3, 10);
1251 /* Return the polling or NAK interval.
1253 * The polling interval is expressed in "microframes". If xHCI's Interval field
1254 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1256 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1259 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1260 struct usb_host_endpoint *ep)
1262 unsigned int interval = 0;
1264 switch (udev->speed) {
1265 case USB_SPEED_HIGH:
1267 if (usb_endpoint_xfer_control(&ep->desc) ||
1268 usb_endpoint_xfer_bulk(&ep->desc)) {
1269 interval = xhci_parse_microframe_interval(udev, ep);
1272 /* Fall through - SS and HS isoc/int have same decoding */
1274 case USB_SPEED_SUPER:
1275 if (usb_endpoint_xfer_int(&ep->desc) ||
1276 usb_endpoint_xfer_isoc(&ep->desc)) {
1277 interval = xhci_parse_exponent_interval(udev, ep);
1281 case USB_SPEED_FULL:
1282 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1283 interval = xhci_parse_exponent_interval(udev, ep);
1287 * Fall through for interrupt endpoint interval decoding
1288 * since it uses the same rules as low speed interrupt
1293 if (usb_endpoint_xfer_int(&ep->desc) ||
1294 usb_endpoint_xfer_isoc(&ep->desc)) {
1296 interval = xhci_parse_frame_interval(udev, ep);
1303 return EP_INTERVAL(interval);
1306 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1307 * High speed endpoint descriptors can define "the number of additional
1308 * transaction opportunities per microframe", but that goes in the Max Burst
1309 * endpoint context field.
1311 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1312 struct usb_host_endpoint *ep)
1314 if (udev->speed != USB_SPEED_SUPER ||
1315 !usb_endpoint_xfer_isoc(&ep->desc))
1317 return ep->ss_ep_comp.bmAttributes;
1320 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1321 struct usb_host_endpoint *ep)
1326 in = usb_endpoint_dir_in(&ep->desc);
1327 if (usb_endpoint_xfer_control(&ep->desc)) {
1328 type = EP_TYPE(CTRL_EP);
1329 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1331 type = EP_TYPE(BULK_IN_EP);
1333 type = EP_TYPE(BULK_OUT_EP);
1334 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1336 type = EP_TYPE(ISOC_IN_EP);
1338 type = EP_TYPE(ISOC_OUT_EP);
1339 } else if (usb_endpoint_xfer_int(&ep->desc)) {
1341 type = EP_TYPE(INT_IN_EP);
1343 type = EP_TYPE(INT_OUT_EP);
1350 /* Return the maximum endpoint service interval time (ESIT) payload.
1351 * Basically, this is the maxpacket size, multiplied by the burst size
1354 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1355 struct usb_device *udev,
1356 struct usb_host_endpoint *ep)
1361 /* Only applies for interrupt or isochronous endpoints */
1362 if (usb_endpoint_xfer_control(&ep->desc) ||
1363 usb_endpoint_xfer_bulk(&ep->desc))
1366 if (udev->speed == USB_SPEED_SUPER)
1367 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1369 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1370 max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1371 /* A 0 in max burst means 1 transfer per ESIT */
1372 return max_packet * (max_burst + 1);
1375 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1376 * Drivers will have to call usb_alloc_streams() to do that.
1378 int xhci_endpoint_init(struct xhci_hcd *xhci,
1379 struct xhci_virt_device *virt_dev,
1380 struct usb_device *udev,
1381 struct usb_host_endpoint *ep,
1384 unsigned int ep_index;
1385 struct xhci_ep_ctx *ep_ctx;
1386 struct xhci_ring *ep_ring;
1387 unsigned int max_packet;
1388 unsigned int max_burst;
1389 enum xhci_ring_type type;
1390 u32 max_esit_payload;
1392 ep_index = xhci_get_endpoint_index(&ep->desc);
1393 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1395 type = usb_endpoint_type(&ep->desc);
1396 /* Set up the endpoint ring */
1397 virt_dev->eps[ep_index].new_ring =
1398 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1399 if (!virt_dev->eps[ep_index].new_ring) {
1400 /* Attempt to use the ring cache */
1401 if (virt_dev->num_rings_cached == 0)
1403 virt_dev->eps[ep_index].new_ring =
1404 virt_dev->ring_cache[virt_dev->num_rings_cached];
1405 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1406 virt_dev->num_rings_cached--;
1407 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1410 virt_dev->eps[ep_index].skip = false;
1411 ep_ring = virt_dev->eps[ep_index].new_ring;
1412 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1414 ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1415 | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1417 /* FIXME dig Mult and streams info out of ep companion desc */
1419 /* Allow 3 retries for everything but isoc;
1420 * CErr shall be set to 0 for Isoch endpoints.
1422 if (!usb_endpoint_xfer_isoc(&ep->desc))
1423 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1425 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1427 ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1429 /* Set the max packet size and max burst */
1430 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1432 switch (udev->speed) {
1433 case USB_SPEED_SUPER:
1434 /* dig out max burst from ep companion desc */
1435 max_burst = ep->ss_ep_comp.bMaxBurst;
1437 case USB_SPEED_HIGH:
1438 /* Some devices get this wrong */
1439 if (usb_endpoint_xfer_bulk(&ep->desc))
1441 /* bits 11:12 specify the number of additional transaction
1442 * opportunities per microframe (USB 2.0, section 9.6.6)
1444 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1445 usb_endpoint_xfer_int(&ep->desc)) {
1446 max_burst = (usb_endpoint_maxp(&ep->desc)
1450 case USB_SPEED_FULL:
1456 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
1457 MAX_BURST(max_burst));
1458 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1459 ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1462 * XXX no idea how to calculate the average TRB buffer length for bulk
1463 * endpoints, as the driver gives us no clue how big each scatter gather
1464 * list entry (or buffer) is going to be.
1466 * For isochronous and interrupt endpoints, we set it to the max
1467 * available, until we have new API in the USB core to allow drivers to
1468 * declare how much bandwidth they actually need.
1470 * Normally, it would be calculated by taking the total of the buffer
1471 * lengths in the TD and then dividing by the number of TRBs in a TD,
1472 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1473 * use Event Data TRBs, and we don't chain in a link TRB on short
1474 * transfers, we're basically dividing by 1.
1476 * xHCI 1.0 specification indicates that the Average TRB Length should
1477 * be set to 8 for control endpoints.
1479 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1480 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1483 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1485 /* FIXME Debug endpoint context */
1489 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1490 struct xhci_virt_device *virt_dev,
1491 struct usb_host_endpoint *ep)
1493 unsigned int ep_index;
1494 struct xhci_ep_ctx *ep_ctx;
1496 ep_index = xhci_get_endpoint_index(&ep->desc);
1497 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1499 ep_ctx->ep_info = 0;
1500 ep_ctx->ep_info2 = 0;
1502 ep_ctx->tx_info = 0;
1503 /* Don't free the endpoint ring until the set interface or configuration
1508 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1510 bw_info->ep_interval = 0;
1512 bw_info->num_packets = 0;
1513 bw_info->max_packet_size = 0;
1515 bw_info->max_esit_payload = 0;
1518 void xhci_update_bw_info(struct xhci_hcd *xhci,
1519 struct xhci_container_ctx *in_ctx,
1520 struct xhci_input_control_ctx *ctrl_ctx,
1521 struct xhci_virt_device *virt_dev)
1523 struct xhci_bw_info *bw_info;
1524 struct xhci_ep_ctx *ep_ctx;
1525 unsigned int ep_type;
1528 for (i = 1; i < 31; ++i) {
1529 bw_info = &virt_dev->eps[i].bw_info;
1531 /* We can't tell what endpoint type is being dropped, but
1532 * unconditionally clearing the bandwidth info for non-periodic
1533 * endpoints should be harmless because the info will never be
1534 * set in the first place.
1536 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1537 /* Dropped endpoint */
1538 xhci_clear_endpoint_bw_info(bw_info);
1542 if (EP_IS_ADDED(ctrl_ctx, i)) {
1543 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1544 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1546 /* Ignore non-periodic endpoints */
1547 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1548 ep_type != ISOC_IN_EP &&
1549 ep_type != INT_IN_EP)
1552 /* Added or changed endpoint */
1553 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1554 le32_to_cpu(ep_ctx->ep_info));
1555 /* Number of packets and mult are zero-based in the
1556 * input context, but we want one-based for the
1559 bw_info->mult = CTX_TO_EP_MULT(
1560 le32_to_cpu(ep_ctx->ep_info)) + 1;
1561 bw_info->num_packets = CTX_TO_MAX_BURST(
1562 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1563 bw_info->max_packet_size = MAX_PACKET_DECODED(
1564 le32_to_cpu(ep_ctx->ep_info2));
1565 bw_info->type = ep_type;
1566 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1567 le32_to_cpu(ep_ctx->tx_info));
1572 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1573 * Useful when you want to change one particular aspect of the endpoint and then
1574 * issue a configure endpoint command.
1576 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1577 struct xhci_container_ctx *in_ctx,
1578 struct xhci_container_ctx *out_ctx,
1579 unsigned int ep_index)
1581 struct xhci_ep_ctx *out_ep_ctx;
1582 struct xhci_ep_ctx *in_ep_ctx;
1584 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1585 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1587 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1588 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1589 in_ep_ctx->deq = out_ep_ctx->deq;
1590 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1593 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1594 * Useful when you want to change one particular aspect of the endpoint and then
1595 * issue a configure endpoint command. Only the context entries field matters,
1596 * but we'll copy the whole thing anyway.
1598 void xhci_slot_copy(struct xhci_hcd *xhci,
1599 struct xhci_container_ctx *in_ctx,
1600 struct xhci_container_ctx *out_ctx)
1602 struct xhci_slot_ctx *in_slot_ctx;
1603 struct xhci_slot_ctx *out_slot_ctx;
1605 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1606 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1608 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1609 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1610 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1611 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1614 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1615 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1618 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1619 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1621 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1626 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1627 if (!xhci->scratchpad)
1630 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1631 num_sp * sizeof(u64),
1632 &xhci->scratchpad->sp_dma, flags);
1633 if (!xhci->scratchpad->sp_array)
1636 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1637 if (!xhci->scratchpad->sp_buffers)
1640 xhci->scratchpad->sp_dma_buffers =
1641 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1643 if (!xhci->scratchpad->sp_dma_buffers)
1646 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1647 for (i = 0; i < num_sp; i++) {
1649 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1654 xhci->scratchpad->sp_array[i] = dma;
1655 xhci->scratchpad->sp_buffers[i] = buf;
1656 xhci->scratchpad->sp_dma_buffers[i] = dma;
1662 for (i = i - 1; i >= 0; i--) {
1663 dma_free_coherent(dev, xhci->page_size,
1664 xhci->scratchpad->sp_buffers[i],
1665 xhci->scratchpad->sp_dma_buffers[i]);
1667 kfree(xhci->scratchpad->sp_dma_buffers);
1670 kfree(xhci->scratchpad->sp_buffers);
1673 dma_free_coherent(dev, num_sp * sizeof(u64),
1674 xhci->scratchpad->sp_array,
1675 xhci->scratchpad->sp_dma);
1678 kfree(xhci->scratchpad);
1679 xhci->scratchpad = NULL;
1685 static void scratchpad_free(struct xhci_hcd *xhci)
1689 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1691 if (!xhci->scratchpad)
1694 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1696 for (i = 0; i < num_sp; i++) {
1697 dma_free_coherent(&pdev->dev, xhci->page_size,
1698 xhci->scratchpad->sp_buffers[i],
1699 xhci->scratchpad->sp_dma_buffers[i]);
1701 kfree(xhci->scratchpad->sp_dma_buffers);
1702 kfree(xhci->scratchpad->sp_buffers);
1703 dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1704 xhci->scratchpad->sp_array,
1705 xhci->scratchpad->sp_dma);
1706 kfree(xhci->scratchpad);
1707 xhci->scratchpad = NULL;
1710 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1711 bool allocate_in_ctx, bool allocate_completion,
1714 struct xhci_command *command;
1716 command = kzalloc(sizeof(*command), mem_flags);
1720 if (allocate_in_ctx) {
1722 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1724 if (!command->in_ctx) {
1730 if (allocate_completion) {
1731 command->completion =
1732 kzalloc(sizeof(struct completion), mem_flags);
1733 if (!command->completion) {
1734 xhci_free_container_ctx(xhci, command->in_ctx);
1738 init_completion(command->completion);
1741 command->status = 0;
1742 INIT_LIST_HEAD(&command->cmd_list);
1746 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1749 kfree(urb_priv->td[0]);
1754 void xhci_free_command(struct xhci_hcd *xhci,
1755 struct xhci_command *command)
1757 xhci_free_container_ctx(xhci,
1759 kfree(command->completion);
1763 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1765 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1766 struct dev_info *dev_info, *next;
1767 struct xhci_cd *cur_cd, *next_cd;
1768 unsigned long flags;
1770 int i, j, num_ports;
1772 /* Free the Event Ring Segment Table and the actual Event Ring */
1773 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1774 if (xhci->erst.entries)
1775 dma_free_coherent(&pdev->dev, size,
1776 xhci->erst.entries, xhci->erst.erst_dma_addr);
1777 xhci->erst.entries = NULL;
1778 xhci_dbg(xhci, "Freed ERST\n");
1779 if (xhci->event_ring)
1780 xhci_ring_free(xhci, xhci->event_ring);
1781 xhci->event_ring = NULL;
1782 xhci_dbg(xhci, "Freed event ring\n");
1784 if (xhci->lpm_command)
1785 xhci_free_command(xhci, xhci->lpm_command);
1786 xhci->cmd_ring_reserved_trbs = 0;
1788 xhci_ring_free(xhci, xhci->cmd_ring);
1789 xhci->cmd_ring = NULL;
1790 xhci_dbg(xhci, "Freed command ring\n");
1791 list_for_each_entry_safe(cur_cd, next_cd,
1792 &xhci->cancel_cmd_list, cancel_cmd_list) {
1793 list_del(&cur_cd->cancel_cmd_list);
1797 for (i = 1; i < MAX_HC_SLOTS; ++i)
1798 xhci_free_virt_device(xhci, i);
1800 if (xhci->segment_pool)
1801 dma_pool_destroy(xhci->segment_pool);
1802 xhci->segment_pool = NULL;
1803 xhci_dbg(xhci, "Freed segment pool\n");
1805 if (xhci->device_pool)
1806 dma_pool_destroy(xhci->device_pool);
1807 xhci->device_pool = NULL;
1808 xhci_dbg(xhci, "Freed device context pool\n");
1810 if (xhci->small_streams_pool)
1811 dma_pool_destroy(xhci->small_streams_pool);
1812 xhci->small_streams_pool = NULL;
1813 xhci_dbg(xhci, "Freed small stream array pool\n");
1815 if (xhci->medium_streams_pool)
1816 dma_pool_destroy(xhci->medium_streams_pool);
1817 xhci->medium_streams_pool = NULL;
1818 xhci_dbg(xhci, "Freed medium stream array pool\n");
1821 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1822 xhci->dcbaa, xhci->dcbaa->dma);
1825 scratchpad_free(xhci);
1827 spin_lock_irqsave(&xhci->lock, flags);
1828 list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1829 list_del(&dev_info->list);
1832 spin_unlock_irqrestore(&xhci->lock, flags);
1837 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1838 for (i = 0; i < num_ports; i++) {
1839 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1840 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1841 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1842 while (!list_empty(ep))
1843 list_del_init(ep->next);
1847 for (i = 0; i < num_ports; i++) {
1848 struct xhci_tt_bw_info *tt, *n;
1849 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1850 list_del(&tt->tt_list);
1856 xhci->num_usb2_ports = 0;
1857 xhci->num_usb3_ports = 0;
1858 xhci->num_active_eps = 0;
1859 kfree(xhci->usb2_ports);
1860 kfree(xhci->usb3_ports);
1861 kfree(xhci->port_array);
1864 xhci->page_size = 0;
1865 xhci->page_shift = 0;
1866 xhci->bus_state[0].bus_suspended = 0;
1867 xhci->bus_state[1].bus_suspended = 0;
1870 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1871 struct xhci_segment *input_seg,
1872 union xhci_trb *start_trb,
1873 union xhci_trb *end_trb,
1874 dma_addr_t input_dma,
1875 struct xhci_segment *result_seg,
1876 char *test_name, int test_number)
1878 unsigned long long start_dma;
1879 unsigned long long end_dma;
1880 struct xhci_segment *seg;
1882 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1883 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1885 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1886 if (seg != result_seg) {
1887 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1888 test_name, test_number);
1889 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1890 "input DMA 0x%llx\n",
1892 (unsigned long long) input_dma);
1893 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1894 "ending TRB %p (0x%llx DMA)\n",
1895 start_trb, start_dma,
1897 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1904 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1905 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1908 dma_addr_t input_dma;
1909 struct xhci_segment *result_seg;
1910 } simple_test_vector [] = {
1911 /* A zeroed DMA field should fail */
1913 /* One TRB before the ring start should fail */
1914 { xhci->event_ring->first_seg->dma - 16, NULL },
1915 /* One byte before the ring start should fail */
1916 { xhci->event_ring->first_seg->dma - 1, NULL },
1917 /* Starting TRB should succeed */
1918 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1919 /* Ending TRB should succeed */
1920 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1921 xhci->event_ring->first_seg },
1922 /* One byte after the ring end should fail */
1923 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1924 /* One TRB after the ring end should fail */
1925 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1926 /* An address of all ones should fail */
1927 { (dma_addr_t) (~0), NULL },
1930 struct xhci_segment *input_seg;
1931 union xhci_trb *start_trb;
1932 union xhci_trb *end_trb;
1933 dma_addr_t input_dma;
1934 struct xhci_segment *result_seg;
1935 } complex_test_vector [] = {
1936 /* Test feeding a valid DMA address from a different ring */
1937 { .input_seg = xhci->event_ring->first_seg,
1938 .start_trb = xhci->event_ring->first_seg->trbs,
1939 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1940 .input_dma = xhci->cmd_ring->first_seg->dma,
1943 /* Test feeding a valid end TRB from a different ring */
1944 { .input_seg = xhci->event_ring->first_seg,
1945 .start_trb = xhci->event_ring->first_seg->trbs,
1946 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1947 .input_dma = xhci->cmd_ring->first_seg->dma,
1950 /* Test feeding a valid start and end TRB from a different ring */
1951 { .input_seg = xhci->event_ring->first_seg,
1952 .start_trb = xhci->cmd_ring->first_seg->trbs,
1953 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1954 .input_dma = xhci->cmd_ring->first_seg->dma,
1957 /* TRB in this ring, but after this TD */
1958 { .input_seg = xhci->event_ring->first_seg,
1959 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1960 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1961 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1964 /* TRB in this ring, but before this TD */
1965 { .input_seg = xhci->event_ring->first_seg,
1966 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1967 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1968 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1971 /* TRB in this ring, but after this wrapped TD */
1972 { .input_seg = xhci->event_ring->first_seg,
1973 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1974 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1975 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1978 /* TRB in this ring, but before this wrapped TD */
1979 { .input_seg = xhci->event_ring->first_seg,
1980 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1981 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1982 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1985 /* TRB not in this ring, and we have a wrapped TD */
1986 { .input_seg = xhci->event_ring->first_seg,
1987 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1988 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1989 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1994 unsigned int num_tests;
1997 num_tests = ARRAY_SIZE(simple_test_vector);
1998 for (i = 0; i < num_tests; i++) {
1999 ret = xhci_test_trb_in_td(xhci,
2000 xhci->event_ring->first_seg,
2001 xhci->event_ring->first_seg->trbs,
2002 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2003 simple_test_vector[i].input_dma,
2004 simple_test_vector[i].result_seg,
2010 num_tests = ARRAY_SIZE(complex_test_vector);
2011 for (i = 0; i < num_tests; i++) {
2012 ret = xhci_test_trb_in_td(xhci,
2013 complex_test_vector[i].input_seg,
2014 complex_test_vector[i].start_trb,
2015 complex_test_vector[i].end_trb,
2016 complex_test_vector[i].input_dma,
2017 complex_test_vector[i].result_seg,
2022 xhci_dbg(xhci, "TRB math tests passed.\n");
2026 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2031 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2032 xhci->event_ring->dequeue);
2033 if (deq == 0 && !in_interrupt())
2034 xhci_warn(xhci, "WARN something wrong with SW event ring "
2036 /* Update HC event ring dequeue pointer */
2037 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2038 temp &= ERST_PTR_MASK;
2039 /* Don't clear the EHB bit (which is RW1C) because
2040 * there might be more events to service.
2043 xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2044 "preserving EHB bit\n");
2045 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2046 &xhci->ir_set->erst_dequeue);
2049 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2050 __le32 __iomem *addr, u8 major_revision)
2052 u32 temp, port_offset, port_count;
2055 if (major_revision > 0x03) {
2056 xhci_warn(xhci, "Ignoring unknown port speed, "
2057 "Ext Cap %p, revision = 0x%x\n",
2058 addr, major_revision);
2059 /* Ignoring port protocol we can't understand. FIXME */
2063 /* Port offset and count in the third dword, see section 7.2 */
2064 temp = xhci_readl(xhci, addr + 2);
2065 port_offset = XHCI_EXT_PORT_OFF(temp);
2066 port_count = XHCI_EXT_PORT_COUNT(temp);
2067 xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2068 "count = %u, revision = 0x%x\n",
2069 addr, port_offset, port_count, major_revision);
2070 /* Port count includes the current port offset */
2071 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2072 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2075 /* Check the host's USB2 LPM capability */
2076 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2077 (temp & XHCI_L1C)) {
2078 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2079 xhci->sw_lpm_support = 1;
2082 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2083 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2084 xhci->sw_lpm_support = 1;
2085 if (temp & XHCI_HLC) {
2086 xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2087 xhci->hw_lpm_support = 1;
2092 for (i = port_offset; i < (port_offset + port_count); i++) {
2093 /* Duplicate entry. Ignore the port if the revisions differ. */
2094 if (xhci->port_array[i] != 0) {
2095 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2096 " port %u\n", addr, i);
2097 xhci_warn(xhci, "Port was marked as USB %u, "
2098 "duplicated as USB %u\n",
2099 xhci->port_array[i], major_revision);
2100 /* Only adjust the roothub port counts if we haven't
2101 * found a similar duplicate.
2103 if (xhci->port_array[i] != major_revision &&
2104 xhci->port_array[i] != DUPLICATE_ENTRY) {
2105 if (xhci->port_array[i] == 0x03)
2106 xhci->num_usb3_ports--;
2108 xhci->num_usb2_ports--;
2109 xhci->port_array[i] = DUPLICATE_ENTRY;
2111 /* FIXME: Should we disable the port? */
2114 xhci->port_array[i] = major_revision;
2115 if (major_revision == 0x03)
2116 xhci->num_usb3_ports++;
2118 xhci->num_usb2_ports++;
2120 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2124 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2125 * specify what speeds each port is supposed to be. We can't count on the port
2126 * speed bits in the PORTSC register being correct until a device is connected,
2127 * but we need to set up the two fake roothubs with the correct number of USB
2128 * 3.0 and USB 2.0 ports at host controller initialization time.
2130 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2132 __le32 __iomem *addr;
2134 unsigned int num_ports;
2135 int i, j, port_index;
2137 addr = &xhci->cap_regs->hcc_params;
2138 offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2140 xhci_err(xhci, "No Extended Capability registers, "
2141 "unable to set up roothub.\n");
2145 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2146 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2147 if (!xhci->port_array)
2150 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2153 for (i = 0; i < num_ports; i++) {
2154 struct xhci_interval_bw_table *bw_table;
2156 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2157 bw_table = &xhci->rh_bw[i].bw_table;
2158 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2159 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2163 * For whatever reason, the first capability offset is from the
2164 * capability register base, not from the HCCPARAMS register.
2165 * See section 5.3.6 for offset calculation.
2167 addr = &xhci->cap_regs->hc_capbase + offset;
2171 cap_id = xhci_readl(xhci, addr);
2172 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2173 xhci_add_in_port(xhci, num_ports, addr,
2174 (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2175 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2176 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2180 * Once you're into the Extended Capabilities, the offset is
2181 * always relative to the register holding the offset.
2186 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2187 xhci_warn(xhci, "No ports on the roothubs?\n");
2190 xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2191 xhci->num_usb2_ports, xhci->num_usb3_ports);
2193 /* Place limits on the number of roothub ports so that the hub
2194 * descriptors aren't longer than the USB core will allocate.
2196 if (xhci->num_usb3_ports > 15) {
2197 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2198 xhci->num_usb3_ports = 15;
2200 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2201 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2203 xhci->num_usb2_ports = USB_MAXCHILDREN;
2207 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2208 * Not sure how the USB core will handle a hub with no ports...
2210 if (xhci->num_usb2_ports) {
2211 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2212 xhci->num_usb2_ports, flags);
2213 if (!xhci->usb2_ports)
2217 for (i = 0; i < num_ports; i++) {
2218 if (xhci->port_array[i] == 0x03 ||
2219 xhci->port_array[i] == 0 ||
2220 xhci->port_array[i] == DUPLICATE_ENTRY)
2223 xhci->usb2_ports[port_index] =
2224 &xhci->op_regs->port_status_base +
2226 xhci_dbg(xhci, "USB 2.0 port at index %u, "
2228 xhci->usb2_ports[port_index]);
2230 if (port_index == xhci->num_usb2_ports)
2234 if (xhci->num_usb3_ports) {
2235 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2236 xhci->num_usb3_ports, flags);
2237 if (!xhci->usb3_ports)
2241 for (i = 0; i < num_ports; i++)
2242 if (xhci->port_array[i] == 0x03) {
2243 xhci->usb3_ports[port_index] =
2244 &xhci->op_regs->port_status_base +
2246 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2248 xhci->usb3_ports[port_index]);
2250 if (port_index == xhci->num_usb3_ports)
2257 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2260 struct device *dev = xhci_to_hcd(xhci)->self.controller;
2261 unsigned int val, val2;
2263 struct xhci_segment *seg;
2264 u32 page_size, temp;
2267 INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2268 INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2270 page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2271 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2272 for (i = 0; i < 16; i++) {
2273 if ((0x1 & page_size) != 0)
2275 page_size = page_size >> 1;
2278 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2280 xhci_warn(xhci, "WARN: no supported page size\n");
2281 /* Use 4K pages, since that's common and the minimum the HC supports */
2282 xhci->page_shift = 12;
2283 xhci->page_size = 1 << xhci->page_shift;
2284 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2287 * Program the Number of Device Slots Enabled field in the CONFIG
2288 * register with the max value of slots the HC can handle.
2290 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2291 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2292 (unsigned int) val);
2293 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2294 val |= (val2 & ~HCS_SLOTS_MASK);
2295 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2296 (unsigned int) val);
2297 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2300 * Section 5.4.8 - doorbell array must be
2301 * "physically contiguous and 64-byte (cache line) aligned".
2303 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2307 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2308 xhci->dcbaa->dma = dma;
2309 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2310 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2311 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2314 * Initialize the ring segment pool. The ring must be a contiguous
2315 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2316 * however, the command ring segment needs 64-byte aligned segments,
2317 * so we pick the greater alignment need.
2319 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2320 TRB_SEGMENT_SIZE, 64, xhci->page_size);
2322 /* See Table 46 and Note on Figure 55 */
2323 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2324 2112, 64, xhci->page_size);
2325 if (!xhci->segment_pool || !xhci->device_pool)
2328 /* Linear stream context arrays don't have any boundary restrictions,
2329 * and only need to be 16-byte aligned.
2331 xhci->small_streams_pool =
2332 dma_pool_create("xHCI 256 byte stream ctx arrays",
2333 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2334 xhci->medium_streams_pool =
2335 dma_pool_create("xHCI 1KB stream ctx arrays",
2336 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2337 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2338 * will be allocated with dma_alloc_coherent()
2341 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2344 /* Set up the command ring to have one segments for now. */
2345 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2346 if (!xhci->cmd_ring)
2348 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2349 xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2350 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2352 /* Set the address in the Command Ring Control register */
2353 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2354 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2355 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2356 xhci->cmd_ring->cycle_state;
2357 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2358 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2359 xhci_dbg_cmd_ptrs(xhci);
2361 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2362 if (!xhci->lpm_command)
2365 /* Reserve one command ring TRB for disabling LPM.
2366 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2367 * disabling LPM, we only need to reserve one TRB for all devices.
2369 xhci->cmd_ring_reserved_trbs++;
2371 val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2373 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2374 " from cap regs base addr\n", val);
2375 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2376 xhci_dbg_regs(xhci);
2377 xhci_print_run_regs(xhci);
2378 /* Set ir_set to interrupt register set 0 */
2379 xhci->ir_set = &xhci->run_regs->ir_set[0];
2382 * Event ring setup: Allocate a normal ring, but also setup
2383 * the event ring segment table (ERST). Section 4.9.3.
2385 xhci_dbg(xhci, "// Allocating event ring\n");
2386 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2388 if (!xhci->event_ring)
2390 if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2393 xhci->erst.entries = dma_alloc_coherent(dev,
2394 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2396 if (!xhci->erst.entries)
2398 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2399 (unsigned long long)dma);
2401 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2402 xhci->erst.num_entries = ERST_NUM_SEGS;
2403 xhci->erst.erst_dma_addr = dma;
2404 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2405 xhci->erst.num_entries,
2407 (unsigned long long)xhci->erst.erst_dma_addr);
2409 /* set ring base address and size for each segment table entry */
2410 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2411 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2412 entry->seg_addr = cpu_to_le64(seg->dma);
2413 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2418 /* set ERST count with the number of entries in the segment table */
2419 val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2420 val &= ERST_SIZE_MASK;
2421 val |= ERST_NUM_SEGS;
2422 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2424 xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2426 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2427 /* set the segment table base address */
2428 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2429 (unsigned long long)xhci->erst.erst_dma_addr);
2430 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2431 val_64 &= ERST_PTR_MASK;
2432 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2433 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2435 /* Set the event ring dequeue address */
2436 xhci_set_hc_event_deq(xhci);
2437 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2438 xhci_print_ir_set(xhci, 0);
2441 * XXX: Might need to set the Interrupter Moderation Register to
2442 * something other than the default (~1ms minimum between interrupts).
2443 * See section 5.5.1.2.
2445 init_completion(&xhci->addr_dev);
2446 for (i = 0; i < MAX_HC_SLOTS; ++i)
2447 xhci->devs[i] = NULL;
2448 for (i = 0; i < USB_MAXCHILDREN; ++i) {
2449 xhci->bus_state[0].resume_done[i] = 0;
2450 xhci->bus_state[1].resume_done[i] = 0;
2453 if (scratchpad_alloc(xhci, flags))
2455 if (xhci_setup_port_arrays(xhci, flags))
2458 /* Enable USB 3.0 device notifications for function remote wake, which
2459 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2460 * U3 (device suspend).
2462 temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2463 temp &= ~DEV_NOTE_MASK;
2464 temp |= DEV_NOTE_FWAKE;
2465 xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2470 xhci_warn(xhci, "Couldn't initialize memory\n");
2473 xhci_mem_cleanup(xhci);