2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x0c, /* bLength 12, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x00, 0x00, 0x00, 0x00, /* bmAttributes, get from xhci psic */
58 0x00, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */
63 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 desc_size, ssp_cap_size, ssa_size = 0;
71 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
72 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
74 /* does xhci support USB 3.1 Enhanced SuperSpeed */
75 if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) {
76 /* two SSA entries for each unique PSI ID, one RX and one TX */
77 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
78 ssa_size = ssa_count * sizeof(u32);
79 desc_size += ssp_cap_size;
82 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
85 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
87 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
90 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
93 /* Indicate whether the host has LTM support. */
94 temp = readl(&xhci->cap_regs->hcc_params);
96 buf[8] |= USB_LTM_SUPPORT;
98 /* Set the U1 and U2 exit latencies. */
99 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
100 temp = readl(&xhci->cap_regs->hcs_params3);
101 buf[12] = HCS_U1_LATENCY(temp);
102 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
106 u32 ssp_cap_base, bm_attrib, psi;
109 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
111 if (wLength < desc_size)
113 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
115 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
116 bm_attrib = (ssa_count - 1) & 0x1f;
117 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
118 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
120 if (wLength < desc_size + ssa_size)
123 * Create the Sublink Speed Attributes (SSA) array.
124 * The xhci PSI field and USB 3.1 SSA fields are very similar,
125 * but link type bits 7:6 differ for values 01b and 10b.
126 * xhci has also only one PSI entry for a symmetric link when
127 * USB 3.1 requires two SSA entries (RX and TX) for every link
130 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
131 psi = xhci->usb3_rhub.psi[i];
132 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
133 if ((psi & PLT_MASK) == PLT_SYM) {
134 /* Symmetric, create SSA RX and TX from one PSI entry */
135 put_unaligned_le32(psi, &buf[offset]);
136 psi |= 1 << 7; /* turn entry to TX */
138 if (offset >= desc_size + ssa_size)
139 return desc_size + ssa_size;
140 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
141 /* Asymetric RX, flip bits 7:6 for SSA */
144 put_unaligned_le32(psi, &buf[offset]);
146 if (offset >= desc_size + ssa_size)
147 return desc_size + ssa_size;
150 /* ssa_size is 0 for other than usb 3.1 hosts */
151 return desc_size + ssa_size;
154 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
155 struct usb_hub_descriptor *desc, int ports)
159 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
160 desc->bHubContrCurrent = 0;
162 desc->bNbrPorts = ports;
164 /* Bits 1:0 - support per-port power switching, or power always on */
165 if (HCC_PPC(xhci->hcc_params))
166 temp |= HUB_CHAR_INDV_PORT_LPSM;
168 temp |= HUB_CHAR_NO_LPSM;
169 /* Bit 2 - root hubs are not part of a compound device */
170 /* Bits 4:3 - individual port over current protection */
171 temp |= HUB_CHAR_INDV_PORT_OCPM;
172 /* Bits 6:5 - no TTs in root ports */
173 /* Bit 7 - no port indicators */
174 desc->wHubCharacteristics = cpu_to_le16(temp);
177 /* Fill in the USB 2.0 roothub descriptor */
178 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
179 struct usb_hub_descriptor *desc)
183 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
187 ports = xhci->num_usb2_ports;
189 xhci_common_hub_descriptor(xhci, desc, ports);
190 desc->bDescriptorType = USB_DT_HUB;
191 temp = 1 + (ports / 8);
192 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
194 /* The Device Removable bits are reported on a byte granularity.
195 * If the port doesn't exist within that byte, the bit is set to 0.
197 memset(port_removable, 0, sizeof(port_removable));
198 for (i = 0; i < ports; i++) {
199 portsc = readl(xhci->usb2_ports[i]);
200 /* If a device is removable, PORTSC reports a 0, same as in the
201 * hub descriptor DeviceRemovable bits.
203 if (portsc & PORT_DEV_REMOVE)
204 /* This math is hairy because bit 0 of DeviceRemovable
205 * is reserved, and bit 1 is for port 1, etc.
207 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
210 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
211 * ports on it. The USB 2.0 specification says that there are two
212 * variable length fields at the end of the hub descriptor:
213 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
214 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
215 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
216 * 0xFF, so we initialize the both arrays (DeviceRemovable and
217 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
218 * set of ports that actually exist.
220 memset(desc->u.hs.DeviceRemovable, 0xff,
221 sizeof(desc->u.hs.DeviceRemovable));
222 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
223 sizeof(desc->u.hs.PortPwrCtrlMask));
225 for (i = 0; i < (ports + 1 + 7) / 8; i++)
226 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
230 /* Fill in the USB 3.0 roothub descriptor */
231 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
232 struct usb_hub_descriptor *desc)
239 ports = xhci->num_usb3_ports;
240 xhci_common_hub_descriptor(xhci, desc, ports);
241 desc->bDescriptorType = USB_DT_SS_HUB;
242 desc->bDescLength = USB_DT_SS_HUB_SIZE;
244 /* header decode latency should be zero for roothubs,
245 * see section 4.23.5.2.
247 desc->u.ss.bHubHdrDecLat = 0;
248 desc->u.ss.wHubDelay = 0;
251 /* bit 0 is reserved, bit 1 is for port 1, etc. */
252 for (i = 0; i < ports; i++) {
253 portsc = readl(xhci->usb3_ports[i]);
254 if (portsc & PORT_DEV_REMOVE)
255 port_removable |= 1 << (i + 1);
258 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
261 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
262 struct usb_hub_descriptor *desc)
265 if (hcd->speed >= HCD_USB3)
266 xhci_usb3_hub_descriptor(hcd, xhci, desc);
268 xhci_usb2_hub_descriptor(hcd, xhci, desc);
272 static unsigned int xhci_port_speed(unsigned int port_status)
274 if (DEV_LOWSPEED(port_status))
275 return USB_PORT_STAT_LOW_SPEED;
276 if (DEV_HIGHSPEED(port_status))
277 return USB_PORT_STAT_HIGH_SPEED;
279 * FIXME: Yes, we should check for full speed, but the core uses that as
280 * a default in portspeed() in usb/core/hub.c (which is the only place
281 * USB_PORT_STAT_*_SPEED is used).
287 * These bits are Read Only (RO) and should be saved and written to the
288 * registers: 0, 3, 10:13, 30
289 * connect status, over-current status, port speed, and device removable.
290 * connect status and port speed are also sticky - meaning they're in
291 * the AUX well and they aren't changed by a hot, warm, or cold reset.
293 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
295 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
296 * bits 5:8, 9, 14:15, 25:27
297 * link state, port power, port indicator state, "wake on" enable state
299 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
301 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
304 #define XHCI_PORT_RW1S ((1<<4))
306 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
307 * bits 1, 17, 18, 19, 20, 21, 22, 23
308 * port enable/disable, and
309 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
310 * over-current, reset, link state, and L1 change
312 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
314 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
317 #define XHCI_PORT_RW ((1<<16))
319 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
322 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
325 * Given a port state, this function returns a value that would result in the
326 * port being in the same state, if the value was written to the port status
328 * Save Read Only (RO) bits and save read/write bits where
329 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
330 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
332 u32 xhci_port_state_to_neutral(u32 state)
334 /* Save read-only status and port state */
335 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
339 * find slot id based on port number.
340 * @port: The one-based port number from one of the two split roothubs.
342 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
347 enum usb_device_speed speed;
350 for (i = 0; i < MAX_HC_SLOTS; i++) {
353 speed = xhci->devs[i]->udev->speed;
354 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
355 && xhci->devs[i]->fake_port == port) {
366 * It issues stop endpoint command for EP 0 to 30. And wait the last command
368 * suspend will set to 1, if suspend bit need to set in command.
370 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
372 struct xhci_virt_device *virt_dev;
373 struct xhci_command *cmd;
379 virt_dev = xhci->devs[slot_id];
383 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
385 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
389 spin_lock_irqsave(&xhci->lock, flags);
390 for (i = LAST_EP_INDEX; i > 0; i--) {
391 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
392 struct xhci_command *command;
393 command = xhci_alloc_command(xhci, false, false,
396 spin_unlock_irqrestore(&xhci->lock, flags);
397 xhci_free_command(xhci, cmd);
401 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
405 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
406 xhci_ring_cmd_db(xhci);
407 spin_unlock_irqrestore(&xhci->lock, flags);
409 /* Wait for last stop endpoint command to finish */
410 wait_for_completion(cmd->completion);
412 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
413 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
416 xhci_free_command(xhci, cmd);
421 * Ring device, it rings the all doorbells unconditionally.
423 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
426 struct xhci_virt_ep *ep;
428 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
429 ep = &xhci->devs[slot_id]->eps[i];
431 if (ep->ep_state & EP_HAS_STREAMS) {
432 for (s = 1; s < ep->stream_info->num_streams; s++)
433 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
434 } else if (ep->ring && ep->ring->dequeue) {
435 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
442 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
443 u16 wIndex, __le32 __iomem *addr, u32 port_status)
445 /* Don't allow the USB core to disable SuperSpeed ports. */
446 if (hcd->speed >= HCD_USB3) {
447 xhci_dbg(xhci, "Ignoring request to disable "
448 "SuperSpeed port.\n");
452 /* Write 1 to disable the port */
453 writel(port_status | PORT_PE, addr);
454 port_status = readl(addr);
455 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
456 wIndex, port_status);
459 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
460 u16 wIndex, __le32 __iomem *addr, u32 port_status)
462 char *port_change_bit;
466 case USB_PORT_FEAT_C_RESET:
468 port_change_bit = "reset";
470 case USB_PORT_FEAT_C_BH_PORT_RESET:
472 port_change_bit = "warm(BH) reset";
474 case USB_PORT_FEAT_C_CONNECTION:
476 port_change_bit = "connect";
478 case USB_PORT_FEAT_C_OVER_CURRENT:
480 port_change_bit = "over-current";
482 case USB_PORT_FEAT_C_ENABLE:
484 port_change_bit = "enable/disable";
486 case USB_PORT_FEAT_C_SUSPEND:
488 port_change_bit = "suspend/resume";
490 case USB_PORT_FEAT_C_PORT_LINK_STATE:
492 port_change_bit = "link state";
494 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
496 port_change_bit = "config error";
499 /* Should never happen */
502 /* Change bits are all write 1 to clear */
503 writel(port_status | status, addr);
504 port_status = readl(addr);
505 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
506 port_change_bit, wIndex, port_status);
509 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
512 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
514 if (hcd->speed >= HCD_USB3) {
515 max_ports = xhci->num_usb3_ports;
516 *port_array = xhci->usb3_ports;
518 max_ports = xhci->num_usb2_ports;
519 *port_array = xhci->usb2_ports;
525 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
526 int port_id, u32 link_state)
530 temp = readl(port_array[port_id]);
531 temp = xhci_port_state_to_neutral(temp);
532 temp &= ~PORT_PLS_MASK;
533 temp |= PORT_LINK_STROBE | link_state;
534 writel(temp, port_array[port_id]);
537 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
538 __le32 __iomem **port_array, int port_id, u16 wake_mask)
542 temp = readl(port_array[port_id]);
543 temp = xhci_port_state_to_neutral(temp);
545 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
546 temp |= PORT_WKCONN_E;
548 temp &= ~PORT_WKCONN_E;
550 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
551 temp |= PORT_WKDISC_E;
553 temp &= ~PORT_WKDISC_E;
555 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
558 temp &= ~PORT_WKOC_E;
560 writel(temp, port_array[port_id]);
563 /* Test and clear port RWC bit */
564 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
565 int port_id, u32 port_bit)
569 temp = readl(port_array[port_id]);
570 if (temp & port_bit) {
571 temp = xhci_port_state_to_neutral(temp);
573 writel(temp, port_array[port_id]);
577 /* Updates Link Status for USB 2.1 port */
578 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
580 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
581 *status |= USB_PORT_STAT_L1;
584 /* Updates Link Status for super Speed port */
585 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
586 u32 *status, u32 status_reg)
588 u32 pls = status_reg & PORT_PLS_MASK;
590 /* resume state is a xHCI internal state.
591 * Do not report it to usb core, instead, pretend to be U3,
592 * thus usb core knows it's not ready for transfer
594 if (pls == XDEV_RESUME) {
595 *status |= USB_SS_PORT_LS_U3;
599 /* When the CAS bit is set then warm reset
600 * should be performed on port
602 if (status_reg & PORT_CAS) {
603 /* The CAS bit can be set while the port is
605 * Only roothubs have CAS bit, so we
606 * pretend to be in compliance mode
607 * unless we're already in compliance
608 * or the inactive state.
610 if (pls != USB_SS_PORT_LS_COMP_MOD &&
611 pls != USB_SS_PORT_LS_SS_INACTIVE) {
612 pls = USB_SS_PORT_LS_COMP_MOD;
614 /* Return also connection bit -
615 * hub state machine resets port
616 * when this bit is set.
618 pls |= USB_PORT_STAT_CONNECTION;
621 * If CAS bit isn't set but the Port is already at
622 * Compliance Mode, fake a connection so the USB core
623 * notices the Compliance state and resets the port.
624 * This resolves an issue generated by the SN65LVPE502CP
625 * in which sometimes the port enters compliance mode
626 * caused by a delay on the host-device negotiation.
628 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
629 (pls == USB_SS_PORT_LS_COMP_MOD))
630 pls |= USB_PORT_STAT_CONNECTION;
633 /* update status field */
638 * Function for Compliance Mode Quirk.
640 * This Function verifies if all xhc USB3 ports have entered U0, if so,
641 * the compliance mode timer is deleted. A port won't enter
642 * compliance mode if it has previously entered U0.
644 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
647 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
648 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
650 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
653 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
654 xhci->port_status_u0 |= 1 << wIndex;
655 if (xhci->port_status_u0 == all_ports_seen_u0) {
656 del_timer_sync(&xhci->comp_mode_recovery_timer);
657 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
658 "All USB3 ports have entered U0 already!");
659 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
660 "Compliance Mode Recovery Timer Deleted.");
665 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
670 /* only support rx and tx lane counts of 1 in usb3.1 spec */
671 speed_id = DEV_PORT_SPEED(raw_port_status);
672 ext_stat |= speed_id; /* bits 3:0, RX speed id */
673 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
675 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
676 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
682 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
685 * Possible side effects:
686 * - Mark a port as being done with device resume,
687 * and ring the endpoint doorbells.
688 * - Stop the Synopsys redriver Compliance Mode polling.
689 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
691 static u32 xhci_get_port_status(struct usb_hcd *hcd,
692 struct xhci_bus_state *bus_state,
693 __le32 __iomem **port_array,
694 u16 wIndex, u32 raw_port_status,
696 __releases(&xhci->lock)
697 __acquires(&xhci->lock)
699 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
703 /* wPortChange bits */
704 if (raw_port_status & PORT_CSC)
705 status |= USB_PORT_STAT_C_CONNECTION << 16;
706 if (raw_port_status & PORT_PEC)
707 status |= USB_PORT_STAT_C_ENABLE << 16;
708 if ((raw_port_status & PORT_OCC))
709 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
710 if ((raw_port_status & PORT_RC))
711 status |= USB_PORT_STAT_C_RESET << 16;
713 if (hcd->speed >= HCD_USB3) {
714 /* Port link change with port in resume state should not be
715 * reported to usbcore, as this is an internal state to be
716 * handled by xhci driver. Reporting PLC to usbcore may
717 * cause usbcore clearing PLC first and port change event
718 * irq won't be generated.
720 if ((raw_port_status & PORT_PLC) &&
721 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
722 status |= USB_PORT_STAT_C_LINK_STATE << 16;
723 if ((raw_port_status & PORT_WRC))
724 status |= USB_PORT_STAT_C_BH_RESET << 16;
725 if ((raw_port_status & PORT_CEC))
726 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
729 if (hcd->speed < HCD_USB3) {
730 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
731 && (raw_port_status & PORT_POWER))
732 status |= USB_PORT_STAT_SUSPEND;
734 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
735 !DEV_SUPERSPEED_ANY(raw_port_status)) {
736 if ((raw_port_status & PORT_RESET) ||
737 !(raw_port_status & PORT_PE))
739 /* did port event handler already start resume timing? */
740 if (!bus_state->resume_done[wIndex]) {
741 /* If not, maybe we are in a host initated resume? */
742 if (test_bit(wIndex, &bus_state->resuming_ports)) {
743 /* Host initated resume doesn't time the resume
744 * signalling using resume_done[].
745 * It manually sets RESUME state, sleeps 20ms
746 * and sets U0 state. This should probably be
747 * changed, but not right now.
750 /* port resume was discovered now and here,
751 * start resume timing
753 unsigned long timeout = jiffies +
754 msecs_to_jiffies(USB_RESUME_TIMEOUT);
756 set_bit(wIndex, &bus_state->resuming_ports);
757 bus_state->resume_done[wIndex] = timeout;
758 mod_timer(&hcd->rh_timer, timeout);
760 /* Has resume been signalled for USB_RESUME_TIME yet? */
761 } else if (time_after_eq(jiffies,
762 bus_state->resume_done[wIndex])) {
765 xhci_dbg(xhci, "Resume USB2 port %d\n",
767 bus_state->resume_done[wIndex] = 0;
768 clear_bit(wIndex, &bus_state->resuming_ports);
770 set_bit(wIndex, &bus_state->rexit_ports);
771 xhci_set_link_state(xhci, port_array, wIndex,
774 spin_unlock_irqrestore(&xhci->lock, flags);
775 time_left = wait_for_completion_timeout(
776 &bus_state->rexit_done[wIndex],
778 XHCI_MAX_REXIT_TIMEOUT));
779 spin_lock_irqsave(&xhci->lock, flags);
782 slot_id = xhci_find_slot_id_by_port(hcd,
785 xhci_dbg(xhci, "slot_id is zero\n");
788 xhci_ring_device(xhci, slot_id);
790 int port_status = readl(port_array[wIndex]);
791 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
792 XHCI_MAX_REXIT_TIMEOUT,
794 status |= USB_PORT_STAT_SUSPEND;
795 clear_bit(wIndex, &bus_state->rexit_ports);
798 bus_state->port_c_suspend |= 1 << wIndex;
799 bus_state->suspended_ports &= ~(1 << wIndex);
802 * The resume has been signaling for less than
803 * USB_RESUME_TIME. Report the port status as SUSPEND,
804 * let the usbcore check port status again and clear
805 * resume signaling later.
807 status |= USB_PORT_STAT_SUSPEND;
811 * Clear stale usb2 resume signalling variables in case port changed
812 * state during resume signalling. For example on error
814 if ((bus_state->resume_done[wIndex] ||
815 test_bit(wIndex, &bus_state->resuming_ports)) &&
816 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
817 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
818 bus_state->resume_done[wIndex] = 0;
819 clear_bit(wIndex, &bus_state->resuming_ports);
823 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
824 (raw_port_status & PORT_POWER)) {
825 if (bus_state->suspended_ports & (1 << wIndex)) {
826 bus_state->suspended_ports &= ~(1 << wIndex);
827 if (hcd->speed < HCD_USB3)
828 bus_state->port_c_suspend |= 1 << wIndex;
830 bus_state->resume_done[wIndex] = 0;
831 clear_bit(wIndex, &bus_state->resuming_ports);
833 if (raw_port_status & PORT_CONNECT) {
834 status |= USB_PORT_STAT_CONNECTION;
835 status |= xhci_port_speed(raw_port_status);
837 if (raw_port_status & PORT_PE)
838 status |= USB_PORT_STAT_ENABLE;
839 if (raw_port_status & PORT_OC)
840 status |= USB_PORT_STAT_OVERCURRENT;
841 if (raw_port_status & PORT_RESET)
842 status |= USB_PORT_STAT_RESET;
843 if (raw_port_status & PORT_POWER) {
844 if (hcd->speed >= HCD_USB3)
845 status |= USB_SS_PORT_STAT_POWER;
847 status |= USB_PORT_STAT_POWER;
849 /* Update Port Link State */
850 if (hcd->speed >= HCD_USB3) {
851 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
853 * Verify if all USB3 Ports Have entered U0 already.
854 * Delete Compliance Mode Timer if so.
856 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
858 xhci_hub_report_usb2_link_state(&status, raw_port_status);
860 if (bus_state->port_c_suspend & (1 << wIndex))
861 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
866 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
867 u16 wIndex, char *buf, u16 wLength)
869 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
874 __le32 __iomem **port_array;
876 struct xhci_bus_state *bus_state;
881 max_ports = xhci_get_ports(hcd, &port_array);
882 bus_state = &xhci->bus_state[hcd_index(hcd)];
884 spin_lock_irqsave(&xhci->lock, flags);
887 /* No power source, over-current reported per port */
890 case GetHubDescriptor:
891 /* Check to make sure userspace is asking for the USB 3.0 hub
892 * descriptor for the USB 3.0 roothub. If not, we stall the
893 * endpoint, like external hubs do.
895 if (hcd->speed >= HCD_USB3 &&
896 (wLength < USB_DT_SS_HUB_SIZE ||
897 wValue != (USB_DT_SS_HUB << 8))) {
898 xhci_dbg(xhci, "Wrong hub descriptor type for "
899 "USB 3.0 roothub.\n");
902 xhci_hub_descriptor(hcd, xhci,
903 (struct usb_hub_descriptor *) buf);
905 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
906 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
909 if (hcd->speed < HCD_USB3)
912 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
913 spin_unlock_irqrestore(&xhci->lock, flags);
916 if (!wIndex || wIndex > max_ports)
919 temp = readl(port_array[wIndex]);
920 if (temp == 0xffffffff) {
924 status = xhci_get_port_status(hcd, bus_state, port_array,
925 wIndex, temp, flags);
926 if (status == 0xffffffff)
929 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
931 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
933 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
934 /* if USB 3.1 extended port status return additional 4 bytes */
935 if (wValue == 0x02) {
938 if (hcd->speed < HCD_USB31 || wLength != 8) {
939 xhci_err(xhci, "get ext port status invalid parameter\n");
943 port_li = readl(port_array[wIndex] + PORTLI);
944 status = xhci_get_ext_port_status(temp, port_li);
945 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
949 if (wValue == USB_PORT_FEAT_LINK_STATE)
950 link_state = (wIndex & 0xff00) >> 3;
951 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
952 wake_mask = wIndex & 0xff00;
953 /* The MSB of wIndex is the U1/U2 timeout */
954 timeout = (wIndex & 0xff00) >> 8;
956 if (!wIndex || wIndex > max_ports)
959 temp = readl(port_array[wIndex]);
960 if (temp == 0xffffffff) {
964 temp = xhci_port_state_to_neutral(temp);
965 /* FIXME: What new port features do we need to support? */
967 case USB_PORT_FEAT_SUSPEND:
968 temp = readl(port_array[wIndex]);
969 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
970 /* Resume the port to U0 first */
971 xhci_set_link_state(xhci, port_array, wIndex,
973 spin_unlock_irqrestore(&xhci->lock, flags);
975 spin_lock_irqsave(&xhci->lock, flags);
977 /* In spec software should not attempt to suspend
978 * a port unless the port reports that it is in the
979 * enabled (PED = ‘1’,PLS < ‘3’) state.
981 temp = readl(port_array[wIndex]);
982 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
983 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
984 xhci_warn(xhci, "USB core suspending device "
985 "not in U0/U1/U2.\n");
989 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
992 xhci_warn(xhci, "slot_id is zero\n");
995 /* unlock to execute stop endpoint commands */
996 spin_unlock_irqrestore(&xhci->lock, flags);
997 xhci_stop_device(xhci, slot_id, 1);
998 spin_lock_irqsave(&xhci->lock, flags);
1000 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1002 spin_unlock_irqrestore(&xhci->lock, flags);
1003 msleep(10); /* wait device to enter */
1004 spin_lock_irqsave(&xhci->lock, flags);
1006 temp = readl(port_array[wIndex]);
1007 bus_state->suspended_ports |= 1 << wIndex;
1009 case USB_PORT_FEAT_LINK_STATE:
1010 temp = readl(port_array[wIndex]);
1013 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1014 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1015 temp = xhci_port_state_to_neutral(temp);
1017 * Clear all change bits, so that we get a new
1020 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1021 PORT_OCC | PORT_RC | PORT_PLC |
1023 writel(temp | PORT_PE, port_array[wIndex]);
1024 temp = readl(port_array[wIndex]);
1028 /* Put link in RxDetect (enable port) */
1029 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1030 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1031 xhci_set_link_state(xhci, port_array, wIndex,
1033 temp = readl(port_array[wIndex]);
1037 /* Software should not attempt to set
1038 * port link state above '3' (U3) and the port
1041 if ((temp & PORT_PE) == 0 ||
1042 (link_state > USB_SS_PORT_LS_U3)) {
1043 xhci_warn(xhci, "Cannot set link state.\n");
1047 if (link_state == USB_SS_PORT_LS_U3) {
1048 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1051 /* unlock to execute stop endpoint
1053 spin_unlock_irqrestore(&xhci->lock,
1055 xhci_stop_device(xhci, slot_id, 1);
1056 spin_lock_irqsave(&xhci->lock, flags);
1060 xhci_set_link_state(xhci, port_array, wIndex,
1063 spin_unlock_irqrestore(&xhci->lock, flags);
1064 msleep(20); /* wait device to enter */
1065 spin_lock_irqsave(&xhci->lock, flags);
1067 temp = readl(port_array[wIndex]);
1068 if (link_state == USB_SS_PORT_LS_U3)
1069 bus_state->suspended_ports |= 1 << wIndex;
1071 case USB_PORT_FEAT_POWER:
1073 * Turn on ports, even if there isn't per-port switching.
1074 * HC will report connect events even before this is set.
1075 * However, hub_wq will ignore the roothub events until
1076 * the roothub is registered.
1078 writel(temp | PORT_POWER, port_array[wIndex]);
1080 temp = readl(port_array[wIndex]);
1081 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1083 spin_unlock_irqrestore(&xhci->lock, flags);
1084 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1087 usb_acpi_set_power_state(hcd->self.root_hub,
1089 spin_lock_irqsave(&xhci->lock, flags);
1091 case USB_PORT_FEAT_RESET:
1092 temp = (temp | PORT_RESET);
1093 writel(temp, port_array[wIndex]);
1095 temp = readl(port_array[wIndex]);
1096 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1098 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1099 xhci_set_remote_wake_mask(xhci, port_array,
1101 temp = readl(port_array[wIndex]);
1102 xhci_dbg(xhci, "set port remote wake mask, "
1103 "actual port %d status = 0x%x\n",
1106 case USB_PORT_FEAT_BH_PORT_RESET:
1108 writel(temp, port_array[wIndex]);
1110 temp = readl(port_array[wIndex]);
1112 case USB_PORT_FEAT_U1_TIMEOUT:
1113 if (hcd->speed < HCD_USB3)
1115 temp = readl(port_array[wIndex] + PORTPMSC);
1116 temp &= ~PORT_U1_TIMEOUT_MASK;
1117 temp |= PORT_U1_TIMEOUT(timeout);
1118 writel(temp, port_array[wIndex] + PORTPMSC);
1120 case USB_PORT_FEAT_U2_TIMEOUT:
1121 if (hcd->speed < HCD_USB3)
1123 temp = readl(port_array[wIndex] + PORTPMSC);
1124 temp &= ~PORT_U2_TIMEOUT_MASK;
1125 temp |= PORT_U2_TIMEOUT(timeout);
1126 writel(temp, port_array[wIndex] + PORTPMSC);
1131 /* unblock any posted writes */
1132 temp = readl(port_array[wIndex]);
1134 case ClearPortFeature:
1135 if (!wIndex || wIndex > max_ports)
1138 temp = readl(port_array[wIndex]);
1139 if (temp == 0xffffffff) {
1143 /* FIXME: What new port features do we need to support? */
1144 temp = xhci_port_state_to_neutral(temp);
1146 case USB_PORT_FEAT_SUSPEND:
1147 temp = readl(port_array[wIndex]);
1148 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1149 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1150 if (temp & PORT_RESET)
1152 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1153 if ((temp & PORT_PE) == 0)
1156 set_bit(wIndex, &bus_state->resuming_ports);
1157 xhci_set_link_state(xhci, port_array, wIndex,
1159 spin_unlock_irqrestore(&xhci->lock, flags);
1160 msleep(USB_RESUME_TIMEOUT);
1161 spin_lock_irqsave(&xhci->lock, flags);
1162 xhci_set_link_state(xhci, port_array, wIndex,
1164 clear_bit(wIndex, &bus_state->resuming_ports);
1166 bus_state->port_c_suspend |= 1 << wIndex;
1168 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1171 xhci_dbg(xhci, "slot_id is zero\n");
1174 xhci_ring_device(xhci, slot_id);
1176 case USB_PORT_FEAT_C_SUSPEND:
1177 bus_state->port_c_suspend &= ~(1 << wIndex);
1178 case USB_PORT_FEAT_C_RESET:
1179 case USB_PORT_FEAT_C_BH_PORT_RESET:
1180 case USB_PORT_FEAT_C_CONNECTION:
1181 case USB_PORT_FEAT_C_OVER_CURRENT:
1182 case USB_PORT_FEAT_C_ENABLE:
1183 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1184 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1185 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1186 port_array[wIndex], temp);
1188 case USB_PORT_FEAT_ENABLE:
1189 xhci_disable_port(hcd, xhci, wIndex,
1190 port_array[wIndex], temp);
1192 case USB_PORT_FEAT_POWER:
1193 writel(temp & ~PORT_POWER, port_array[wIndex]);
1195 spin_unlock_irqrestore(&xhci->lock, flags);
1196 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1199 usb_acpi_set_power_state(hcd->self.root_hub,
1201 spin_lock_irqsave(&xhci->lock, flags);
1209 /* "stall" on error */
1212 spin_unlock_irqrestore(&xhci->lock, flags);
1217 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1218 * Ports are 0-indexed from the HCD point of view,
1219 * and 1-indexed from the USB core pointer of view.
1221 * Note that the status change bits will be cleared as soon as a port status
1222 * change event is generated, so we use the saved status from that event.
1224 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1226 unsigned long flags;
1230 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1232 __le32 __iomem **port_array;
1233 struct xhci_bus_state *bus_state;
1234 bool reset_change = false;
1236 max_ports = xhci_get_ports(hcd, &port_array);
1237 bus_state = &xhci->bus_state[hcd_index(hcd)];
1239 /* Initial status is no changes */
1240 retval = (max_ports + 8) / 8;
1241 memset(buf, 0, retval);
1244 * Inform the usbcore about resume-in-progress by returning
1245 * a non-zero value even if there are no status changes.
1247 status = bus_state->resuming_ports;
1249 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1251 spin_lock_irqsave(&xhci->lock, flags);
1252 /* For each port, did anything change? If so, set that bit in buf. */
1253 for (i = 0; i < max_ports; i++) {
1254 temp = readl(port_array[i]);
1255 if (temp == 0xffffffff) {
1259 if ((temp & mask) != 0 ||
1260 (bus_state->port_c_suspend & 1 << i) ||
1261 (bus_state->resume_done[i] && time_after_eq(
1262 jiffies, bus_state->resume_done[i]))) {
1263 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1266 if ((temp & PORT_RC))
1267 reset_change = true;
1269 if (!status && !reset_change) {
1270 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1271 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1273 spin_unlock_irqrestore(&xhci->lock, flags);
1274 return status ? retval : 0;
1279 int xhci_bus_suspend(struct usb_hcd *hcd)
1281 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1282 int max_ports, port_index;
1283 __le32 __iomem **port_array;
1284 struct xhci_bus_state *bus_state;
1285 unsigned long flags;
1287 max_ports = xhci_get_ports(hcd, &port_array);
1288 bus_state = &xhci->bus_state[hcd_index(hcd)];
1290 spin_lock_irqsave(&xhci->lock, flags);
1292 if (hcd->self.root_hub->do_remote_wakeup) {
1293 if (bus_state->resuming_ports || /* USB2 */
1294 bus_state->port_remote_wakeup) { /* USB3 */
1295 spin_unlock_irqrestore(&xhci->lock, flags);
1296 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1301 port_index = max_ports;
1302 bus_state->bus_suspended = 0;
1303 while (port_index--) {
1304 /* suspend the port if the port is not suspended */
1308 t1 = readl(port_array[port_index]);
1309 t2 = xhci_port_state_to_neutral(t1);
1311 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1312 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1313 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1316 spin_unlock_irqrestore(&xhci->lock, flags);
1317 xhci_stop_device(xhci, slot_id, 1);
1318 spin_lock_irqsave(&xhci->lock, flags);
1320 t2 &= ~PORT_PLS_MASK;
1321 t2 |= PORT_LINK_STROBE | XDEV_U3;
1322 set_bit(port_index, &bus_state->bus_suspended);
1324 /* USB core sets remote wake mask for USB 3.0 hubs,
1325 * including the USB 3.0 roothub, but only if CONFIG_PM
1326 * is enabled, so also enable remote wake here.
1328 if (hcd->self.root_hub->do_remote_wakeup) {
1329 if (t1 & PORT_CONNECT) {
1330 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1331 t2 &= ~PORT_WKCONN_E;
1333 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1334 t2 &= ~PORT_WKDISC_E;
1337 t2 &= ~PORT_WAKE_BITS;
1339 t1 = xhci_port_state_to_neutral(t1);
1341 writel(t2, port_array[port_index]);
1343 hcd->state = HC_STATE_SUSPENDED;
1344 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1345 spin_unlock_irqrestore(&xhci->lock, flags);
1350 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1351 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1352 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1354 static bool xhci_port_missing_cas_quirk(int port_index,
1355 __le32 __iomem **port_array)
1359 portsc = readl(port_array[port_index]);
1361 /* if any of these are set we are not stuck */
1362 if (portsc & (PORT_CONNECT | PORT_CAS))
1365 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1366 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1369 /* clear wakeup/change bits, and do a warm port reset */
1370 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1372 writel(portsc, port_array[port_index]);
1374 readl(port_array[port_index]);
1378 int xhci_bus_resume(struct usb_hcd *hcd)
1380 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1381 int max_ports, port_index;
1382 __le32 __iomem **port_array;
1383 struct xhci_bus_state *bus_state;
1385 unsigned long flags;
1386 unsigned long port_was_suspended = 0;
1387 bool need_usb2_u3_exit = false;
1391 max_ports = xhci_get_ports(hcd, &port_array);
1392 bus_state = &xhci->bus_state[hcd_index(hcd)];
1394 if (time_before(jiffies, bus_state->next_statechange))
1397 spin_lock_irqsave(&xhci->lock, flags);
1398 if (!HCD_HW_ACCESSIBLE(hcd)) {
1399 spin_unlock_irqrestore(&xhci->lock, flags);
1403 /* delay the irqs */
1404 temp = readl(&xhci->op_regs->command);
1406 writel(temp, &xhci->op_regs->command);
1408 port_index = max_ports;
1409 while (port_index--) {
1410 /* Check whether need resume ports. If needed
1411 resume port and disable remote wakeup */
1414 temp = readl(port_array[port_index]);
1416 /* warm reset CAS limited ports stuck in polling/compliance */
1417 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1418 (hcd->speed >= HCD_USB3) &&
1419 xhci_port_missing_cas_quirk(port_index, port_array)) {
1420 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1423 if (DEV_SUPERSPEED_ANY(temp))
1424 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1426 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1427 if (test_bit(port_index, &bus_state->bus_suspended) &&
1428 (temp & PORT_PLS_MASK)) {
1429 set_bit(port_index, &port_was_suspended);
1430 if (!DEV_SUPERSPEED_ANY(temp)) {
1431 xhci_set_link_state(xhci, port_array,
1432 port_index, XDEV_RESUME);
1433 need_usb2_u3_exit = true;
1436 writel(temp, port_array[port_index]);
1439 if (need_usb2_u3_exit) {
1440 spin_unlock_irqrestore(&xhci->lock, flags);
1441 msleep(USB_RESUME_TIMEOUT);
1442 spin_lock_irqsave(&xhci->lock, flags);
1445 port_index = max_ports;
1446 while (port_index--) {
1447 if (!(port_was_suspended & BIT(port_index)))
1449 /* Clear PLC to poll it later after XDEV_U0 */
1450 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1451 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1454 port_index = max_ports;
1455 while (port_index--) {
1456 if (!(port_was_suspended & BIT(port_index)))
1458 /* Poll and Clear PLC */
1459 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1460 PORT_PLC, 10 * 1000);
1462 xhci_warn(xhci, "port %d resume PLC timeout\n",
1464 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1465 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1467 xhci_ring_device(xhci, slot_id);
1470 (void) readl(&xhci->op_regs->command);
1472 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1473 /* re-enable irqs */
1474 temp = readl(&xhci->op_regs->command);
1476 writel(temp, &xhci->op_regs->command);
1477 temp = readl(&xhci->op_regs->command);
1479 spin_unlock_irqrestore(&xhci->lock, flags);
1483 #endif /* CONFIG_PM */