2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
27 #include "xhci-trace.h"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
30 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
31 PORT_RC | PORT_PLC | PORT_PE)
33 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
34 static u8 usb_bos_descriptor [] = {
35 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
36 USB_DT_BOS, /* __u8 bDescriptorType */
37 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
38 0x1, /* __u8 bNumDeviceCaps */
39 /* First device capability */
40 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
41 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
42 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
43 0x00, /* bmAttributes, LTM off by default */
44 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
45 0x03, /* bFunctionalitySupport,
47 0x00, /* bU1DevExitLat, set later. */
48 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
52 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
53 struct usb_hub_descriptor *desc, int ports)
57 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
58 desc->bHubContrCurrent = 0;
60 desc->bNbrPorts = ports;
62 /* Bits 1:0 - support per-port power switching, or power always on */
63 if (HCC_PPC(xhci->hcc_params))
64 temp |= HUB_CHAR_INDV_PORT_LPSM;
66 temp |= HUB_CHAR_NO_LPSM;
67 /* Bit 2 - root hubs are not part of a compound device */
68 /* Bits 4:3 - individual port over current protection */
69 temp |= HUB_CHAR_INDV_PORT_OCPM;
70 /* Bits 6:5 - no TTs in root ports */
71 /* Bit 7 - no port indicators */
72 desc->wHubCharacteristics = cpu_to_le16(temp);
75 /* Fill in the USB 2.0 roothub descriptor */
76 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
77 struct usb_hub_descriptor *desc)
81 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
85 ports = xhci->num_usb2_ports;
87 xhci_common_hub_descriptor(xhci, desc, ports);
88 desc->bDescriptorType = USB_DT_HUB;
89 temp = 1 + (ports / 8);
90 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
92 /* The Device Removable bits are reported on a byte granularity.
93 * If the port doesn't exist within that byte, the bit is set to 0.
95 memset(port_removable, 0, sizeof(port_removable));
96 for (i = 0; i < ports; i++) {
97 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
98 /* If a device is removable, PORTSC reports a 0, same as in the
99 * hub descriptor DeviceRemovable bits.
101 if (portsc & PORT_DEV_REMOVE)
102 /* This math is hairy because bit 0 of DeviceRemovable
103 * is reserved, and bit 1 is for port 1, etc.
105 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
108 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
109 * ports on it. The USB 2.0 specification says that there are two
110 * variable length fields at the end of the hub descriptor:
111 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
112 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
113 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
114 * 0xFF, so we initialize the both arrays (DeviceRemovable and
115 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
116 * set of ports that actually exist.
118 memset(desc->u.hs.DeviceRemovable, 0xff,
119 sizeof(desc->u.hs.DeviceRemovable));
120 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
121 sizeof(desc->u.hs.PortPwrCtrlMask));
123 for (i = 0; i < (ports + 1 + 7) / 8; i++)
124 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
128 /* Fill in the USB 3.0 roothub descriptor */
129 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
130 struct usb_hub_descriptor *desc)
137 ports = xhci->num_usb3_ports;
138 xhci_common_hub_descriptor(xhci, desc, ports);
139 desc->bDescriptorType = USB_DT_SS_HUB;
140 desc->bDescLength = USB_DT_SS_HUB_SIZE;
142 /* header decode latency should be zero for roothubs,
143 * see section 4.23.5.2.
145 desc->u.ss.bHubHdrDecLat = 0;
146 desc->u.ss.wHubDelay = 0;
149 /* bit 0 is reserved, bit 1 is for port 1, etc. */
150 for (i = 0; i < ports; i++) {
151 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
152 if (portsc & PORT_DEV_REMOVE)
153 port_removable |= 1 << (i + 1);
156 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
170 static unsigned int xhci_port_speed(unsigned int port_status)
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
191 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
197 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
202 #define XHCI_PORT_RW1S ((1<<4))
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
215 #define XHCI_PORT_RW ((1<<16))
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
220 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
230 u32 xhci_port_state_to_neutral(u32 state)
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
245 enum usb_device_speed speed;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
266 * suspend will set to 1, if suspend bit need to set in command.
268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
299 USB_CTRL_SET_TIMEOUT);
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
311 goto command_cleanup;
315 xhci_free_command(xhci, cmd);
320 * Ring device, it rings the all doorbells unconditionally.
322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
354 char *port_change_bit;
358 case USB_PORT_FEAT_C_RESET:
360 port_change_bit = "reset";
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
364 port_change_bit = "warm(BH) reset";
366 case USB_PORT_FEAT_C_CONNECTION:
368 port_change_bit = "connect";
370 case USB_PORT_FEAT_C_OVER_CURRENT:
372 port_change_bit = "over-current";
374 case USB_PORT_FEAT_C_ENABLE:
376 port_change_bit = "enable/disable";
378 case USB_PORT_FEAT_C_SUSPEND:
380 port_change_bit = "suspend/resume";
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
384 port_change_bit = "link state";
387 /* Should never happen */
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
425 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
436 temp &= ~PORT_WKCONN_E;
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
441 temp &= ~PORT_WKDISC_E;
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
446 temp &= ~PORT_WKOC_E;
448 xhci_writel(xhci, temp, port_array[port_id]);
451 /* Test and clear port RWC bit */
452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
461 xhci_writel(xhci, temp, port_array[port_id]);
465 /* Updates Link Status for USB 2.1 port */
466 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
468 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
469 *status |= USB_PORT_STAT_L1;
472 /* Updates Link Status for super Speed port */
473 static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
475 u32 pls = status_reg & PORT_PLS_MASK;
477 /* resume state is a xHCI internal state.
478 * Do not report it to usb core.
480 if (pls == XDEV_RESUME)
483 /* When the CAS bit is set then warm reset
484 * should be performed on port
486 if (status_reg & PORT_CAS) {
487 /* The CAS bit can be set while the port is
489 * Only roothubs have CAS bit, so we
490 * pretend to be in compliance mode
491 * unless we're already in compliance
492 * or the inactive state.
494 if (pls != USB_SS_PORT_LS_COMP_MOD &&
495 pls != USB_SS_PORT_LS_SS_INACTIVE) {
496 pls = USB_SS_PORT_LS_COMP_MOD;
498 /* Return also connection bit -
499 * hub state machine resets port
500 * when this bit is set.
502 pls |= USB_PORT_STAT_CONNECTION;
505 * If CAS bit isn't set but the Port is already at
506 * Compliance Mode, fake a connection so the USB core
507 * notices the Compliance state and resets the port.
508 * This resolves an issue generated by the SN65LVPE502CP
509 * in which sometimes the port enters compliance mode
510 * caused by a delay on the host-device negotiation.
512 if (pls == USB_SS_PORT_LS_COMP_MOD)
513 pls |= USB_PORT_STAT_CONNECTION;
516 /* update status field */
521 * Function for Compliance Mode Quirk.
523 * This Function verifies if all xhc USB3 ports have entered U0, if so,
524 * the compliance mode timer is deleted. A port won't enter
525 * compliance mode if it has previously entered U0.
527 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
529 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
530 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
532 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
535 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
536 xhci->port_status_u0 |= 1 << wIndex;
537 if (xhci->port_status_u0 == all_ports_seen_u0) {
538 del_timer_sync(&xhci->comp_mode_recovery_timer);
539 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
540 "All USB3 ports have entered U0 already!");
541 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
542 "Compliance Mode Recovery Timer Deleted.");
548 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
551 * Possible side effects:
552 * - Mark a port as being done with device resume,
553 * and ring the endpoint doorbells.
554 * - Stop the Synopsys redriver Compliance Mode polling.
556 static u32 xhci_get_port_status(struct usb_hcd *hcd,
557 struct xhci_bus_state *bus_state,
558 __le32 __iomem **port_array,
559 u16 wIndex, u32 raw_port_status)
561 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
565 /* wPortChange bits */
566 if (raw_port_status & PORT_CSC)
567 status |= USB_PORT_STAT_C_CONNECTION << 16;
568 if (raw_port_status & PORT_PEC)
569 status |= USB_PORT_STAT_C_ENABLE << 16;
570 if ((raw_port_status & PORT_OCC))
571 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
572 if ((raw_port_status & PORT_RC))
573 status |= USB_PORT_STAT_C_RESET << 16;
575 if (hcd->speed == HCD_USB3) {
576 if ((raw_port_status & PORT_PLC))
577 status |= USB_PORT_STAT_C_LINK_STATE << 16;
578 if ((raw_port_status & PORT_WRC))
579 status |= USB_PORT_STAT_C_BH_RESET << 16;
582 if (hcd->speed != HCD_USB3) {
583 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
584 && (raw_port_status & PORT_POWER))
585 status |= USB_PORT_STAT_SUSPEND;
587 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
588 !DEV_SUPERSPEED(raw_port_status)) {
589 if ((raw_port_status & PORT_RESET) ||
590 !(raw_port_status & PORT_PE))
592 if (time_after_eq(jiffies,
593 bus_state->resume_done[wIndex])) {
594 xhci_dbg(xhci, "Resume USB2 port %d\n",
596 bus_state->resume_done[wIndex] = 0;
597 clear_bit(wIndex, &bus_state->resuming_ports);
598 xhci_set_link_state(xhci, port_array, wIndex,
600 xhci_dbg(xhci, "set port %d resume\n",
602 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
605 xhci_dbg(xhci, "slot_id is zero\n");
608 xhci_ring_device(xhci, slot_id);
609 bus_state->port_c_suspend |= 1 << wIndex;
610 bus_state->suspended_ports &= ~(1 << wIndex);
613 * The resume has been signaling for less than
614 * 20ms. Report the port status as SUSPEND,
615 * let the usbcore check port status again
616 * and clear resume signaling later.
618 status |= USB_PORT_STAT_SUSPEND;
621 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
622 && (raw_port_status & PORT_POWER)
623 && (bus_state->suspended_ports & (1 << wIndex))) {
624 bus_state->suspended_ports &= ~(1 << wIndex);
625 if (hcd->speed != HCD_USB3)
626 bus_state->port_c_suspend |= 1 << wIndex;
628 if (raw_port_status & PORT_CONNECT) {
629 status |= USB_PORT_STAT_CONNECTION;
630 status |= xhci_port_speed(raw_port_status);
632 if (raw_port_status & PORT_PE)
633 status |= USB_PORT_STAT_ENABLE;
634 if (raw_port_status & PORT_OC)
635 status |= USB_PORT_STAT_OVERCURRENT;
636 if (raw_port_status & PORT_RESET)
637 status |= USB_PORT_STAT_RESET;
638 if (raw_port_status & PORT_POWER) {
639 if (hcd->speed == HCD_USB3)
640 status |= USB_SS_PORT_STAT_POWER;
642 status |= USB_PORT_STAT_POWER;
644 /* Update Port Link State */
645 if (hcd->speed == HCD_USB3) {
646 xhci_hub_report_usb3_link_state(&status, raw_port_status);
648 * Verify if all USB3 Ports Have entered U0 already.
649 * Delete Compliance Mode Timer if so.
651 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
653 xhci_hub_report_usb2_link_state(&status, raw_port_status);
655 if (bus_state->port_c_suspend & (1 << wIndex))
656 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
661 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
662 u16 wIndex, char *buf, u16 wLength)
664 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
669 __le32 __iomem **port_array;
671 struct xhci_bus_state *bus_state;
676 max_ports = xhci_get_ports(hcd, &port_array);
677 bus_state = &xhci->bus_state[hcd_index(hcd)];
679 spin_lock_irqsave(&xhci->lock, flags);
682 /* No power source, over-current reported per port */
685 case GetHubDescriptor:
686 /* Check to make sure userspace is asking for the USB 3.0 hub
687 * descriptor for the USB 3.0 roothub. If not, we stall the
688 * endpoint, like external hubs do.
690 if (hcd->speed == HCD_USB3 &&
691 (wLength < USB_DT_SS_HUB_SIZE ||
692 wValue != (USB_DT_SS_HUB << 8))) {
693 xhci_dbg(xhci, "Wrong hub descriptor type for "
694 "USB 3.0 roothub.\n");
697 xhci_hub_descriptor(hcd, xhci,
698 (struct usb_hub_descriptor *) buf);
700 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
701 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
704 if (hcd->speed != HCD_USB3)
707 /* Set the U1 and U2 exit latencies. */
708 memcpy(buf, &usb_bos_descriptor,
709 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
710 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
711 buf[12] = HCS_U1_LATENCY(temp);
712 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
714 /* Indicate whether the host has LTM support. */
715 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
717 buf[8] |= USB_LTM_SUPPORT;
719 spin_unlock_irqrestore(&xhci->lock, flags);
720 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
722 if (!wIndex || wIndex > max_ports)
725 temp = xhci_readl(xhci, port_array[wIndex]);
726 if (temp == 0xffffffff) {
730 status = xhci_get_port_status(hcd, bus_state, port_array,
732 if (status == 0xffffffff)
735 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
737 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
739 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
742 if (wValue == USB_PORT_FEAT_LINK_STATE)
743 link_state = (wIndex & 0xff00) >> 3;
744 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
745 wake_mask = wIndex & 0xff00;
746 /* The MSB of wIndex is the U1/U2 timeout */
747 timeout = (wIndex & 0xff00) >> 8;
749 if (!wIndex || wIndex > max_ports)
752 temp = xhci_readl(xhci, port_array[wIndex]);
753 if (temp == 0xffffffff) {
757 temp = xhci_port_state_to_neutral(temp);
758 /* FIXME: What new port features do we need to support? */
760 case USB_PORT_FEAT_SUSPEND:
761 temp = xhci_readl(xhci, port_array[wIndex]);
762 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
763 /* Resume the port to U0 first */
764 xhci_set_link_state(xhci, port_array, wIndex,
766 spin_unlock_irqrestore(&xhci->lock, flags);
768 spin_lock_irqsave(&xhci->lock, flags);
770 /* In spec software should not attempt to suspend
771 * a port unless the port reports that it is in the
772 * enabled (PED = ‘1’,PLS < ‘3’) state.
774 temp = xhci_readl(xhci, port_array[wIndex]);
775 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
776 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
777 xhci_warn(xhci, "USB core suspending device "
778 "not in U0/U1/U2.\n");
782 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
785 xhci_warn(xhci, "slot_id is zero\n");
788 /* unlock to execute stop endpoint commands */
789 spin_unlock_irqrestore(&xhci->lock, flags);
790 xhci_stop_device(xhci, slot_id, 1);
791 spin_lock_irqsave(&xhci->lock, flags);
793 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
795 spin_unlock_irqrestore(&xhci->lock, flags);
796 msleep(10); /* wait device to enter */
797 spin_lock_irqsave(&xhci->lock, flags);
799 temp = xhci_readl(xhci, port_array[wIndex]);
800 bus_state->suspended_ports |= 1 << wIndex;
802 case USB_PORT_FEAT_LINK_STATE:
803 temp = xhci_readl(xhci, port_array[wIndex]);
806 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
807 xhci_dbg(xhci, "Disable port %d\n", wIndex);
808 temp = xhci_port_state_to_neutral(temp);
810 * Clear all change bits, so that we get a new
813 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
814 PORT_OCC | PORT_RC | PORT_PLC |
816 xhci_writel(xhci, temp | PORT_PE,
818 temp = xhci_readl(xhci, port_array[wIndex]);
822 /* Put link in RxDetect (enable port) */
823 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
824 xhci_dbg(xhci, "Enable port %d\n", wIndex);
825 xhci_set_link_state(xhci, port_array, wIndex,
827 temp = xhci_readl(xhci, port_array[wIndex]);
831 /* Software should not attempt to set
832 * port link state above '3' (U3) and the port
835 if ((temp & PORT_PE) == 0 ||
836 (link_state > USB_SS_PORT_LS_U3)) {
837 xhci_warn(xhci, "Cannot set link state.\n");
841 if (link_state == USB_SS_PORT_LS_U3) {
842 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
845 /* unlock to execute stop endpoint
847 spin_unlock_irqrestore(&xhci->lock,
849 xhci_stop_device(xhci, slot_id, 1);
850 spin_lock_irqsave(&xhci->lock, flags);
854 xhci_set_link_state(xhci, port_array, wIndex,
857 spin_unlock_irqrestore(&xhci->lock, flags);
858 msleep(20); /* wait device to enter */
859 spin_lock_irqsave(&xhci->lock, flags);
861 temp = xhci_readl(xhci, port_array[wIndex]);
862 if (link_state == USB_SS_PORT_LS_U3)
863 bus_state->suspended_ports |= 1 << wIndex;
865 case USB_PORT_FEAT_POWER:
867 * Turn on ports, even if there isn't per-port switching.
868 * HC will report connect events even before this is set.
869 * However, khubd will ignore the roothub events until
870 * the roothub is registered.
872 xhci_writel(xhci, temp | PORT_POWER,
875 temp = xhci_readl(xhci, port_array[wIndex]);
876 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
878 spin_unlock_irqrestore(&xhci->lock, flags);
879 temp = usb_acpi_power_manageable(hcd->self.root_hub,
882 usb_acpi_set_power_state(hcd->self.root_hub,
884 spin_lock_irqsave(&xhci->lock, flags);
886 case USB_PORT_FEAT_RESET:
887 temp = (temp | PORT_RESET);
888 xhci_writel(xhci, temp, port_array[wIndex]);
890 temp = xhci_readl(xhci, port_array[wIndex]);
891 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
893 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
894 xhci_set_remote_wake_mask(xhci, port_array,
896 temp = xhci_readl(xhci, port_array[wIndex]);
897 xhci_dbg(xhci, "set port remote wake mask, "
898 "actual port %d status = 0x%x\n",
901 case USB_PORT_FEAT_BH_PORT_RESET:
903 xhci_writel(xhci, temp, port_array[wIndex]);
905 temp = xhci_readl(xhci, port_array[wIndex]);
907 case USB_PORT_FEAT_U1_TIMEOUT:
908 if (hcd->speed != HCD_USB3)
910 temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
911 temp &= ~PORT_U1_TIMEOUT_MASK;
912 temp |= PORT_U1_TIMEOUT(timeout);
913 xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
915 case USB_PORT_FEAT_U2_TIMEOUT:
916 if (hcd->speed != HCD_USB3)
918 temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
919 temp &= ~PORT_U2_TIMEOUT_MASK;
920 temp |= PORT_U2_TIMEOUT(timeout);
921 xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
926 /* unblock any posted writes */
927 temp = xhci_readl(xhci, port_array[wIndex]);
929 case ClearPortFeature:
930 if (!wIndex || wIndex > max_ports)
933 temp = xhci_readl(xhci, port_array[wIndex]);
934 if (temp == 0xffffffff) {
938 /* FIXME: What new port features do we need to support? */
939 temp = xhci_port_state_to_neutral(temp);
941 case USB_PORT_FEAT_SUSPEND:
942 temp = xhci_readl(xhci, port_array[wIndex]);
943 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
944 xhci_dbg(xhci, "PORTSC %04x\n", temp);
945 if (temp & PORT_RESET)
947 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
948 if ((temp & PORT_PE) == 0)
951 xhci_set_link_state(xhci, port_array, wIndex,
953 spin_unlock_irqrestore(&xhci->lock, flags);
955 spin_lock_irqsave(&xhci->lock, flags);
956 xhci_set_link_state(xhci, port_array, wIndex,
959 bus_state->port_c_suspend |= 1 << wIndex;
961 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
964 xhci_dbg(xhci, "slot_id is zero\n");
967 xhci_ring_device(xhci, slot_id);
969 case USB_PORT_FEAT_C_SUSPEND:
970 bus_state->port_c_suspend &= ~(1 << wIndex);
971 case USB_PORT_FEAT_C_RESET:
972 case USB_PORT_FEAT_C_BH_PORT_RESET:
973 case USB_PORT_FEAT_C_CONNECTION:
974 case USB_PORT_FEAT_C_OVER_CURRENT:
975 case USB_PORT_FEAT_C_ENABLE:
976 case USB_PORT_FEAT_C_PORT_LINK_STATE:
977 xhci_clear_port_change_bit(xhci, wValue, wIndex,
978 port_array[wIndex], temp);
980 case USB_PORT_FEAT_ENABLE:
981 xhci_disable_port(hcd, xhci, wIndex,
982 port_array[wIndex], temp);
984 case USB_PORT_FEAT_POWER:
985 xhci_writel(xhci, temp & ~PORT_POWER,
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 temp = usb_acpi_power_manageable(hcd->self.root_hub,
992 usb_acpi_set_power_state(hcd->self.root_hub,
994 spin_lock_irqsave(&xhci->lock, flags);
1002 /* "stall" on error */
1005 spin_unlock_irqrestore(&xhci->lock, flags);
1010 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1011 * Ports are 0-indexed from the HCD point of view,
1012 * and 1-indexed from the USB core pointer of view.
1014 * Note that the status change bits will be cleared as soon as a port status
1015 * change event is generated, so we use the saved status from that event.
1017 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1019 unsigned long flags;
1023 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1025 __le32 __iomem **port_array;
1026 struct xhci_bus_state *bus_state;
1027 bool reset_change = false;
1029 max_ports = xhci_get_ports(hcd, &port_array);
1030 bus_state = &xhci->bus_state[hcd_index(hcd)];
1032 /* Initial status is no changes */
1033 retval = (max_ports + 8) / 8;
1034 memset(buf, 0, retval);
1037 * Inform the usbcore about resume-in-progress by returning
1038 * a non-zero value even if there are no status changes.
1040 status = bus_state->resuming_ports;
1042 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1044 spin_lock_irqsave(&xhci->lock, flags);
1045 /* For each port, did anything change? If so, set that bit in buf. */
1046 for (i = 0; i < max_ports; i++) {
1047 temp = xhci_readl(xhci, port_array[i]);
1048 if (temp == 0xffffffff) {
1052 if ((temp & mask) != 0 ||
1053 (bus_state->port_c_suspend & 1 << i) ||
1054 (bus_state->resume_done[i] && time_after_eq(
1055 jiffies, bus_state->resume_done[i]))) {
1056 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1059 if ((temp & PORT_RC))
1060 reset_change = true;
1062 if (!status && !reset_change) {
1063 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1064 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1066 spin_unlock_irqrestore(&xhci->lock, flags);
1067 return status ? retval : 0;
1072 int xhci_bus_suspend(struct usb_hcd *hcd)
1074 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1075 int max_ports, port_index;
1076 __le32 __iomem **port_array;
1077 struct xhci_bus_state *bus_state;
1078 unsigned long flags;
1080 max_ports = xhci_get_ports(hcd, &port_array);
1081 bus_state = &xhci->bus_state[hcd_index(hcd)];
1083 spin_lock_irqsave(&xhci->lock, flags);
1085 if (hcd->self.root_hub->do_remote_wakeup) {
1086 if (bus_state->resuming_ports) {
1087 spin_unlock_irqrestore(&xhci->lock, flags);
1088 xhci_dbg(xhci, "suspend failed because "
1089 "a port is resuming\n");
1094 port_index = max_ports;
1095 bus_state->bus_suspended = 0;
1096 while (port_index--) {
1097 /* suspend the port if the port is not suspended */
1101 t1 = xhci_readl(xhci, port_array[port_index]);
1102 t2 = xhci_port_state_to_neutral(t1);
1104 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1105 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1106 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1109 spin_unlock_irqrestore(&xhci->lock, flags);
1110 xhci_stop_device(xhci, slot_id, 1);
1111 spin_lock_irqsave(&xhci->lock, flags);
1113 t2 &= ~PORT_PLS_MASK;
1114 t2 |= PORT_LINK_STROBE | XDEV_U3;
1115 set_bit(port_index, &bus_state->bus_suspended);
1117 /* USB core sets remote wake mask for USB 3.0 hubs,
1118 * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1119 * is enabled, so also enable remote wake here.
1121 if (hcd->self.root_hub->do_remote_wakeup) {
1122 if (t1 & PORT_CONNECT) {
1123 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1124 t2 &= ~PORT_WKCONN_E;
1126 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1127 t2 &= ~PORT_WKDISC_E;
1130 t2 &= ~PORT_WAKE_BITS;
1132 t1 = xhci_port_state_to_neutral(t1);
1134 xhci_writel(xhci, t2, port_array[port_index]);
1136 if (hcd->speed != HCD_USB3) {
1137 /* enable remote wake up for USB 2.0 */
1138 __le32 __iomem *addr;
1141 /* Get the port power control register address. */
1142 addr = port_array[port_index] + PORTPMSC;
1143 tmp = xhci_readl(xhci, addr);
1145 xhci_writel(xhci, tmp, addr);
1148 hcd->state = HC_STATE_SUSPENDED;
1149 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1150 spin_unlock_irqrestore(&xhci->lock, flags);
1154 int xhci_bus_resume(struct usb_hcd *hcd)
1156 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1157 int max_ports, port_index;
1158 __le32 __iomem **port_array;
1159 struct xhci_bus_state *bus_state;
1161 unsigned long flags;
1163 max_ports = xhci_get_ports(hcd, &port_array);
1164 bus_state = &xhci->bus_state[hcd_index(hcd)];
1166 if (time_before(jiffies, bus_state->next_statechange))
1169 spin_lock_irqsave(&xhci->lock, flags);
1170 if (!HCD_HW_ACCESSIBLE(hcd)) {
1171 spin_unlock_irqrestore(&xhci->lock, flags);
1175 /* delay the irqs */
1176 temp = xhci_readl(xhci, &xhci->op_regs->command);
1178 xhci_writel(xhci, temp, &xhci->op_regs->command);
1180 port_index = max_ports;
1181 while (port_index--) {
1182 /* Check whether need resume ports. If needed
1183 resume port and disable remote wakeup */
1187 temp = xhci_readl(xhci, port_array[port_index]);
1188 if (DEV_SUPERSPEED(temp))
1189 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1191 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1192 if (test_bit(port_index, &bus_state->bus_suspended) &&
1193 (temp & PORT_PLS_MASK)) {
1194 if (DEV_SUPERSPEED(temp)) {
1195 xhci_set_link_state(xhci, port_array,
1196 port_index, XDEV_U0);
1198 xhci_set_link_state(xhci, port_array,
1199 port_index, XDEV_RESUME);
1201 spin_unlock_irqrestore(&xhci->lock, flags);
1203 spin_lock_irqsave(&xhci->lock, flags);
1205 xhci_set_link_state(xhci, port_array,
1206 port_index, XDEV_U0);
1208 /* wait for the port to enter U0 and report port link
1211 spin_unlock_irqrestore(&xhci->lock, flags);
1213 spin_lock_irqsave(&xhci->lock, flags);
1216 xhci_test_and_clear_bit(xhci, port_array, port_index,
1219 slot_id = xhci_find_slot_id_by_port(hcd,
1220 xhci, port_index + 1);
1222 xhci_ring_device(xhci, slot_id);
1224 xhci_writel(xhci, temp, port_array[port_index]);
1226 if (hcd->speed != HCD_USB3) {
1227 /* disable remote wake up for USB 2.0 */
1228 __le32 __iomem *addr;
1231 /* Add one to the port status register address to get
1232 * the port power control register address.
1234 addr = port_array[port_index] + PORTPMSC;
1235 tmp = xhci_readl(xhci, addr);
1237 xhci_writel(xhci, tmp, addr);
1241 (void) xhci_readl(xhci, &xhci->op_regs->command);
1243 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1244 /* re-enable irqs */
1245 temp = xhci_readl(xhci, &xhci->op_regs->command);
1247 xhci_writel(xhci, temp, &xhci->op_regs->command);
1248 temp = xhci_readl(xhci, &xhci->op_regs->command);
1250 spin_unlock_irqrestore(&xhci->lock, flags);
1254 #endif /* CONFIG_PM */