2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x0c, /* bLength 12, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x00, 0x00, 0x00, 0x00, /* bmAttributes, get from xhci psic */
58 0x00, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */
63 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 desc_size, ssp_cap_size, ssa_size = 0;
71 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
72 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
74 /* does xhci support USB 3.1 Enhanced SuperSpeed */
75 if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) {
76 /* two SSA entries for each unique PSI ID, one RX and one TX */
77 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
78 ssa_size = ssa_count * sizeof(u32);
79 desc_size += ssp_cap_size;
82 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
85 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
87 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
90 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
93 /* Indicate whether the host has LTM support. */
94 temp = readl(&xhci->cap_regs->hcc_params);
96 buf[8] |= USB_LTM_SUPPORT;
98 /* Set the U1 and U2 exit latencies. */
99 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
100 temp = readl(&xhci->cap_regs->hcs_params3);
101 buf[12] = HCS_U1_LATENCY(temp);
102 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
106 u32 ssp_cap_base, bm_attrib, psi;
109 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
111 if (wLength < desc_size)
113 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
115 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
116 bm_attrib = (ssa_count - 1) & 0x1f;
117 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
118 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
120 if (wLength < desc_size + ssa_size)
123 * Create the Sublink Speed Attributes (SSA) array.
124 * The xhci PSI field and USB 3.1 SSA fields are very similar,
125 * but link type bits 7:6 differ for values 01b and 10b.
126 * xhci has also only one PSI entry for a symmetric link when
127 * USB 3.1 requires two SSA entries (RX and TX) for every link
130 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
131 psi = xhci->usb3_rhub.psi[i];
132 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
133 if ((psi & PLT_MASK) == PLT_SYM) {
134 /* Symmetric, create SSA RX and TX from one PSI entry */
135 put_unaligned_le32(psi, &buf[offset]);
136 psi |= 1 << 7; /* turn entry to TX */
138 if (offset >= desc_size + ssa_size)
139 return desc_size + ssa_size;
140 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
141 /* Asymetric RX, flip bits 7:6 for SSA */
144 put_unaligned_le32(psi, &buf[offset]);
146 if (offset >= desc_size + ssa_size)
147 return desc_size + ssa_size;
150 /* ssa_size is 0 for other than usb 3.1 hosts */
151 return desc_size + ssa_size;
154 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
155 struct usb_hub_descriptor *desc, int ports)
159 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
160 desc->bHubContrCurrent = 0;
162 desc->bNbrPorts = ports;
164 /* Bits 1:0 - support per-port power switching, or power always on */
165 if (HCC_PPC(xhci->hcc_params))
166 temp |= HUB_CHAR_INDV_PORT_LPSM;
168 temp |= HUB_CHAR_NO_LPSM;
169 /* Bit 2 - root hubs are not part of a compound device */
170 /* Bits 4:3 - individual port over current protection */
171 temp |= HUB_CHAR_INDV_PORT_OCPM;
172 /* Bits 6:5 - no TTs in root ports */
173 /* Bit 7 - no port indicators */
174 desc->wHubCharacteristics = cpu_to_le16(temp);
177 /* Fill in the USB 2.0 roothub descriptor */
178 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
179 struct usb_hub_descriptor *desc)
183 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
187 ports = xhci->num_usb2_ports;
189 xhci_common_hub_descriptor(xhci, desc, ports);
190 desc->bDescriptorType = USB_DT_HUB;
191 temp = 1 + (ports / 8);
192 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
194 /* The Device Removable bits are reported on a byte granularity.
195 * If the port doesn't exist within that byte, the bit is set to 0.
197 memset(port_removable, 0, sizeof(port_removable));
198 for (i = 0; i < ports; i++) {
199 portsc = readl(xhci->usb2_ports[i]);
200 /* If a device is removable, PORTSC reports a 0, same as in the
201 * hub descriptor DeviceRemovable bits.
203 if (portsc & PORT_DEV_REMOVE)
204 /* This math is hairy because bit 0 of DeviceRemovable
205 * is reserved, and bit 1 is for port 1, etc.
207 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
210 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
211 * ports on it. The USB 2.0 specification says that there are two
212 * variable length fields at the end of the hub descriptor:
213 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
214 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
215 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
216 * 0xFF, so we initialize the both arrays (DeviceRemovable and
217 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
218 * set of ports that actually exist.
220 memset(desc->u.hs.DeviceRemovable, 0xff,
221 sizeof(desc->u.hs.DeviceRemovable));
222 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
223 sizeof(desc->u.hs.PortPwrCtrlMask));
225 for (i = 0; i < (ports + 1 + 7) / 8; i++)
226 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
230 /* Fill in the USB 3.0 roothub descriptor */
231 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
232 struct usb_hub_descriptor *desc)
239 ports = xhci->num_usb3_ports;
240 xhci_common_hub_descriptor(xhci, desc, ports);
241 desc->bDescriptorType = USB_DT_SS_HUB;
242 desc->bDescLength = USB_DT_SS_HUB_SIZE;
244 /* header decode latency should be zero for roothubs,
245 * see section 4.23.5.2.
247 desc->u.ss.bHubHdrDecLat = 0;
248 desc->u.ss.wHubDelay = 0;
251 /* bit 0 is reserved, bit 1 is for port 1, etc. */
252 for (i = 0; i < ports; i++) {
253 portsc = readl(xhci->usb3_ports[i]);
254 if (portsc & PORT_DEV_REMOVE)
255 port_removable |= 1 << (i + 1);
258 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
261 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
262 struct usb_hub_descriptor *desc)
265 if (hcd->speed >= HCD_USB3)
266 xhci_usb3_hub_descriptor(hcd, xhci, desc);
268 xhci_usb2_hub_descriptor(hcd, xhci, desc);
272 static unsigned int xhci_port_speed(unsigned int port_status)
274 if (DEV_LOWSPEED(port_status))
275 return USB_PORT_STAT_LOW_SPEED;
276 if (DEV_HIGHSPEED(port_status))
277 return USB_PORT_STAT_HIGH_SPEED;
279 * FIXME: Yes, we should check for full speed, but the core uses that as
280 * a default in portspeed() in usb/core/hub.c (which is the only place
281 * USB_PORT_STAT_*_SPEED is used).
287 * These bits are Read Only (RO) and should be saved and written to the
288 * registers: 0, 3, 10:13, 30
289 * connect status, over-current status, port speed, and device removable.
290 * connect status and port speed are also sticky - meaning they're in
291 * the AUX well and they aren't changed by a hot, warm, or cold reset.
293 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
295 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
296 * bits 5:8, 9, 14:15, 25:27
297 * link state, port power, port indicator state, "wake on" enable state
299 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
301 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
304 #define XHCI_PORT_RW1S ((1<<4))
306 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
307 * bits 1, 17, 18, 19, 20, 21, 22, 23
308 * port enable/disable, and
309 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
310 * over-current, reset, link state, and L1 change
312 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
314 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
317 #define XHCI_PORT_RW ((1<<16))
319 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
322 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
325 * Given a port state, this function returns a value that would result in the
326 * port being in the same state, if the value was written to the port status
328 * Save Read Only (RO) bits and save read/write bits where
329 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
330 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
332 u32 xhci_port_state_to_neutral(u32 state)
334 /* Save read-only status and port state */
335 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
339 * find slot id based on port number.
340 * @port: The one-based port number from one of the two split roothubs.
342 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
347 enum usb_device_speed speed;
350 for (i = 0; i < MAX_HC_SLOTS; i++) {
353 speed = xhci->devs[i]->udev->speed;
354 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
355 && xhci->devs[i]->fake_port == port) {
366 * It issues stop endpoint command for EP 0 to 30. And wait the last command
368 * suspend will set to 1, if suspend bit need to set in command.
370 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
372 struct xhci_virt_device *virt_dev;
373 struct xhci_command *cmd;
379 virt_dev = xhci->devs[slot_id];
380 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
382 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
386 spin_lock_irqsave(&xhci->lock, flags);
387 for (i = LAST_EP_INDEX; i > 0; i--) {
388 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
389 struct xhci_command *command;
390 command = xhci_alloc_command(xhci, false, false,
393 spin_unlock_irqrestore(&xhci->lock, flags);
394 xhci_free_command(xhci, cmd);
398 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
402 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
403 xhci_ring_cmd_db(xhci);
404 spin_unlock_irqrestore(&xhci->lock, flags);
406 /* Wait for last stop endpoint command to finish */
407 wait_for_completion(cmd->completion);
409 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
410 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
413 xhci_free_command(xhci, cmd);
418 * Ring device, it rings the all doorbells unconditionally.
420 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
423 struct xhci_virt_ep *ep;
425 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
426 ep = &xhci->devs[slot_id]->eps[i];
428 if (ep->ep_state & EP_HAS_STREAMS) {
429 for (s = 1; s < ep->stream_info->num_streams; s++)
430 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
431 } else if (ep->ring && ep->ring->dequeue) {
432 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
439 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
440 u16 wIndex, __le32 __iomem *addr, u32 port_status)
442 /* Don't allow the USB core to disable SuperSpeed ports. */
443 if (hcd->speed >= HCD_USB3) {
444 xhci_dbg(xhci, "Ignoring request to disable "
445 "SuperSpeed port.\n");
449 /* Write 1 to disable the port */
450 writel(port_status | PORT_PE, addr);
451 port_status = readl(addr);
452 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
453 wIndex, port_status);
456 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
457 u16 wIndex, __le32 __iomem *addr, u32 port_status)
459 char *port_change_bit;
463 case USB_PORT_FEAT_C_RESET:
465 port_change_bit = "reset";
467 case USB_PORT_FEAT_C_BH_PORT_RESET:
469 port_change_bit = "warm(BH) reset";
471 case USB_PORT_FEAT_C_CONNECTION:
473 port_change_bit = "connect";
475 case USB_PORT_FEAT_C_OVER_CURRENT:
477 port_change_bit = "over-current";
479 case USB_PORT_FEAT_C_ENABLE:
481 port_change_bit = "enable/disable";
483 case USB_PORT_FEAT_C_SUSPEND:
485 port_change_bit = "suspend/resume";
487 case USB_PORT_FEAT_C_PORT_LINK_STATE:
489 port_change_bit = "link state";
491 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
493 port_change_bit = "config error";
496 /* Should never happen */
499 /* Change bits are all write 1 to clear */
500 writel(port_status | status, addr);
501 port_status = readl(addr);
502 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
503 port_change_bit, wIndex, port_status);
506 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
509 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
511 if (hcd->speed >= HCD_USB3) {
512 max_ports = xhci->num_usb3_ports;
513 *port_array = xhci->usb3_ports;
515 max_ports = xhci->num_usb2_ports;
516 *port_array = xhci->usb2_ports;
522 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
523 int port_id, u32 link_state)
527 temp = readl(port_array[port_id]);
528 temp = xhci_port_state_to_neutral(temp);
529 temp &= ~PORT_PLS_MASK;
530 temp |= PORT_LINK_STROBE | link_state;
531 writel(temp, port_array[port_id]);
534 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
535 __le32 __iomem **port_array, int port_id, u16 wake_mask)
539 temp = readl(port_array[port_id]);
540 temp = xhci_port_state_to_neutral(temp);
542 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
543 temp |= PORT_WKCONN_E;
545 temp &= ~PORT_WKCONN_E;
547 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
548 temp |= PORT_WKDISC_E;
550 temp &= ~PORT_WKDISC_E;
552 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
555 temp &= ~PORT_WKOC_E;
557 writel(temp, port_array[port_id]);
560 /* Test and clear port RWC bit */
561 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
562 int port_id, u32 port_bit)
566 temp = readl(port_array[port_id]);
567 if (temp & port_bit) {
568 temp = xhci_port_state_to_neutral(temp);
570 writel(temp, port_array[port_id]);
574 /* Updates Link Status for USB 2.1 port */
575 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
577 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
578 *status |= USB_PORT_STAT_L1;
581 /* Updates Link Status for super Speed port */
582 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
583 u32 *status, u32 status_reg)
585 u32 pls = status_reg & PORT_PLS_MASK;
587 /* resume state is a xHCI internal state.
588 * Do not report it to usb core, instead, pretend to be U3,
589 * thus usb core knows it's not ready for transfer
591 if (pls == XDEV_RESUME) {
592 *status |= USB_SS_PORT_LS_U3;
596 /* When the CAS bit is set then warm reset
597 * should be performed on port
599 if (status_reg & PORT_CAS) {
600 /* The CAS bit can be set while the port is
602 * Only roothubs have CAS bit, so we
603 * pretend to be in compliance mode
604 * unless we're already in compliance
605 * or the inactive state.
607 if (pls != USB_SS_PORT_LS_COMP_MOD &&
608 pls != USB_SS_PORT_LS_SS_INACTIVE) {
609 pls = USB_SS_PORT_LS_COMP_MOD;
611 /* Return also connection bit -
612 * hub state machine resets port
613 * when this bit is set.
615 pls |= USB_PORT_STAT_CONNECTION;
618 * If CAS bit isn't set but the Port is already at
619 * Compliance Mode, fake a connection so the USB core
620 * notices the Compliance state and resets the port.
621 * This resolves an issue generated by the SN65LVPE502CP
622 * in which sometimes the port enters compliance mode
623 * caused by a delay on the host-device negotiation.
625 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
626 (pls == USB_SS_PORT_LS_COMP_MOD))
627 pls |= USB_PORT_STAT_CONNECTION;
630 /* update status field */
635 * Function for Compliance Mode Quirk.
637 * This Function verifies if all xhc USB3 ports have entered U0, if so,
638 * the compliance mode timer is deleted. A port won't enter
639 * compliance mode if it has previously entered U0.
641 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
644 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
645 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
647 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
650 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
651 xhci->port_status_u0 |= 1 << wIndex;
652 if (xhci->port_status_u0 == all_ports_seen_u0) {
653 del_timer_sync(&xhci->comp_mode_recovery_timer);
654 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
655 "All USB3 ports have entered U0 already!");
656 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
657 "Compliance Mode Recovery Timer Deleted.");
662 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
667 /* only support rx and tx lane counts of 1 in usb3.1 spec */
668 speed_id = DEV_PORT_SPEED(raw_port_status);
669 ext_stat |= speed_id; /* bits 3:0, RX speed id */
670 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
672 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
673 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
679 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
682 * Possible side effects:
683 * - Mark a port as being done with device resume,
684 * and ring the endpoint doorbells.
685 * - Stop the Synopsys redriver Compliance Mode polling.
686 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
688 static u32 xhci_get_port_status(struct usb_hcd *hcd,
689 struct xhci_bus_state *bus_state,
690 __le32 __iomem **port_array,
691 u16 wIndex, u32 raw_port_status,
693 __releases(&xhci->lock)
694 __acquires(&xhci->lock)
696 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
700 /* wPortChange bits */
701 if (raw_port_status & PORT_CSC)
702 status |= USB_PORT_STAT_C_CONNECTION << 16;
703 if (raw_port_status & PORT_PEC)
704 status |= USB_PORT_STAT_C_ENABLE << 16;
705 if ((raw_port_status & PORT_OCC))
706 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
707 if ((raw_port_status & PORT_RC))
708 status |= USB_PORT_STAT_C_RESET << 16;
710 if (hcd->speed >= HCD_USB3) {
711 /* Port link change with port in resume state should not be
712 * reported to usbcore, as this is an internal state to be
713 * handled by xhci driver. Reporting PLC to usbcore may
714 * cause usbcore clearing PLC first and port change event
715 * irq won't be generated.
717 if ((raw_port_status & PORT_PLC) &&
718 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
719 status |= USB_PORT_STAT_C_LINK_STATE << 16;
720 if ((raw_port_status & PORT_WRC))
721 status |= USB_PORT_STAT_C_BH_RESET << 16;
722 if ((raw_port_status & PORT_CEC))
723 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
726 if (hcd->speed < HCD_USB3) {
727 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
728 && (raw_port_status & PORT_POWER))
729 status |= USB_PORT_STAT_SUSPEND;
731 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
732 !DEV_SUPERSPEED_ANY(raw_port_status)) {
733 if ((raw_port_status & PORT_RESET) ||
734 !(raw_port_status & PORT_PE))
736 if (time_after_eq(jiffies,
737 bus_state->resume_done[wIndex])) {
740 xhci_dbg(xhci, "Resume USB2 port %d\n",
742 bus_state->resume_done[wIndex] = 0;
743 clear_bit(wIndex, &bus_state->resuming_ports);
745 set_bit(wIndex, &bus_state->rexit_ports);
746 xhci_set_link_state(xhci, port_array, wIndex,
749 spin_unlock_irqrestore(&xhci->lock, flags);
750 time_left = wait_for_completion_timeout(
751 &bus_state->rexit_done[wIndex],
753 XHCI_MAX_REXIT_TIMEOUT));
754 spin_lock_irqsave(&xhci->lock, flags);
757 slot_id = xhci_find_slot_id_by_port(hcd,
760 xhci_dbg(xhci, "slot_id is zero\n");
763 xhci_ring_device(xhci, slot_id);
765 int port_status = readl(port_array[wIndex]);
766 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
767 XHCI_MAX_REXIT_TIMEOUT,
769 status |= USB_PORT_STAT_SUSPEND;
770 clear_bit(wIndex, &bus_state->rexit_ports);
773 bus_state->port_c_suspend |= 1 << wIndex;
774 bus_state->suspended_ports &= ~(1 << wIndex);
777 * The resume has been signaling for less than
778 * 20ms. Report the port status as SUSPEND,
779 * let the usbcore check port status again
780 * and clear resume signaling later.
782 status |= USB_PORT_STAT_SUSPEND;
785 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
786 (raw_port_status & PORT_POWER)) {
787 if (bus_state->suspended_ports & (1 << wIndex)) {
788 bus_state->suspended_ports &= ~(1 << wIndex);
789 if (hcd->speed < HCD_USB3)
790 bus_state->port_c_suspend |= 1 << wIndex;
792 bus_state->resume_done[wIndex] = 0;
793 clear_bit(wIndex, &bus_state->resuming_ports);
795 if (raw_port_status & PORT_CONNECT) {
796 status |= USB_PORT_STAT_CONNECTION;
797 status |= xhci_port_speed(raw_port_status);
799 if (raw_port_status & PORT_PE)
800 status |= USB_PORT_STAT_ENABLE;
801 if (raw_port_status & PORT_OC)
802 status |= USB_PORT_STAT_OVERCURRENT;
803 if (raw_port_status & PORT_RESET)
804 status |= USB_PORT_STAT_RESET;
805 if (raw_port_status & PORT_POWER) {
806 if (hcd->speed >= HCD_USB3)
807 status |= USB_SS_PORT_STAT_POWER;
809 status |= USB_PORT_STAT_POWER;
811 /* Update Port Link State */
812 if (hcd->speed >= HCD_USB3) {
813 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
815 * Verify if all USB3 Ports Have entered U0 already.
816 * Delete Compliance Mode Timer if so.
818 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
820 xhci_hub_report_usb2_link_state(&status, raw_port_status);
822 if (bus_state->port_c_suspend & (1 << wIndex))
823 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
828 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
829 u16 wIndex, char *buf, u16 wLength)
831 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
836 __le32 __iomem **port_array;
838 struct xhci_bus_state *bus_state;
843 max_ports = xhci_get_ports(hcd, &port_array);
844 bus_state = &xhci->bus_state[hcd_index(hcd)];
846 spin_lock_irqsave(&xhci->lock, flags);
849 /* No power source, over-current reported per port */
852 case GetHubDescriptor:
853 /* Check to make sure userspace is asking for the USB 3.0 hub
854 * descriptor for the USB 3.0 roothub. If not, we stall the
855 * endpoint, like external hubs do.
857 if (hcd->speed >= HCD_USB3 &&
858 (wLength < USB_DT_SS_HUB_SIZE ||
859 wValue != (USB_DT_SS_HUB << 8))) {
860 xhci_dbg(xhci, "Wrong hub descriptor type for "
861 "USB 3.0 roothub.\n");
864 xhci_hub_descriptor(hcd, xhci,
865 (struct usb_hub_descriptor *) buf);
867 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
868 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
871 if (hcd->speed < HCD_USB3)
874 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
875 spin_unlock_irqrestore(&xhci->lock, flags);
878 if (!wIndex || wIndex > max_ports)
881 temp = readl(port_array[wIndex]);
882 if (temp == 0xffffffff) {
886 status = xhci_get_port_status(hcd, bus_state, port_array,
887 wIndex, temp, flags);
888 if (status == 0xffffffff)
891 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
893 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
895 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
896 /* if USB 3.1 extended port status return additional 4 bytes */
897 if (wValue == 0x02) {
900 if (hcd->speed < HCD_USB31 || wLength != 8) {
901 xhci_err(xhci, "get ext port status invalid parameter\n");
905 port_li = readl(port_array[wIndex] + PORTLI);
906 status = xhci_get_ext_port_status(temp, port_li);
907 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
911 if (wValue == USB_PORT_FEAT_LINK_STATE)
912 link_state = (wIndex & 0xff00) >> 3;
913 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
914 wake_mask = wIndex & 0xff00;
915 /* The MSB of wIndex is the U1/U2 timeout */
916 timeout = (wIndex & 0xff00) >> 8;
918 if (!wIndex || wIndex > max_ports)
921 temp = readl(port_array[wIndex]);
922 if (temp == 0xffffffff) {
926 temp = xhci_port_state_to_neutral(temp);
927 /* FIXME: What new port features do we need to support? */
929 case USB_PORT_FEAT_SUSPEND:
930 temp = readl(port_array[wIndex]);
931 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
932 /* Resume the port to U0 first */
933 xhci_set_link_state(xhci, port_array, wIndex,
935 spin_unlock_irqrestore(&xhci->lock, flags);
937 spin_lock_irqsave(&xhci->lock, flags);
939 /* In spec software should not attempt to suspend
940 * a port unless the port reports that it is in the
941 * enabled (PED = ‘1’,PLS < ‘3’) state.
943 temp = readl(port_array[wIndex]);
944 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
945 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
946 xhci_warn(xhci, "USB core suspending device "
947 "not in U0/U1/U2.\n");
951 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
954 xhci_warn(xhci, "slot_id is zero\n");
957 /* unlock to execute stop endpoint commands */
958 spin_unlock_irqrestore(&xhci->lock, flags);
959 xhci_stop_device(xhci, slot_id, 1);
960 spin_lock_irqsave(&xhci->lock, flags);
962 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
964 spin_unlock_irqrestore(&xhci->lock, flags);
965 msleep(10); /* wait device to enter */
966 spin_lock_irqsave(&xhci->lock, flags);
968 temp = readl(port_array[wIndex]);
969 bus_state->suspended_ports |= 1 << wIndex;
971 case USB_PORT_FEAT_LINK_STATE:
972 temp = readl(port_array[wIndex]);
975 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
976 xhci_dbg(xhci, "Disable port %d\n", wIndex);
977 temp = xhci_port_state_to_neutral(temp);
979 * Clear all change bits, so that we get a new
982 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
983 PORT_OCC | PORT_RC | PORT_PLC |
985 writel(temp | PORT_PE, port_array[wIndex]);
986 temp = readl(port_array[wIndex]);
990 /* Put link in RxDetect (enable port) */
991 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
992 xhci_dbg(xhci, "Enable port %d\n", wIndex);
993 xhci_set_link_state(xhci, port_array, wIndex,
995 temp = readl(port_array[wIndex]);
999 /* Software should not attempt to set
1000 * port link state above '3' (U3) and the port
1003 if ((temp & PORT_PE) == 0 ||
1004 (link_state > USB_SS_PORT_LS_U3)) {
1005 xhci_warn(xhci, "Cannot set link state.\n");
1009 if (link_state == USB_SS_PORT_LS_U3) {
1010 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1013 /* unlock to execute stop endpoint
1015 spin_unlock_irqrestore(&xhci->lock,
1017 xhci_stop_device(xhci, slot_id, 1);
1018 spin_lock_irqsave(&xhci->lock, flags);
1022 xhci_set_link_state(xhci, port_array, wIndex,
1025 spin_unlock_irqrestore(&xhci->lock, flags);
1026 msleep(20); /* wait device to enter */
1027 spin_lock_irqsave(&xhci->lock, flags);
1029 temp = readl(port_array[wIndex]);
1030 if (link_state == USB_SS_PORT_LS_U3)
1031 bus_state->suspended_ports |= 1 << wIndex;
1033 case USB_PORT_FEAT_POWER:
1035 * Turn on ports, even if there isn't per-port switching.
1036 * HC will report connect events even before this is set.
1037 * However, hub_wq will ignore the roothub events until
1038 * the roothub is registered.
1040 writel(temp | PORT_POWER, port_array[wIndex]);
1042 temp = readl(port_array[wIndex]);
1043 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1045 spin_unlock_irqrestore(&xhci->lock, flags);
1046 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1049 usb_acpi_set_power_state(hcd->self.root_hub,
1051 spin_lock_irqsave(&xhci->lock, flags);
1053 case USB_PORT_FEAT_RESET:
1054 temp = (temp | PORT_RESET);
1055 writel(temp, port_array[wIndex]);
1057 temp = readl(port_array[wIndex]);
1058 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1060 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1061 xhci_set_remote_wake_mask(xhci, port_array,
1063 temp = readl(port_array[wIndex]);
1064 xhci_dbg(xhci, "set port remote wake mask, "
1065 "actual port %d status = 0x%x\n",
1068 case USB_PORT_FEAT_BH_PORT_RESET:
1070 writel(temp, port_array[wIndex]);
1072 temp = readl(port_array[wIndex]);
1074 case USB_PORT_FEAT_U1_TIMEOUT:
1075 if (hcd->speed < HCD_USB3)
1077 temp = readl(port_array[wIndex] + PORTPMSC);
1078 temp &= ~PORT_U1_TIMEOUT_MASK;
1079 temp |= PORT_U1_TIMEOUT(timeout);
1080 writel(temp, port_array[wIndex] + PORTPMSC);
1082 case USB_PORT_FEAT_U2_TIMEOUT:
1083 if (hcd->speed < HCD_USB3)
1085 temp = readl(port_array[wIndex] + PORTPMSC);
1086 temp &= ~PORT_U2_TIMEOUT_MASK;
1087 temp |= PORT_U2_TIMEOUT(timeout);
1088 writel(temp, port_array[wIndex] + PORTPMSC);
1093 /* unblock any posted writes */
1094 temp = readl(port_array[wIndex]);
1096 case ClearPortFeature:
1097 if (!wIndex || wIndex > max_ports)
1100 temp = readl(port_array[wIndex]);
1101 if (temp == 0xffffffff) {
1105 /* FIXME: What new port features do we need to support? */
1106 temp = xhci_port_state_to_neutral(temp);
1108 case USB_PORT_FEAT_SUSPEND:
1109 temp = readl(port_array[wIndex]);
1110 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1111 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1112 if (temp & PORT_RESET)
1114 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1115 if ((temp & PORT_PE) == 0)
1118 xhci_set_link_state(xhci, port_array, wIndex,
1120 spin_unlock_irqrestore(&xhci->lock, flags);
1122 spin_lock_irqsave(&xhci->lock, flags);
1123 xhci_set_link_state(xhci, port_array, wIndex,
1126 bus_state->port_c_suspend |= 1 << wIndex;
1128 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1131 xhci_dbg(xhci, "slot_id is zero\n");
1134 xhci_ring_device(xhci, slot_id);
1136 case USB_PORT_FEAT_C_SUSPEND:
1137 bus_state->port_c_suspend &= ~(1 << wIndex);
1138 case USB_PORT_FEAT_C_RESET:
1139 case USB_PORT_FEAT_C_BH_PORT_RESET:
1140 case USB_PORT_FEAT_C_CONNECTION:
1141 case USB_PORT_FEAT_C_OVER_CURRENT:
1142 case USB_PORT_FEAT_C_ENABLE:
1143 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1144 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1145 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1146 port_array[wIndex], temp);
1148 case USB_PORT_FEAT_ENABLE:
1149 xhci_disable_port(hcd, xhci, wIndex,
1150 port_array[wIndex], temp);
1152 case USB_PORT_FEAT_POWER:
1153 writel(temp & ~PORT_POWER, port_array[wIndex]);
1155 spin_unlock_irqrestore(&xhci->lock, flags);
1156 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1159 usb_acpi_set_power_state(hcd->self.root_hub,
1161 spin_lock_irqsave(&xhci->lock, flags);
1169 /* "stall" on error */
1172 spin_unlock_irqrestore(&xhci->lock, flags);
1177 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1178 * Ports are 0-indexed from the HCD point of view,
1179 * and 1-indexed from the USB core pointer of view.
1181 * Note that the status change bits will be cleared as soon as a port status
1182 * change event is generated, so we use the saved status from that event.
1184 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1186 unsigned long flags;
1190 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1192 __le32 __iomem **port_array;
1193 struct xhci_bus_state *bus_state;
1194 bool reset_change = false;
1196 max_ports = xhci_get_ports(hcd, &port_array);
1197 bus_state = &xhci->bus_state[hcd_index(hcd)];
1199 /* Initial status is no changes */
1200 retval = (max_ports + 8) / 8;
1201 memset(buf, 0, retval);
1204 * Inform the usbcore about resume-in-progress by returning
1205 * a non-zero value even if there are no status changes.
1207 status = bus_state->resuming_ports;
1209 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1211 spin_lock_irqsave(&xhci->lock, flags);
1212 /* For each port, did anything change? If so, set that bit in buf. */
1213 for (i = 0; i < max_ports; i++) {
1214 temp = readl(port_array[i]);
1215 if (temp == 0xffffffff) {
1219 if ((temp & mask) != 0 ||
1220 (bus_state->port_c_suspend & 1 << i) ||
1221 (bus_state->resume_done[i] && time_after_eq(
1222 jiffies, bus_state->resume_done[i]))) {
1223 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1226 if ((temp & PORT_RC))
1227 reset_change = true;
1229 if (!status && !reset_change) {
1230 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1231 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1233 spin_unlock_irqrestore(&xhci->lock, flags);
1234 return status ? retval : 0;
1239 int xhci_bus_suspend(struct usb_hcd *hcd)
1241 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1242 int max_ports, port_index;
1243 __le32 __iomem **port_array;
1244 struct xhci_bus_state *bus_state;
1245 unsigned long flags;
1247 max_ports = xhci_get_ports(hcd, &port_array);
1248 bus_state = &xhci->bus_state[hcd_index(hcd)];
1250 spin_lock_irqsave(&xhci->lock, flags);
1252 if (hcd->self.root_hub->do_remote_wakeup) {
1253 if (bus_state->resuming_ports || /* USB2 */
1254 bus_state->port_remote_wakeup) { /* USB3 */
1255 spin_unlock_irqrestore(&xhci->lock, flags);
1256 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1261 port_index = max_ports;
1262 bus_state->bus_suspended = 0;
1263 while (port_index--) {
1264 /* suspend the port if the port is not suspended */
1268 t1 = readl(port_array[port_index]);
1269 t2 = xhci_port_state_to_neutral(t1);
1271 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1272 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1273 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1276 spin_unlock_irqrestore(&xhci->lock, flags);
1277 xhci_stop_device(xhci, slot_id, 1);
1278 spin_lock_irqsave(&xhci->lock, flags);
1280 t2 &= ~PORT_PLS_MASK;
1281 t2 |= PORT_LINK_STROBE | XDEV_U3;
1282 set_bit(port_index, &bus_state->bus_suspended);
1284 /* USB core sets remote wake mask for USB 3.0 hubs,
1285 * including the USB 3.0 roothub, but only if CONFIG_PM
1286 * is enabled, so also enable remote wake here.
1288 if (hcd->self.root_hub->do_remote_wakeup) {
1289 if (t1 & PORT_CONNECT) {
1290 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1291 t2 &= ~PORT_WKCONN_E;
1293 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1294 t2 &= ~PORT_WKDISC_E;
1297 t2 &= ~PORT_WAKE_BITS;
1299 t1 = xhci_port_state_to_neutral(t1);
1301 writel(t2, port_array[port_index]);
1303 hcd->state = HC_STATE_SUSPENDED;
1304 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1305 spin_unlock_irqrestore(&xhci->lock, flags);
1309 int xhci_bus_resume(struct usb_hcd *hcd)
1311 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1312 int max_ports, port_index;
1313 __le32 __iomem **port_array;
1314 struct xhci_bus_state *bus_state;
1316 unsigned long flags;
1317 unsigned long port_was_suspended = 0;
1318 bool need_usb2_u3_exit = false;
1322 max_ports = xhci_get_ports(hcd, &port_array);
1323 bus_state = &xhci->bus_state[hcd_index(hcd)];
1325 if (time_before(jiffies, bus_state->next_statechange))
1328 spin_lock_irqsave(&xhci->lock, flags);
1329 if (!HCD_HW_ACCESSIBLE(hcd)) {
1330 spin_unlock_irqrestore(&xhci->lock, flags);
1334 /* delay the irqs */
1335 temp = readl(&xhci->op_regs->command);
1337 writel(temp, &xhci->op_regs->command);
1339 port_index = max_ports;
1340 while (port_index--) {
1341 /* Check whether need resume ports. If needed
1342 resume port and disable remote wakeup */
1345 temp = readl(port_array[port_index]);
1346 if (DEV_SUPERSPEED_ANY(temp))
1347 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1349 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1350 if (test_bit(port_index, &bus_state->bus_suspended) &&
1351 (temp & PORT_PLS_MASK)) {
1352 set_bit(port_index, &port_was_suspended);
1353 if (!DEV_SUPERSPEED_ANY(temp)) {
1354 xhci_set_link_state(xhci, port_array,
1355 port_index, XDEV_RESUME);
1356 need_usb2_u3_exit = true;
1359 writel(temp, port_array[port_index]);
1362 if (need_usb2_u3_exit) {
1363 spin_unlock_irqrestore(&xhci->lock, flags);
1365 spin_lock_irqsave(&xhci->lock, flags);
1368 port_index = max_ports;
1369 while (port_index--) {
1370 if (!(port_was_suspended & BIT(port_index)))
1372 /* Clear PLC to poll it later after XDEV_U0 */
1373 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1374 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1377 port_index = max_ports;
1378 while (port_index--) {
1379 if (!(port_was_suspended & BIT(port_index)))
1381 /* Poll and Clear PLC */
1382 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1383 PORT_PLC, 10 * 1000);
1385 xhci_warn(xhci, "port %d resume PLC timeout\n",
1387 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1388 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1390 xhci_ring_device(xhci, slot_id);
1393 (void) readl(&xhci->op_regs->command);
1395 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1396 /* re-enable irqs */
1397 temp = readl(&xhci->op_regs->command);
1399 writel(temp, &xhci->op_regs->command);
1400 temp = readl(&xhci->op_regs->command);
1402 spin_unlock_irqrestore(&xhci->lock, flags);
1406 #endif /* CONFIG_PM */