drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44         struct usb_host_endpoint *ep = urb->ep;
  45         struct urb_priv *urb_priv;
  46
  47         // ASSERT (urb->hcpriv != 0);
  48
  49  restart:
  50         urb_free_priv (ohci, urb->hcpriv);
  51         urb->hcpriv = NULL;
  52         if (likely(status == -EINPROGRESS))
  53                 status = 0;
  54
  55         switch (usb_pipetype (urb->pipe)) {
  56         case PIPE_ISOCHRONOUS:
  57                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  58                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  59                         if (quirk_amdiso(ohci))
  60                                 usb_amd_quirk_pll_enable();
  61                         if (quirk_amdprefetch(ohci))
  62                                 sb800_prefetch(ohci, 0);
  63                 }
  64                 break;
  65         case PIPE_INTERRUPT:
  66                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  67                 break;
  68         }
  69
  70 #ifdef OHCI_VERBOSE_DEBUG
  71         urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
  72 #endif
  73
  74         /* urb->complete() can reenter this HCD */
  75         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  76         spin_unlock (&ohci->lock);
  77         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  78         spin_lock (&ohci->lock);
  79
  80         /* stop periodic dma if it's not needed */
  81         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  82                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  83                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  84                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  85         }
  86
  87         /*
  88          * An isochronous URB that is sumitted too late won't have any TDs
  89          * (marked by the fact that the td_cnt value is larger than the
  90          * actual number of TDs).  If the next URB on this endpoint is like
  91          * that, give it back now.
  92          */
  93         if (!list_empty(&ep->urb_list)) {
  94                 urb = list_first_entry(&ep->urb_list, struct urb, urb_list);
  95                 urb_priv = urb->hcpriv;
  96                 if (urb_priv->td_cnt > urb_priv->length) {
  97                         status = 0;
  98                         goto restart;
  99                 }
 100         }
 101 }
 102
 103
 104 /*-------------------------------------------------------------------------*
 105  * ED handling functions
 106  *-------------------------------------------------------------------------*/
 107
 108 /* search for the right schedule branch to use for a periodic ed.
 109  * does some load balancing; returns the branch, or negative errno.
 110  */
 111 static int balance (struct ohci_hcd *ohci, int interval, int load)
 112 {
 113         int     i, branch = -ENOSPC;
 114
 115         /* iso periods can be huge; iso tds specify frame numbers */
 116         if (interval > NUM_INTS)
 117                 interval = NUM_INTS;
 118
 119         /* search for the least loaded schedule branch of that period
 120          * that has enough bandwidth left unreserved.
 121          */
 122         for (i = 0; i < interval ; i++) {
 123                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 124                         int     j;
 125
 126                         /* usb 1.1 says 90% of one frame */
 127                         for (j = i; j < NUM_INTS; j += interval) {
 128                                 if ((ohci->load [j] + load) > 900)
 129                                         break;
 130                         }
 131                         if (j < NUM_INTS)
 132                                 continue;
 133                         branch = i;
 134                 }
 135         }
 136         return branch;
 137 }
 138
 139 /*-------------------------------------------------------------------------*/
 140
 141 /* both iso and interrupt requests have periods; this routine puts them
 142  * into the schedule tree in the apppropriate place.  most iso devices use
 143  * 1msec periods, but that's not required.
 144  */
 145 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 146 {
 147         unsigned        i;
 148
 149         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 150                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 151                 ed, ed->branch, ed->load, ed->interval);
 152
 153         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 154                 struct ed       **prev = &ohci->periodic [i];
 155                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 156                 struct ed       *here = *prev;
 157
 158                 /* sorting each branch by period (slow before fast)
 159                  * lets us share the faster parts of the tree.
 160                  * (plus maybe: put interrupt eds before iso)
 161                  */
 162                 while (here && ed != here) {
 163                         if (ed->interval > here->interval)
 164                                 break;
 165                         prev = &here->ed_next;
 166                         prev_p = &here->hwNextED;
 167                         here = *prev;
 168                 }
 169                 if (ed != here) {
 170                         ed->ed_next = here;
 171                         if (here)
 172                                 ed->hwNextED = *prev_p;
 173                         wmb ();
 174                         *prev = ed;
 175                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 176                         wmb();
 177                 }
 178                 ohci->load [i] += ed->load;
 179         }
 180         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 181 }
 182
 183 /* link an ed into one of the HC chains */
 184
 185 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 186 {
 187         int     branch;
 188
 189         ed->state = ED_OPER;
 190         ed->ed_prev = NULL;
 191         ed->ed_next = NULL;
 192         ed->hwNextED = 0;
 193         if (quirk_zfmicro(ohci)
 194                         && (ed->type == PIPE_INTERRUPT)
 195                         && !(ohci->eds_scheduled++))
 196                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 197         wmb ();
 198
 199         /* we care about rm_list when setting CLE/BLE in case the HC was at
 200          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 201          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 202          *
 203          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 204          * periodic ones are singly linked (ed_next). that's because the
 205          * periodic schedule encodes a tree like figure 3-5 in the ohci
 206          * spec:  each qh can have several "previous" nodes, and the tree
 207          * doesn't have unused/idle descriptors.
 208          */
 209         switch (ed->type) {
 210         case PIPE_CONTROL:
 211                 if (ohci->ed_controltail == NULL) {
 212                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 213                         ohci_writel (ohci, ed->dma,
 214                                         &ohci->regs->ed_controlhead);
 215                 } else {
 216                         ohci->ed_controltail->ed_next = ed;
 217                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 218                                                                 ed->dma);
 219                 }
 220                 ed->ed_prev = ohci->ed_controltail;
 221                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 222                         wmb();
 223                         ohci->hc_control |= OHCI_CTRL_CLE;
 224                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 225                         ohci_writel (ohci, ohci->hc_control,
 226                                         &ohci->regs->control);
 227                 }
 228                 ohci->ed_controltail = ed;
 229                 break;
 230
 231         case PIPE_BULK:
 232                 if (ohci->ed_bulktail == NULL) {
 233                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 234                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 235                 } else {
 236                         ohci->ed_bulktail->ed_next = ed;
 237                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 238                                                                 ed->dma);
 239                 }
 240                 ed->ed_prev = ohci->ed_bulktail;
 241                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 242                         wmb();
 243                         ohci->hc_control |= OHCI_CTRL_BLE;
 244                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 245                         ohci_writel (ohci, ohci->hc_control,
 246                                         &ohci->regs->control);
 247                 }
 248                 ohci->ed_bulktail = ed;
 249                 break;
 250
 251         // case PIPE_INTERRUPT:
 252         // case PIPE_ISOCHRONOUS:
 253         default:
 254                 branch = balance (ohci, ed->interval, ed->load);
 255                 if (branch < 0) {
 256                         ohci_dbg (ohci,
 257                                 "ERR %d, interval %d msecs, load %d\n",
 258                                 branch, ed->interval, ed->load);
 259                         // FIXME if there are TDs queued, fail them!
 260                         return branch;
 261                 }
 262                 ed->branch = branch;
 263                 periodic_link (ohci, ed);
 264         }
 265
 266         /* the HC may not see the schedule updates yet, but if it does
 267          * then they'll be properly ordered.
 268          */
 269         return 0;
 270 }
 271
 272 /*-------------------------------------------------------------------------*/
 273
 274 /* scan the periodic table to find and unlink this ED */
 275 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 276 {
 277         int     i;
 278
 279         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 280                 struct ed       *temp;
 281                 struct ed       **prev = &ohci->periodic [i];
 282                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 283
 284                 while (*prev && (temp = *prev) != ed) {
 285                         prev_p = &temp->hwNextED;
 286                         prev = &temp->ed_next;
 287                 }
 288                 if (*prev) {
 289                         *prev_p = ed->hwNextED;
 290                         *prev = ed->ed_next;
 291                 }
 292                 ohci->load [i] -= ed->load;
 293         }
 294         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 295
 296         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 297                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 298                 ed, ed->branch, ed->load, ed->interval);
 299 }
 300
 301 /* unlink an ed from one of the HC chains.
 302  * just the link to the ed is unlinked.
 303  * the link from the ed still points to another operational ed or 0
 304  * so the HC can eventually finish the processing of the unlinked ed
 305  * (assuming it already started that, which needn't be true).
 306  *
 307  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 308  * it won't.  ED_SKIP means the HC will finish its current transaction,
 309  * but won't start anything new.  The TD queue may still grow; device
 310  * drivers don't know about this HCD-internal state.
 311  *
 312  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 313  *
 314  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 315  *    immediately.  HC should be working on them.
 316  *
 317  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 318  *    to care about this ED; safe to disable the endpoint.
 319  *
 320  * When finish_unlinks() runs later, after SOF interrupt, it will often
 321  * complete one or more URB unlinks before making that state change.
 322  */
 323 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 324 {
 325         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 326         wmb ();
 327         ed->state = ED_UNLINK;
 328
 329         /* To deschedule something from the control or bulk list, just
 330          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 331          * head/current registers until later, and "later" isn't very
 332          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 333          * the HC is reading the ED queues (while we modify them).
 334          *
 335          * For now, ed_schedule() is "later".  It might be good paranoia
 336          * to scrub those registers in finish_unlinks(), in case of bugs
 337          * that make the HC try to use them.
 338          */
 339         switch (ed->type) {
 340         case PIPE_CONTROL:
 341                 /* remove ED from the HC's list: */
 342                 if (ed->ed_prev == NULL) {
 343                         if (!ed->hwNextED) {
 344                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 345                                 ohci_writel (ohci, ohci->hc_control,
 346                                                 &ohci->regs->control);
 347                                 // a ohci_readl() later syncs CLE with the HC
 348                         } else
 349                                 ohci_writel (ohci,
 350                                         hc32_to_cpup (ohci, &ed->hwNextED),
 351                                         &ohci->regs->ed_controlhead);
 352                 } else {
 353                         ed->ed_prev->ed_next = ed->ed_next;
 354                         ed->ed_prev->hwNextED = ed->hwNextED;
 355                 }
 356                 /* remove ED from the HCD's list: */
 357                 if (ohci->ed_controltail == ed) {
 358                         ohci->ed_controltail = ed->ed_prev;
 359                         if (ohci->ed_controltail)
 360                                 ohci->ed_controltail->ed_next = NULL;
 361                 } else if (ed->ed_next) {
 362                         ed->ed_next->ed_prev = ed->ed_prev;
 363                 }
 364                 break;
 365
 366         case PIPE_BULK:
 367                 /* remove ED from the HC's list: */
 368                 if (ed->ed_prev == NULL) {
 369                         if (!ed->hwNextED) {
 370                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 371                                 ohci_writel (ohci, ohci->hc_control,
 372                                                 &ohci->regs->control);
 373                                 // a ohci_readl() later syncs BLE with the HC
 374                         } else
 375                                 ohci_writel (ohci,
 376                                         hc32_to_cpup (ohci, &ed->hwNextED),
 377                                         &ohci->regs->ed_bulkhead);
 378                 } else {
 379                         ed->ed_prev->ed_next = ed->ed_next;
 380                         ed->ed_prev->hwNextED = ed->hwNextED;
 381                 }
 382                 /* remove ED from the HCD's list: */
 383                 if (ohci->ed_bulktail == ed) {
 384                         ohci->ed_bulktail = ed->ed_prev;
 385                         if (ohci->ed_bulktail)
 386                                 ohci->ed_bulktail->ed_next = NULL;
 387                 } else if (ed->ed_next) {
 388                         ed->ed_next->ed_prev = ed->ed_prev;
 389                 }
 390                 break;
 391
 392         // case PIPE_INTERRUPT:
 393         // case PIPE_ISOCHRONOUS:
 394         default:
 395                 periodic_unlink (ohci, ed);
 396                 break;
 397         }
 398 }
 399
 400
 401 /*-------------------------------------------------------------------------*/
 402
 403 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 404  * of enumeration, usb_set_configuration() or usb_set_interface().
 405  */
 406 static struct ed *ed_get (
 407         struct ohci_hcd         *ohci,
 408         struct usb_host_endpoint *ep,
 409         struct usb_device       *udev,
 410         unsigned int            pipe,
 411         int                     interval
 412 ) {
 413         struct ed               *ed;
 414         unsigned long           flags;
 415
 416         spin_lock_irqsave (&ohci->lock, flags);
 417
 418         if (!(ed = ep->hcpriv)) {
 419                 struct td       *td;
 420                 int             is_out;
 421                 u32             info;
 422
 423                 ed = ed_alloc (ohci, GFP_ATOMIC);
 424                 if (!ed) {
 425                         /* out of memory */
 426                         goto done;
 427                 }
 428
 429                 /* dummy td; end of td list for ed */
 430                 td = td_alloc (ohci, GFP_ATOMIC);
 431                 if (!td) {
 432                         /* out of memory */
 433                         ed_free (ohci, ed);
 434                         ed = NULL;
 435                         goto done;
 436                 }
 437                 ed->dummy = td;
 438                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 439                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 440                 ed->state = ED_IDLE;
 441
 442                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 443
 444                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 445                  * succeeds ... otherwise we wouldn't need "pipe".
 446                  */
 447                 info = usb_pipedevice (pipe);
 448                 ed->type = usb_pipetype(pipe);
 449
 450                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 451                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 452                 if (udev->speed == USB_SPEED_LOW)
 453                         info |= ED_LOWSPEED;
 454                 /* only control transfers store pids in tds */
 455                 if (ed->type != PIPE_CONTROL) {
 456                         info |= is_out ? ED_OUT : ED_IN;
 457                         if (ed->type != PIPE_BULK) {
 458                                 /* periodic transfers... */
 459                                 if (ed->type == PIPE_ISOCHRONOUS)
 460                                         info |= ED_ISO;
 461                                 else if (interval > 32) /* iso can be bigger */
 462                                         interval = 32;
 463                                 ed->interval = interval;
 464                                 ed->load = usb_calc_bus_time (
 465                                         udev->speed, !is_out,
 466                                         ed->type == PIPE_ISOCHRONOUS,
 467                                         usb_endpoint_maxp(&ep->desc))
 468                                                 / 1000;
 469                         }
 470                 }
 471                 ed->hwINFO = cpu_to_hc32(ohci, info);
 472
 473                 ep->hcpriv = ed;
 474         }
 475
 476 done:
 477         spin_unlock_irqrestore (&ohci->lock, flags);
 478         return ed;
 479 }
 480
 481 /*-------------------------------------------------------------------------*/
 482
 483 /* request unlinking of an endpoint from an operational HC.
 484  * put the ep on the rm_list
 485  * real work is done at the next start frame (SF) hardware interrupt
 486  * caller guarantees HCD is running, so hardware access is safe,
 487  * and that ed->state is ED_OPER
 488  */
 489 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 490 {
 491         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 492         ed_deschedule (ohci, ed);
 493
 494         /* rm_list is just singly linked, for simplicity */
 495         ed->ed_next = ohci->ed_rm_list;
 496         ed->ed_prev = NULL;
 497         ohci->ed_rm_list = ed;
 498
 499         /* enable SOF interrupt */
 500         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 501         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 502         // flush those writes, and get latest HCCA contents
 503         (void) ohci_readl (ohci, &ohci->regs->control);
 504
 505         /* SF interrupt might get delayed; record the frame counter value that
 506          * indicates when the HC isn't looking at it, so concurrent unlinks
 507          * behave.  frame_no wraps every 2^16 msec, and changes right before
 508          * SF is triggered.
 509          */
 510         ed->tick = ohci_frame_no(ohci) + 1;
 511
 512 }
 513
 514 /*-------------------------------------------------------------------------*
 515  * TD handling functions
 516  *-------------------------------------------------------------------------*/
 517
 518 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 519
 520 static void
 521 td_fill (struct ohci_hcd *ohci, u32 info,
 522         dma_addr_t data, int len,
 523         struct urb *urb, int index)
 524 {
 525         struct td               *td, *td_pt;
 526         struct urb_priv         *urb_priv = urb->hcpriv;
 527         int                     is_iso = info & TD_ISO;
 528         int                     hash;
 529
 530         // ASSERT (index < urb_priv->length);
 531
 532         /* aim for only one interrupt per urb.  mostly applies to control
 533          * and iso; other urbs rarely need more than one TD per urb.
 534          * this way, only final tds (or ones with an error) cause IRQs.
 535          * at least immediately; use DI=6 in case any control request is
 536          * tempted to die part way through.  (and to force the hc to flush
 537          * its donelist soonish, even on unlink paths.)
 538          *
 539          * NOTE: could delay interrupts even for the last TD, and get fewer
 540          * interrupts ... increasing per-urb latency by sharing interrupts.
 541          * Drivers that queue bulk urbs may request that behavior.
 542          */
 543         if (index != (urb_priv->length - 1)
 544                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 545                 info |= TD_DI_SET (6);
 546
 547         /* use this td as the next dummy */
 548         td_pt = urb_priv->td [index];
 549
 550         /* fill the old dummy TD */
 551         td = urb_priv->td [index] = urb_priv->ed->dummy;
 552         urb_priv->ed->dummy = td_pt;
 553
 554         td->ed = urb_priv->ed;
 555         td->next_dl_td = NULL;
 556         td->index = index;
 557         td->urb = urb;
 558         td->data_dma = data;
 559         if (!len)
 560                 data = 0;
 561
 562         td->hwINFO = cpu_to_hc32 (ohci, info);
 563         if (is_iso) {
 564                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 565                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 566                                                 (data & 0x0FFF) | 0xE000);
 567         } else {
 568                 td->hwCBP = cpu_to_hc32 (ohci, data);
 569         }
 570         if (data)
 571                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 572         else
 573                 td->hwBE = 0;
 574         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 575
 576         /* append to queue */
 577         list_add_tail (&td->td_list, &td->ed->td_list);
 578
 579         /* hash it for later reverse mapping */
 580         hash = TD_HASH_FUNC (td->td_dma);
 581         td->td_hash = ohci->td_hash [hash];
 582         ohci->td_hash [hash] = td;
 583
 584         /* HC might read the TD (or cachelines) right away ... */
 585         wmb ();
 586         td->ed->hwTailP = td->hwNextTD;
 587 }
 588
 589 /*-------------------------------------------------------------------------*/
 590
 591 /* Prepare all TDs of a transfer, and queue them onto the ED.
 592  * Caller guarantees HC is active.
 593  * Usually the ED is already on the schedule, so TDs might be
 594  * processed as soon as they're queued.
 595  */
 596 static void td_submit_urb (
 597         struct ohci_hcd *ohci,
 598         struct urb      *urb
 599 ) {
 600         struct urb_priv *urb_priv = urb->hcpriv;
 601         dma_addr_t      data;
 602         int             data_len = urb->transfer_buffer_length;
 603         int             cnt = 0;
 604         u32             info = 0;
 605         int             is_out = usb_pipeout (urb->pipe);
 606         int             periodic = 0;
 607
 608         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 609          * use the device toggle bits for resetting, and rely on the fact
 610          * that resetting toggle is meaningless if the endpoint is active.
 611          */
 612         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 613                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 614                         is_out, 1);
 615                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 616         }
 617
 618         list_add (&urb_priv->pending, &ohci->pending);
 619
 620         if (data_len)
 621                 data = urb->transfer_dma;
 622         else
 623                 data = 0;
 624
 625         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 626          * using TD_CC_GET, as well as by seeing them on the done list.
 627          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 628          */
 629         switch (urb_priv->ed->type) {
 630
 631         /* Bulk and interrupt are identical except for where in the schedule
 632          * their EDs live.
 633          */
 634         case PIPE_INTERRUPT:
 635                 /* ... and periodic urbs have extra accounting */
 636                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 637                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 638                 /* FALLTHROUGH */
 639         case PIPE_BULK:
 640                 info = is_out
 641                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 642                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 643                 /* TDs _could_ transfer up to 8K each */
 644                 while (data_len > 4096) {
 645                         td_fill (ohci, info, data, 4096, urb, cnt);
 646                         data += 4096;
 647                         data_len -= 4096;
 648                         cnt++;
 649                 }
 650                 /* maybe avoid ED halt on final TD short read */
 651                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 652                         info |= TD_R;
 653                 td_fill (ohci, info, data, data_len, urb, cnt);
 654                 cnt++;
 655                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 656                                 && cnt < urb_priv->length) {
 657                         td_fill (ohci, info, 0, 0, urb, cnt);
 658                         cnt++;
 659                 }
 660                 /* maybe kickstart bulk list */
 661                 if (urb_priv->ed->type == PIPE_BULK) {
 662                         wmb ();
 663                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 664                 }
 665                 break;
 666
 667         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 668          * any DATA phase works normally, and the STATUS ack is special.
 669          */
 670         case PIPE_CONTROL:
 671                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 672                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 673                 if (data_len > 0) {
 674                         info = TD_CC | TD_R | TD_T_DATA1;
 675                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 676                         /* NOTE:  mishandles transfers >8K, some >4K */
 677                         td_fill (ohci, info, data, data_len, urb, cnt++);
 678                 }
 679                 info = (is_out || data_len == 0)
 680                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 681                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 682                 td_fill (ohci, info, data, 0, urb, cnt++);
 683                 /* maybe kickstart control list */
 684                 wmb ();
 685                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 686                 break;
 687
 688         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 689          * Each TD could handle multiple consecutive frames (interval 1);
 690          * we could often reduce the number of TDs here.
 691          */
 692         case PIPE_ISOCHRONOUS:
 693                 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
 694                                 cnt++) {
 695                         int     frame = urb->start_frame;
 696
 697                         // FIXME scheduling should handle frame counter
 698                         // roll-around ... exotic case (and OHCI has
 699                         // a 2^16 iso range, vs other HCs max of 2^10)
 700                         frame += cnt * urb->interval;
 701                         frame &= 0xffff;
 702                         td_fill (ohci, TD_CC | TD_ISO | frame,
 703                                 data + urb->iso_frame_desc [cnt].offset,
 704                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 705                 }
 706                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 707                         if (quirk_amdiso(ohci))
 708                                 usb_amd_quirk_pll_disable();
 709                         if (quirk_amdprefetch(ohci))
 710                                 sb800_prefetch(ohci, 1);
 711                 }
 712                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 713                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 714                 break;
 715         }
 716
 717         /* start periodic dma if needed */
 718         if (periodic) {
 719                 wmb ();
 720                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 721                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 722         }
 723
 724         // ASSERT (urb_priv->length == cnt);
 725 }
 726
 727 /*-------------------------------------------------------------------------*
 728  * Done List handling functions
 729  *-------------------------------------------------------------------------*/
 730
 731 /* calculate transfer length/status and update the urb */
 732 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 733 {
 734         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 735         int     cc = 0;
 736         int     status = -EINPROGRESS;
 737
 738         list_del (&td->td_list);
 739
 740         /* ISO ... drivers see per-TD length/status */
 741         if (tdINFO & TD_ISO) {
 742                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 743                 int     dlen = 0;
 744
 745                 /* NOTE:  assumes FC in tdINFO == 0, and that
 746                  * only the first of 0..MAXPSW psws is used.
 747                  */
 748
 749                 cc = (tdPSW >> 12) & 0xF;
 750                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 751                         return status;
 752
 753                 if (usb_pipeout (urb->pipe))
 754                         dlen = urb->iso_frame_desc [td->index].length;
 755                 else {
 756                         /* short reads are always OK for ISO */
 757                         if (cc == TD_DATAUNDERRUN)
 758                                 cc = TD_CC_NOERROR;
 759                         dlen = tdPSW & 0x3ff;
 760                 }
 761                 urb->actual_length += dlen;
 762                 urb->iso_frame_desc [td->index].actual_length = dlen;
 763                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 764
 765                 if (cc != TD_CC_NOERROR)
 766                         ohci_vdbg (ohci,
 767                                 "urb %p iso td %p (%d) len %d cc %d\n",
 768                                 urb, td, 1 + td->index, dlen, cc);
 769
 770         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 771          * except that "setup" bytes aren't counted and "short" transfers
 772          * might not be reported as errors.
 773          */
 774         } else {
 775                 int     type = usb_pipetype (urb->pipe);
 776                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 777
 778                 cc = TD_CC_GET (tdINFO);
 779
 780                 /* update packet status if needed (short is normally ok) */
 781                 if (cc == TD_DATAUNDERRUN
 782                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 783                         cc = TD_CC_NOERROR;
 784                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 785                         status = cc_to_error[cc];
 786
 787                 /* count all non-empty packets except control SETUP packet */
 788                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 789                         if (td->hwCBP == 0)
 790                                 urb->actual_length += tdBE - td->data_dma + 1;
 791                         else
 792                                 urb->actual_length +=
 793                                           hc32_to_cpup (ohci, &td->hwCBP)
 794                                         - td->data_dma;
 795                 }
 796
 797                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 798                         ohci_vdbg (ohci,
 799                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 800                                 urb, td, 1 + td->index, cc,
 801                                 urb->actual_length,
 802                                 urb->transfer_buffer_length);
 803         }
 804         return status;
 805 }
 806
 807 /*-------------------------------------------------------------------------*/
 808
 809 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 810 {
 811         struct urb              *urb = td->urb;
 812         urb_priv_t              *urb_priv = urb->hcpriv;
 813         struct ed               *ed = td->ed;
 814         struct list_head        *tmp = td->td_list.next;
 815         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 816
 817         /* clear ed halt; this is the td that caused it, but keep it inactive
 818          * until its urb->complete() has a chance to clean up.
 819          */
 820         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 821         wmb ();
 822         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 823
 824         /* Get rid of all later tds from this urb.  We don't have
 825          * to be careful: no errors and nothing was transferred.
 826          * Also patch the ed so it looks as if those tds completed normally.
 827          */
 828         while (tmp != &ed->td_list) {
 829                 struct td       *next;
 830
 831                 next = list_entry (tmp, struct td, td_list);
 832                 tmp = next->td_list.next;
 833
 834                 if (next->urb != urb)
 835                         break;
 836
 837                 /* NOTE: if multi-td control DATA segments get supported,
 838                  * this urb had one of them, this td wasn't the last td
 839                  * in that segment (TD_R clear), this ed halted because
 840                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 841                  * then we need to leave the control STATUS packet queued
 842                  * and clear ED_SKIP.
 843                  */
 844
 845                 list_del(&next->td_list);
 846                 urb_priv->td_cnt++;
 847                 ed->hwHeadP = next->hwNextTD | toggle;
 848         }
 849
 850         /* help for troubleshooting:  report anything that
 851          * looks odd ... that doesn't include protocol stalls
 852          * (or maybe some other things)
 853          */
 854         switch (cc) {
 855         case TD_DATAUNDERRUN:
 856                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 857                         break;
 858                 /* fallthrough */
 859         case TD_CC_STALL:
 860                 if (usb_pipecontrol (urb->pipe))
 861                         break;
 862                 /* fallthrough */
 863         default:
 864                 ohci_dbg (ohci,
 865                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 866                         urb, urb->dev->devpath,
 867                         usb_pipeendpoint (urb->pipe),
 868                         usb_pipein (urb->pipe) ? "in" : "out",
 869                         hc32_to_cpu (ohci, td->hwINFO),
 870                         cc, cc_to_error [cc]);
 871         }
 872 }
 873
 874 /* replies to the request have to be on a FIFO basis so
 875  * we unreverse the hc-reversed done-list
 876  */
 877 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 878 {
 879         u32             td_dma;
 880         struct td       *td_rev = NULL;
 881         struct td       *td = NULL;
 882
 883         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 884         ohci->hcca->done_head = 0;
 885         wmb();
 886
 887         /* get TD from hc's singly linked list, and
 888          * prepend to ours.  ed->td_list changes later.
 889          */
 890         while (td_dma) {
 891                 int             cc;
 892
 893                 td = dma_to_td (ohci, td_dma);
 894                 if (!td) {
 895                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 896                         break;
 897                 }
 898
 899                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 900                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 901
 902                 /* Non-iso endpoints can halt on error; un-halt,
 903                  * and dequeue any other TDs from this urb.
 904                  * No other TD could have caused the halt.
 905                  */
 906                 if (cc != TD_CC_NOERROR
 907                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 908                         ed_halted(ohci, td, cc);
 909
 910                 td->next_dl_td = td_rev;
 911                 td_rev = td;
 912                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 913         }
 914         return td_rev;
 915 }
 916
 917 /*-------------------------------------------------------------------------*/
 918
 919 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 920 static void
 921 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 922 {
 923         struct ed       *ed, **last;
 924
 925 rescan_all:
 926         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 927                 struct list_head        *entry, *tmp;
 928                 int                     completed, modified;
 929                 __hc32                  *prev;
 930
 931                 /* only take off EDs that the HC isn't using, accounting for
 932                  * frame counter wraps and EDs with partially retired TDs
 933                  */
 934                 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
 935                         if (tick_before (tick, ed->tick)) {
 936 skip_ed:
 937                                 last = &ed->ed_next;
 938                                 continue;
 939                         }
 940
 941                         if (!list_empty (&ed->td_list)) {
 942                                 struct td       *td;
 943                                 u32             head;
 944
 945                                 td = list_entry (ed->td_list.next, struct td,
 946                                                         td_list);
 947                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 948                                                                 TD_MASK;
 949
 950                                 /* INTR_WDH may need to clean up first */
 951                                 if (td->td_dma != head) {
 952                                         if (ed == ohci->ed_to_check)
 953                                                 ohci->ed_to_check = NULL;
 954                                         else
 955                                                 goto skip_ed;
 956                                 }
 957                         }
 958                 }
 959
 960                 /* reentrancy:  if we drop the schedule lock, someone might
 961                  * have modified this list.  normally it's just prepending
 962                  * entries (which we'd ignore), but paranoia won't hurt.
 963                  */
 964                 *last = ed->ed_next;
 965                 ed->ed_next = NULL;
 966                 modified = 0;
 967
 968                 /* unlink urbs as requested, but rescan the list after
 969                  * we call a completion since it might have unlinked
 970                  * another (earlier) urb
 971                  *
 972                  * When we get here, the HC doesn't see this ed.  But it
 973                  * must not be rescheduled until all completed URBs have
 974                  * been given back to the driver.
 975                  */
 976 rescan_this:
 977                 completed = 0;
 978                 prev = &ed->hwHeadP;
 979                 list_for_each_safe (entry, tmp, &ed->td_list) {
 980                         struct td       *td;
 981                         struct urb      *urb;
 982                         urb_priv_t      *urb_priv;
 983                         __hc32          savebits;
 984                         u32             tdINFO;
 985
 986                         td = list_entry (entry, struct td, td_list);
 987                         urb = td->urb;
 988                         urb_priv = td->urb->hcpriv;
 989
 990                         if (!urb->unlinked) {
 991                                 prev = &td->hwNextTD;
 992                                 continue;
 993                         }
 994
 995                         /* patch pointer hc uses */
 996                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 997                         *prev = td->hwNextTD | savebits;
 998
 999                         /* If this was unlinked, the TD may not have been
1000                          * retired ... so manually save the data toggle.
1001                          * The controller ignores the value we save for
1002                          * control and ISO endpoints.
1003                          */
1004                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
1005                         if ((tdINFO & TD_T) == TD_T_DATA0)
1006                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
1007                         else if ((tdINFO & TD_T) == TD_T_DATA1)
1008                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
1009
1010                         /* HC may have partly processed this TD */
1011                         td_done (ohci, urb, td);
1012                         urb_priv->td_cnt++;
1013
1014                         /* if URB is done, clean up */
1015                         if (urb_priv->td_cnt >= urb_priv->length) {
1016                                 modified = completed = 1;
1017                                 finish_urb(ohci, urb, 0);
1018                         }
1019                 }
1020                 if (completed && !list_empty (&ed->td_list))
1021                         goto rescan_this;
1022
1023                 /* ED's now officially unlinked, hc doesn't see */
1024                 ed->state = ED_IDLE;
1025                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1026                         ohci->eds_scheduled--;
1027                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1028                 ed->hwNextED = 0;
1029                 wmb ();
1030                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1031
1032                 /* but if there's work queued, reschedule */
1033                 if (!list_empty (&ed->td_list)) {
1034                         if (ohci->rh_state == OHCI_RH_RUNNING)
1035                                 ed_schedule (ohci, ed);
1036                 }
1037
1038                 if (modified)
1039                         goto rescan_all;
1040         }
1041
1042         /* maybe reenable control and bulk lists */
1043         if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1044                 u32     command = 0, control = 0;
1045
1046                 if (ohci->ed_controltail) {
1047                         command |= OHCI_CLF;
1048                         if (quirk_zfmicro(ohci))
1049                                 mdelay(1);
1050                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1051                                 control |= OHCI_CTRL_CLE;
1052                                 ohci_writel (ohci, 0,
1053                                         &ohci->regs->ed_controlcurrent);
1054                         }
1055                 }
1056                 if (ohci->ed_bulktail) {
1057                         command |= OHCI_BLF;
1058                         if (quirk_zfmicro(ohci))
1059                                 mdelay(1);
1060                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1061                                 control |= OHCI_CTRL_BLE;
1062                                 ohci_writel (ohci, 0,
1063                                         &ohci->regs->ed_bulkcurrent);
1064                         }
1065                 }
1066
1067                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1068                 if (control) {
1069                         ohci->hc_control |= control;
1070                         if (quirk_zfmicro(ohci))
1071                                 mdelay(1);
1072                         ohci_writel (ohci, ohci->hc_control,
1073                                         &ohci->regs->control);
1074                 }
1075                 if (command) {
1076                         if (quirk_zfmicro(ohci))
1077                                 mdelay(1);
1078                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1079                 }
1080         }
1081 }
1082
1083
1084
1085 /*-------------------------------------------------------------------------*/
1086
1087 /*
1088  * Used to take back a TD from the host controller. This would normally be
1089  * called from within dl_done_list, however it may be called directly if the
1090  * HC no longer sees the TD and it has not appeared on the donelist (after
1091  * two frames).  This bug has been observed on ZF Micro systems.
1092  */
1093 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1094 {
1095         struct urb      *urb = td->urb;
1096         urb_priv_t      *urb_priv = urb->hcpriv;
1097         struct ed       *ed = td->ed;
1098         int             status;
1099
1100         /* update URB's length and status from TD */
1101         status = td_done(ohci, urb, td);
1102         urb_priv->td_cnt++;
1103
1104         /* If all this urb's TDs are done, call complete() */
1105         if (urb_priv->td_cnt >= urb_priv->length)
1106                 finish_urb(ohci, urb, status);
1107
1108         /* clean schedule:  unlink EDs that are no longer busy */
1109         if (list_empty(&ed->td_list)) {
1110                 if (ed->state == ED_OPER)
1111                         start_ed_unlink(ohci, ed);
1112
1113         /* ... reenabling halted EDs only after fault cleanup */
1114         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1115                         == cpu_to_hc32(ohci, ED_SKIP)) {
1116                 td = list_entry(ed->td_list.next, struct td, td_list);
1117                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1118                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1119                         /* ... hc may need waking-up */
1120                         switch (ed->type) {
1121                         case PIPE_CONTROL:
1122                                 ohci_writel(ohci, OHCI_CLF,
1123                                                 &ohci->regs->cmdstatus);
1124                                 break;
1125                         case PIPE_BULK:
1126                                 ohci_writel(ohci, OHCI_BLF,
1127                                                 &ohci->regs->cmdstatus);
1128                                 break;
1129                         }
1130                 }
1131         }
1132 }
1133
1134 /*
1135  * Process normal completions (error or success) and clean the schedules.
1136  *
1137  * This is the main path for handing urbs back to drivers.  The only other
1138  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1139  * instead of scanning the (re-reversed) donelist as this does.  There's
1140  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1141  * with TDs that appear to be orphaned are directly reclaimed.
1142  */
1143 static void
1144 dl_done_list (struct ohci_hcd *ohci)
1145 {
1146         struct td       *td = dl_reverse_done_list (ohci);
1147
1148         while (td) {
1149                 struct td       *td_next = td->next_dl_td;
1150                 struct ed       *ed = td->ed;
1151
1152                 /*
1153                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1154                  * occasionally forget to add TDs to the done queue.  Since
1155                  * TDs for a given endpoint are always processed in order,
1156                  * if we find a TD on the donelist then all of its
1157                  * predecessors must be finished as well.
1158                  */
1159                 for (;;) {
1160                         struct td       *td2;
1161
1162                         td2 = list_first_entry(&ed->td_list, struct td,
1163                                         td_list);
1164                         if (td2 == td)
1165                                 break;
1166                         takeback_td(ohci, td2);
1167                 }
1168
1169                 takeback_td(ohci, td);
1170                 td = td_next;
1171         }
1172 }