2 * Open Host Controller Interface (OHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
20 * This file is licenced under the GPL.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name [] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
79 #include "pci-quirks.h"
81 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
82 static int ohci_init (struct ohci_hcd *ohci);
83 static void ohci_stop (struct usb_hcd *hcd);
85 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
86 static int ohci_restart (struct ohci_hcd *ohci);
90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
92 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
100 #include "ohci-dbg.c"
101 #include "ohci-mem.c"
106 * On architectures with edge-triggered interrupts we must never return
109 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
110 #define IRQ_NOTMINE IRQ_HANDLED
112 #define IRQ_NOTMINE IRQ_NONE
116 /* Some boards misreport power switching/overcurrent */
117 static bool distrust_firmware = 1;
118 module_param (distrust_firmware, bool, 0);
119 MODULE_PARM_DESC (distrust_firmware,
120 "true to distrust firmware power/overcurrent setup");
122 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
123 static bool no_handshake = 0;
124 module_param (no_handshake, bool, 0);
125 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
127 /*-------------------------------------------------------------------------*/
130 * queue up an urb for anything except the root hub
132 static int ohci_urb_enqueue (
137 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
139 urb_priv_t *urb_priv;
140 unsigned int pipe = urb->pipe;
145 #ifdef OHCI_VERBOSE_DEBUG
146 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
149 /* every endpoint has a ed, locate and maybe (re)initialize it */
150 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
153 /* for the private part of the URB we need the number of TDs (size) */
156 /* td_submit_urb() doesn't yet handle these */
157 if (urb->transfer_buffer_length > 4096)
160 /* 1 TD for setup, 1 for ACK, plus ... */
163 // case PIPE_INTERRUPT:
166 /* one TD for every 4096 Bytes (can be up to 8K) */
167 size += urb->transfer_buffer_length / 4096;
168 /* ... and for any remaining bytes ... */
169 if ((urb->transfer_buffer_length % 4096) != 0)
171 /* ... and maybe a zero length packet to wrap it up */
174 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
175 && (urb->transfer_buffer_length
176 % usb_maxpacket (urb->dev, pipe,
177 usb_pipeout (pipe))) == 0)
180 case PIPE_ISOCHRONOUS: /* number of packets from URB */
181 size = urb->number_of_packets;
185 /* allocate the private part of the URB */
186 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
190 INIT_LIST_HEAD (&urb_priv->pending);
191 urb_priv->length = size;
194 /* allocate the TDs (deferring hash chain updates) */
195 for (i = 0; i < size; i++) {
196 urb_priv->td [i] = td_alloc (ohci, mem_flags);
197 if (!urb_priv->td [i]) {
198 urb_priv->length = i;
199 urb_free_priv (ohci, urb_priv);
204 spin_lock_irqsave (&ohci->lock, flags);
206 /* don't submit to a dead HC */
207 if (!HCD_HW_ACCESSIBLE(hcd)) {
211 if (ohci->rh_state != OHCI_RH_RUNNING) {
215 retval = usb_hcd_link_urb_to_ep(hcd, urb);
219 /* schedule the ed if needed */
220 if (ed->state == ED_IDLE) {
221 retval = ed_schedule (ohci, ed);
223 usb_hcd_unlink_urb_from_ep(hcd, urb);
226 if (ed->type == PIPE_ISOCHRONOUS) {
227 u16 frame = ohci_frame_no(ohci);
229 /* delay a few frames before the first TD */
230 frame += max_t (u16, 8, ed->interval);
231 frame &= ~(ed->interval - 1);
233 urb->start_frame = frame;
234 ed->last_iso = frame + ed->interval * (size - 1);
236 } else if (ed->type == PIPE_ISOCHRONOUS) {
237 u16 next = ohci_frame_no(ohci) + 1;
238 u16 frame = ed->last_iso + ed->interval;
239 u16 length = ed->interval * (size - 1);
241 /* Behind the scheduling threshold? */
242 if (unlikely(tick_before(frame, next))) {
244 /* URB_ISO_ASAP: Round up to the first available slot */
245 if (urb->transfer_flags & URB_ISO_ASAP) {
246 frame += (next - frame + ed->interval - 1) &
250 * Not ASAP: Use the next slot in the stream,
255 * Some OHCI hardware doesn't handle late TDs
256 * correctly. After retiring them it proceeds
257 * to the next ED instead of the next TD.
258 * Therefore we have to omit the late TDs
261 urb_priv->td_cnt = DIV_ROUND_UP(
262 (u16) (next - frame),
264 if (urb_priv->td_cnt >= urb_priv->length) {
265 ++urb_priv->td_cnt; /* Mark it */
266 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
272 urb->start_frame = frame;
273 ed->last_iso = frame + length;
276 /* fill the TDs and link them to the ed; and
277 * enable that part of the schedule, if needed
278 * and update count of queued periodic urbs
280 urb->hcpriv = urb_priv;
281 td_submit_urb (ohci, urb);
285 urb_free_priv (ohci, urb_priv);
286 spin_unlock_irqrestore (&ohci->lock, flags);
291 * decouple the URB from the HC queues (TDs, urb_priv).
292 * reporting is always done
293 * asynchronously, and we might be dealing with an urb that's
294 * partially transferred, or an ED with other urbs being unlinked.
296 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
298 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
302 #ifdef OHCI_VERBOSE_DEBUG
303 urb_print(urb, "UNLINK", 1, status);
306 spin_lock_irqsave (&ohci->lock, flags);
307 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
310 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
311 urb_priv_t *urb_priv;
313 /* Unless an IRQ completed the unlink while it was being
314 * handed to us, flag it for unlink and giveback, and force
315 * some upcoming INTR_SF to call finish_unlinks()
317 urb_priv = urb->hcpriv;
319 if (urb_priv->ed->state == ED_OPER)
320 start_ed_unlink (ohci, urb_priv->ed);
324 * with HC dead, we won't respect hc queue pointers
325 * any more ... just clean up every urb's memory.
328 finish_urb(ohci, urb, status);
330 spin_unlock_irqrestore (&ohci->lock, flags);
334 /*-------------------------------------------------------------------------*/
336 /* frees config/altsetting state for endpoints,
337 * including ED memory, dummy TD, and bulk/intr data toggle
341 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
343 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
345 struct ed *ed = ep->hcpriv;
346 unsigned limit = 1000;
348 /* ASSERT: any requests/urbs are being unlinked */
349 /* ASSERT: nobody can be submitting urbs for this any more */
355 spin_lock_irqsave (&ohci->lock, flags);
357 if (ohci->rh_state != OHCI_RH_RUNNING) {
360 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
361 ohci->eds_scheduled--;
362 finish_unlinks (ohci, 0);
366 case ED_UNLINK: /* wait for hw to finish? */
367 /* major IRQ delivery trouble loses INTR_SF too... */
369 ohci_warn(ohci, "ED unlink timeout\n");
370 if (quirk_zfmicro(ohci)) {
371 ohci_warn(ohci, "Attempting ZF TD recovery\n");
372 ohci->ed_to_check = ed;
377 spin_unlock_irqrestore (&ohci->lock, flags);
378 schedule_timeout_uninterruptible(1);
380 case ED_IDLE: /* fully unlinked */
381 if (list_empty (&ed->td_list)) {
382 td_free (ohci, ed->dummy);
386 /* else FALL THROUGH */
388 /* caller was supposed to have unlinked any requests;
389 * that's not our job. can't recover; must leak ed.
391 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
392 ed, ep->desc.bEndpointAddress, ed->state,
393 list_empty (&ed->td_list) ? "" : " (has tds)");
394 td_free (ohci, ed->dummy);
398 spin_unlock_irqrestore (&ohci->lock, flags);
401 static int ohci_get_frame (struct usb_hcd *hcd)
403 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
405 return ohci_frame_no(ohci);
408 static void ohci_usb_reset (struct ohci_hcd *ohci)
410 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
411 ohci->hc_control &= OHCI_CTRL_RWC;
412 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
413 ohci->rh_state = OHCI_RH_HALTED;
416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
417 * other cases where the next software may expect clean state from the
418 * "firmware". this is bus-neutral, unlike shutdown() methods.
421 ohci_shutdown (struct usb_hcd *hcd)
423 struct ohci_hcd *ohci;
425 ohci = hcd_to_ohci (hcd);
426 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
428 /* Software reset, after which the controller goes into SUSPEND */
429 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
430 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
433 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
436 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
438 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
439 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
440 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
441 && !list_empty(&ed->td_list);
444 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
445 * an interrupt TD but neglects to add it to the donelist. On systems with
446 * this chipset, we need to periodically check the state of the queues to look
447 * for such "lost" TDs.
449 static void unlink_watchdog_func(unsigned long _ohci)
453 unsigned seen_count = 0;
455 struct ed **seen = NULL;
456 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
458 spin_lock_irqsave(&ohci->lock, flags);
459 max = ohci->eds_scheduled;
463 if (ohci->ed_to_check)
466 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
470 for (i = 0; i < NUM_INTS; i++) {
471 struct ed *ed = ohci->periodic[i];
476 /* scan this branch of the periodic schedule tree */
477 for (temp = 0; temp < seen_count; temp++) {
478 if (seen[temp] == ed) {
479 /* we've checked it and what's after */
486 seen[seen_count++] = ed;
487 if (!check_ed(ohci, ed)) {
492 /* HC's TD list is empty, but HCD sees at least one
493 * TD that's not been sent through the donelist.
495 ohci->ed_to_check = ed;
498 /* The HC may wait until the next frame to report the
499 * TD as done through the donelist and INTR_WDH. (We
500 * just *assume* it's not a multi-TD interrupt URB;
501 * those could defer the IRQ more than one frame, using
502 * DI...) Check again after the next INTR_SF.
504 ohci_writel(ohci, OHCI_INTR_SF,
505 &ohci->regs->intrstatus);
506 ohci_writel(ohci, OHCI_INTR_SF,
507 &ohci->regs->intrenable);
509 /* flush those writes */
510 (void) ohci_readl(ohci, &ohci->regs->control);
517 if (ohci->eds_scheduled)
518 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
520 spin_unlock_irqrestore(&ohci->lock, flags);
523 /*-------------------------------------------------------------------------*
525 *-------------------------------------------------------------------------*/
527 /* init memory, and kick BIOS/SMM off */
529 static int ohci_init (struct ohci_hcd *ohci)
532 struct usb_hcd *hcd = ohci_to_hcd(ohci);
534 if (distrust_firmware)
535 ohci->flags |= OHCI_QUIRK_HUB_POWER;
537 ohci->rh_state = OHCI_RH_HALTED;
538 ohci->regs = hcd->regs;
540 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
541 * was never needed for most non-PCI systems ... remove the code?
545 /* SMM owns the HC? not for long! */
546 if (!no_handshake && ohci_readl (ohci,
547 &ohci->regs->control) & OHCI_CTRL_IR) {
550 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
552 /* this timeout is arbitrary. we make it long, so systems
553 * depending on usb keyboards may be usable even if the
554 * BIOS/SMM code seems pretty broken.
556 temp = 500; /* arbitrary: five seconds */
558 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
559 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
560 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
563 ohci_err (ohci, "USB HC takeover failed!"
564 " (BIOS/SMM bug)\n");
568 ohci_usb_reset (ohci);
572 /* Disable HC interrupts */
573 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
575 /* flush the writes, and save key bits like RWC */
576 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
577 ohci->hc_control |= OHCI_CTRL_RWC;
579 /* Read the number of ports unless overridden */
580 if (ohci->num_ports == 0)
581 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
586 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
587 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
591 if ((ret = ohci_mem_init (ohci)) < 0)
594 create_debug_files (ohci);
600 /*-------------------------------------------------------------------------*/
602 /* Start an OHCI controller, set the BUS operational
603 * resets USB and controller
606 static int ohci_run (struct ohci_hcd *ohci)
609 int first = ohci->fminterval == 0;
610 struct usb_hcd *hcd = ohci_to_hcd(ohci);
612 ohci->rh_state = OHCI_RH_HALTED;
614 /* boot firmware should have set this up (5.1.1.3.1) */
617 val = ohci_readl (ohci, &ohci->regs->fminterval);
618 ohci->fminterval = val & 0x3fff;
619 if (ohci->fminterval != FI)
620 ohci_dbg (ohci, "fminterval delta %d\n",
621 ohci->fminterval - FI);
622 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
623 /* also: power/overcurrent flags in roothub.a */
626 /* Reset USB nearly "by the book". RemoteWakeupConnected has
627 * to be checked in case boot firmware (BIOS/SMM/...) has set up
628 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
629 * If the bus glue detected wakeup capability then it should
630 * already be enabled; if so we'll just enable it again.
632 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
633 device_set_wakeup_capable(hcd->self.controller, 1);
635 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
639 case OHCI_USB_SUSPEND:
640 case OHCI_USB_RESUME:
641 ohci->hc_control &= OHCI_CTRL_RWC;
642 ohci->hc_control |= OHCI_USB_RESUME;
643 val = 10 /* msec wait */;
645 // case OHCI_USB_RESET:
647 ohci->hc_control &= OHCI_CTRL_RWC;
648 ohci->hc_control |= OHCI_USB_RESET;
649 val = 50 /* msec wait */;
652 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
654 (void) ohci_readl (ohci, &ohci->regs->control);
657 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
659 /* 2msec timelimit here means no irqs/preempt */
660 spin_lock_irq (&ohci->lock);
663 /* HC Reset requires max 10 us delay */
664 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
665 val = 30; /* ... allow extra time */
666 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
668 spin_unlock_irq (&ohci->lock);
669 ohci_err (ohci, "USB HC reset timed out!\n");
675 /* now we're in the SUSPEND state ... must go OPERATIONAL
676 * within 2msec else HC enters RESUME
678 * ... but some hardware won't init fmInterval "by the book"
679 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
680 * this if we write fmInterval after we're OPERATIONAL.
681 * Unclear about ALi, ServerWorks, and others ... this could
682 * easily be a longstanding bug in chip init on Linux.
684 if (ohci->flags & OHCI_QUIRK_INITRESET) {
685 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
686 // flush those writes
687 (void) ohci_readl (ohci, &ohci->regs->control);
690 /* Tell the controller where the control and bulk lists are
691 * The lists are empty now. */
692 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
693 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
695 /* a reset clears this */
696 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
698 periodic_reinit (ohci);
700 /* some OHCI implementations are finicky about how they init.
701 * bogus values here mean not even enumeration could work.
703 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
704 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
705 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
706 ohci->flags |= OHCI_QUIRK_INITRESET;
707 ohci_dbg (ohci, "enabling initreset quirk\n");
710 spin_unlock_irq (&ohci->lock);
711 ohci_err (ohci, "init err (%08x %04x)\n",
712 ohci_readl (ohci, &ohci->regs->fminterval),
713 ohci_readl (ohci, &ohci->regs->periodicstart));
717 /* use rhsc irqs after khubd is fully initialized */
718 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
719 hcd->uses_new_polling = 1;
721 /* start controller operations */
722 ohci->hc_control &= OHCI_CTRL_RWC;
723 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
724 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
725 ohci->rh_state = OHCI_RH_RUNNING;
727 /* wake on ConnectStatusChange, matching external hubs */
728 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
730 /* Choose the interrupts we care about now, others later on demand */
731 mask = OHCI_INTR_INIT;
732 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
733 ohci_writel (ohci, mask, &ohci->regs->intrenable);
735 /* handle root hub init quirks ... */
736 val = roothub_a (ohci);
737 val &= ~(RH_A_PSM | RH_A_OCPM);
738 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
739 /* NSC 87560 and maybe others */
741 val &= ~(RH_A_POTPGT | RH_A_NPS);
742 ohci_writel (ohci, val, &ohci->regs->roothub.a);
743 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
744 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
745 /* hub power always on; required for AMD-756 and some
746 * Mac platforms. ganged overcurrent reporting, if any.
749 ohci_writel (ohci, val, &ohci->regs->roothub.a);
751 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
752 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
753 &ohci->regs->roothub.b);
754 // flush those writes
755 (void) ohci_readl (ohci, &ohci->regs->control);
757 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
758 spin_unlock_irq (&ohci->lock);
760 // POTPGT delay is bits 24-31, in 2 ms units.
761 mdelay ((val >> 23) & 0x1fe);
763 if (quirk_zfmicro(ohci)) {
764 /* Create timer to watch for bad queue state on ZF Micro */
765 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
766 (unsigned long) ohci);
768 ohci->eds_scheduled = 0;
769 ohci->ed_to_check = NULL;
777 /*-------------------------------------------------------------------------*/
779 /* an interrupt happens */
781 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
783 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
784 struct ohci_regs __iomem *regs = ohci->regs;
787 /* Read interrupt status (and flush pending writes). We ignore the
788 * optimization of checking the LSB of hcca->done_head; it doesn't
789 * work on all systems (edge triggering for OHCI can be a factor).
791 ints = ohci_readl(ohci, ®s->intrstatus);
793 /* Check for an all 1's result which is a typical consequence
794 * of dead, unclocked, or unplugged (CardBus...) devices
796 if (ints == ~(u32)0) {
797 ohci->rh_state = OHCI_RH_HALTED;
798 ohci_dbg (ohci, "device removed!\n");
803 /* We only care about interrupts that are enabled */
804 ints &= ohci_readl(ohci, ®s->intrenable);
806 /* interrupt for some other device? */
807 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
810 if (ints & OHCI_INTR_UE) {
811 // e.g. due to PCI Master/Target Abort
812 if (quirk_nec(ohci)) {
813 /* Workaround for a silicon bug in some NEC chips used
814 * in Apple's PowerBooks. Adapted from Darwin code.
816 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
818 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
820 schedule_work (&ohci->nec_work);
822 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
823 ohci->rh_state = OHCI_RH_HALTED;
828 ohci_usb_reset (ohci);
831 if (ints & OHCI_INTR_RHSC) {
832 ohci_vdbg(ohci, "rhsc\n");
833 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
834 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
837 /* NOTE: Vendors didn't always make the same implementation
838 * choices for RHSC. Many followed the spec; RHSC triggers
839 * on an edge, like setting and maybe clearing a port status
840 * change bit. With others it's level-triggered, active
841 * until khubd clears all the port status change bits. We'll
842 * always disable it here and rely on polling until khubd
845 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
846 usb_hcd_poll_rh_status(hcd);
849 /* For connect and disconnect events, we expect the controller
850 * to turn on RHSC along with RD. But for remote wakeup events
851 * this might not happen.
853 else if (ints & OHCI_INTR_RD) {
854 ohci_vdbg(ohci, "resume detect\n");
855 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
856 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
857 if (ohci->autostop) {
858 spin_lock (&ohci->lock);
859 ohci_rh_resume (ohci);
860 spin_unlock (&ohci->lock);
862 usb_hcd_resume_root_hub(hcd);
865 if (ints & OHCI_INTR_WDH) {
866 spin_lock (&ohci->lock);
868 spin_unlock (&ohci->lock);
871 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
872 spin_lock(&ohci->lock);
873 if (ohci->ed_to_check) {
874 struct ed *ed = ohci->ed_to_check;
876 if (check_ed(ohci, ed)) {
877 /* HC thinks the TD list is empty; HCD knows
878 * at least one TD is outstanding
880 if (--ohci->zf_delay == 0) {
881 struct td *td = list_entry(
885 "Reclaiming orphan TD %p\n",
887 takeback_td(ohci, td);
888 ohci->ed_to_check = NULL;
891 ohci->ed_to_check = NULL;
893 spin_unlock(&ohci->lock);
896 /* could track INTR_SO to reduce available PCI/... bandwidth */
898 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
899 * when there's still unlinking to be done (next frame).
901 spin_lock (&ohci->lock);
902 if (ohci->ed_rm_list)
903 finish_unlinks (ohci, ohci_frame_no(ohci));
904 if ((ints & OHCI_INTR_SF) != 0
906 && !ohci->ed_to_check
907 && ohci->rh_state == OHCI_RH_RUNNING)
908 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
909 spin_unlock (&ohci->lock);
911 if (ohci->rh_state == OHCI_RH_RUNNING) {
912 ohci_writel (ohci, ints, ®s->intrstatus);
913 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
914 // flush those writes
915 (void) ohci_readl (ohci, &ohci->regs->control);
921 /*-------------------------------------------------------------------------*/
923 static void ohci_stop (struct usb_hcd *hcd)
925 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
930 flush_work(&ohci->nec_work);
932 ohci_usb_reset (ohci);
933 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
934 free_irq(hcd->irq, hcd);
937 if (quirk_zfmicro(ohci))
938 del_timer(&ohci->unlink_watchdog);
939 if (quirk_amdiso(ohci))
942 remove_debug_files (ohci);
943 ohci_mem_cleanup (ohci);
945 dma_free_coherent (hcd->self.controller,
947 ohci->hcca, ohci->hcca_dma);
953 /*-------------------------------------------------------------------------*/
955 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
957 /* must not be called from interrupt context */
958 static int ohci_restart (struct ohci_hcd *ohci)
962 struct urb_priv *priv;
964 spin_lock_irq(&ohci->lock);
965 ohci->rh_state = OHCI_RH_HALTED;
967 /* Recycle any "live" eds/tds (and urbs). */
968 if (!list_empty (&ohci->pending))
969 ohci_dbg(ohci, "abort schedule...\n");
970 list_for_each_entry (priv, &ohci->pending, pending) {
971 struct urb *urb = priv->td[0]->urb;
972 struct ed *ed = priv->ed;
976 ed->state = ED_UNLINK;
977 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
978 ed_deschedule (ohci, ed);
980 ed->ed_next = ohci->ed_rm_list;
982 ohci->ed_rm_list = ed;
987 ohci_dbg(ohci, "bogus ed %p state %d\n",
992 urb->unlinked = -ESHUTDOWN;
994 finish_unlinks (ohci, 0);
995 spin_unlock_irq(&ohci->lock);
997 /* paranoia, in case that didn't work: */
999 /* empty the interrupt branches */
1000 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1001 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1003 /* no EDs to remove */
1004 ohci->ed_rm_list = NULL;
1006 /* empty control and bulk lists */
1007 ohci->ed_controltail = NULL;
1008 ohci->ed_bulktail = NULL;
1010 if ((temp = ohci_run (ohci)) < 0) {
1011 ohci_err (ohci, "can't restart, %d\n", temp);
1014 ohci_dbg(ohci, "restart complete\n");
1022 static int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1024 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1025 unsigned long flags;
1027 /* Disable irq emission and mark HW unaccessible. Use
1028 * the spinlock to properly synchronize with possible pending
1029 * RH suspend or resume activity.
1031 spin_lock_irqsave (&ohci->lock, flags);
1032 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1033 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1035 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1036 spin_unlock_irqrestore (&ohci->lock, flags);
1042 static int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
1044 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1046 bool need_reinit = false;
1048 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1050 /* Make sure resume from hibernation re-enumerates everything */
1052 ohci_usb_reset(ohci);
1054 /* See if the controller is already running or has been reset */
1055 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1056 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1059 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1061 case OHCI_USB_RESET:
1066 /* If needed, reinitialize and suspend the root hub */
1068 spin_lock_irq(&ohci->lock);
1069 ohci_rh_resume(ohci);
1070 ohci_rh_suspend(ohci, 0);
1071 spin_unlock_irq(&ohci->lock);
1074 /* Normally just turn on port power and enable interrupts */
1076 ohci_dbg(ohci, "powerup ports\n");
1077 for (port = 0; port < ohci->num_ports; port++)
1078 ohci_writel(ohci, RH_PS_PPS,
1079 &ohci->regs->roothub.portstatus[port]);
1081 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1082 ohci_readl(ohci, &ohci->regs->intrenable);
1086 usb_hcd_resume_root_hub(hcd);
1093 /*-------------------------------------------------------------------------*/
1095 MODULE_AUTHOR (DRIVER_AUTHOR);
1096 MODULE_DESCRIPTION(DRIVER_DESC);
1097 MODULE_LICENSE ("GPL");
1100 #include "ohci-pci.c"
1101 #define PCI_DRIVER ohci_pci_driver
1104 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1105 #include "ohci-sa1111.c"
1106 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1109 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1110 #include "ohci-s3c2410.c"
1111 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1114 #ifdef CONFIG_USB_OHCI_EXYNOS
1115 #include "ohci-exynos.c"
1116 #define EXYNOS_PLATFORM_DRIVER exynos_ohci_driver
1119 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1120 #include "ohci-omap.c"
1121 #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver
1124 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1125 #include "ohci-omap3.c"
1126 #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver
1129 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1130 #include "ohci-pxa27x.c"
1131 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
1134 #ifdef CONFIG_ARCH_EP93XX
1135 #include "ohci-ep93xx.c"
1136 #define EP93XX_PLATFORM_DRIVER ohci_hcd_ep93xx_driver
1139 #ifdef CONFIG_ARCH_AT91
1140 #include "ohci-at91.c"
1141 #define AT91_PLATFORM_DRIVER ohci_hcd_at91_driver
1144 #ifdef CONFIG_ARCH_LPC32XX
1145 #include "ohci-nxp.c"
1146 #define NXP_PLATFORM_DRIVER usb_hcd_nxp_driver
1149 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1150 #include "ohci-da8xx.c"
1151 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1154 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1155 #include "ohci-ppc-of.c"
1156 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1159 #ifdef CONFIG_PLAT_SPEAR
1160 #include "ohci-spear.c"
1161 #define SPEAR_PLATFORM_DRIVER spear_ohci_hcd_driver
1164 #ifdef CONFIG_PPC_PS3
1165 #include "ohci-ps3.c"
1166 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1169 #ifdef CONFIG_MFD_SM501
1170 #include "ohci-sm501.c"
1171 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1174 #ifdef CONFIG_MFD_TC6393XB
1175 #include "ohci-tmio.c"
1176 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1179 #ifdef CONFIG_MACH_JZ4740
1180 #include "ohci-jz4740.c"
1181 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1184 #ifdef CONFIG_USB_OCTEON_OHCI
1185 #include "ohci-octeon.c"
1186 #define PLATFORM_DRIVER ohci_octeon_driver
1189 #ifdef CONFIG_TILE_USB
1190 #include "ohci-tilegx.c"
1191 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1194 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
1195 #include "ohci-platform.c"
1196 #define PLATFORM_DRIVER ohci_platform_driver
1199 #if !defined(PCI_DRIVER) && \
1200 !defined(PLATFORM_DRIVER) && \
1201 !defined(OMAP1_PLATFORM_DRIVER) && \
1202 !defined(OMAP3_PLATFORM_DRIVER) && \
1203 !defined(OF_PLATFORM_DRIVER) && \
1204 !defined(SA1111_DRIVER) && \
1205 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1206 !defined(SM501_OHCI_DRIVER) && \
1207 !defined(TMIO_OHCI_DRIVER) && \
1208 !defined(S3C2410_PLATFORM_DRIVER) && \
1209 !defined(EXYNOS_PLATFORM_DRIVER) && \
1210 !defined(EP93XX_PLATFORM_DRIVER) && \
1211 !defined(AT91_PLATFORM_DRIVER) && \
1212 !defined(NXP_PLATFORM_DRIVER) && \
1213 !defined(DAVINCI_PLATFORM_DRIVER) && \
1214 !defined(SPEAR_PLATFORM_DRIVER)
1215 #error "missing bus glue for ohci-hcd"
1218 static int __init ohci_hcd_mod_init(void)
1225 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1226 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1227 sizeof (struct ed), sizeof (struct td));
1228 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1231 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1232 if (!ohci_debug_root) {
1238 #ifdef PS3_SYSTEM_BUS_DRIVER
1239 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1244 #ifdef PLATFORM_DRIVER
1245 retval = platform_driver_register(&PLATFORM_DRIVER);
1247 goto error_platform;
1250 #ifdef OMAP1_PLATFORM_DRIVER
1251 retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1253 goto error_omap1_platform;
1256 #ifdef OMAP3_PLATFORM_DRIVER
1257 retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1259 goto error_omap3_platform;
1262 #ifdef OF_PLATFORM_DRIVER
1263 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1265 goto error_of_platform;
1268 #ifdef SA1111_DRIVER
1269 retval = sa1111_driver_register(&SA1111_DRIVER);
1275 retval = pci_register_driver(&PCI_DRIVER);
1280 #ifdef SM501_OHCI_DRIVER
1281 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1286 #ifdef TMIO_OHCI_DRIVER
1287 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1292 #ifdef S3C2410_PLATFORM_DRIVER
1293 retval = platform_driver_register(&S3C2410_PLATFORM_DRIVER);
1298 #ifdef EXYNOS_PLATFORM_DRIVER
1299 retval = platform_driver_register(&EXYNOS_PLATFORM_DRIVER);
1304 #ifdef EP93XX_PLATFORM_DRIVER
1305 retval = platform_driver_register(&EP93XX_PLATFORM_DRIVER);
1310 #ifdef AT91_PLATFORM_DRIVER
1311 retval = platform_driver_register(&AT91_PLATFORM_DRIVER);
1316 #ifdef NXP_PLATFORM_DRIVER
1317 retval = platform_driver_register(&NXP_PLATFORM_DRIVER);
1322 #ifdef DAVINCI_PLATFORM_DRIVER
1323 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1328 #ifdef SPEAR_PLATFORM_DRIVER
1329 retval = platform_driver_register(&SPEAR_PLATFORM_DRIVER);
1337 #ifdef SPEAR_PLATFORM_DRIVER
1338 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1341 #ifdef DAVINCI_PLATFORM_DRIVER
1342 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1345 #ifdef NXP_PLATFORM_DRIVER
1346 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1349 #ifdef AT91_PLATFORM_DRIVER
1350 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1353 #ifdef EP93XX_PLATFORM_DRIVER
1354 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1357 #ifdef EXYNOS_PLATFORM_DRIVER
1358 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1361 #ifdef S3C2410_PLATFORM_DRIVER
1362 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1365 #ifdef TMIO_OHCI_DRIVER
1366 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1369 #ifdef SM501_OHCI_DRIVER
1370 platform_driver_unregister(&SM501_OHCI_DRIVER);
1374 pci_unregister_driver(&PCI_DRIVER);
1377 #ifdef SA1111_DRIVER
1378 sa1111_driver_unregister(&SA1111_DRIVER);
1381 #ifdef OF_PLATFORM_DRIVER
1382 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1385 #ifdef OMAP3_PLATFORM_DRIVER
1386 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1387 error_omap3_platform:
1389 #ifdef OMAP1_PLATFORM_DRIVER
1390 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1391 error_omap1_platform:
1393 #ifdef PLATFORM_DRIVER
1394 platform_driver_unregister(&PLATFORM_DRIVER);
1397 #ifdef PS3_SYSTEM_BUS_DRIVER
1398 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1402 debugfs_remove(ohci_debug_root);
1403 ohci_debug_root = NULL;
1407 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1410 module_init(ohci_hcd_mod_init);
1412 static void __exit ohci_hcd_mod_exit(void)
1414 #ifdef SPEAR_PLATFORM_DRIVER
1415 platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1417 #ifdef DAVINCI_PLATFORM_DRIVER
1418 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1420 #ifdef NXP_PLATFORM_DRIVER
1421 platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1423 #ifdef AT91_PLATFORM_DRIVER
1424 platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1426 #ifdef EP93XX_PLATFORM_DRIVER
1427 platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1429 #ifdef EXYNOS_PLATFORM_DRIVER
1430 platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1432 #ifdef S3C2410_PLATFORM_DRIVER
1433 platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1435 #ifdef TMIO_OHCI_DRIVER
1436 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1438 #ifdef SM501_OHCI_DRIVER
1439 platform_driver_unregister(&SM501_OHCI_DRIVER);
1442 pci_unregister_driver(&PCI_DRIVER);
1444 #ifdef SA1111_DRIVER
1445 sa1111_driver_unregister(&SA1111_DRIVER);
1447 #ifdef OF_PLATFORM_DRIVER
1448 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1450 #ifdef OMAP3_PLATFORM_DRIVER
1451 platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1453 #ifdef OMAP1_PLATFORM_DRIVER
1454 platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1456 #ifdef PLATFORM_DRIVER
1457 platform_driver_unregister(&PLATFORM_DRIVER);
1459 #ifdef PS3_SYSTEM_BUS_DRIVER
1460 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1463 debugfs_remove(ohci_debug_root);
1465 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1467 module_exit(ohci_hcd_mod_exit);