2 * Driver for the NXP ISP1760 chip
4 * Copyright 2014 Laurent Pinchart
5 * Copyright 2007 Sebastian Siewior
8 * Sebastian Siewior <bigeasy@linutronix.de>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
16 #ifndef _ISP1760_REGS_H_
17 #define _ISP1760_REGS_H_
19 /* EHCI capability registers */
20 #define HC_CAPLENGTH 0x000
21 #define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
22 #define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
24 #define HC_HCSPARAMS 0x004
25 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
26 #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
27 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
29 #define HC_HCCPARAMS 0x008
30 #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
31 #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
33 /* EHCI operational registers */
34 #define HC_USBCMD 0x020
35 #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
36 #define CMD_RESET (1 << 1) /* reset HC not bus */
37 #define CMD_RUN (1 << 0) /* start/stop HC */
39 #define HC_USBSTS 0x024
40 #define STS_PCD (1 << 2) /* port change detect */
42 #define HC_FRINDEX 0x02c
44 #define HC_CONFIGFLAG 0x060
45 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
47 #define HC_PORTSC1 0x064
48 #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
49 #define PORT_POWER (1 << 12) /* true: has power (see PPC) */
50 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
51 #define PORT_RESET (1 << 8) /* reset port */
52 #define PORT_SUSPEND (1 << 7) /* suspend port */
53 #define PORT_RESUME (1 << 6) /* resume it */
54 #define PORT_PE (1 << 2) /* port enable */
55 #define PORT_CSC (1 << 1) /* connect status change */
56 #define PORT_CONNECT (1 << 0) /* device connected */
57 #define PORT_RWC_BITS (PORT_CSC)
59 #define HC_ISO_PTD_DONEMAP_REG 0x130
60 #define HC_ISO_PTD_SKIPMAP_REG 0x134
61 #define HC_ISO_PTD_LASTPTD_REG 0x138
62 #define HC_INT_PTD_DONEMAP_REG 0x140
63 #define HC_INT_PTD_SKIPMAP_REG 0x144
64 #define HC_INT_PTD_LASTPTD_REG 0x148
65 #define HC_ATL_PTD_DONEMAP_REG 0x150
66 #define HC_ATL_PTD_SKIPMAP_REG 0x154
67 #define HC_ATL_PTD_LASTPTD_REG 0x158
69 /* Configuration Register */
70 #define HC_HW_MODE_CTRL 0x300
71 #define ALL_ATX_RESET (1 << 31)
72 #define HW_ANA_DIGI_OC (1 << 15)
73 #define HW_DATA_BUS_32BIT (1 << 8)
74 #define HW_DACK_POL_HIGH (1 << 6)
75 #define HW_DREQ_POL_HIGH (1 << 5)
76 #define HW_INTR_HIGH_ACT (1 << 2)
77 #define HW_INTR_EDGE_TRIG (1 << 1)
78 #define HW_GLOBAL_INTR_EN (1 << 0)
80 #define HC_CHIP_ID_REG 0x304
81 #define HC_SCRATCH_REG 0x308
83 #define HC_RESET_REG 0x30c
84 #define SW_RESET_RESET_HC (1 << 1)
85 #define SW_RESET_RESET_ALL (1 << 0)
87 #define HC_BUFFER_STATUS_REG 0x334
88 #define ISO_BUF_FILL (1 << 2)
89 #define INT_BUF_FILL (1 << 1)
90 #define ATL_BUF_FILL (1 << 0)
92 #define HC_MEMORY_REG 0x33c
93 #define ISP_BANK(x) ((x) << 16)
95 #define HC_PORT1_CTRL 0x374
96 #define PORT1_POWER (3 << 3)
97 #define PORT1_INIT1 (1 << 7)
98 #define PORT1_INIT2 (1 << 23)
99 #define HW_OTG_CTRL_SET 0x374
100 #define HW_OTG_CTRL_CLR 0x376
102 /* Interrupt Register */
103 #define HC_INTERRUPT_REG 0x310
105 #define HC_INTERRUPT_ENABLE 0x314
106 #define HC_ISO_INT (1 << 9)
107 #define HC_ATL_INT (1 << 8)
108 #define HC_INTL_INT (1 << 7)
109 #define HC_EOT_INT (1 << 3)
110 #define HC_SOT_INT (1 << 1)
111 #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
113 #define HC_ISO_IRQ_MASK_OR_REG 0x318
114 #define HC_INT_IRQ_MASK_OR_REG 0x31c
115 #define HC_ATL_IRQ_MASK_OR_REG 0x320
116 #define HC_ISO_IRQ_MASK_AND_REG 0x324
117 #define HC_INT_IRQ_MASK_AND_REG 0x328
118 #define HC_ATL_IRQ_MASK_AND_REG 0x32c