2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
14 #include <linux/gpio/consumer.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/usb.h>
20 #include <linux/usb/hcd.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
25 #include <linux/timer.h>
26 #include <asm/unaligned.h>
27 #include <asm/cacheflush.h>
29 #include "isp1760-hcd.h"
31 static struct kmem_cache *qtd_cachep;
32 static struct kmem_cache *qh_cachep;
33 static struct kmem_cache *urb_listitem_cachep;
35 enum queue_head_types {
45 struct slotinfo atl_slots[32];
47 struct slotinfo int_slots[32];
49 struct memory_chunk memory_pool[BLOCKS];
50 struct list_head qh_list[QH_END];
52 /* periodic schedule support */
53 #define DEFAULT_I_TDPS 1024
54 unsigned periodic_size;
56 unsigned long reset_done;
57 unsigned long next_statechange;
58 unsigned int devflags;
60 struct gpio_desc *rst_gpio;
63 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
65 return (struct isp1760_hcd *) (hcd->hcd_priv);
68 /* Section 2.2 Host Controller Capability Registers */
69 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
70 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
71 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
72 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
73 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
74 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
75 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
77 /* Section 2.3 Host Controller Operational Registers */
78 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
79 #define CMD_RESET (1<<1) /* reset HC not bus */
80 #define CMD_RUN (1<<0) /* start/stop HC */
81 #define STS_PCD (1<<2) /* port change detect */
82 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
84 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
85 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
86 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
87 #define PORT_RESET (1<<8) /* reset port */
88 #define PORT_SUSPEND (1<<7) /* suspend port */
89 #define PORT_RESUME (1<<6) /* resume it */
90 #define PORT_PE (1<<2) /* port enable */
91 #define PORT_CSC (1<<1) /* connect status change */
92 #define PORT_CONNECT (1<<0) /* device connected */
93 #define PORT_RWC_BITS (PORT_CSC)
100 /* the rest is HCD-private */
101 struct list_head qtd_list;
104 size_t actual_length;
106 /* QTD_ENQUEUED: waiting for transfer (inactive) */
107 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
108 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
109 interrupt handler may touch this qtd! */
110 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
111 /* QTD_RETIRE: transfer error/abort qtd */
112 #define QTD_ENQUEUED 0
113 #define QTD_PAYLOAD_ALLOC 1
114 #define QTD_XFER_STARTED 2
115 #define QTD_XFER_COMPLETE 3
120 /* Queue head, one for each active endpoint */
122 struct list_head qh_list;
123 struct list_head qtd_list;
127 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
130 struct urb_listitem {
131 struct list_head urb_list;
136 * Access functions for isp176x registers (addresses 0..0x03FF).
138 static u32 reg_read32(void __iomem *base, u32 reg)
140 return readl(base + reg);
143 static void reg_write32(void __iomem *base, u32 reg, u32 val)
145 writel(val, base + reg);
149 * Access functions for isp176x memory (offset >= 0x0400).
151 * bank_reads8() reads memory locations prefetched by an earlier write to
152 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
153 * bank optimizations, you should use the more generic mem_reads8() below.
155 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
158 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
159 * doesn't quite work because some people have to enforce 32-bit access
161 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
162 __u32 *dst, u32 bytes)
169 src = src_base + (bank_addr | src_offset);
171 if (src_offset < PAYLOAD_OFFSET) {
173 *dst = le32_to_cpu(__raw_readl(src));
180 *dst = __raw_readl(src);
190 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
193 if (src_offset < PAYLOAD_OFFSET)
194 val = le32_to_cpu(__raw_readl(src));
196 val = __raw_readl(src);
198 dst_byteptr = (void *) dst;
199 src_byteptr = (void *) &val;
201 *dst_byteptr = *src_byteptr;
208 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
211 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
213 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
216 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
217 __u32 const *src, u32 bytes)
221 dst = dst_base + dst_offset;
223 if (dst_offset < PAYLOAD_OFFSET) {
225 __raw_writel(cpu_to_le32(*src), dst);
232 __raw_writel(*src, dst);
241 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
242 * extra bytes should not be read by the HW.
245 if (dst_offset < PAYLOAD_OFFSET)
246 __raw_writel(cpu_to_le32(*src), dst);
248 __raw_writel(*src, dst);
252 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
253 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
255 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
258 reg_write32(base, HC_MEMORY_REG,
259 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
261 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
262 (void *) ptd, sizeof(*ptd));
265 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
268 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
269 &ptd->dw1, 7*sizeof(ptd->dw1));
270 /* Make sure dw0 gets written last (after other dw's and after payload)
271 since it contains the enable bit */
273 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
278 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
279 static void init_memory(struct isp1760_hcd *priv)
284 payload_addr = PAYLOAD_OFFSET;
285 for (i = 0; i < BLOCK_1_NUM; i++) {
286 priv->memory_pool[i].start = payload_addr;
287 priv->memory_pool[i].size = BLOCK_1_SIZE;
288 priv->memory_pool[i].free = 1;
289 payload_addr += priv->memory_pool[i].size;
293 for (i = 0; i < BLOCK_2_NUM; i++) {
294 priv->memory_pool[curr + i].start = payload_addr;
295 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
296 priv->memory_pool[curr + i].free = 1;
297 payload_addr += priv->memory_pool[curr + i].size;
301 for (i = 0; i < BLOCK_3_NUM; i++) {
302 priv->memory_pool[curr + i].start = payload_addr;
303 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
304 priv->memory_pool[curr + i].free = 1;
305 payload_addr += priv->memory_pool[curr + i].size;
308 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
311 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
313 struct isp1760_hcd *priv = hcd_to_priv(hcd);
316 WARN_ON(qtd->payload_addr);
321 for (i = 0; i < BLOCKS; i++) {
322 if (priv->memory_pool[i].size >= qtd->length &&
323 priv->memory_pool[i].free) {
324 priv->memory_pool[i].free = 0;
325 qtd->payload_addr = priv->memory_pool[i].start;
331 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
333 struct isp1760_hcd *priv = hcd_to_priv(hcd);
336 if (!qtd->payload_addr)
339 for (i = 0; i < BLOCKS; i++) {
340 if (priv->memory_pool[i].start == qtd->payload_addr) {
341 WARN_ON(priv->memory_pool[i].free);
342 priv->memory_pool[i].free = 1;
343 qtd->payload_addr = 0;
348 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
349 __func__, qtd->payload_addr);
351 qtd->payload_addr = 0;
354 static int handshake(struct usb_hcd *hcd, u32 reg,
355 u32 mask, u32 done, int usec)
360 result = reg_read32(hcd->regs, reg);
372 /* reset a non-running (STS_HALT == 1) controller */
373 static int ehci_reset(struct usb_hcd *hcd)
376 struct isp1760_hcd *priv = hcd_to_priv(hcd);
378 u32 command = reg_read32(hcd->regs, HC_USBCMD);
380 command |= CMD_RESET;
381 reg_write32(hcd->regs, HC_USBCMD, command);
382 hcd->state = HC_STATE_HALT;
383 priv->next_statechange = jiffies;
384 retval = handshake(hcd, HC_USBCMD,
385 CMD_RESET, 0, 250 * 1000);
389 static struct isp1760_qh *qh_alloc(gfp_t flags)
391 struct isp1760_qh *qh;
393 qh = kmem_cache_zalloc(qh_cachep, flags);
397 INIT_LIST_HEAD(&qh->qh_list);
398 INIT_LIST_HEAD(&qh->qtd_list);
404 static void qh_free(struct isp1760_qh *qh)
406 WARN_ON(!list_empty(&qh->qtd_list));
407 WARN_ON(qh->slot > -1);
408 kmem_cache_free(qh_cachep, qh);
411 /* one-time init, only for memory state */
412 static int priv_init(struct usb_hcd *hcd)
414 struct isp1760_hcd *priv = hcd_to_priv(hcd);
418 spin_lock_init(&priv->lock);
420 for (i = 0; i < QH_END; i++)
421 INIT_LIST_HEAD(&priv->qh_list[i]);
424 * hw default: 1K periodic list heads, one per frame.
425 * periodic_size can shrink by USBCMD update if hcc_params allows.
427 priv->periodic_size = DEFAULT_I_TDPS;
429 /* controllers may cache some of the periodic schedule ... */
430 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
431 /* full frame cache */
432 if (HCC_ISOC_CACHE(hcc_params))
434 else /* N microframes cached */
435 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
440 static int isp1760_hc_setup(struct usb_hcd *hcd)
442 struct isp1760_hcd *priv = hcd_to_priv(hcd);
446 /* low-level chip reset */
447 if (priv->rst_gpio) {
448 gpiod_set_value_cansleep(priv->rst_gpio, 1);
450 gpiod_set_value_cansleep(priv->rst_gpio, 0);
453 /* Setup HW Mode Control: This assumes a level active-low interrupt */
454 hwmode = HW_DATA_BUS_32BIT;
456 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
457 hwmode &= ~HW_DATA_BUS_32BIT;
458 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
459 hwmode |= HW_ANA_DIGI_OC;
460 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
461 hwmode |= HW_DACK_POL_HIGH;
462 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
463 hwmode |= HW_DREQ_POL_HIGH;
464 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
465 hwmode |= HW_INTR_HIGH_ACT;
466 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
467 hwmode |= HW_INTR_EDGE_TRIG;
470 * We have to set this first in case we're in 16-bit mode.
471 * Write it twice to ensure correct upper bits if switching
474 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
475 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
477 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
478 /* Change bus pattern */
479 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
480 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
481 if (scratch != 0xdeadbabe) {
482 dev_err(hcd->self.controller, "Scratch test failed.\n");
487 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
488 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
489 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
490 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
493 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
496 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
499 result = ehci_reset(hcd);
505 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
506 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
507 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
508 "analog" : "digital");
511 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
513 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
515 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
518 * PORT 1 Control register of the ISP1760 is the OTG control
519 * register on ISP1761. Since there is no OTG or device controller
520 * support in this driver, we use port 1 as a "normal" USB host port on
523 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
526 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
528 return priv_init(hcd);
531 static u32 base_to_chip(u32 base)
533 return ((base - 0x400) >> 3);
536 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
540 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
544 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
545 return (qtd->urb != urb);
548 /* magic numbers that can affect system performance */
549 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
550 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
551 #define EHCI_TUNE_RL_TT 0
552 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
553 #define EHCI_TUNE_MULT_TT 1
554 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
556 static void create_ptd_atl(struct isp1760_qh *qh,
557 struct isp1760_qtd *qtd, struct ptd *ptd)
562 u32 nak = NAK_COUNTER;
564 memset(ptd, 0, sizeof(*ptd));
566 /* according to 3.6.2, max packet len can not be > 0x400 */
567 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
568 usb_pipeout(qtd->urb->pipe));
569 multi = 1 + ((maxpacket >> 11) & 0x3);
573 ptd->dw0 = DW0_VALID_BIT;
574 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
575 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
576 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
579 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
580 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
581 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
583 if (usb_pipebulk(qtd->urb->pipe))
584 ptd->dw1 |= DW1_TRANS_BULK;
585 else if (usb_pipeint(qtd->urb->pipe))
586 ptd->dw1 |= DW1_TRANS_INT;
588 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
589 /* split transaction */
591 ptd->dw1 |= DW1_TRANS_SPLIT;
592 if (qtd->urb->dev->speed == USB_SPEED_LOW)
593 ptd->dw1 |= DW1_SE_USB_LOSPEED;
595 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
596 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
598 /* SE bit for Split INT transfers */
599 if (usb_pipeint(qtd->urb->pipe) &&
600 (qtd->urb->dev->speed == USB_SPEED_LOW))
606 ptd->dw0 |= TO_DW0_MULTI(multi);
607 if (usb_pipecontrol(qtd->urb->pipe) ||
608 usb_pipebulk(qtd->urb->pipe))
609 ptd->dw3 |= TO_DW3_PING(qh->ping);
613 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
614 ptd->dw2 |= TO_DW2_RL(rl);
617 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
618 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
619 if (usb_pipecontrol(qtd->urb->pipe)) {
620 if (qtd->data_buffer == qtd->urb->setup_packet)
621 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
622 else if (last_qtd_of_urb(qtd, qh))
623 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
626 ptd->dw3 |= DW3_ACTIVE_BIT;
628 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
631 static void transform_add_int(struct isp1760_qh *qh,
632 struct isp1760_qtd *qtd, struct ptd *ptd)
638 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
639 * the algorithm from the original Philips driver code, which was
640 * pretty much used in this driver before as well, is quite horrendous
641 * and, i believe, incorrect. The code below follows the datasheet and
642 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
643 * more reliable this way (fingers crossed...).
646 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
647 /* urb->interval is in units of microframes (1/8 ms) */
648 period = qtd->urb->interval >> 3;
650 if (qtd->urb->interval > 4)
651 usof = 0x01; /* One bit set =>
652 interval 1 ms * uFrame-match */
653 else if (qtd->urb->interval > 2)
654 usof = 0x22; /* Two bits set => interval 1/2 ms */
655 else if (qtd->urb->interval > 1)
656 usof = 0x55; /* Four bits set => interval 1/4 ms */
658 usof = 0xff; /* All bits set => interval 1/8 ms */
660 /* urb->interval is in units of frames (1 ms) */
661 period = qtd->urb->interval;
662 usof = 0x0f; /* Execute Start Split on any of the
663 four first uFrames */
666 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
667 * complete split needs to be sent. Valid only for IN." Also,
668 * "All bits can be set to one for every transfer." (p 82,
669 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
670 * that number come from? 0xff seems to work fine...
672 /* ptd->dw5 = 0x1c; */
673 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
676 period = period >> 1;/* Ensure equal or shorter period than requested */
677 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
683 static void create_ptd_int(struct isp1760_qh *qh,
684 struct isp1760_qtd *qtd, struct ptd *ptd)
686 create_ptd_atl(qh, qtd, ptd);
687 transform_add_int(qh, qtd, ptd);
690 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
691 __releases(priv->lock)
692 __acquires(priv->lock)
694 struct isp1760_hcd *priv = hcd_to_priv(hcd);
696 if (!urb->unlinked) {
697 if (urb->status == -EINPROGRESS)
701 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
703 for (ptr = urb->transfer_buffer;
704 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
706 flush_dcache_page(virt_to_page(ptr));
709 /* complete() can reenter this HCD */
710 usb_hcd_unlink_urb_from_ep(hcd, urb);
711 spin_unlock(&priv->lock);
712 usb_hcd_giveback_urb(hcd, urb, urb->status);
713 spin_lock(&priv->lock);
716 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
719 struct isp1760_qtd *qtd;
721 qtd = kmem_cache_zalloc(qtd_cachep, flags);
725 INIT_LIST_HEAD(&qtd->qtd_list);
727 qtd->packet_type = packet_type;
728 qtd->status = QTD_ENQUEUED;
729 qtd->actual_length = 0;
734 static void qtd_free(struct isp1760_qtd *qtd)
736 WARN_ON(qtd->payload_addr);
737 kmem_cache_free(qtd_cachep, qtd);
740 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
741 struct slotinfo *slots, struct isp1760_qtd *qtd,
742 struct isp1760_qh *qh, struct ptd *ptd)
744 struct isp1760_hcd *priv = hcd_to_priv(hcd);
747 WARN_ON((slot < 0) || (slot > 31));
748 WARN_ON(qtd->length && !qtd->payload_addr);
749 WARN_ON(slots[slot].qtd);
750 WARN_ON(slots[slot].qh);
751 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
753 /* Make sure done map has not triggered from some unlinked transfer */
754 if (ptd_offset == ATL_PTD_OFFSET) {
755 priv->atl_done_map |= reg_read32(hcd->regs,
756 HC_ATL_PTD_DONEMAP_REG);
757 priv->atl_done_map &= ~(1 << slot);
759 priv->int_done_map |= reg_read32(hcd->regs,
760 HC_INT_PTD_DONEMAP_REG);
761 priv->int_done_map &= ~(1 << slot);
765 qtd->status = QTD_XFER_STARTED;
766 slots[slot].timestamp = jiffies;
767 slots[slot].qtd = qtd;
769 ptd_write(hcd->regs, ptd_offset, slot, ptd);
771 if (ptd_offset == ATL_PTD_OFFSET) {
772 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
773 skip_map &= ~(1 << qh->slot);
774 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
776 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
777 skip_map &= ~(1 << qh->slot);
778 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
782 static int is_short_bulk(struct isp1760_qtd *qtd)
784 return (usb_pipebulk(qtd->urb->pipe) &&
785 (qtd->actual_length < qtd->length));
788 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
789 struct list_head *urb_list)
792 struct isp1760_qtd *qtd, *qtd_next;
793 struct urb_listitem *urb_listitem;
795 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
796 if (qtd->status < QTD_XFER_COMPLETE)
799 last_qtd = last_qtd_of_urb(qtd, qh);
801 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
802 qtd_next->status = QTD_RETIRE;
804 if (qtd->status == QTD_XFER_COMPLETE) {
805 if (qtd->actual_length) {
806 switch (qtd->packet_type) {
808 mem_reads8(hcd->regs, qtd->payload_addr,
811 /* Fall through (?) */
813 qtd->urb->actual_length +=
815 /* Fall through ... */
821 if (is_short_bulk(qtd)) {
822 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
823 qtd->urb->status = -EREMOTEIO;
825 qtd_next->status = QTD_RETIRE;
829 if (qtd->payload_addr)
833 if ((qtd->status == QTD_RETIRE) &&
834 (qtd->urb->status == -EINPROGRESS))
835 qtd->urb->status = -EPIPE;
836 /* Defer calling of urb_done() since it releases lock */
837 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
839 if (unlikely(!urb_listitem))
840 break; /* Try again on next call */
841 urb_listitem->urb = qtd->urb;
842 list_add_tail(&urb_listitem->urb_list, urb_list);
845 list_del(&qtd->qtd_list);
850 #define ENQUEUE_DEPTH 2
851 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
853 struct isp1760_hcd *priv = hcd_to_priv(hcd);
855 struct slotinfo *slots;
856 int curr_slot, free_slot;
859 struct isp1760_qtd *qtd;
861 if (unlikely(list_empty(&qh->qtd_list))) {
866 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
867 if (qh->tt_buffer_dirty)
870 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
871 qtd_list)->urb->pipe)) {
872 ptd_offset = INT_PTD_OFFSET;
873 slots = priv->int_slots;
875 ptd_offset = ATL_PTD_OFFSET;
876 slots = priv->atl_slots;
880 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
881 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
882 free_slot = curr_slot;
883 if (slots[curr_slot].qh == qh)
888 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
889 if (qtd->status == QTD_ENQUEUED) {
890 WARN_ON(qtd->payload_addr);
892 if ((qtd->length) && (!qtd->payload_addr))
896 ((qtd->packet_type == SETUP_PID) ||
897 (qtd->packet_type == OUT_PID))) {
898 mem_writes8(hcd->regs, qtd->payload_addr,
899 qtd->data_buffer, qtd->length);
902 qtd->status = QTD_PAYLOAD_ALLOC;
905 if (qtd->status == QTD_PAYLOAD_ALLOC) {
907 if ((curr_slot > 31) && (free_slot == -1))
908 dev_dbg(hcd->self.controller, "%s: No slot "
909 "available for transfer\n", __func__);
911 /* Start xfer for this endpoint if not already done */
912 if ((curr_slot > 31) && (free_slot > -1)) {
913 if (usb_pipeint(qtd->urb->pipe))
914 create_ptd_int(qh, qtd, &ptd);
916 create_ptd_atl(qh, qtd, &ptd);
918 start_bus_transfer(hcd, ptd_offset, free_slot,
919 slots, qtd, qh, &ptd);
920 curr_slot = free_slot;
924 if (n >= ENQUEUE_DEPTH)
930 static void schedule_ptds(struct usb_hcd *hcd)
932 struct isp1760_hcd *priv;
933 struct isp1760_qh *qh, *qh_next;
934 struct list_head *ep_queue;
936 struct urb_listitem *urb_listitem, *urb_listitem_next;
944 priv = hcd_to_priv(hcd);
947 * check finished/retired xfers, transfer payloads, call urb_done()
949 for (i = 0; i < QH_END; i++) {
950 ep_queue = &priv->qh_list[i];
951 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
952 collect_qtds(hcd, qh, &urb_list);
953 if (list_empty(&qh->qtd_list))
954 list_del(&qh->qh_list);
958 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
960 isp1760_urb_done(hcd, urb_listitem->urb);
961 kmem_cache_free(urb_listitem_cachep, urb_listitem);
965 * Schedule packets for transfer.
967 * According to USB2.0 specification:
969 * 1st prio: interrupt xfers, up to 80 % of bandwidth
970 * 2nd prio: control xfers
971 * 3rd prio: bulk xfers
973 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
974 * is very unclear on how to prioritize traffic):
976 * 1) Enqueue any queued control transfers, as long as payload chip mem
977 * and PTD ATL slots are available.
978 * 2) Enqueue any queued INT transfers, as long as payload chip mem
979 * and PTD INT slots are available.
980 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
981 * and PTD ATL slots are available.
983 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
984 * conservation of chip mem and performance.
986 * I'm sure this scheme could be improved upon!
988 for (i = 0; i < QH_END; i++) {
989 ep_queue = &priv->qh_list[i];
990 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
991 enqueue_qtds(hcd, qh);
995 #define PTD_STATE_QTD_DONE 1
996 #define PTD_STATE_QTD_RELOAD 2
997 #define PTD_STATE_URB_RETIRE 3
999 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1008 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1009 need to handle these errors? Is it done in hardware? */
1011 if (ptd->dw3 & DW3_HALT_BIT) {
1013 urb->status = -EPROTO; /* Default unknown error */
1015 for (i = 0; i < 8; i++) {
1016 switch (dw4 & 0x7) {
1018 dev_dbg(hcd->self.controller, "%s: underrun "
1019 "during uFrame %d\n",
1021 urb->status = -ECOMM; /* Could not write data */
1024 dev_dbg(hcd->self.controller, "%s: transaction "
1025 "error during uFrame %d\n",
1027 urb->status = -EPROTO; /* timeout, bad CRC, PID
1031 dev_dbg(hcd->self.controller, "%s: babble "
1032 "error during uFrame %d\n",
1034 urb->status = -EOVERFLOW;
1040 return PTD_STATE_URB_RETIRE;
1043 return PTD_STATE_QTD_DONE;
1046 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1050 if (ptd->dw3 & DW3_HALT_BIT) {
1051 if (ptd->dw3 & DW3_BABBLE_BIT)
1052 urb->status = -EOVERFLOW;
1053 else if (FROM_DW3_CERR(ptd->dw3))
1054 urb->status = -EPIPE; /* Stall */
1055 else if (ptd->dw3 & DW3_ERROR_BIT)
1056 urb->status = -EPROTO; /* XactErr */
1058 urb->status = -EPROTO; /* Unknown */
1060 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1061 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1062 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1064 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1065 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1067 return PTD_STATE_URB_RETIRE;
1070 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1071 /* Transfer Error, *but* active and no HALT -> reload */
1072 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1073 return PTD_STATE_QTD_RELOAD;
1076 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1078 * NAKs are handled in HW by the chip. Usually if the
1079 * device is not able to send data fast enough.
1080 * This happens mostly on slower hardware.
1082 return PTD_STATE_QTD_RELOAD;
1085 return PTD_STATE_QTD_DONE;
1088 static void handle_done_ptds(struct usb_hcd *hcd)
1090 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1092 struct isp1760_qh *qh;
1095 struct slotinfo *slots;
1097 struct isp1760_qtd *qtd;
1101 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1102 priv->int_done_map &= ~skip_map;
1103 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1104 priv->atl_done_map &= ~skip_map;
1106 modified = priv->int_done_map || priv->atl_done_map;
1108 while (priv->int_done_map || priv->atl_done_map) {
1109 if (priv->int_done_map) {
1111 slot = __ffs(priv->int_done_map);
1112 priv->int_done_map &= ~(1 << slot);
1113 slots = priv->int_slots;
1114 /* This should not trigger, and could be removed if
1115 noone have any problems with it triggering: */
1116 if (!slots[slot].qh) {
1120 ptd_offset = INT_PTD_OFFSET;
1121 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1122 state = check_int_transfer(hcd, &ptd,
1123 slots[slot].qtd->urb);
1126 slot = __ffs(priv->atl_done_map);
1127 priv->atl_done_map &= ~(1 << slot);
1128 slots = priv->atl_slots;
1129 /* This should not trigger, and could be removed if
1130 noone have any problems with it triggering: */
1131 if (!slots[slot].qh) {
1135 ptd_offset = ATL_PTD_OFFSET;
1136 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1137 state = check_atl_transfer(hcd, &ptd,
1138 slots[slot].qtd->urb);
1141 qtd = slots[slot].qtd;
1142 slots[slot].qtd = NULL;
1143 qh = slots[slot].qh;
1144 slots[slot].qh = NULL;
1147 WARN_ON(qtd->status != QTD_XFER_STARTED);
1150 case PTD_STATE_QTD_DONE:
1151 if ((usb_pipeint(qtd->urb->pipe)) &&
1152 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1153 qtd->actual_length =
1154 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1156 qtd->actual_length =
1157 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1159 qtd->status = QTD_XFER_COMPLETE;
1160 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1164 qtd = list_entry(qtd->qtd_list.next,
1165 typeof(*qtd), qtd_list);
1167 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1168 qh->ping = FROM_DW3_PING(ptd.dw3);
1171 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1172 qtd->status = QTD_PAYLOAD_ALLOC;
1173 ptd.dw0 |= DW0_VALID_BIT;
1174 /* RL counter = ERR counter */
1175 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1176 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1177 ptd.dw3 &= ~TO_DW3_CERR(3);
1178 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1179 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1180 qh->ping = FROM_DW3_PING(ptd.dw3);
1183 case PTD_STATE_URB_RETIRE:
1184 qtd->status = QTD_RETIRE;
1185 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1186 (qtd->urb->status != -EPIPE) &&
1187 (qtd->urb->status != -EREMOTEIO)) {
1188 qh->tt_buffer_dirty = 1;
1189 if (usb_hub_clear_tt_buffer(qtd->urb))
1190 /* Clear failed; let's hope things work
1192 qh->tt_buffer_dirty = 0;
1204 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1205 if (slots == priv->int_slots) {
1206 if (state == PTD_STATE_QTD_RELOAD)
1207 dev_err(hcd->self.controller,
1208 "%s: PTD_STATE_QTD_RELOAD on "
1209 "interrupt packet\n", __func__);
1210 if (state != PTD_STATE_QTD_RELOAD)
1211 create_ptd_int(qh, qtd, &ptd);
1213 if (state != PTD_STATE_QTD_RELOAD)
1214 create_ptd_atl(qh, qtd, &ptd);
1217 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1226 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1228 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1230 irqreturn_t irqret = IRQ_NONE;
1232 spin_lock(&priv->lock);
1234 if (!(hcd->state & HC_STATE_RUNNING))
1237 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1238 if (unlikely(!imask))
1240 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1242 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1243 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1245 handle_done_ptds(hcd);
1247 irqret = IRQ_HANDLED;
1249 spin_unlock(&priv->lock);
1255 * Workaround for problem described in chip errata 2:
1257 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1258 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1259 * ATL done interrupts (the "instead of" might be important since it seems
1260 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1261 * to set the PTD's done bit in addition to not generating an interrupt!).
1263 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1264 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1266 * If we use SOF interrupts only, we get latency between ptd completion and the
1267 * actual handling. This is very noticeable in testusb runs which takes several
1268 * minutes longer without ATL interrupts.
1270 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1271 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1272 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1273 * completed and its done map bit is set.
1275 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1276 * not to cause too much lag when this HW bug occurs, while still hopefully
1277 * ensuring that the check does not falsely trigger.
1279 #define SLOT_TIMEOUT 300
1280 #define SLOT_CHECK_PERIOD 200
1281 static struct timer_list errata2_timer;
1283 static void errata2_function(unsigned long data)
1285 struct usb_hcd *hcd = (struct usb_hcd *) data;
1286 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1289 unsigned long spinflags;
1291 spin_lock_irqsave(&priv->lock, spinflags);
1293 for (slot = 0; slot < 32; slot++)
1294 if (priv->atl_slots[slot].qh && time_after(jiffies,
1295 priv->atl_slots[slot].timestamp +
1296 SLOT_TIMEOUT * HZ / 1000)) {
1297 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1298 if (!FROM_DW0_VALID(ptd.dw0) &&
1299 !FROM_DW3_ACTIVE(ptd.dw3))
1300 priv->atl_done_map |= 1 << slot;
1303 if (priv->atl_done_map)
1304 handle_done_ptds(hcd);
1306 spin_unlock_irqrestore(&priv->lock, spinflags);
1308 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1309 add_timer(&errata2_timer);
1312 static int isp1760_run(struct usb_hcd *hcd)
1319 hcd->uses_new_polling = 1;
1321 hcd->state = HC_STATE_RUNNING;
1323 /* Set PTD interrupt AND & OR maps */
1324 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1325 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1326 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1327 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1328 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1329 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1330 /* step 23 passed */
1332 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1333 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1335 command = reg_read32(hcd->regs, HC_USBCMD);
1336 command &= ~(CMD_LRESET|CMD_RESET);
1338 reg_write32(hcd->regs, HC_USBCMD, command);
1340 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1346 * Spec says to write FLAG_CF as last config action, priv code grabs
1347 * the semaphore while doing so.
1349 down_write(&ehci_cf_port_reset_rwsem);
1350 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1352 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1353 up_write(&ehci_cf_port_reset_rwsem);
1357 init_timer(&errata2_timer);
1358 errata2_timer.function = errata2_function;
1359 errata2_timer.data = (unsigned long) hcd;
1360 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1361 add_timer(&errata2_timer);
1363 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1364 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1365 chipid & 0xffff, chipid >> 16);
1367 /* PTD Register Init Part 2, Step 28 */
1369 /* Setup registers controlling PTD checking */
1370 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1371 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1372 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1373 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1374 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1375 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1376 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1377 ATL_BUF_FILL | INT_BUF_FILL);
1379 /* GRR this is run-once init(), being done every time the HC starts.
1380 * So long as they're part of class devices, we can't do it init()
1381 * since the class device isn't created that early.
1386 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1388 qtd->data_buffer = databuffer;
1390 if (len > MAX_PAYLOAD_SIZE)
1391 len = MAX_PAYLOAD_SIZE;
1397 static void qtd_list_free(struct list_head *qtd_list)
1399 struct isp1760_qtd *qtd, *qtd_next;
1401 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1402 list_del(&qtd->qtd_list);
1408 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1409 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1411 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1412 static void packetize_urb(struct usb_hcd *hcd,
1413 struct urb *urb, struct list_head *head, gfp_t flags)
1415 struct isp1760_qtd *qtd;
1417 int len, maxpacketsize;
1421 * URBs map to sequences of QTDs: one logical transaction
1424 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1425 /* XXX This looks like usb storage / SCSI bug */
1426 dev_err(hcd->self.controller,
1427 "buf is null, dma is %08lx len is %d\n",
1428 (long unsigned)urb->transfer_dma,
1429 urb->transfer_buffer_length);
1433 if (usb_pipein(urb->pipe))
1434 packet_type = IN_PID;
1436 packet_type = OUT_PID;
1438 if (usb_pipecontrol(urb->pipe)) {
1439 qtd = qtd_alloc(flags, urb, SETUP_PID);
1442 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1443 list_add_tail(&qtd->qtd_list, head);
1445 /* for zero length DATA stages, STATUS is always IN */
1446 if (urb->transfer_buffer_length == 0)
1447 packet_type = IN_PID;
1450 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1451 usb_pipeout(urb->pipe)));
1454 * buffer gets wrapped in one or more qtds;
1455 * last one may be "short" (including zero len)
1456 * and may serve as a control status ack
1458 buf = urb->transfer_buffer;
1459 len = urb->transfer_buffer_length;
1464 qtd = qtd_alloc(flags, urb, packet_type);
1467 this_qtd_len = qtd_fill(qtd, buf, len);
1468 list_add_tail(&qtd->qtd_list, head);
1470 len -= this_qtd_len;
1471 buf += this_qtd_len;
1478 * control requests may need a terminating data "status" ack;
1479 * bulk ones may need a terminating short packet (zero length).
1481 if (urb->transfer_buffer_length != 0) {
1484 if (usb_pipecontrol(urb->pipe)) {
1486 if (packet_type == IN_PID)
1487 packet_type = OUT_PID;
1489 packet_type = IN_PID;
1490 } else if (usb_pipebulk(urb->pipe)
1491 && (urb->transfer_flags & URB_ZERO_PACKET)
1492 && !(urb->transfer_buffer_length %
1497 qtd = qtd_alloc(flags, urb, packet_type);
1501 /* never any data in such packets */
1502 qtd_fill(qtd, NULL, 0);
1503 list_add_tail(&qtd->qtd_list, head);
1510 qtd_list_free(head);
1513 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1516 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1517 struct list_head *ep_queue;
1518 struct isp1760_qh *qh, *qhit;
1519 unsigned long spinflags;
1520 LIST_HEAD(new_qtds);
1524 switch (usb_pipetype(urb->pipe)) {
1526 ep_queue = &priv->qh_list[QH_CONTROL];
1529 ep_queue = &priv->qh_list[QH_BULK];
1531 case PIPE_INTERRUPT:
1532 if (urb->interval < 0)
1534 /* FIXME: Check bandwidth */
1535 ep_queue = &priv->qh_list[QH_INTERRUPT];
1537 case PIPE_ISOCHRONOUS:
1538 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1539 "not yet supported\n",
1543 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1548 if (usb_pipein(urb->pipe))
1549 urb->actual_length = 0;
1551 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1552 if (list_empty(&new_qtds))
1556 spin_lock_irqsave(&priv->lock, spinflags);
1558 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1559 retval = -ESHUTDOWN;
1560 qtd_list_free(&new_qtds);
1563 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1565 qtd_list_free(&new_qtds);
1569 qh = urb->ep->hcpriv;
1572 list_for_each_entry(qhit, ep_queue, qh_list) {
1579 list_add_tail(&qh->qh_list, ep_queue);
1581 qh = qh_alloc(GFP_ATOMIC);
1584 usb_hcd_unlink_urb_from_ep(hcd, urb);
1585 qtd_list_free(&new_qtds);
1588 list_add_tail(&qh->qh_list, ep_queue);
1589 urb->ep->hcpriv = qh;
1592 list_splice_tail(&new_qtds, &qh->qtd_list);
1596 spin_unlock_irqrestore(&priv->lock, spinflags);
1600 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1601 struct isp1760_qh *qh)
1603 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1606 WARN_ON(qh->slot == -1);
1608 /* We need to forcefully reclaim the slot since some transfers never
1609 return, e.g. interrupt transfers and NAKed bulk transfers. */
1610 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1611 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1612 skip_map |= (1 << qh->slot);
1613 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1614 priv->atl_slots[qh->slot].qh = NULL;
1615 priv->atl_slots[qh->slot].qtd = NULL;
1617 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1618 skip_map |= (1 << qh->slot);
1619 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1620 priv->int_slots[qh->slot].qh = NULL;
1621 priv->int_slots[qh->slot].qtd = NULL;
1628 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1629 * any active transfer belonging to the urb in the process.
1631 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1632 struct isp1760_qtd *qtd)
1635 int urb_was_running;
1638 urb_was_running = 0;
1639 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1640 if (qtd->urb != urb)
1643 if (qtd->status >= QTD_XFER_STARTED)
1644 urb_was_running = 1;
1645 if (last_qtd_of_urb(qtd, qh) &&
1646 (qtd->status >= QTD_XFER_COMPLETE))
1647 urb_was_running = 0;
1649 if (qtd->status == QTD_XFER_STARTED)
1650 kill_transfer(hcd, urb, qh);
1651 qtd->status = QTD_RETIRE;
1654 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1655 qh->tt_buffer_dirty = 1;
1656 if (usb_hub_clear_tt_buffer(urb))
1657 /* Clear failed; let's hope things work anyway */
1658 qh->tt_buffer_dirty = 0;
1662 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1665 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1666 unsigned long spinflags;
1667 struct isp1760_qh *qh;
1668 struct isp1760_qtd *qtd;
1671 spin_lock_irqsave(&priv->lock, spinflags);
1672 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1676 qh = urb->ep->hcpriv;
1682 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1683 if (qtd->urb == urb) {
1684 dequeue_urb_from_qtd(hcd, qh, qtd);
1685 list_move(&qtd->qtd_list, &qh->qtd_list);
1689 urb->status = status;
1693 spin_unlock_irqrestore(&priv->lock, spinflags);
1697 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1698 struct usb_host_endpoint *ep)
1700 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1701 unsigned long spinflags;
1702 struct isp1760_qh *qh, *qh_iter;
1705 spin_lock_irqsave(&priv->lock, spinflags);
1711 WARN_ON(!list_empty(&qh->qtd_list));
1713 for (i = 0; i < QH_END; i++)
1714 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1715 if (qh_iter == qh) {
1716 list_del(&qh_iter->qh_list);
1726 spin_unlock_irqrestore(&priv->lock, spinflags);
1729 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1731 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1732 u32 temp, status = 0;
1735 unsigned long flags;
1737 /* if !PM, root hub timers won't get shut down ... */
1738 if (!HC_IS_RUNNING(hcd->state))
1741 /* init status to no-changes */
1745 spin_lock_irqsave(&priv->lock, flags);
1746 temp = reg_read32(hcd->regs, HC_PORTSC1);
1748 if (temp & PORT_OWNER) {
1749 if (temp & PORT_CSC) {
1751 reg_write32(hcd->regs, HC_PORTSC1, temp);
1757 * Return status information even for ports with OWNER set.
1758 * Otherwise hub_wq wouldn't see the disconnect event when a
1759 * high-speed device is switched over to the companion
1760 * controller by the user.
1763 if ((temp & mask) != 0
1764 || ((temp & PORT_RESUME) != 0
1765 && time_after_eq(jiffies,
1766 priv->reset_done))) {
1767 buf [0] |= 1 << (0 + 1);
1770 /* FIXME autosuspend idle root hubs */
1772 spin_unlock_irqrestore(&priv->lock, flags);
1773 return status ? retval : 0;
1776 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1777 struct usb_hub_descriptor *desc)
1779 int ports = HCS_N_PORTS(priv->hcs_params);
1782 desc->bDescriptorType = 0x29;
1783 /* priv 1.0, 2.3.9 says 20ms max */
1784 desc->bPwrOn2PwrGood = 10;
1785 desc->bHubContrCurrent = 0;
1787 desc->bNbrPorts = ports;
1788 temp = 1 + (ports / 8);
1789 desc->bDescLength = 7 + 2 * temp;
1791 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1792 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1793 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1795 /* per-port overcurrent reporting */
1797 if (HCS_PPC(priv->hcs_params))
1798 /* per-port power control */
1801 /* no power switching */
1803 desc->wHubCharacteristics = cpu_to_le16(temp);
1806 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1808 static int check_reset_complete(struct usb_hcd *hcd, int index,
1811 if (!(port_status & PORT_CONNECT))
1814 /* if reset finished and it's still not enabled -- handoff */
1815 if (!(port_status & PORT_PE)) {
1817 dev_info(hcd->self.controller,
1818 "port %d full speed --> companion\n",
1821 port_status |= PORT_OWNER;
1822 port_status &= ~PORT_RWC_BITS;
1823 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1826 dev_info(hcd->self.controller, "port %d high speed\n",
1832 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1833 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1835 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1836 int ports = HCS_N_PORTS(priv->hcs_params);
1838 unsigned long flags;
1843 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1844 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1845 * (track current state ourselves) ... blink for diagnostics,
1846 * power, "this is the one", etc. EHCI spec supports this.
1849 spin_lock_irqsave(&priv->lock, flags);
1851 case ClearHubFeature:
1853 case C_HUB_LOCAL_POWER:
1854 case C_HUB_OVER_CURRENT:
1855 /* no hub-wide feature/status flags */
1861 case ClearPortFeature:
1862 if (!wIndex || wIndex > ports)
1865 temp = reg_read32(hcd->regs, HC_PORTSC1);
1868 * Even if OWNER is set, so the port is owned by the
1869 * companion controller, hub_wq needs to be able to clear
1870 * the port-change status bits (especially
1871 * USB_PORT_STAT_C_CONNECTION).
1875 case USB_PORT_FEAT_ENABLE:
1876 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1878 case USB_PORT_FEAT_C_ENABLE:
1881 case USB_PORT_FEAT_SUSPEND:
1882 if (temp & PORT_RESET)
1885 if (temp & PORT_SUSPEND) {
1886 if ((temp & PORT_PE) == 0)
1888 /* resume signaling for 20 msec */
1889 temp &= ~(PORT_RWC_BITS);
1890 reg_write32(hcd->regs, HC_PORTSC1,
1891 temp | PORT_RESUME);
1892 priv->reset_done = jiffies +
1893 msecs_to_jiffies(20);
1896 case USB_PORT_FEAT_C_SUSPEND:
1897 /* we auto-clear this feature */
1899 case USB_PORT_FEAT_POWER:
1900 if (HCS_PPC(priv->hcs_params))
1901 reg_write32(hcd->regs, HC_PORTSC1,
1902 temp & ~PORT_POWER);
1904 case USB_PORT_FEAT_C_CONNECTION:
1905 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1907 case USB_PORT_FEAT_C_OVER_CURRENT:
1910 case USB_PORT_FEAT_C_RESET:
1911 /* GetPortStatus clears reset */
1916 reg_read32(hcd->regs, HC_USBCMD);
1918 case GetHubDescriptor:
1919 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1923 /* no hub-wide feature/status flags */
1927 if (!wIndex || wIndex > ports)
1931 temp = reg_read32(hcd->regs, HC_PORTSC1);
1933 /* wPortChange bits */
1934 if (temp & PORT_CSC)
1935 status |= USB_PORT_STAT_C_CONNECTION << 16;
1938 /* whoever resumes must GetPortStatus to complete it!! */
1939 if (temp & PORT_RESUME) {
1940 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1942 /* Remote Wakeup received? */
1943 if (!priv->reset_done) {
1944 /* resume signaling for 20 msec */
1945 priv->reset_done = jiffies
1946 + msecs_to_jiffies(20);
1947 /* check the port again */
1948 mod_timer(&hcd->rh_timer, priv->reset_done);
1951 /* resume completed? */
1952 else if (time_after_eq(jiffies,
1953 priv->reset_done)) {
1954 status |= USB_PORT_STAT_C_SUSPEND << 16;
1955 priv->reset_done = 0;
1957 /* stop resume signaling */
1958 temp = reg_read32(hcd->regs, HC_PORTSC1);
1959 reg_write32(hcd->regs, HC_PORTSC1,
1960 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1961 retval = handshake(hcd, HC_PORTSC1,
1962 PORT_RESUME, 0, 2000 /* 2msec */);
1964 dev_err(hcd->self.controller,
1965 "port %d resume error %d\n",
1966 wIndex + 1, retval);
1969 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1973 /* whoever resets must GetPortStatus to complete it!! */
1974 if ((temp & PORT_RESET)
1975 && time_after_eq(jiffies,
1976 priv->reset_done)) {
1977 status |= USB_PORT_STAT_C_RESET << 16;
1978 priv->reset_done = 0;
1980 /* force reset to complete */
1981 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1982 /* REVISIT: some hardware needs 550+ usec to clear
1983 * this bit; seems too long to spin routinely...
1985 retval = handshake(hcd, HC_PORTSC1,
1986 PORT_RESET, 0, 750);
1988 dev_err(hcd->self.controller, "port %d reset error %d\n",
1989 wIndex + 1, retval);
1993 /* see what we found out */
1994 temp = check_reset_complete(hcd, wIndex,
1995 reg_read32(hcd->regs, HC_PORTSC1));
1998 * Even if OWNER is set, there's no harm letting hub_wq
1999 * see the wPortStatus values (they should all be 0 except
2000 * for PORT_POWER anyway).
2003 if (temp & PORT_OWNER)
2004 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2006 if (temp & PORT_CONNECT) {
2007 status |= USB_PORT_STAT_CONNECTION;
2008 /* status may be from integrated TT */
2009 status |= USB_PORT_STAT_HIGH_SPEED;
2012 status |= USB_PORT_STAT_ENABLE;
2013 if (temp & (PORT_SUSPEND|PORT_RESUME))
2014 status |= USB_PORT_STAT_SUSPEND;
2015 if (temp & PORT_RESET)
2016 status |= USB_PORT_STAT_RESET;
2017 if (temp & PORT_POWER)
2018 status |= USB_PORT_STAT_POWER;
2020 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2024 case C_HUB_LOCAL_POWER:
2025 case C_HUB_OVER_CURRENT:
2026 /* no hub-wide feature/status flags */
2032 case SetPortFeature:
2033 selector = wIndex >> 8;
2035 if (!wIndex || wIndex > ports)
2038 temp = reg_read32(hcd->regs, HC_PORTSC1);
2039 if (temp & PORT_OWNER)
2042 /* temp &= ~PORT_RWC_BITS; */
2044 case USB_PORT_FEAT_ENABLE:
2045 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2048 case USB_PORT_FEAT_SUSPEND:
2049 if ((temp & PORT_PE) == 0
2050 || (temp & PORT_RESET) != 0)
2053 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2055 case USB_PORT_FEAT_POWER:
2056 if (HCS_PPC(priv->hcs_params))
2057 reg_write32(hcd->regs, HC_PORTSC1,
2060 case USB_PORT_FEAT_RESET:
2061 if (temp & PORT_RESUME)
2063 /* line status bits may report this as low speed,
2064 * which can be fine if this root hub has a
2065 * transaction translator built in.
2067 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2068 && PORT_USB11(temp)) {
2075 * caller must wait, then call GetPortStatus
2076 * usb 2.0 spec says 50 ms resets on root
2078 priv->reset_done = jiffies +
2079 msecs_to_jiffies(50);
2081 reg_write32(hcd->regs, HC_PORTSC1, temp);
2086 reg_read32(hcd->regs, HC_USBCMD);
2091 /* "stall" on error */
2094 spin_unlock_irqrestore(&priv->lock, flags);
2098 static int isp1760_get_frame(struct usb_hcd *hcd)
2100 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2103 fr = reg_read32(hcd->regs, HC_FRINDEX);
2104 return (fr >> 3) % priv->periodic_size;
2107 static void isp1760_stop(struct usb_hcd *hcd)
2109 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2112 del_timer(&errata2_timer);
2114 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2118 spin_lock_irq(&priv->lock);
2121 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2122 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2123 spin_unlock_irq(&priv->lock);
2125 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2128 static void isp1760_shutdown(struct usb_hcd *hcd)
2133 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2134 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2136 command = reg_read32(hcd->regs, HC_USBCMD);
2137 command &= ~CMD_RUN;
2138 reg_write32(hcd->regs, HC_USBCMD, command);
2141 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2142 struct usb_host_endpoint *ep)
2144 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2145 struct isp1760_qh *qh = ep->hcpriv;
2146 unsigned long spinflags;
2151 spin_lock_irqsave(&priv->lock, spinflags);
2152 qh->tt_buffer_dirty = 0;
2154 spin_unlock_irqrestore(&priv->lock, spinflags);
2158 static const struct hc_driver isp1760_hc_driver = {
2159 .description = "isp1760-hcd",
2160 .product_desc = "NXP ISP1760 USB Host Controller",
2161 .hcd_priv_size = sizeof(struct isp1760_hcd),
2163 .flags = HCD_MEMORY | HCD_USB2,
2164 .reset = isp1760_hc_setup,
2165 .start = isp1760_run,
2166 .stop = isp1760_stop,
2167 .shutdown = isp1760_shutdown,
2168 .urb_enqueue = isp1760_urb_enqueue,
2169 .urb_dequeue = isp1760_urb_dequeue,
2170 .endpoint_disable = isp1760_endpoint_disable,
2171 .get_frame_number = isp1760_get_frame,
2172 .hub_status_data = isp1760_hub_status_data,
2173 .hub_control = isp1760_hub_control,
2174 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2177 int __init init_kmem_once(void)
2179 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2180 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2181 SLAB_MEM_SPREAD, NULL);
2183 if (!urb_listitem_cachep)
2186 qtd_cachep = kmem_cache_create("isp1760_qtd",
2187 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2188 SLAB_MEM_SPREAD, NULL);
2193 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2194 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2197 kmem_cache_destroy(qtd_cachep);
2204 void deinit_kmem_cache(void)
2206 kmem_cache_destroy(qtd_cachep);
2207 kmem_cache_destroy(qh_cachep);
2208 kmem_cache_destroy(urb_listitem_cachep);
2211 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2212 int irq, unsigned long irqflags,
2213 struct device *dev, const char *busname,
2214 unsigned int devflags)
2216 struct usb_hcd *hcd;
2217 struct isp1760_hcd *priv;
2221 return ERR_PTR(-ENODEV);
2223 /* prevent usb-core allocating DMA pages */
2224 dev->dma_mask = NULL;
2226 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2228 return ERR_PTR(-ENOMEM);
2230 priv = hcd_to_priv(hcd);
2231 priv->devflags = devflags;
2233 priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
2234 if (IS_ERR(priv->rst_gpio)) {
2235 ret = PTR_ERR(priv->rst_gpio);
2240 hcd->regs = ioremap(res_start, res_len);
2247 hcd->rsrc_start = res_start;
2248 hcd->rsrc_len = res_len;
2250 ret = usb_add_hcd(hcd, irq, irqflags);
2253 device_wakeup_enable(hcd->self.controller);
2263 return ERR_PTR(ret);
2266 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2267 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2268 MODULE_LICENSE("GPL v2");