drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  12  *
  13  */
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/list.h>
  19 #include <linux/usb.h>
  20 #include <linux/usb/hcd.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/timer.h>
  26 #include <asm/unaligned.h>
  27 #include <asm/cacheflush.h>
  28
  29 #include "isp1760-hcd.h"
  30
  31 static struct kmem_cache *qtd_cachep;
  32 static struct kmem_cache *qh_cachep;
  33 static struct kmem_cache *urb_listitem_cachep;
  34
  35 enum queue_head_types {
  36         QH_CONTROL,
  37         QH_BULK,
  38         QH_INTERRUPT,
  39         QH_END
  40 };
  41
  42 struct isp1760_hcd {
  43         struct usb_hcd          *hcd;
  44
  45         u32 hcs_params;
  46         spinlock_t              lock;
  47         struct isp1760_slotinfo atl_slots[32];
  48         int                     atl_done_map;
  49         struct isp1760_slotinfo int_slots[32];
  50         int                     int_done_map;
  51         struct isp1760_memory_chunk memory_pool[BLOCKS];
  52         struct list_head        qh_list[QH_END];
  53
  54         /* periodic schedule support */
  55 #define DEFAULT_I_TDPS          1024
  56         unsigned                periodic_size;
  57         unsigned                i_thresh;
  58         unsigned long           reset_done;
  59         unsigned long           next_statechange;
  60         unsigned int            devflags;
  61
  62         struct gpio_desc        *rst_gpio;
  63 };
  64
  65 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
  66                 struct isp1760_qtd *qtd);
  67
  68 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  69 {
  70         return *(struct isp1760_hcd **)hcd->hcd_priv;
  71 }
  72
  73 /* Section 2.2 Host Controller Capability Registers */
  74 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
  75 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
  76 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
  77 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
  78 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
  79 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
  80 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
  81
  82 /* Section 2.3 Host Controller Operational Registers */
  83 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
  84 #define CMD_RESET       (1<<1)          /* reset HC not bus */
  85 #define CMD_RUN         (1<<0)          /* start/stop HC */
  86 #define STS_PCD         (1<<2)          /* port change detect */
  87 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
  88
  89 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
  90 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
  91 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10))  /* USB 1.1 device */
  92 #define PORT_RESET      (1<<8)          /* reset port */
  93 #define PORT_SUSPEND    (1<<7)          /* suspend port */
  94 #define PORT_RESUME     (1<<6)          /* resume it */
  95 #define PORT_PE         (1<<2)          /* port enable */
  96 #define PORT_CSC        (1<<1)          /* connect status change */
  97 #define PORT_CONNECT    (1<<0)          /* device connected */
  98 #define PORT_RWC_BITS   (PORT_CSC)
  99
 100 struct isp1760_qtd {
 101         u8 packet_type;
 102         void *data_buffer;
 103         u32 payload_addr;
 104
 105         /* the rest is HCD-private */
 106         struct list_head qtd_list;
 107         struct urb *urb;
 108         size_t length;
 109         size_t actual_length;
 110
 111         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
 112         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
 113         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
 114                                 interrupt handler may touch this qtd! */
 115         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
 116         /* QTD_RETIRE:          transfer error/abort qtd */
 117 #define QTD_ENQUEUED            0
 118 #define QTD_PAYLOAD_ALLOC       1
 119 #define QTD_XFER_STARTED        2
 120 #define QTD_XFER_COMPLETE       3
 121 #define QTD_RETIRE              4
 122         u32 status;
 123 };
 124
 125 /* Queue head, one for each active endpoint */
 126 struct isp1760_qh {
 127         struct list_head qh_list;
 128         struct list_head qtd_list;
 129         u32 toggle;
 130         u32 ping;
 131         int slot;
 132         int tt_buffer_dirty;    /* See USB2.0 spec section 11.17.5 */
 133 };
 134
 135 struct urb_listitem {
 136         struct list_head urb_list;
 137         struct urb *urb;
 138 };
 139
 140 /*
 141  * Access functions for isp176x registers (addresses 0..0x03FF).
 142  */
 143 static u32 reg_read32(void __iomem *base, u32 reg)
 144 {
 145         return readl(base + reg);
 146 }
 147
 148 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 149 {
 150         writel(val, base + reg);
 151 }
 152
 153 /*
 154  * Access functions for isp176x memory (offset >= 0x0400).
 155  *
 156  * bank_reads8() reads memory locations prefetched by an earlier write to
 157  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 158  * bank optimizations, you should use the more generic mem_reads8() below.
 159  *
 160  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 161  * below.
 162  *
 163  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 164  * doesn't quite work because some people have to enforce 32-bit access
 165  */
 166 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 167                                                         __u32 *dst, u32 bytes)
 168 {
 169         __u32 __iomem *src;
 170         u32 val;
 171         __u8 *src_byteptr;
 172         __u8 *dst_byteptr;
 173
 174         src = src_base + (bank_addr | src_offset);
 175
 176         if (src_offset < PAYLOAD_OFFSET) {
 177                 while (bytes >= 4) {
 178                         *dst = le32_to_cpu(__raw_readl(src));
 179                         bytes -= 4;
 180                         src++;
 181                         dst++;
 182                 }
 183         } else {
 184                 while (bytes >= 4) {
 185                         *dst = __raw_readl(src);
 186                         bytes -= 4;
 187                         src++;
 188                         dst++;
 189                 }
 190         }
 191
 192         if (!bytes)
 193                 return;
 194
 195         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 196          * allocated.
 197          */
 198         if (src_offset < PAYLOAD_OFFSET)
 199                 val = le32_to_cpu(__raw_readl(src));
 200         else
 201                 val = __raw_readl(src);
 202
 203         dst_byteptr = (void *) dst;
 204         src_byteptr = (void *) &val;
 205         while (bytes > 0) {
 206                 *dst_byteptr = *src_byteptr;
 207                 dst_byteptr++;
 208                 src_byteptr++;
 209                 bytes--;
 210         }
 211 }
 212
 213 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 214                                                                 u32 bytes)
 215 {
 216         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 217         ndelay(90);
 218         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 219 }
 220
 221 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 222                                                 __u32 const *src, u32 bytes)
 223 {
 224         __u32 __iomem *dst;
 225
 226         dst = dst_base + dst_offset;
 227
 228         if (dst_offset < PAYLOAD_OFFSET) {
 229                 while (bytes >= 4) {
 230                         __raw_writel(cpu_to_le32(*src), dst);
 231                         bytes -= 4;
 232                         src++;
 233                         dst++;
 234                 }
 235         } else {
 236                 while (bytes >= 4) {
 237                         __raw_writel(*src, dst);
 238                         bytes -= 4;
 239                         src++;
 240                         dst++;
 241                 }
 242         }
 243
 244         if (!bytes)
 245                 return;
 246         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 247          * extra bytes should not be read by the HW.
 248          */
 249
 250         if (dst_offset < PAYLOAD_OFFSET)
 251                 __raw_writel(cpu_to_le32(*src), dst);
 252         else
 253                 __raw_writel(*src, dst);
 254 }
 255
 256 /*
 257  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 258  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 259  */
 260 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 261                                                                 struct ptd *ptd)
 262 {
 263         reg_write32(base, HC_MEMORY_REG,
 264                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 265         ndelay(90);
 266         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 267                                                 (void *) ptd, sizeof(*ptd));
 268 }
 269
 270 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 271                                                                 struct ptd *ptd)
 272 {
 273         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 274                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 275         /* Make sure dw0 gets written last (after other dw's and after payload)
 276            since it contains the enable bit */
 277         wmb();
 278         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 279                                                         sizeof(ptd->dw0));
 280 }
 281
 282
 283 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 284 static void init_memory(struct isp1760_hcd *priv)
 285 {
 286         int i, curr;
 287         u32 payload_addr;
 288
 289         payload_addr = PAYLOAD_OFFSET;
 290         for (i = 0; i < BLOCK_1_NUM; i++) {
 291                 priv->memory_pool[i].start = payload_addr;
 292                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 293                 priv->memory_pool[i].free = 1;
 294                 payload_addr += priv->memory_pool[i].size;
 295         }
 296
 297         curr = i;
 298         for (i = 0; i < BLOCK_2_NUM; i++) {
 299                 priv->memory_pool[curr + i].start = payload_addr;
 300                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 301                 priv->memory_pool[curr + i].free = 1;
 302                 payload_addr += priv->memory_pool[curr + i].size;
 303         }
 304
 305         curr = i;
 306         for (i = 0; i < BLOCK_3_NUM; i++) {
 307                 priv->memory_pool[curr + i].start = payload_addr;
 308                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 309                 priv->memory_pool[curr + i].free = 1;
 310                 payload_addr += priv->memory_pool[curr + i].size;
 311         }
 312
 313         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 314 }
 315
 316 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 317 {
 318         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 319         int i;
 320
 321         WARN_ON(qtd->payload_addr);
 322
 323         if (!qtd->length)
 324                 return;
 325
 326         for (i = 0; i < BLOCKS; i++) {
 327                 if (priv->memory_pool[i].size >= qtd->length &&
 328                                 priv->memory_pool[i].free) {
 329                         priv->memory_pool[i].free = 0;
 330                         qtd->payload_addr = priv->memory_pool[i].start;
 331                         return;
 332                 }
 333         }
 334 }
 335
 336 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 337 {
 338         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 339         int i;
 340
 341         if (!qtd->payload_addr)
 342                 return;
 343
 344         for (i = 0; i < BLOCKS; i++) {
 345                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 346                         WARN_ON(priv->memory_pool[i].free);
 347                         priv->memory_pool[i].free = 1;
 348                         qtd->payload_addr = 0;
 349                         return;
 350                 }
 351         }
 352
 353         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 354                                                 __func__, qtd->payload_addr);
 355         WARN_ON(1);
 356         qtd->payload_addr = 0;
 357 }
 358
 359 static int handshake(struct usb_hcd *hcd, u32 reg,
 360                       u32 mask, u32 done, int usec)
 361 {
 362         u32 result;
 363
 364         do {
 365                 result = reg_read32(hcd->regs, reg);
 366                 if (result == ~0)
 367                         return -ENODEV;
 368                 result &= mask;
 369                 if (result == done)
 370                         return 0;
 371                 udelay(1);
 372                 usec--;
 373         } while (usec > 0);
 374         return -ETIMEDOUT;
 375 }
 376
 377 /* reset a non-running (STS_HALT == 1) controller */
 378 static int ehci_reset(struct usb_hcd *hcd)
 379 {
 380         int retval;
 381         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 382
 383         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 384
 385         command |= CMD_RESET;
 386         reg_write32(hcd->regs, HC_USBCMD, command);
 387         hcd->state = HC_STATE_HALT;
 388         priv->next_statechange = jiffies;
 389         retval = handshake(hcd, HC_USBCMD,
 390                             CMD_RESET, 0, 250 * 1000);
 391         return retval;
 392 }
 393
 394 static struct isp1760_qh *qh_alloc(gfp_t flags)
 395 {
 396         struct isp1760_qh *qh;
 397
 398         qh = kmem_cache_zalloc(qh_cachep, flags);
 399         if (!qh)
 400                 return NULL;
 401
 402         INIT_LIST_HEAD(&qh->qh_list);
 403         INIT_LIST_HEAD(&qh->qtd_list);
 404         qh->slot = -1;
 405
 406         return qh;
 407 }
 408
 409 static void qh_free(struct isp1760_qh *qh)
 410 {
 411         WARN_ON(!list_empty(&qh->qtd_list));
 412         WARN_ON(qh->slot > -1);
 413         kmem_cache_free(qh_cachep, qh);
 414 }
 415
 416 /* one-time init, only for memory state */
 417 static int priv_init(struct usb_hcd *hcd)
 418 {
 419         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 420         u32                     hcc_params;
 421         int i;
 422
 423         spin_lock_init(&priv->lock);
 424
 425         for (i = 0; i < QH_END; i++)
 426                 INIT_LIST_HEAD(&priv->qh_list[i]);
 427
 428         /*
 429          * hw default: 1K periodic list heads, one per frame.
 430          * periodic_size can shrink by USBCMD update if hcc_params allows.
 431          */
 432         priv->periodic_size = DEFAULT_I_TDPS;
 433
 434         /* controllers may cache some of the periodic schedule ... */
 435         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 436         /* full frame cache */
 437         if (HCC_ISOC_CACHE(hcc_params))
 438                 priv->i_thresh = 8;
 439         else /* N microframes cached */
 440                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 441
 442         return 0;
 443 }
 444
 445 static int isp1760_hc_setup(struct usb_hcd *hcd)
 446 {
 447         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 448         int result;
 449         u32 scratch, hwmode;
 450
 451         /* low-level chip reset */
 452         if (priv->rst_gpio) {
 453                 gpiod_set_value_cansleep(priv->rst_gpio, 1);
 454                 mdelay(50);
 455                 gpiod_set_value_cansleep(priv->rst_gpio, 0);
 456         }
 457
 458         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 459         hwmode = HW_DATA_BUS_32BIT;
 460
 461         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 462                 hwmode &= ~HW_DATA_BUS_32BIT;
 463         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 464                 hwmode |= HW_ANA_DIGI_OC;
 465         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 466                 hwmode |= HW_DACK_POL_HIGH;
 467         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 468                 hwmode |= HW_DREQ_POL_HIGH;
 469         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 470                 hwmode |= HW_INTR_HIGH_ACT;
 471         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 472                 hwmode |= HW_INTR_EDGE_TRIG;
 473
 474         /*
 475          * We have to set this first in case we're in 16-bit mode.
 476          * Write it twice to ensure correct upper bits if switching
 477          * to 16-bit mode.
 478          */
 479         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 480         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 481
 482         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 483         /* Change bus pattern */
 484         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 485         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 486         if (scratch != 0xdeadbabe) {
 487                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 488                 return -ENODEV;
 489         }
 490
 491         /* pre reset */
 492         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 493         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 494         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 495         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 496
 497         /* reset */
 498         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 499         mdelay(100);
 500
 501         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 502         mdelay(100);
 503
 504         result = ehci_reset(hcd);
 505         if (result)
 506                 return result;
 507
 508         /* Step 11 passed */
 509
 510         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 511                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 512                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 513                            "analog" : "digital");
 514
 515         /* ATL reset */
 516         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 517         mdelay(10);
 518         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 519
 520         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 521
 522         /*
 523          * PORT 1 Control register of the ISP1760 is the OTG control
 524          * register on ISP1761. Since there is no OTG or device controller
 525          * support in this driver, we use port 1 as a "normal" USB host port on
 526          * both chips.
 527          */
 528         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 529         mdelay(10);
 530
 531         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 532
 533         return priv_init(hcd);
 534 }
 535
 536 static u32 base_to_chip(u32 base)
 537 {
 538         return ((base - 0x400) >> 3);
 539 }
 540
 541 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 542 {
 543         struct urb *urb;
 544
 545         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 546                 return 1;
 547
 548         urb = qtd->urb;
 549         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 550         return (qtd->urb != urb);
 551 }
 552
 553 /* magic numbers that can affect system performance */
 554 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 555 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 556 #define EHCI_TUNE_RL_TT         0
 557 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 558 #define EHCI_TUNE_MULT_TT       1
 559 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 560
 561 static void create_ptd_atl(struct isp1760_qh *qh,
 562                         struct isp1760_qtd *qtd, struct ptd *ptd)
 563 {
 564         u32 maxpacket;
 565         u32 multi;
 566         u32 rl = RL_COUNTER;
 567         u32 nak = NAK_COUNTER;
 568
 569         memset(ptd, 0, sizeof(*ptd));
 570
 571         /* according to 3.6.2, max packet len can not be > 0x400 */
 572         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 573                                                 usb_pipeout(qtd->urb->pipe));
 574         multi =  1 + ((maxpacket >> 11) & 0x3);
 575         maxpacket &= 0x7ff;
 576
 577         /* DW0 */
 578         ptd->dw0 = DW0_VALID_BIT;
 579         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 580         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 581         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 582
 583         /* DW1 */
 584         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 585         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 586         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 587
 588         if (usb_pipebulk(qtd->urb->pipe))
 589                 ptd->dw1 |= DW1_TRANS_BULK;
 590         else if  (usb_pipeint(qtd->urb->pipe))
 591                 ptd->dw1 |= DW1_TRANS_INT;
 592
 593         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 594                 /* split transaction */
 595
 596                 ptd->dw1 |= DW1_TRANS_SPLIT;
 597                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 598                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 599
 600                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 601                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 602
 603                 /* SE bit for Split INT transfers */
 604                 if (usb_pipeint(qtd->urb->pipe) &&
 605                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 606                         ptd->dw1 |= 2 << 16;
 607
 608                 rl = 0;
 609                 nak = 0;
 610         } else {
 611                 ptd->dw0 |= TO_DW0_MULTI(multi);
 612                 if (usb_pipecontrol(qtd->urb->pipe) ||
 613                                                 usb_pipebulk(qtd->urb->pipe))
 614                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 615         }
 616         /* DW2 */
 617         ptd->dw2 = 0;
 618         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 619         ptd->dw2 |= TO_DW2_RL(rl);
 620
 621         /* DW3 */
 622         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 623         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 624         if (usb_pipecontrol(qtd->urb->pipe)) {
 625                 if (qtd->data_buffer == qtd->urb->setup_packet)
 626                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 627                 else if (last_qtd_of_urb(qtd, qh))
 628                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 629         }
 630
 631         ptd->dw3 |= DW3_ACTIVE_BIT;
 632         /* Cerr */
 633         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 634 }
 635
 636 static void transform_add_int(struct isp1760_qh *qh,
 637                         struct isp1760_qtd *qtd, struct ptd *ptd)
 638 {
 639         u32 usof;
 640         u32 period;
 641
 642         /*
 643          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 644          * the algorithm from the original Philips driver code, which was
 645          * pretty much used in this driver before as well, is quite horrendous
 646          * and, i believe, incorrect. The code below follows the datasheet and
 647          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 648          * more reliable this way (fingers crossed...).
 649          */
 650
 651         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 652                 /* urb->interval is in units of microframes (1/8 ms) */
 653                 period = qtd->urb->interval >> 3;
 654
 655                 if (qtd->urb->interval > 4)
 656                         usof = 0x01; /* One bit set =>
 657                                                 interval 1 ms * uFrame-match */
 658                 else if (qtd->urb->interval > 2)
 659                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 660                 else if (qtd->urb->interval > 1)
 661                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 662                 else
 663                         usof = 0xff; /* All bits set => interval 1/8 ms */
 664         } else {
 665                 /* urb->interval is in units of frames (1 ms) */
 666                 period = qtd->urb->interval;
 667                 usof = 0x0f;            /* Execute Start Split on any of the
 668                                            four first uFrames */
 669
 670                 /*
 671                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 672                  * complete split needs to be sent. Valid only for IN." Also,
 673                  * "All bits can be set to one for every transfer." (p 82,
 674                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 675                  * that number come from? 0xff seems to work fine...
 676                  */
 677                 /* ptd->dw5 = 0x1c; */
 678                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 679         }
 680
 681         period = period >> 1;/* Ensure equal or shorter period than requested */
 682         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 683
 684         ptd->dw2 |= period;
 685         ptd->dw4 = usof;
 686 }
 687
 688 static void create_ptd_int(struct isp1760_qh *qh,
 689                         struct isp1760_qtd *qtd, struct ptd *ptd)
 690 {
 691         create_ptd_atl(qh, qtd, ptd);
 692         transform_add_int(qh, qtd, ptd);
 693 }
 694
 695 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 696 __releases(priv->lock)
 697 __acquires(priv->lock)
 698 {
 699         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 700
 701         if (!urb->unlinked) {
 702                 if (urb->status == -EINPROGRESS)
 703                         urb->status = 0;
 704         }
 705
 706         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 707                 void *ptr;
 708                 for (ptr = urb->transfer_buffer;
 709                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 710                      ptr += PAGE_SIZE)
 711                         flush_dcache_page(virt_to_page(ptr));
 712         }
 713
 714         /* complete() can reenter this HCD */
 715         usb_hcd_unlink_urb_from_ep(hcd, urb);
 716         spin_unlock(&priv->lock);
 717         usb_hcd_giveback_urb(hcd, urb, urb->status);
 718         spin_lock(&priv->lock);
 719 }
 720
 721 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 722                                                                 u8 packet_type)
 723 {
 724         struct isp1760_qtd *qtd;
 725
 726         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 727         if (!qtd)
 728                 return NULL;
 729
 730         INIT_LIST_HEAD(&qtd->qtd_list);
 731         qtd->urb = urb;
 732         qtd->packet_type = packet_type;
 733         qtd->status = QTD_ENQUEUED;
 734         qtd->actual_length = 0;
 735
 736         return qtd;
 737 }
 738
 739 static void qtd_free(struct isp1760_qtd *qtd)
 740 {
 741         WARN_ON(qtd->payload_addr);
 742         kmem_cache_free(qtd_cachep, qtd);
 743 }
 744
 745 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 746                                 struct isp1760_slotinfo *slots,
 747                                 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
 748                                 struct ptd *ptd)
 749 {
 750         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 751         int skip_map;
 752
 753         WARN_ON((slot < 0) || (slot > 31));
 754         WARN_ON(qtd->length && !qtd->payload_addr);
 755         WARN_ON(slots[slot].qtd);
 756         WARN_ON(slots[slot].qh);
 757         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 758
 759         /* Make sure done map has not triggered from some unlinked transfer */
 760         if (ptd_offset == ATL_PTD_OFFSET) {
 761                 priv->atl_done_map |= reg_read32(hcd->regs,
 762                                                 HC_ATL_PTD_DONEMAP_REG);
 763                 priv->atl_done_map &= ~(1 << slot);
 764         } else {
 765                 priv->int_done_map |= reg_read32(hcd->regs,
 766                                                 HC_INT_PTD_DONEMAP_REG);
 767                 priv->int_done_map &= ~(1 << slot);
 768         }
 769
 770         qh->slot = slot;
 771         qtd->status = QTD_XFER_STARTED;
 772         slots[slot].timestamp = jiffies;
 773         slots[slot].qtd = qtd;
 774         slots[slot].qh = qh;
 775         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 776
 777         if (ptd_offset == ATL_PTD_OFFSET) {
 778                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 779                 skip_map &= ~(1 << qh->slot);
 780                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 781         } else {
 782                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 783                 skip_map &= ~(1 << qh->slot);
 784                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 785         }
 786 }
 787
 788 static int is_short_bulk(struct isp1760_qtd *qtd)
 789 {
 790         return (usb_pipebulk(qtd->urb->pipe) &&
 791                                         (qtd->actual_length < qtd->length));
 792 }
 793
 794 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 795                                                 struct list_head *urb_list)
 796 {
 797         int last_qtd;
 798         struct isp1760_qtd *qtd, *qtd_next;
 799         struct urb_listitem *urb_listitem;
 800
 801         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 802                 if (qtd->status < QTD_XFER_COMPLETE)
 803                         break;
 804
 805                 last_qtd = last_qtd_of_urb(qtd, qh);
 806
 807                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 808                         qtd_next->status = QTD_RETIRE;
 809
 810                 if (qtd->status == QTD_XFER_COMPLETE) {
 811                         if (qtd->actual_length) {
 812                                 switch (qtd->packet_type) {
 813                                 case IN_PID:
 814                                         mem_reads8(hcd->regs, qtd->payload_addr,
 815                                                         qtd->data_buffer,
 816                                                         qtd->actual_length);
 817                                         /* Fall through (?) */
 818                                 case OUT_PID:
 819                                         qtd->urb->actual_length +=
 820                                                         qtd->actual_length;
 821                                         /* Fall through ... */
 822                                 case SETUP_PID:
 823                                         break;
 824                                 }
 825                         }
 826
 827                         if (is_short_bulk(qtd)) {
 828                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 829                                         qtd->urb->status = -EREMOTEIO;
 830                                 if (!last_qtd)
 831                                         qtd_next->status = QTD_RETIRE;
 832                         }
 833                 }
 834
 835                 if (qtd->payload_addr)
 836                         free_mem(hcd, qtd);
 837
 838                 if (last_qtd) {
 839                         if ((qtd->status == QTD_RETIRE) &&
 840                                         (qtd->urb->status == -EINPROGRESS))
 841                                 qtd->urb->status = -EPIPE;
 842                         /* Defer calling of urb_done() since it releases lock */
 843                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 844                                                                 GFP_ATOMIC);
 845                         if (unlikely(!urb_listitem))
 846                                 break; /* Try again on next call */
 847                         urb_listitem->urb = qtd->urb;
 848                         list_add_tail(&urb_listitem->urb_list, urb_list);
 849                 }
 850
 851                 list_del(&qtd->qtd_list);
 852                 qtd_free(qtd);
 853         }
 854 }
 855
 856 #define ENQUEUE_DEPTH   2
 857 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 858 {
 859         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 860         int ptd_offset;
 861         struct isp1760_slotinfo *slots;
 862         int curr_slot, free_slot;
 863         int n;
 864         struct ptd ptd;
 865         struct isp1760_qtd *qtd;
 866
 867         if (unlikely(list_empty(&qh->qtd_list))) {
 868                 WARN_ON(1);
 869                 return;
 870         }
 871
 872         /* Make sure this endpoint's TT buffer is clean before queueing ptds */
 873         if (qh->tt_buffer_dirty)
 874                 return;
 875
 876         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 877                                                         qtd_list)->urb->pipe)) {
 878                 ptd_offset = INT_PTD_OFFSET;
 879                 slots = priv->int_slots;
 880         } else {
 881                 ptd_offset = ATL_PTD_OFFSET;
 882                 slots = priv->atl_slots;
 883         }
 884
 885         free_slot = -1;
 886         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 887                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 888                         free_slot = curr_slot;
 889                 if (slots[curr_slot].qh == qh)
 890                         break;
 891         }
 892
 893         n = 0;
 894         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 895                 if (qtd->status == QTD_ENQUEUED) {
 896                         WARN_ON(qtd->payload_addr);
 897                         alloc_mem(hcd, qtd);
 898                         if ((qtd->length) && (!qtd->payload_addr))
 899                                 break;
 900
 901                         if ((qtd->length) &&
 902                             ((qtd->packet_type == SETUP_PID) ||
 903                              (qtd->packet_type == OUT_PID))) {
 904                                 mem_writes8(hcd->regs, qtd->payload_addr,
 905                                                 qtd->data_buffer, qtd->length);
 906                         }
 907
 908                         qtd->status = QTD_PAYLOAD_ALLOC;
 909                 }
 910
 911                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 912 /*
 913                         if ((curr_slot > 31) && (free_slot == -1))
 914                                 dev_dbg(hcd->self.controller, "%s: No slot "
 915                                         "available for transfer\n", __func__);
 916 */
 917                         /* Start xfer for this endpoint if not already done */
 918                         if ((curr_slot > 31) && (free_slot > -1)) {
 919                                 if (usb_pipeint(qtd->urb->pipe))
 920                                         create_ptd_int(qh, qtd, &ptd);
 921                                 else
 922                                         create_ptd_atl(qh, qtd, &ptd);
 923
 924                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 925                                                         slots, qtd, qh, &ptd);
 926                                 curr_slot = free_slot;
 927                         }
 928
 929                         n++;
 930                         if (n >= ENQUEUE_DEPTH)
 931                                 break;
 932                 }
 933         }
 934 }
 935
 936 static void schedule_ptds(struct usb_hcd *hcd)
 937 {
 938         struct isp1760_hcd *priv;
 939         struct isp1760_qh *qh, *qh_next;
 940         struct list_head *ep_queue;
 941         LIST_HEAD(urb_list);
 942         struct urb_listitem *urb_listitem, *urb_listitem_next;
 943         int i;
 944
 945         if (!hcd) {
 946                 WARN_ON(1);
 947                 return;
 948         }
 949
 950         priv = hcd_to_priv(hcd);
 951
 952         /*
 953          * check finished/retired xfers, transfer payloads, call urb_done()
 954          */
 955         for (i = 0; i < QH_END; i++) {
 956                 ep_queue = &priv->qh_list[i];
 957                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 958                         collect_qtds(hcd, qh, &urb_list);
 959                         if (list_empty(&qh->qtd_list))
 960                                 list_del(&qh->qh_list);
 961                 }
 962         }
 963
 964         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
 965                                                                 urb_list) {
 966                 isp1760_urb_done(hcd, urb_listitem->urb);
 967                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
 968         }
 969
 970         /*
 971          * Schedule packets for transfer.
 972          *
 973          * According to USB2.0 specification:
 974          *
 975          * 1st prio: interrupt xfers, up to 80 % of bandwidth
 976          * 2nd prio: control xfers
 977          * 3rd prio: bulk xfers
 978          *
 979          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
 980          * is very unclear on how to prioritize traffic):
 981          *
 982          * 1) Enqueue any queued control transfers, as long as payload chip mem
 983          *    and PTD ATL slots are available.
 984          * 2) Enqueue any queued INT transfers, as long as payload chip mem
 985          *    and PTD INT slots are available.
 986          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
 987          *    and PTD ATL slots are available.
 988          *
 989          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
 990          * conservation of chip mem and performance.
 991          *
 992          * I'm sure this scheme could be improved upon!
 993          */
 994         for (i = 0; i < QH_END; i++) {
 995                 ep_queue = &priv->qh_list[i];
 996                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
 997                         enqueue_qtds(hcd, qh);
 998         }
 999 }
1000
1001 #define PTD_STATE_QTD_DONE      1
1002 #define PTD_STATE_QTD_RELOAD    2
1003 #define PTD_STATE_URB_RETIRE    3
1004
1005 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1006                                                                 struct urb *urb)
1007 {
1008         __dw dw4;
1009         int i;
1010
1011         dw4 = ptd->dw4;
1012         dw4 >>= 8;
1013
1014         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1015            need to handle these errors? Is it done in hardware? */
1016
1017         if (ptd->dw3 & DW3_HALT_BIT) {
1018
1019                 urb->status = -EPROTO; /* Default unknown error */
1020
1021                 for (i = 0; i < 8; i++) {
1022                         switch (dw4 & 0x7) {
1023                         case INT_UNDERRUN:
1024                                 dev_dbg(hcd->self.controller, "%s: underrun "
1025                                                 "during uFrame %d\n",
1026                                                 __func__, i);
1027                                 urb->status = -ECOMM; /* Could not write data */
1028                                 break;
1029                         case INT_EXACT:
1030                                 dev_dbg(hcd->self.controller, "%s: transaction "
1031                                                 "error during uFrame %d\n",
1032                                                 __func__, i);
1033                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1034                                                           error etc. */
1035                                 break;
1036                         case INT_BABBLE:
1037                                 dev_dbg(hcd->self.controller, "%s: babble "
1038                                                 "error during uFrame %d\n",
1039                                                 __func__, i);
1040                                 urb->status = -EOVERFLOW;
1041                                 break;
1042                         }
1043                         dw4 >>= 3;
1044                 }
1045
1046                 return PTD_STATE_URB_RETIRE;
1047         }
1048
1049         return PTD_STATE_QTD_DONE;
1050 }
1051
1052 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1053                                                                 struct urb *urb)
1054 {
1055         WARN_ON(!ptd);
1056         if (ptd->dw3 & DW3_HALT_BIT) {
1057                 if (ptd->dw3 & DW3_BABBLE_BIT)
1058                         urb->status = -EOVERFLOW;
1059                 else if (FROM_DW3_CERR(ptd->dw3))
1060                         urb->status = -EPIPE;  /* Stall */
1061                 else if (ptd->dw3 & DW3_ERROR_BIT)
1062                         urb->status = -EPROTO; /* XactErr */
1063                 else
1064                         urb->status = -EPROTO; /* Unknown */
1065 /*
1066                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1067                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1068                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1069                         __func__,
1070                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1071                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1072 */
1073                 return PTD_STATE_URB_RETIRE;
1074         }
1075
1076         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1077                 /* Transfer Error, *but* active and no HALT -> reload */
1078                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1079                 return PTD_STATE_QTD_RELOAD;
1080         }
1081
1082         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1083                 /*
1084                  * NAKs are handled in HW by the chip. Usually if the
1085                  * device is not able to send data fast enough.
1086                  * This happens mostly on slower hardware.
1087                  */
1088                 return PTD_STATE_QTD_RELOAD;
1089         }
1090
1091         return PTD_STATE_QTD_DONE;
1092 }
1093
1094 static void handle_done_ptds(struct usb_hcd *hcd)
1095 {
1096         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1097         struct ptd ptd;
1098         struct isp1760_qh *qh;
1099         int slot;
1100         int state;
1101         struct isp1760_slotinfo *slots;
1102         u32 ptd_offset;
1103         struct isp1760_qtd *qtd;
1104         int modified;
1105         int skip_map;
1106
1107         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1108         priv->int_done_map &= ~skip_map;
1109         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1110         priv->atl_done_map &= ~skip_map;
1111
1112         modified = priv->int_done_map || priv->atl_done_map;
1113
1114         while (priv->int_done_map || priv->atl_done_map) {
1115                 if (priv->int_done_map) {
1116                         /* INT ptd */
1117                         slot = __ffs(priv->int_done_map);
1118                         priv->int_done_map &= ~(1 << slot);
1119                         slots = priv->int_slots;
1120                         /* This should not trigger, and could be removed if
1121                            noone have any problems with it triggering: */
1122                         if (!slots[slot].qh) {
1123                                 WARN_ON(1);
1124                                 continue;
1125                         }
1126                         ptd_offset = INT_PTD_OFFSET;
1127                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1128                         state = check_int_transfer(hcd, &ptd,
1129                                                         slots[slot].qtd->urb);
1130                 } else {
1131                         /* ATL ptd */
1132                         slot = __ffs(priv->atl_done_map);
1133                         priv->atl_done_map &= ~(1 << slot);
1134                         slots = priv->atl_slots;
1135                         /* This should not trigger, and could be removed if
1136                            noone have any problems with it triggering: */
1137                         if (!slots[slot].qh) {
1138                                 WARN_ON(1);
1139                                 continue;
1140                         }
1141                         ptd_offset = ATL_PTD_OFFSET;
1142                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1143                         state = check_atl_transfer(hcd, &ptd,
1144                                                         slots[slot].qtd->urb);
1145                 }
1146
1147                 qtd = slots[slot].qtd;
1148                 slots[slot].qtd = NULL;
1149                 qh = slots[slot].qh;
1150                 slots[slot].qh = NULL;
1151                 qh->slot = -1;
1152
1153                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1154
1155                 switch (state) {
1156                 case PTD_STATE_QTD_DONE:
1157                         if ((usb_pipeint(qtd->urb->pipe)) &&
1158                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1159                                 qtd->actual_length =
1160                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1161                         else
1162                                 qtd->actual_length =
1163                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1164
1165                         qtd->status = QTD_XFER_COMPLETE;
1166                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1167                                                         is_short_bulk(qtd))
1168                                 qtd = NULL;
1169                         else
1170                                 qtd = list_entry(qtd->qtd_list.next,
1171                                                         typeof(*qtd), qtd_list);
1172
1173                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1174                         qh->ping = FROM_DW3_PING(ptd.dw3);
1175                         break;
1176
1177                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1178                         qtd->status = QTD_PAYLOAD_ALLOC;
1179                         ptd.dw0 |= DW0_VALID_BIT;
1180                         /* RL counter = ERR counter */
1181                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1182                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1183                         ptd.dw3 &= ~TO_DW3_CERR(3);
1184                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1185                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1186                         qh->ping = FROM_DW3_PING(ptd.dw3);
1187                         break;
1188
1189                 case PTD_STATE_URB_RETIRE:
1190                         qtd->status = QTD_RETIRE;
1191                         if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1192                                         (qtd->urb->status != -EPIPE) &&
1193                                         (qtd->urb->status != -EREMOTEIO)) {
1194                                 qh->tt_buffer_dirty = 1;
1195                                 if (usb_hub_clear_tt_buffer(qtd->urb))
1196                                         /* Clear failed; let's hope things work
1197                                            anyway */
1198                                         qh->tt_buffer_dirty = 0;
1199                         }
1200                         qtd = NULL;
1201                         qh->toggle = 0;
1202                         qh->ping = 0;
1203                         break;
1204
1205                 default:
1206                         WARN_ON(1);
1207                         continue;
1208                 }
1209
1210                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1211                         if (slots == priv->int_slots) {
1212                                 if (state == PTD_STATE_QTD_RELOAD)
1213                                         dev_err(hcd->self.controller,
1214                                                 "%s: PTD_STATE_QTD_RELOAD on "
1215                                                 "interrupt packet\n", __func__);
1216                                 if (state != PTD_STATE_QTD_RELOAD)
1217                                         create_ptd_int(qh, qtd, &ptd);
1218                         } else {
1219                                 if (state != PTD_STATE_QTD_RELOAD)
1220                                         create_ptd_atl(qh, qtd, &ptd);
1221                         }
1222
1223                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1224                                 qh, &ptd);
1225                 }
1226         }
1227
1228         if (modified)
1229                 schedule_ptds(hcd);
1230 }
1231
1232 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1233 {
1234         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1235         u32 imask;
1236         irqreturn_t irqret = IRQ_NONE;
1237
1238         spin_lock(&priv->lock);
1239
1240         if (!(hcd->state & HC_STATE_RUNNING))
1241                 goto leave;
1242
1243         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1244         if (unlikely(!imask))
1245                 goto leave;
1246         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1247
1248         priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1249         priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1250
1251         handle_done_ptds(hcd);
1252
1253         irqret = IRQ_HANDLED;
1254 leave:
1255         spin_unlock(&priv->lock);
1256
1257         return irqret;
1258 }
1259
1260 /*
1261  * Workaround for problem described in chip errata 2:
1262  *
1263  * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1264  * One solution suggested in the errata is to use SOF interrupts _instead_of_
1265  * ATL done interrupts (the "instead of" might be important since it seems
1266  * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1267  * to set the PTD's done bit in addition to not generating an interrupt!).
1268  *
1269  * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1270  * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1271  *
1272  * If we use SOF interrupts only, we get latency between ptd completion and the
1273  * actual handling. This is very noticeable in testusb runs which takes several
1274  * minutes longer without ATL interrupts.
1275  *
1276  * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1277  * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1278  * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1279  * completed and its done map bit is set.
1280  *
1281  * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1282  * not to cause too much lag when this HW bug occurs, while still hopefully
1283  * ensuring that the check does not falsely trigger.
1284  */
1285 #define SLOT_TIMEOUT 300
1286 #define SLOT_CHECK_PERIOD 200
1287 static struct timer_list errata2_timer;
1288
1289 static void errata2_function(unsigned long data)
1290 {
1291         struct usb_hcd *hcd = (struct usb_hcd *) data;
1292         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1293         int slot;
1294         struct ptd ptd;
1295         unsigned long spinflags;
1296
1297         spin_lock_irqsave(&priv->lock, spinflags);
1298
1299         for (slot = 0; slot < 32; slot++)
1300                 if (priv->atl_slots[slot].qh && time_after(jiffies,
1301                                         priv->atl_slots[slot].timestamp +
1302                                         SLOT_TIMEOUT * HZ / 1000)) {
1303                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1304                         if (!FROM_DW0_VALID(ptd.dw0) &&
1305                                         !FROM_DW3_ACTIVE(ptd.dw3))
1306                                 priv->atl_done_map |= 1 << slot;
1307                 }
1308
1309         if (priv->atl_done_map)
1310                 handle_done_ptds(hcd);
1311
1312         spin_unlock_irqrestore(&priv->lock, spinflags);
1313
1314         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1315         add_timer(&errata2_timer);
1316 }
1317
1318 static int isp1760_run(struct usb_hcd *hcd)
1319 {
1320         int retval;
1321         u32 temp;
1322         u32 command;
1323         u32 chipid;
1324
1325         hcd->uses_new_polling = 1;
1326
1327         hcd->state = HC_STATE_RUNNING;
1328
1329         /* Set PTD interrupt AND & OR maps */
1330         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1331         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1332         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1333         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1334         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1335         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1336         /* step 23 passed */
1337
1338         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1339         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1340
1341         command = reg_read32(hcd->regs, HC_USBCMD);
1342         command &= ~(CMD_LRESET|CMD_RESET);
1343         command |= CMD_RUN;
1344         reg_write32(hcd->regs, HC_USBCMD, command);
1345
1346         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1347         if (retval)
1348                 return retval;
1349
1350         /*
1351          * XXX
1352          * Spec says to write FLAG_CF as last config action, priv code grabs
1353          * the semaphore while doing so.
1354          */
1355         down_write(&ehci_cf_port_reset_rwsem);
1356         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1357
1358         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1359         up_write(&ehci_cf_port_reset_rwsem);
1360         if (retval)
1361                 return retval;
1362
1363         init_timer(&errata2_timer);
1364         errata2_timer.function = errata2_function;
1365         errata2_timer.data = (unsigned long) hcd;
1366         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1367         add_timer(&errata2_timer);
1368
1369         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1370         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1371                                         chipid & 0xffff, chipid >> 16);
1372
1373         /* PTD Register Init Part 2, Step 28 */
1374
1375         /* Setup registers controlling PTD checking */
1376         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1377         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1378         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1379         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1380         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1381         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1382         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1383                                                 ATL_BUF_FILL | INT_BUF_FILL);
1384
1385         /* GRR this is run-once init(), being done every time the HC starts.
1386          * So long as they're part of class devices, we can't do it init()
1387          * since the class device isn't created that early.
1388          */
1389         return 0;
1390 }
1391
1392 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1393 {
1394         qtd->data_buffer = databuffer;
1395
1396         if (len > MAX_PAYLOAD_SIZE)
1397                 len = MAX_PAYLOAD_SIZE;
1398         qtd->length = len;
1399
1400         return qtd->length;
1401 }
1402
1403 static void qtd_list_free(struct list_head *qtd_list)
1404 {
1405         struct isp1760_qtd *qtd, *qtd_next;
1406
1407         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1408                 list_del(&qtd->qtd_list);
1409                 qtd_free(qtd);
1410         }
1411 }
1412
1413 /*
1414  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1415  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1416  */
1417 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1418 static void packetize_urb(struct usb_hcd *hcd,
1419                 struct urb *urb, struct list_head *head, gfp_t flags)
1420 {
1421         struct isp1760_qtd *qtd;
1422         void *buf;
1423         int len, maxpacketsize;
1424         u8 packet_type;
1425
1426         /*
1427          * URBs map to sequences of QTDs:  one logical transaction
1428          */
1429
1430         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1431                 /* XXX This looks like usb storage / SCSI bug */
1432                 dev_err(hcd->self.controller,
1433                                 "buf is null, dma is %08lx len is %d\n",
1434                                 (long unsigned)urb->transfer_dma,
1435                                 urb->transfer_buffer_length);
1436                 WARN_ON(1);
1437         }
1438
1439         if (usb_pipein(urb->pipe))
1440                 packet_type = IN_PID;
1441         else
1442                 packet_type = OUT_PID;
1443
1444         if (usb_pipecontrol(urb->pipe)) {
1445                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1446                 if (!qtd)
1447                         goto cleanup;
1448                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1449                 list_add_tail(&qtd->qtd_list, head);
1450
1451                 /* for zero length DATA stages, STATUS is always IN */
1452                 if (urb->transfer_buffer_length == 0)
1453                         packet_type = IN_PID;
1454         }
1455
1456         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1457                                                 usb_pipeout(urb->pipe)));
1458
1459         /*
1460          * buffer gets wrapped in one or more qtds;
1461          * last one may be "short" (including zero len)
1462          * and may serve as a control status ack
1463          */
1464         buf = urb->transfer_buffer;
1465         len = urb->transfer_buffer_length;
1466
1467         for (;;) {
1468                 int this_qtd_len;
1469
1470                 qtd = qtd_alloc(flags, urb, packet_type);
1471                 if (!qtd)
1472                         goto cleanup;
1473                 this_qtd_len = qtd_fill(qtd, buf, len);
1474                 list_add_tail(&qtd->qtd_list, head);
1475
1476                 len -= this_qtd_len;
1477                 buf += this_qtd_len;
1478
1479                 if (len <= 0)
1480                         break;
1481         }
1482
1483         /*
1484          * control requests may need a terminating data "status" ack;
1485          * bulk ones may need a terminating short packet (zero length).
1486          */
1487         if (urb->transfer_buffer_length != 0) {
1488                 int one_more = 0;
1489
1490                 if (usb_pipecontrol(urb->pipe)) {
1491                         one_more = 1;
1492                         if (packet_type == IN_PID)
1493                                 packet_type = OUT_PID;
1494                         else
1495                                 packet_type = IN_PID;
1496                 } else if (usb_pipebulk(urb->pipe)
1497                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1498                                 && !(urb->transfer_buffer_length %
1499                                                         maxpacketsize)) {
1500                         one_more = 1;
1501                 }
1502                 if (one_more) {
1503                         qtd = qtd_alloc(flags, urb, packet_type);
1504                         if (!qtd)
1505                                 goto cleanup;
1506
1507                         /* never any data in such packets */
1508                         qtd_fill(qtd, NULL, 0);
1509                         list_add_tail(&qtd->qtd_list, head);
1510                 }
1511         }
1512
1513         return;
1514
1515 cleanup:
1516         qtd_list_free(head);
1517 }
1518
1519 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1520                 gfp_t mem_flags)
1521 {
1522         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1523         struct list_head *ep_queue;
1524         struct isp1760_qh *qh, *qhit;
1525         unsigned long spinflags;
1526         LIST_HEAD(new_qtds);
1527         int retval;
1528         int qh_in_queue;
1529
1530         switch (usb_pipetype(urb->pipe)) {
1531         case PIPE_CONTROL:
1532                 ep_queue = &priv->qh_list[QH_CONTROL];
1533                 break;
1534         case PIPE_BULK:
1535                 ep_queue = &priv->qh_list[QH_BULK];
1536                 break;
1537         case PIPE_INTERRUPT:
1538                 if (urb->interval < 0)
1539                         return -EINVAL;
1540                 /* FIXME: Check bandwidth  */
1541                 ep_queue = &priv->qh_list[QH_INTERRUPT];
1542                 break;
1543         case PIPE_ISOCHRONOUS:
1544                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1545                                                         "not yet supported\n",
1546                                                         __func__);
1547                 return -EPIPE;
1548         default:
1549                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1550                                                         __func__);
1551                 return -EPIPE;
1552         }
1553
1554         if (usb_pipein(urb->pipe))
1555                 urb->actual_length = 0;
1556
1557         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1558         if (list_empty(&new_qtds))
1559                 return -ENOMEM;
1560
1561         retval = 0;
1562         spin_lock_irqsave(&priv->lock, spinflags);
1563
1564         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1565                 retval = -ESHUTDOWN;
1566                 qtd_list_free(&new_qtds);
1567                 goto out;
1568         }
1569         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1570         if (retval) {
1571                 qtd_list_free(&new_qtds);
1572                 goto out;
1573         }
1574
1575         qh = urb->ep->hcpriv;
1576         if (qh) {
1577                 qh_in_queue = 0;
1578                 list_for_each_entry(qhit, ep_queue, qh_list) {
1579                         if (qhit == qh) {
1580                                 qh_in_queue = 1;
1581                                 break;
1582                         }
1583                 }
1584                 if (!qh_in_queue)
1585                         list_add_tail(&qh->qh_list, ep_queue);
1586         } else {
1587                 qh = qh_alloc(GFP_ATOMIC);
1588                 if (!qh) {
1589                         retval = -ENOMEM;
1590                         usb_hcd_unlink_urb_from_ep(hcd, urb);
1591                         qtd_list_free(&new_qtds);
1592                         goto out;
1593                 }
1594                 list_add_tail(&qh->qh_list, ep_queue);
1595                 urb->ep->hcpriv = qh;
1596         }
1597
1598         list_splice_tail(&new_qtds, &qh->qtd_list);
1599         schedule_ptds(hcd);
1600
1601 out:
1602         spin_unlock_irqrestore(&priv->lock, spinflags);
1603         return retval;
1604 }
1605
1606 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1607                 struct isp1760_qh *qh)
1608 {
1609         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1610         int skip_map;
1611
1612         WARN_ON(qh->slot == -1);
1613
1614         /* We need to forcefully reclaim the slot since some transfers never
1615            return, e.g. interrupt transfers and NAKed bulk transfers. */
1616         if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1617                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1618                 skip_map |= (1 << qh->slot);
1619                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1620                 priv->atl_slots[qh->slot].qh = NULL;
1621                 priv->atl_slots[qh->slot].qtd = NULL;
1622         } else {
1623                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1624                 skip_map |= (1 << qh->slot);
1625                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1626                 priv->int_slots[qh->slot].qh = NULL;
1627                 priv->int_slots[qh->slot].qtd = NULL;
1628         }
1629
1630         qh->slot = -1;
1631 }
1632
1633 /*
1634  * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1635  * any active transfer belonging to the urb in the process.
1636  */
1637 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1638                                                 struct isp1760_qtd *qtd)
1639 {
1640         struct urb *urb;
1641         int urb_was_running;
1642
1643         urb = qtd->urb;
1644         urb_was_running = 0;
1645         list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1646                 if (qtd->urb != urb)
1647                         break;
1648
1649                 if (qtd->status >= QTD_XFER_STARTED)
1650                         urb_was_running = 1;
1651                 if (last_qtd_of_urb(qtd, qh) &&
1652                                         (qtd->status >= QTD_XFER_COMPLETE))
1653                         urb_was_running = 0;
1654
1655                 if (qtd->status == QTD_XFER_STARTED)
1656                         kill_transfer(hcd, urb, qh);
1657                 qtd->status = QTD_RETIRE;
1658         }
1659
1660         if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1661                 qh->tt_buffer_dirty = 1;
1662                 if (usb_hub_clear_tt_buffer(urb))
1663                         /* Clear failed; let's hope things work anyway */
1664                         qh->tt_buffer_dirty = 0;
1665         }
1666 }
1667
1668 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1669                 int status)
1670 {
1671         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1672         unsigned long spinflags;
1673         struct isp1760_qh *qh;
1674         struct isp1760_qtd *qtd;
1675         int retval = 0;
1676
1677         spin_lock_irqsave(&priv->lock, spinflags);
1678         retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1679         if (retval)
1680                 goto out;
1681
1682         qh = urb->ep->hcpriv;
1683         if (!qh) {
1684                 retval = -EINVAL;
1685                 goto out;
1686         }
1687
1688         list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1689                 if (qtd->urb == urb) {
1690                         dequeue_urb_from_qtd(hcd, qh, qtd);
1691                         list_move(&qtd->qtd_list, &qh->qtd_list);
1692                         break;
1693                 }
1694
1695         urb->status = status;
1696         schedule_ptds(hcd);
1697
1698 out:
1699         spin_unlock_irqrestore(&priv->lock, spinflags);
1700         return retval;
1701 }
1702
1703 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1704                 struct usb_host_endpoint *ep)
1705 {
1706         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1707         unsigned long spinflags;
1708         struct isp1760_qh *qh, *qh_iter;
1709         int i;
1710
1711         spin_lock_irqsave(&priv->lock, spinflags);
1712
1713         qh = ep->hcpriv;
1714         if (!qh)
1715                 goto out;
1716
1717         WARN_ON(!list_empty(&qh->qtd_list));
1718
1719         for (i = 0; i < QH_END; i++)
1720                 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1721                         if (qh_iter == qh) {
1722                                 list_del(&qh_iter->qh_list);
1723                                 i = QH_END;
1724                                 break;
1725                         }
1726         qh_free(qh);
1727         ep->hcpriv = NULL;
1728
1729         schedule_ptds(hcd);
1730
1731 out:
1732         spin_unlock_irqrestore(&priv->lock, spinflags);
1733 }
1734
1735 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1736 {
1737         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1738         u32 temp, status = 0;
1739         u32 mask;
1740         int retval = 1;
1741         unsigned long flags;
1742
1743         /* if !PM, root hub timers won't get shut down ... */
1744         if (!HC_IS_RUNNING(hcd->state))
1745                 return 0;
1746
1747         /* init status to no-changes */
1748         buf[0] = 0;
1749         mask = PORT_CSC;
1750
1751         spin_lock_irqsave(&priv->lock, flags);
1752         temp = reg_read32(hcd->regs, HC_PORTSC1);
1753
1754         if (temp & PORT_OWNER) {
1755                 if (temp & PORT_CSC) {
1756                         temp &= ~PORT_CSC;
1757                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1758                         goto done;
1759                 }
1760         }
1761
1762         /*
1763          * Return status information even for ports with OWNER set.
1764          * Otherwise hub_wq wouldn't see the disconnect event when a
1765          * high-speed device is switched over to the companion
1766          * controller by the user.
1767          */
1768
1769         if ((temp & mask) != 0
1770                         || ((temp & PORT_RESUME) != 0
1771                                 && time_after_eq(jiffies,
1772                                         priv->reset_done))) {
1773                 buf [0] |= 1 << (0 + 1);
1774                 status = STS_PCD;
1775         }
1776         /* FIXME autosuspend idle root hubs */
1777 done:
1778         spin_unlock_irqrestore(&priv->lock, flags);
1779         return status ? retval : 0;
1780 }
1781
1782 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1783                 struct usb_hub_descriptor *desc)
1784 {
1785         int ports = HCS_N_PORTS(priv->hcs_params);
1786         u16 temp;
1787
1788         desc->bDescriptorType = 0x29;
1789         /* priv 1.0, 2.3.9 says 20ms max */
1790         desc->bPwrOn2PwrGood = 10;
1791         desc->bHubContrCurrent = 0;
1792
1793         desc->bNbrPorts = ports;
1794         temp = 1 + (ports / 8);
1795         desc->bDescLength = 7 + 2 * temp;
1796
1797         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1798         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1799         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1800
1801         /* per-port overcurrent reporting */
1802         temp = 0x0008;
1803         if (HCS_PPC(priv->hcs_params))
1804                 /* per-port power control */
1805                 temp |= 0x0001;
1806         else
1807                 /* no power switching */
1808                 temp |= 0x0002;
1809         desc->wHubCharacteristics = cpu_to_le16(temp);
1810 }
1811
1812 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1813
1814 static int check_reset_complete(struct usb_hcd *hcd, int index,
1815                 int port_status)
1816 {
1817         if (!(port_status & PORT_CONNECT))
1818                 return port_status;
1819
1820         /* if reset finished and it's still not enabled -- handoff */
1821         if (!(port_status & PORT_PE)) {
1822
1823                 dev_info(hcd->self.controller,
1824                                         "port %d full speed --> companion\n",
1825                                         index + 1);
1826
1827                 port_status |= PORT_OWNER;
1828                 port_status &= ~PORT_RWC_BITS;
1829                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1830
1831         } else
1832                 dev_info(hcd->self.controller, "port %d high speed\n",
1833                                                                 index + 1);
1834
1835         return port_status;
1836 }
1837
1838 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1839                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1840 {
1841         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1842         int ports = HCS_N_PORTS(priv->hcs_params);
1843         u32 temp, status;
1844         unsigned long flags;
1845         int retval = 0;
1846         unsigned selector;
1847
1848         /*
1849          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1850          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1851          * (track current state ourselves) ... blink for diagnostics,
1852          * power, "this is the one", etc.  EHCI spec supports this.
1853          */
1854
1855         spin_lock_irqsave(&priv->lock, flags);
1856         switch (typeReq) {
1857         case ClearHubFeature:
1858                 switch (wValue) {
1859                 case C_HUB_LOCAL_POWER:
1860                 case C_HUB_OVER_CURRENT:
1861                         /* no hub-wide feature/status flags */
1862                         break;
1863                 default:
1864                         goto error;
1865                 }
1866                 break;
1867         case ClearPortFeature:
1868                 if (!wIndex || wIndex > ports)
1869                         goto error;
1870                 wIndex--;
1871                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1872
1873                 /*
1874                  * Even if OWNER is set, so the port is owned by the
1875                  * companion controller, hub_wq needs to be able to clear
1876                  * the port-change status bits (especially
1877                  * USB_PORT_STAT_C_CONNECTION).
1878                  */
1879
1880                 switch (wValue) {
1881                 case USB_PORT_FEAT_ENABLE:
1882                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1883                         break;
1884                 case USB_PORT_FEAT_C_ENABLE:
1885                         /* XXX error? */
1886                         break;
1887                 case USB_PORT_FEAT_SUSPEND:
1888                         if (temp & PORT_RESET)
1889                                 goto error;
1890
1891                         if (temp & PORT_SUSPEND) {
1892                                 if ((temp & PORT_PE) == 0)
1893                                         goto error;
1894                                 /* resume signaling for 20 msec */
1895                                 temp &= ~(PORT_RWC_BITS);
1896                                 reg_write32(hcd->regs, HC_PORTSC1,
1897                                                         temp | PORT_RESUME);
1898                                 priv->reset_done = jiffies +
1899                                         msecs_to_jiffies(20);
1900                         }
1901                         break;
1902                 case USB_PORT_FEAT_C_SUSPEND:
1903                         /* we auto-clear this feature */
1904                         break;
1905                 case USB_PORT_FEAT_POWER:
1906                         if (HCS_PPC(priv->hcs_params))
1907                                 reg_write32(hcd->regs, HC_PORTSC1,
1908                                                         temp & ~PORT_POWER);
1909                         break;
1910                 case USB_PORT_FEAT_C_CONNECTION:
1911                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1912                         break;
1913                 case USB_PORT_FEAT_C_OVER_CURRENT:
1914                         /* XXX error ?*/
1915                         break;
1916                 case USB_PORT_FEAT_C_RESET:
1917                         /* GetPortStatus clears reset */
1918                         break;
1919                 default:
1920                         goto error;
1921                 }
1922                 reg_read32(hcd->regs, HC_USBCMD);
1923                 break;
1924         case GetHubDescriptor:
1925                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1926                         buf);
1927                 break;
1928         case GetHubStatus:
1929                 /* no hub-wide feature/status flags */
1930                 memset(buf, 0, 4);
1931                 break;
1932         case GetPortStatus:
1933                 if (!wIndex || wIndex > ports)
1934                         goto error;
1935                 wIndex--;
1936                 status = 0;
1937                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1938
1939                 /* wPortChange bits */
1940                 if (temp & PORT_CSC)
1941                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1942
1943
1944                 /* whoever resumes must GetPortStatus to complete it!! */
1945                 if (temp & PORT_RESUME) {
1946                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1947
1948                         /* Remote Wakeup received? */
1949                         if (!priv->reset_done) {
1950                                 /* resume signaling for 20 msec */
1951                                 priv->reset_done = jiffies
1952                                                 + msecs_to_jiffies(20);
1953                                 /* check the port again */
1954                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1955                         }
1956
1957                         /* resume completed? */
1958                         else if (time_after_eq(jiffies,
1959                                         priv->reset_done)) {
1960                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1961                                 priv->reset_done = 0;
1962
1963                                 /* stop resume signaling */
1964                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1965                                 reg_write32(hcd->regs, HC_PORTSC1,
1966                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1967                                 retval = handshake(hcd, HC_PORTSC1,
1968                                            PORT_RESUME, 0, 2000 /* 2msec */);
1969                                 if (retval != 0) {
1970                                         dev_err(hcd->self.controller,
1971                                                 "port %d resume error %d\n",
1972                                                 wIndex + 1, retval);
1973                                         goto error;
1974                                 }
1975                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1976                         }
1977                 }
1978
1979                 /* whoever resets must GetPortStatus to complete it!! */
1980                 if ((temp & PORT_RESET)
1981                                 && time_after_eq(jiffies,
1982                                         priv->reset_done)) {
1983                         status |= USB_PORT_STAT_C_RESET << 16;
1984                         priv->reset_done = 0;
1985
1986                         /* force reset to complete */
1987                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1988                         /* REVISIT:  some hardware needs 550+ usec to clear
1989                          * this bit; seems too long to spin routinely...
1990                          */
1991                         retval = handshake(hcd, HC_PORTSC1,
1992                                         PORT_RESET, 0, 750);
1993                         if (retval != 0) {
1994                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1995                                                 wIndex + 1, retval);
1996                                 goto error;
1997                         }
1998
1999                         /* see what we found out */
2000                         temp = check_reset_complete(hcd, wIndex,
2001                                         reg_read32(hcd->regs, HC_PORTSC1));
2002                 }
2003                 /*
2004                  * Even if OWNER is set, there's no harm letting hub_wq
2005                  * see the wPortStatus values (they should all be 0 except
2006                  * for PORT_POWER anyway).
2007                  */
2008
2009                 if (temp & PORT_OWNER)
2010                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2011
2012                 if (temp & PORT_CONNECT) {
2013                         status |= USB_PORT_STAT_CONNECTION;
2014                         /* status may be from integrated TT */
2015                         status |= USB_PORT_STAT_HIGH_SPEED;
2016                 }
2017                 if (temp & PORT_PE)
2018                         status |= USB_PORT_STAT_ENABLE;
2019                 if (temp & (PORT_SUSPEND|PORT_RESUME))
2020                         status |= USB_PORT_STAT_SUSPEND;
2021                 if (temp & PORT_RESET)
2022                         status |= USB_PORT_STAT_RESET;
2023                 if (temp & PORT_POWER)
2024                         status |= USB_PORT_STAT_POWER;
2025
2026                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2027                 break;
2028         case SetHubFeature:
2029                 switch (wValue) {
2030                 case C_HUB_LOCAL_POWER:
2031                 case C_HUB_OVER_CURRENT:
2032                         /* no hub-wide feature/status flags */
2033                         break;
2034                 default:
2035                         goto error;
2036                 }
2037                 break;
2038         case SetPortFeature:
2039                 selector = wIndex >> 8;
2040                 wIndex &= 0xff;
2041                 if (!wIndex || wIndex > ports)
2042                         goto error;
2043                 wIndex--;
2044                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2045                 if (temp & PORT_OWNER)
2046                         break;
2047
2048 /*              temp &= ~PORT_RWC_BITS; */
2049                 switch (wValue) {
2050                 case USB_PORT_FEAT_ENABLE:
2051                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2052                         break;
2053
2054                 case USB_PORT_FEAT_SUSPEND:
2055                         if ((temp & PORT_PE) == 0
2056                                         || (temp & PORT_RESET) != 0)
2057                                 goto error;
2058
2059                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2060                         break;
2061                 case USB_PORT_FEAT_POWER:
2062                         if (HCS_PPC(priv->hcs_params))
2063                                 reg_write32(hcd->regs, HC_PORTSC1,
2064                                                         temp | PORT_POWER);
2065                         break;
2066                 case USB_PORT_FEAT_RESET:
2067                         if (temp & PORT_RESUME)
2068                                 goto error;
2069                         /* line status bits may report this as low speed,
2070                          * which can be fine if this root hub has a
2071                          * transaction translator built in.
2072                          */
2073                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2074                                         && PORT_USB11(temp)) {
2075                                 temp |= PORT_OWNER;
2076                         } else {
2077                                 temp |= PORT_RESET;
2078                                 temp &= ~PORT_PE;
2079
2080                                 /*
2081                                  * caller must wait, then call GetPortStatus
2082                                  * usb 2.0 spec says 50 ms resets on root
2083                                  */
2084                                 priv->reset_done = jiffies +
2085                                         msecs_to_jiffies(50);
2086                         }
2087                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2088                         break;
2089                 default:
2090                         goto error;
2091                 }
2092                 reg_read32(hcd->regs, HC_USBCMD);
2093                 break;
2094
2095         default:
2096 error:
2097                 /* "stall" on error */
2098                 retval = -EPIPE;
2099         }
2100         spin_unlock_irqrestore(&priv->lock, flags);
2101         return retval;
2102 }
2103
2104 static int isp1760_get_frame(struct usb_hcd *hcd)
2105 {
2106         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2107         u32 fr;
2108
2109         fr = reg_read32(hcd->regs, HC_FRINDEX);
2110         return (fr >> 3) % priv->periodic_size;
2111 }
2112
2113 static void isp1760_stop(struct usb_hcd *hcd)
2114 {
2115         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2116         u32 temp;
2117
2118         del_timer(&errata2_timer);
2119
2120         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2121                         NULL, 0);
2122         mdelay(20);
2123
2124         spin_lock_irq(&priv->lock);
2125         ehci_reset(hcd);
2126         /* Disable IRQ */
2127         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2128         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2129         spin_unlock_irq(&priv->lock);
2130
2131         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2132 }
2133
2134 static void isp1760_shutdown(struct usb_hcd *hcd)
2135 {
2136         u32 command, temp;
2137
2138         isp1760_stop(hcd);
2139         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2140         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2141
2142         command = reg_read32(hcd->regs, HC_USBCMD);
2143         command &= ~CMD_RUN;
2144         reg_write32(hcd->regs, HC_USBCMD, command);
2145 }
2146
2147 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2148                                                 struct usb_host_endpoint *ep)
2149 {
2150         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2151         struct isp1760_qh *qh = ep->hcpriv;
2152         unsigned long spinflags;
2153
2154         if (!qh)
2155                 return;
2156
2157         spin_lock_irqsave(&priv->lock, spinflags);
2158         qh->tt_buffer_dirty = 0;
2159         schedule_ptds(hcd);
2160         spin_unlock_irqrestore(&priv->lock, spinflags);
2161 }
2162
2163
2164 static const struct hc_driver isp1760_hc_driver = {
2165         .description            = "isp1760-hcd",
2166         .product_desc           = "NXP ISP1760 USB Host Controller",
2167         .hcd_priv_size          = sizeof(struct isp1760_hcd *),
2168         .irq                    = isp1760_irq,
2169         .flags                  = HCD_MEMORY | HCD_USB2,
2170         .reset                  = isp1760_hc_setup,
2171         .start                  = isp1760_run,
2172         .stop                   = isp1760_stop,
2173         .shutdown               = isp1760_shutdown,
2174         .urb_enqueue            = isp1760_urb_enqueue,
2175         .urb_dequeue            = isp1760_urb_dequeue,
2176         .endpoint_disable       = isp1760_endpoint_disable,
2177         .get_frame_number       = isp1760_get_frame,
2178         .hub_status_data        = isp1760_hub_status_data,
2179         .hub_control            = isp1760_hub_control,
2180         .clear_tt_buffer_complete       = isp1760_clear_tt_buffer_complete,
2181 };
2182
2183 int __init isp1760_init_kmem_once(void)
2184 {
2185         urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2186                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2187                         SLAB_MEM_SPREAD, NULL);
2188
2189         if (!urb_listitem_cachep)
2190                 return -ENOMEM;
2191
2192         qtd_cachep = kmem_cache_create("isp1760_qtd",
2193                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2194                         SLAB_MEM_SPREAD, NULL);
2195
2196         if (!qtd_cachep)
2197                 return -ENOMEM;
2198
2199         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2200                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2201
2202         if (!qh_cachep) {
2203                 kmem_cache_destroy(qtd_cachep);
2204                 return -ENOMEM;
2205         }
2206
2207         return 0;
2208 }
2209
2210 void isp1760_deinit_kmem_cache(void)
2211 {
2212         kmem_cache_destroy(qtd_cachep);
2213         kmem_cache_destroy(qh_cachep);
2214         kmem_cache_destroy(urb_listitem_cachep);
2215 }
2216
2217 int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
2218                      struct device *dev, unsigned int devflags)
2219 {
2220         struct usb_hcd *hcd = NULL;
2221         struct isp1760_hcd *priv;
2222         int ret;
2223
2224         if (usb_disabled())
2225                 return -ENODEV;
2226
2227         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2228         if (!priv)
2229                 return -ENOMEM;
2230
2231         /* prevent usb-core allocating DMA pages */
2232         dev->dma_mask = NULL;
2233
2234         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2235         if (!hcd)
2236                 return -ENOMEM;
2237
2238         priv->hcd = hcd;
2239         *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2240
2241         priv->devflags = devflags;
2242
2243         priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
2244         if (IS_ERR(priv->rst_gpio)) {
2245                 ret = PTR_ERR(priv->rst_gpio);
2246                 goto error;
2247         }
2248
2249         init_memory(priv);
2250         hcd->regs = devm_ioremap_resource(dev, mem);
2251         if (IS_ERR(hcd->regs)) {
2252                 ret = PTR_ERR(hcd->regs);
2253                 goto error;
2254         }
2255
2256         hcd->irq = irq;
2257         hcd->rsrc_start = mem->start;
2258         hcd->rsrc_len = resource_size(mem);
2259
2260         ret = usb_add_hcd(hcd, irq, irqflags);
2261         if (ret)
2262                 goto error;
2263         device_wakeup_enable(hcd->self.controller);
2264
2265         dev_set_drvdata(dev, priv);
2266
2267         return 0;
2268
2269 error:
2270         usb_put_hcd(hcd);
2271         return ret;
2272 }
2273
2274 void isp1760_unregister(struct device *dev)
2275 {
2276         struct isp1760_hcd *priv = dev_get_drvdata(dev);
2277         struct usb_hcd *hcd = priv->hcd;
2278
2279         usb_remove_hcd(hcd);
2280         usb_put_hcd(hcd);
2281 }
2282
2283 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2284 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2285 MODULE_LICENSE("GPL v2");