drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  12  *
  13  */
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/list.h>
  19 #include <linux/usb.h>
  20 #include <linux/usb/hcd.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/timer.h>
  26 #include <asm/unaligned.h>
  27 #include <asm/cacheflush.h>
  28
  29 #include "isp1760-core.h"
  30 #include "isp1760-hcd.h"
  31 #include "isp1760-regs.h"
  32
  33 static struct kmem_cache *qtd_cachep;
  34 static struct kmem_cache *qh_cachep;
  35 static struct kmem_cache *urb_listitem_cachep;
  36
  37 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
  38                 struct isp1760_qtd *qtd);
  39
  40 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  41 {
  42         return *(struct isp1760_hcd **)hcd->hcd_priv;
  43 }
  44
  45 /* urb state*/
  46 #define DELETE_URB              (0x0008)
  47 #define NO_TRANSFER_ACTIVE      (0xffffffff)
  48
  49 /* Philips Proprietary Transfer Descriptor (PTD) */
  50 typedef __u32 __bitwise __dw;
  51 struct ptd {
  52         __dw dw0;
  53         __dw dw1;
  54         __dw dw2;
  55         __dw dw3;
  56         __dw dw4;
  57         __dw dw5;
  58         __dw dw6;
  59         __dw dw7;
  60 };
  61 #define PTD_OFFSET              0x0400
  62 #define ISO_PTD_OFFSET          0x0400
  63 #define INT_PTD_OFFSET          0x0800
  64 #define ATL_PTD_OFFSET          0x0c00
  65 #define PAYLOAD_OFFSET          0x1000
  66
  67
  68 /* ATL */
  69 /* DW0 */
  70 #define DW0_VALID_BIT                   1
  71 #define FROM_DW0_VALID(x)               ((x) & 0x01)
  72 #define TO_DW0_LENGTH(x)                (((u32) x) << 3)
  73 #define TO_DW0_MAXPACKET(x)             (((u32) x) << 18)
  74 #define TO_DW0_MULTI(x)                 (((u32) x) << 29)
  75 #define TO_DW0_ENDPOINT(x)              (((u32) x) << 31)
  76 /* DW1 */
  77 #define TO_DW1_DEVICE_ADDR(x)           (((u32) x) << 3)
  78 #define TO_DW1_PID_TOKEN(x)             (((u32) x) << 10)
  79 #define DW1_TRANS_BULK                  ((u32) 2 << 12)
  80 #define DW1_TRANS_INT                   ((u32) 3 << 12)
  81 #define DW1_TRANS_SPLIT                 ((u32) 1 << 14)
  82 #define DW1_SE_USB_LOSPEED              ((u32) 2 << 16)
  83 #define TO_DW1_PORT_NUM(x)              (((u32) x) << 18)
  84 #define TO_DW1_HUB_NUM(x)               (((u32) x) << 25)
  85 /* DW2 */
  86 #define TO_DW2_DATA_START_ADDR(x)       (((u32) x) << 8)
  87 #define TO_DW2_RL(x)                    ((x) << 25)
  88 #define FROM_DW2_RL(x)                  (((x) >> 25) & 0xf)
  89 /* DW3 */
  90 #define FROM_DW3_NRBYTESTRANSFERRED(x)          ((x) & 0x7fff)
  91 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x)      ((x) & 0x07ff)
  92 #define TO_DW3_NAKCOUNT(x)              ((x) << 19)
  93 #define FROM_DW3_NAKCOUNT(x)            (((x) >> 19) & 0xf)
  94 #define TO_DW3_CERR(x)                  ((x) << 23)
  95 #define FROM_DW3_CERR(x)                (((x) >> 23) & 0x3)
  96 #define TO_DW3_DATA_TOGGLE(x)           ((x) << 25)
  97 #define FROM_DW3_DATA_TOGGLE(x)         (((x) >> 25) & 0x1)
  98 #define TO_DW3_PING(x)                  ((x) << 26)
  99 #define FROM_DW3_PING(x)                (((x) >> 26) & 0x1)
 100 #define DW3_ERROR_BIT                   (1 << 28)
 101 #define DW3_BABBLE_BIT                  (1 << 29)
 102 #define DW3_HALT_BIT                    (1 << 30)
 103 #define DW3_ACTIVE_BIT                  (1 << 31)
 104 #define FROM_DW3_ACTIVE(x)              (((x) >> 31) & 0x01)
 105
 106 #define INT_UNDERRUN                    (1 << 2)
 107 #define INT_BABBLE                      (1 << 1)
 108 #define INT_EXACT                       (1 << 0)
 109
 110 #define SETUP_PID       (2)
 111 #define IN_PID          (1)
 112 #define OUT_PID         (0)
 113
 114 /* Errata 1 */
 115 #define RL_COUNTER      (0)
 116 #define NAK_COUNTER     (0)
 117 #define ERR_COUNTER     (2)
 118
 119 struct isp1760_qtd {
 120         u8 packet_type;
 121         void *data_buffer;
 122         u32 payload_addr;
 123
 124         /* the rest is HCD-private */
 125         struct list_head qtd_list;
 126         struct urb *urb;
 127         size_t length;
 128         size_t actual_length;
 129
 130         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
 131         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
 132         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
 133                                 interrupt handler may touch this qtd! */
 134         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
 135         /* QTD_RETIRE:          transfer error/abort qtd */
 136 #define QTD_ENQUEUED            0
 137 #define QTD_PAYLOAD_ALLOC       1
 138 #define QTD_XFER_STARTED        2
 139 #define QTD_XFER_COMPLETE       3
 140 #define QTD_RETIRE              4
 141         u32 status;
 142 };
 143
 144 /* Queue head, one for each active endpoint */
 145 struct isp1760_qh {
 146         struct list_head qh_list;
 147         struct list_head qtd_list;
 148         u32 toggle;
 149         u32 ping;
 150         int slot;
 151         int tt_buffer_dirty;    /* See USB2.0 spec section 11.17.5 */
 152 };
 153
 154 struct urb_listitem {
 155         struct list_head urb_list;
 156         struct urb *urb;
 157 };
 158
 159 /*
 160  * Access functions for isp176x registers (addresses 0..0x03FF).
 161  */
 162 static u32 reg_read32(void __iomem *base, u32 reg)
 163 {
 164         return isp1760_read32(base, reg);
 165 }
 166
 167 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 168 {
 169         isp1760_write32(base, reg, val);
 170 }
 171
 172 /*
 173  * Access functions for isp176x memory (offset >= 0x0400).
 174  *
 175  * bank_reads8() reads memory locations prefetched by an earlier write to
 176  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 177  * bank optimizations, you should use the more generic mem_reads8() below.
 178  *
 179  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 180  * below.
 181  *
 182  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 183  * doesn't quite work because some people have to enforce 32-bit access
 184  */
 185 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 186                                                         __u32 *dst, u32 bytes)
 187 {
 188         __u32 __iomem *src;
 189         u32 val;
 190         __u8 *src_byteptr;
 191         __u8 *dst_byteptr;
 192
 193         src = src_base + (bank_addr | src_offset);
 194
 195         if (src_offset < PAYLOAD_OFFSET) {
 196                 while (bytes >= 4) {
 197                         *dst = le32_to_cpu(__raw_readl(src));
 198                         bytes -= 4;
 199                         src++;
 200                         dst++;
 201                 }
 202         } else {
 203                 while (bytes >= 4) {
 204                         *dst = __raw_readl(src);
 205                         bytes -= 4;
 206                         src++;
 207                         dst++;
 208                 }
 209         }
 210
 211         if (!bytes)
 212                 return;
 213
 214         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 215          * allocated.
 216          */
 217         if (src_offset < PAYLOAD_OFFSET)
 218                 val = le32_to_cpu(__raw_readl(src));
 219         else
 220                 val = __raw_readl(src);
 221
 222         dst_byteptr = (void *) dst;
 223         src_byteptr = (void *) &val;
 224         while (bytes > 0) {
 225                 *dst_byteptr = *src_byteptr;
 226                 dst_byteptr++;
 227                 src_byteptr++;
 228                 bytes--;
 229         }
 230 }
 231
 232 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 233                                                                 u32 bytes)
 234 {
 235         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 236         ndelay(90);
 237         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 238 }
 239
 240 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 241                                                 __u32 const *src, u32 bytes)
 242 {
 243         __u32 __iomem *dst;
 244
 245         dst = dst_base + dst_offset;
 246
 247         if (dst_offset < PAYLOAD_OFFSET) {
 248                 while (bytes >= 4) {
 249                         __raw_writel(cpu_to_le32(*src), dst);
 250                         bytes -= 4;
 251                         src++;
 252                         dst++;
 253                 }
 254         } else {
 255                 while (bytes >= 4) {
 256                         __raw_writel(*src, dst);
 257                         bytes -= 4;
 258                         src++;
 259                         dst++;
 260                 }
 261         }
 262
 263         if (!bytes)
 264                 return;
 265         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 266          * extra bytes should not be read by the HW.
 267          */
 268
 269         if (dst_offset < PAYLOAD_OFFSET)
 270                 __raw_writel(cpu_to_le32(*src), dst);
 271         else
 272                 __raw_writel(*src, dst);
 273 }
 274
 275 /*
 276  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 277  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 278  */
 279 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 280                                                                 struct ptd *ptd)
 281 {
 282         reg_write32(base, HC_MEMORY_REG,
 283                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 284         ndelay(90);
 285         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 286                                                 (void *) ptd, sizeof(*ptd));
 287 }
 288
 289 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 290                                                                 struct ptd *ptd)
 291 {
 292         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 293                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 294         /* Make sure dw0 gets written last (after other dw's and after payload)
 295            since it contains the enable bit */
 296         wmb();
 297         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 298                                                         sizeof(ptd->dw0));
 299 }
 300
 301
 302 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 303 static void init_memory(struct isp1760_hcd *priv)
 304 {
 305         int i, curr;
 306         u32 payload_addr;
 307
 308         payload_addr = PAYLOAD_OFFSET;
 309         for (i = 0; i < BLOCK_1_NUM; i++) {
 310                 priv->memory_pool[i].start = payload_addr;
 311                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 312                 priv->memory_pool[i].free = 1;
 313                 payload_addr += priv->memory_pool[i].size;
 314         }
 315
 316         curr = i;
 317         for (i = 0; i < BLOCK_2_NUM; i++) {
 318                 priv->memory_pool[curr + i].start = payload_addr;
 319                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 320                 priv->memory_pool[curr + i].free = 1;
 321                 payload_addr += priv->memory_pool[curr + i].size;
 322         }
 323
 324         curr = i;
 325         for (i = 0; i < BLOCK_3_NUM; i++) {
 326                 priv->memory_pool[curr + i].start = payload_addr;
 327                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 328                 priv->memory_pool[curr + i].free = 1;
 329                 payload_addr += priv->memory_pool[curr + i].size;
 330         }
 331
 332         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 333 }
 334
 335 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 336 {
 337         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 338         int i;
 339
 340         WARN_ON(qtd->payload_addr);
 341
 342         if (!qtd->length)
 343                 return;
 344
 345         for (i = 0; i < BLOCKS; i++) {
 346                 if (priv->memory_pool[i].size >= qtd->length &&
 347                                 priv->memory_pool[i].free) {
 348                         priv->memory_pool[i].free = 0;
 349                         qtd->payload_addr = priv->memory_pool[i].start;
 350                         return;
 351                 }
 352         }
 353 }
 354
 355 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 356 {
 357         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 358         int i;
 359
 360         if (!qtd->payload_addr)
 361                 return;
 362
 363         for (i = 0; i < BLOCKS; i++) {
 364                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 365                         WARN_ON(priv->memory_pool[i].free);
 366                         priv->memory_pool[i].free = 1;
 367                         qtd->payload_addr = 0;
 368                         return;
 369                 }
 370         }
 371
 372         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 373                                                 __func__, qtd->payload_addr);
 374         WARN_ON(1);
 375         qtd->payload_addr = 0;
 376 }
 377
 378 static int handshake(struct usb_hcd *hcd, u32 reg,
 379                       u32 mask, u32 done, int usec)
 380 {
 381         u32 result;
 382
 383         do {
 384                 result = reg_read32(hcd->regs, reg);
 385                 if (result == ~0)
 386                         return -ENODEV;
 387                 result &= mask;
 388                 if (result == done)
 389                         return 0;
 390                 udelay(1);
 391                 usec--;
 392         } while (usec > 0);
 393         return -ETIMEDOUT;
 394 }
 395
 396 /* reset a non-running (STS_HALT == 1) controller */
 397 static int ehci_reset(struct usb_hcd *hcd)
 398 {
 399         int retval;
 400         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 401
 402         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 403
 404         command |= CMD_RESET;
 405         reg_write32(hcd->regs, HC_USBCMD, command);
 406         hcd->state = HC_STATE_HALT;
 407         priv->next_statechange = jiffies;
 408         retval = handshake(hcd, HC_USBCMD,
 409                             CMD_RESET, 0, 250 * 1000);
 410         return retval;
 411 }
 412
 413 static struct isp1760_qh *qh_alloc(gfp_t flags)
 414 {
 415         struct isp1760_qh *qh;
 416
 417         qh = kmem_cache_zalloc(qh_cachep, flags);
 418         if (!qh)
 419                 return NULL;
 420
 421         INIT_LIST_HEAD(&qh->qh_list);
 422         INIT_LIST_HEAD(&qh->qtd_list);
 423         qh->slot = -1;
 424
 425         return qh;
 426 }
 427
 428 static void qh_free(struct isp1760_qh *qh)
 429 {
 430         WARN_ON(!list_empty(&qh->qtd_list));
 431         WARN_ON(qh->slot > -1);
 432         kmem_cache_free(qh_cachep, qh);
 433 }
 434
 435 /* one-time init, only for memory state */
 436 static int priv_init(struct usb_hcd *hcd)
 437 {
 438         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 439         u32                     hcc_params;
 440         int i;
 441
 442         spin_lock_init(&priv->lock);
 443
 444         for (i = 0; i < QH_END; i++)
 445                 INIT_LIST_HEAD(&priv->qh_list[i]);
 446
 447         /*
 448          * hw default: 1K periodic list heads, one per frame.
 449          * periodic_size can shrink by USBCMD update if hcc_params allows.
 450          */
 451         priv->periodic_size = DEFAULT_I_TDPS;
 452
 453         /* controllers may cache some of the periodic schedule ... */
 454         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 455         /* full frame cache */
 456         if (HCC_ISOC_CACHE(hcc_params))
 457                 priv->i_thresh = 8;
 458         else /* N microframes cached */
 459                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 460
 461         return 0;
 462 }
 463
 464 static int isp1760_hc_setup(struct usb_hcd *hcd)
 465 {
 466         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 467         int result;
 468         u32 scratch, hwmode;
 469
 470         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 471         /* Change bus pattern */
 472         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 473         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 474         if (scratch != 0xdeadbabe) {
 475                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 476                 return -ENODEV;
 477         }
 478
 479         /*
 480          * The RESET_HC bit in the SW_RESET register is supposed to reset the
 481          * host controller without touching the CPU interface registers, but at
 482          * least on the ISP1761 it seems to behave as the RESET_ALL bit and
 483          * reset the whole device. We thus can't use it here, so let's reset
 484          * the host controller through the EHCI USB Command register. The device
 485          * has been reset in core code anyway, so this shouldn't matter.
 486          */
 487         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 488         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 489         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 490         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 491
 492         result = ehci_reset(hcd);
 493         if (result)
 494                 return result;
 495
 496         /* Step 11 passed */
 497
 498         /* ATL reset */
 499         hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET;
 500         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 501         mdelay(10);
 502         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 503
 504         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 505
 506         /*
 507          * PORT 1 Control register of the ISP1760 is the OTG control
 508          * register on ISP1761. Since there is no OTG or device controller
 509          * support in this driver, we use port 1 as a "normal" USB host port on
 510          * both chips.
 511          */
 512         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 513         mdelay(10);
 514
 515         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 516
 517         return priv_init(hcd);
 518 }
 519
 520 static u32 base_to_chip(u32 base)
 521 {
 522         return ((base - 0x400) >> 3);
 523 }
 524
 525 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 526 {
 527         struct urb *urb;
 528
 529         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 530                 return 1;
 531
 532         urb = qtd->urb;
 533         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 534         return (qtd->urb != urb);
 535 }
 536
 537 /* magic numbers that can affect system performance */
 538 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 539 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 540 #define EHCI_TUNE_RL_TT         0
 541 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 542 #define EHCI_TUNE_MULT_TT       1
 543 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 544
 545 static void create_ptd_atl(struct isp1760_qh *qh,
 546                         struct isp1760_qtd *qtd, struct ptd *ptd)
 547 {
 548         u32 maxpacket;
 549         u32 multi;
 550         u32 rl = RL_COUNTER;
 551         u32 nak = NAK_COUNTER;
 552
 553         memset(ptd, 0, sizeof(*ptd));
 554
 555         /* according to 3.6.2, max packet len can not be > 0x400 */
 556         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 557                                                 usb_pipeout(qtd->urb->pipe));
 558         multi =  1 + ((maxpacket >> 11) & 0x3);
 559         maxpacket &= 0x7ff;
 560
 561         /* DW0 */
 562         ptd->dw0 = DW0_VALID_BIT;
 563         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 564         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 565         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 566
 567         /* DW1 */
 568         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 569         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 570         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 571
 572         if (usb_pipebulk(qtd->urb->pipe))
 573                 ptd->dw1 |= DW1_TRANS_BULK;
 574         else if  (usb_pipeint(qtd->urb->pipe))
 575                 ptd->dw1 |= DW1_TRANS_INT;
 576
 577         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 578                 /* split transaction */
 579
 580                 ptd->dw1 |= DW1_TRANS_SPLIT;
 581                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 582                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 583
 584                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 585                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 586
 587                 /* SE bit for Split INT transfers */
 588                 if (usb_pipeint(qtd->urb->pipe) &&
 589                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 590                         ptd->dw1 |= 2 << 16;
 591
 592                 rl = 0;
 593                 nak = 0;
 594         } else {
 595                 ptd->dw0 |= TO_DW0_MULTI(multi);
 596                 if (usb_pipecontrol(qtd->urb->pipe) ||
 597                                                 usb_pipebulk(qtd->urb->pipe))
 598                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 599         }
 600         /* DW2 */
 601         ptd->dw2 = 0;
 602         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 603         ptd->dw2 |= TO_DW2_RL(rl);
 604
 605         /* DW3 */
 606         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 607         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 608         if (usb_pipecontrol(qtd->urb->pipe)) {
 609                 if (qtd->data_buffer == qtd->urb->setup_packet)
 610                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 611                 else if (last_qtd_of_urb(qtd, qh))
 612                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 613         }
 614
 615         ptd->dw3 |= DW3_ACTIVE_BIT;
 616         /* Cerr */
 617         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 618 }
 619
 620 static void transform_add_int(struct isp1760_qh *qh,
 621                         struct isp1760_qtd *qtd, struct ptd *ptd)
 622 {
 623         u32 usof;
 624         u32 period;
 625
 626         /*
 627          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 628          * the algorithm from the original Philips driver code, which was
 629          * pretty much used in this driver before as well, is quite horrendous
 630          * and, i believe, incorrect. The code below follows the datasheet and
 631          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 632          * more reliable this way (fingers crossed...).
 633          */
 634
 635         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 636                 /* urb->interval is in units of microframes (1/8 ms) */
 637                 period = qtd->urb->interval >> 3;
 638
 639                 if (qtd->urb->interval > 4)
 640                         usof = 0x01; /* One bit set =>
 641                                                 interval 1 ms * uFrame-match */
 642                 else if (qtd->urb->interval > 2)
 643                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 644                 else if (qtd->urb->interval > 1)
 645                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 646                 else
 647                         usof = 0xff; /* All bits set => interval 1/8 ms */
 648         } else {
 649                 /* urb->interval is in units of frames (1 ms) */
 650                 period = qtd->urb->interval;
 651                 usof = 0x0f;            /* Execute Start Split on any of the
 652                                            four first uFrames */
 653
 654                 /*
 655                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 656                  * complete split needs to be sent. Valid only for IN." Also,
 657                  * "All bits can be set to one for every transfer." (p 82,
 658                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 659                  * that number come from? 0xff seems to work fine...
 660                  */
 661                 /* ptd->dw5 = 0x1c; */
 662                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 663         }
 664
 665         period = period >> 1;/* Ensure equal or shorter period than requested */
 666         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 667
 668         ptd->dw2 |= period;
 669         ptd->dw4 = usof;
 670 }
 671
 672 static void create_ptd_int(struct isp1760_qh *qh,
 673                         struct isp1760_qtd *qtd, struct ptd *ptd)
 674 {
 675         create_ptd_atl(qh, qtd, ptd);
 676         transform_add_int(qh, qtd, ptd);
 677 }
 678
 679 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 680 __releases(priv->lock)
 681 __acquires(priv->lock)
 682 {
 683         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 684
 685         if (!urb->unlinked) {
 686                 if (urb->status == -EINPROGRESS)
 687                         urb->status = 0;
 688         }
 689
 690         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 691                 void *ptr;
 692                 for (ptr = urb->transfer_buffer;
 693                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 694                      ptr += PAGE_SIZE)
 695                         flush_dcache_page(virt_to_page(ptr));
 696         }
 697
 698         /* complete() can reenter this HCD */
 699         usb_hcd_unlink_urb_from_ep(hcd, urb);
 700         spin_unlock(&priv->lock);
 701         usb_hcd_giveback_urb(hcd, urb, urb->status);
 702         spin_lock(&priv->lock);
 703 }
 704
 705 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 706                                                                 u8 packet_type)
 707 {
 708         struct isp1760_qtd *qtd;
 709
 710         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 711         if (!qtd)
 712                 return NULL;
 713
 714         INIT_LIST_HEAD(&qtd->qtd_list);
 715         qtd->urb = urb;
 716         qtd->packet_type = packet_type;
 717         qtd->status = QTD_ENQUEUED;
 718         qtd->actual_length = 0;
 719
 720         return qtd;
 721 }
 722
 723 static void qtd_free(struct isp1760_qtd *qtd)
 724 {
 725         WARN_ON(qtd->payload_addr);
 726         kmem_cache_free(qtd_cachep, qtd);
 727 }
 728
 729 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 730                                 struct isp1760_slotinfo *slots,
 731                                 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
 732                                 struct ptd *ptd)
 733 {
 734         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 735         int skip_map;
 736
 737         WARN_ON((slot < 0) || (slot > 31));
 738         WARN_ON(qtd->length && !qtd->payload_addr);
 739         WARN_ON(slots[slot].qtd);
 740         WARN_ON(slots[slot].qh);
 741         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 742
 743         /* Make sure done map has not triggered from some unlinked transfer */
 744         if (ptd_offset == ATL_PTD_OFFSET) {
 745                 priv->atl_done_map |= reg_read32(hcd->regs,
 746                                                 HC_ATL_PTD_DONEMAP_REG);
 747                 priv->atl_done_map &= ~(1 << slot);
 748         } else {
 749                 priv->int_done_map |= reg_read32(hcd->regs,
 750                                                 HC_INT_PTD_DONEMAP_REG);
 751                 priv->int_done_map &= ~(1 << slot);
 752         }
 753
 754         qh->slot = slot;
 755         qtd->status = QTD_XFER_STARTED;
 756         slots[slot].timestamp = jiffies;
 757         slots[slot].qtd = qtd;
 758         slots[slot].qh = qh;
 759         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 760
 761         if (ptd_offset == ATL_PTD_OFFSET) {
 762                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 763                 skip_map &= ~(1 << qh->slot);
 764                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 765         } else {
 766                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 767                 skip_map &= ~(1 << qh->slot);
 768                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 769         }
 770 }
 771
 772 static int is_short_bulk(struct isp1760_qtd *qtd)
 773 {
 774         return (usb_pipebulk(qtd->urb->pipe) &&
 775                                         (qtd->actual_length < qtd->length));
 776 }
 777
 778 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 779                                                 struct list_head *urb_list)
 780 {
 781         int last_qtd;
 782         struct isp1760_qtd *qtd, *qtd_next;
 783         struct urb_listitem *urb_listitem;
 784
 785         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 786                 if (qtd->status < QTD_XFER_COMPLETE)
 787                         break;
 788
 789                 last_qtd = last_qtd_of_urb(qtd, qh);
 790
 791                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 792                         qtd_next->status = QTD_RETIRE;
 793
 794                 if (qtd->status == QTD_XFER_COMPLETE) {
 795                         if (qtd->actual_length) {
 796                                 switch (qtd->packet_type) {
 797                                 case IN_PID:
 798                                         mem_reads8(hcd->regs, qtd->payload_addr,
 799                                                         qtd->data_buffer,
 800                                                         qtd->actual_length);
 801                                         /* Fall through (?) */
 802                                 case OUT_PID:
 803                                         qtd->urb->actual_length +=
 804                                                         qtd->actual_length;
 805                                         /* Fall through ... */
 806                                 case SETUP_PID:
 807                                         break;
 808                                 }
 809                         }
 810
 811                         if (is_short_bulk(qtd)) {
 812                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 813                                         qtd->urb->status = -EREMOTEIO;
 814                                 if (!last_qtd)
 815                                         qtd_next->status = QTD_RETIRE;
 816                         }
 817                 }
 818
 819                 if (qtd->payload_addr)
 820                         free_mem(hcd, qtd);
 821
 822                 if (last_qtd) {
 823                         if ((qtd->status == QTD_RETIRE) &&
 824                                         (qtd->urb->status == -EINPROGRESS))
 825                                 qtd->urb->status = -EPIPE;
 826                         /* Defer calling of urb_done() since it releases lock */
 827                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 828                                                                 GFP_ATOMIC);
 829                         if (unlikely(!urb_listitem))
 830                                 break; /* Try again on next call */
 831                         urb_listitem->urb = qtd->urb;
 832                         list_add_tail(&urb_listitem->urb_list, urb_list);
 833                 }
 834
 835                 list_del(&qtd->qtd_list);
 836                 qtd_free(qtd);
 837         }
 838 }
 839
 840 #define ENQUEUE_DEPTH   2
 841 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 842 {
 843         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 844         int ptd_offset;
 845         struct isp1760_slotinfo *slots;
 846         int curr_slot, free_slot;
 847         int n;
 848         struct ptd ptd;
 849         struct isp1760_qtd *qtd;
 850
 851         if (unlikely(list_empty(&qh->qtd_list))) {
 852                 WARN_ON(1);
 853                 return;
 854         }
 855
 856         /* Make sure this endpoint's TT buffer is clean before queueing ptds */
 857         if (qh->tt_buffer_dirty)
 858                 return;
 859
 860         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 861                                                         qtd_list)->urb->pipe)) {
 862                 ptd_offset = INT_PTD_OFFSET;
 863                 slots = priv->int_slots;
 864         } else {
 865                 ptd_offset = ATL_PTD_OFFSET;
 866                 slots = priv->atl_slots;
 867         }
 868
 869         free_slot = -1;
 870         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 871                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 872                         free_slot = curr_slot;
 873                 if (slots[curr_slot].qh == qh)
 874                         break;
 875         }
 876
 877         n = 0;
 878         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 879                 if (qtd->status == QTD_ENQUEUED) {
 880                         WARN_ON(qtd->payload_addr);
 881                         alloc_mem(hcd, qtd);
 882                         if ((qtd->length) && (!qtd->payload_addr))
 883                                 break;
 884
 885                         if ((qtd->length) &&
 886                             ((qtd->packet_type == SETUP_PID) ||
 887                              (qtd->packet_type == OUT_PID))) {
 888                                 mem_writes8(hcd->regs, qtd->payload_addr,
 889                                                 qtd->data_buffer, qtd->length);
 890                         }
 891
 892                         qtd->status = QTD_PAYLOAD_ALLOC;
 893                 }
 894
 895                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 896 /*
 897                         if ((curr_slot > 31) && (free_slot == -1))
 898                                 dev_dbg(hcd->self.controller, "%s: No slot "
 899                                         "available for transfer\n", __func__);
 900 */
 901                         /* Start xfer for this endpoint if not already done */
 902                         if ((curr_slot > 31) && (free_slot > -1)) {
 903                                 if (usb_pipeint(qtd->urb->pipe))
 904                                         create_ptd_int(qh, qtd, &ptd);
 905                                 else
 906                                         create_ptd_atl(qh, qtd, &ptd);
 907
 908                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 909                                                         slots, qtd, qh, &ptd);
 910                                 curr_slot = free_slot;
 911                         }
 912
 913                         n++;
 914                         if (n >= ENQUEUE_DEPTH)
 915                                 break;
 916                 }
 917         }
 918 }
 919
 920 static void schedule_ptds(struct usb_hcd *hcd)
 921 {
 922         struct isp1760_hcd *priv;
 923         struct isp1760_qh *qh, *qh_next;
 924         struct list_head *ep_queue;
 925         LIST_HEAD(urb_list);
 926         struct urb_listitem *urb_listitem, *urb_listitem_next;
 927         int i;
 928
 929         if (!hcd) {
 930                 WARN_ON(1);
 931                 return;
 932         }
 933
 934         priv = hcd_to_priv(hcd);
 935
 936         /*
 937          * check finished/retired xfers, transfer payloads, call urb_done()
 938          */
 939         for (i = 0; i < QH_END; i++) {
 940                 ep_queue = &priv->qh_list[i];
 941                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 942                         collect_qtds(hcd, qh, &urb_list);
 943                         if (list_empty(&qh->qtd_list))
 944                                 list_del(&qh->qh_list);
 945                 }
 946         }
 947
 948         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
 949                                                                 urb_list) {
 950                 isp1760_urb_done(hcd, urb_listitem->urb);
 951                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
 952         }
 953
 954         /*
 955          * Schedule packets for transfer.
 956          *
 957          * According to USB2.0 specification:
 958          *
 959          * 1st prio: interrupt xfers, up to 80 % of bandwidth
 960          * 2nd prio: control xfers
 961          * 3rd prio: bulk xfers
 962          *
 963          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
 964          * is very unclear on how to prioritize traffic):
 965          *
 966          * 1) Enqueue any queued control transfers, as long as payload chip mem
 967          *    and PTD ATL slots are available.
 968          * 2) Enqueue any queued INT transfers, as long as payload chip mem
 969          *    and PTD INT slots are available.
 970          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
 971          *    and PTD ATL slots are available.
 972          *
 973          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
 974          * conservation of chip mem and performance.
 975          *
 976          * I'm sure this scheme could be improved upon!
 977          */
 978         for (i = 0; i < QH_END; i++) {
 979                 ep_queue = &priv->qh_list[i];
 980                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
 981                         enqueue_qtds(hcd, qh);
 982         }
 983 }
 984
 985 #define PTD_STATE_QTD_DONE      1
 986 #define PTD_STATE_QTD_RELOAD    2
 987 #define PTD_STATE_URB_RETIRE    3
 988
 989 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
 990                                                                 struct urb *urb)
 991 {
 992         __dw dw4;
 993         int i;
 994
 995         dw4 = ptd->dw4;
 996         dw4 >>= 8;
 997
 998         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
 999            need to handle these errors? Is it done in hardware? */
1000
1001         if (ptd->dw3 & DW3_HALT_BIT) {
1002
1003                 urb->status = -EPROTO; /* Default unknown error */
1004
1005                 for (i = 0; i < 8; i++) {
1006                         switch (dw4 & 0x7) {
1007                         case INT_UNDERRUN:
1008                                 dev_dbg(hcd->self.controller, "%s: underrun "
1009                                                 "during uFrame %d\n",
1010                                                 __func__, i);
1011                                 urb->status = -ECOMM; /* Could not write data */
1012                                 break;
1013                         case INT_EXACT:
1014                                 dev_dbg(hcd->self.controller, "%s: transaction "
1015                                                 "error during uFrame %d\n",
1016                                                 __func__, i);
1017                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1018                                                           error etc. */
1019                                 break;
1020                         case INT_BABBLE:
1021                                 dev_dbg(hcd->self.controller, "%s: babble "
1022                                                 "error during uFrame %d\n",
1023                                                 __func__, i);
1024                                 urb->status = -EOVERFLOW;
1025                                 break;
1026                         }
1027                         dw4 >>= 3;
1028                 }
1029
1030                 return PTD_STATE_URB_RETIRE;
1031         }
1032
1033         return PTD_STATE_QTD_DONE;
1034 }
1035
1036 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1037                                                                 struct urb *urb)
1038 {
1039         WARN_ON(!ptd);
1040         if (ptd->dw3 & DW3_HALT_BIT) {
1041                 if (ptd->dw3 & DW3_BABBLE_BIT)
1042                         urb->status = -EOVERFLOW;
1043                 else if (FROM_DW3_CERR(ptd->dw3))
1044                         urb->status = -EPIPE;  /* Stall */
1045                 else if (ptd->dw3 & DW3_ERROR_BIT)
1046                         urb->status = -EPROTO; /* XactErr */
1047                 else
1048                         urb->status = -EPROTO; /* Unknown */
1049 /*
1050                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1051                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1052                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1053                         __func__,
1054                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1055                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1056 */
1057                 return PTD_STATE_URB_RETIRE;
1058         }
1059
1060         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1061                 /* Transfer Error, *but* active and no HALT -> reload */
1062                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1063                 return PTD_STATE_QTD_RELOAD;
1064         }
1065
1066         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1067                 /*
1068                  * NAKs are handled in HW by the chip. Usually if the
1069                  * device is not able to send data fast enough.
1070                  * This happens mostly on slower hardware.
1071                  */
1072                 return PTD_STATE_QTD_RELOAD;
1073         }
1074
1075         return PTD_STATE_QTD_DONE;
1076 }
1077
1078 static void handle_done_ptds(struct usb_hcd *hcd)
1079 {
1080         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1081         struct ptd ptd;
1082         struct isp1760_qh *qh;
1083         int slot;
1084         int state;
1085         struct isp1760_slotinfo *slots;
1086         u32 ptd_offset;
1087         struct isp1760_qtd *qtd;
1088         int modified;
1089         int skip_map;
1090
1091         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1092         priv->int_done_map &= ~skip_map;
1093         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1094         priv->atl_done_map &= ~skip_map;
1095
1096         modified = priv->int_done_map || priv->atl_done_map;
1097
1098         while (priv->int_done_map || priv->atl_done_map) {
1099                 if (priv->int_done_map) {
1100                         /* INT ptd */
1101                         slot = __ffs(priv->int_done_map);
1102                         priv->int_done_map &= ~(1 << slot);
1103                         slots = priv->int_slots;
1104                         /* This should not trigger, and could be removed if
1105                            noone have any problems with it triggering: */
1106                         if (!slots[slot].qh) {
1107                                 WARN_ON(1);
1108                                 continue;
1109                         }
1110                         ptd_offset = INT_PTD_OFFSET;
1111                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1112                         state = check_int_transfer(hcd, &ptd,
1113                                                         slots[slot].qtd->urb);
1114                 } else {
1115                         /* ATL ptd */
1116                         slot = __ffs(priv->atl_done_map);
1117                         priv->atl_done_map &= ~(1 << slot);
1118                         slots = priv->atl_slots;
1119                         /* This should not trigger, and could be removed if
1120                            noone have any problems with it triggering: */
1121                         if (!slots[slot].qh) {
1122                                 WARN_ON(1);
1123                                 continue;
1124                         }
1125                         ptd_offset = ATL_PTD_OFFSET;
1126                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1127                         state = check_atl_transfer(hcd, &ptd,
1128                                                         slots[slot].qtd->urb);
1129                 }
1130
1131                 qtd = slots[slot].qtd;
1132                 slots[slot].qtd = NULL;
1133                 qh = slots[slot].qh;
1134                 slots[slot].qh = NULL;
1135                 qh->slot = -1;
1136
1137                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1138
1139                 switch (state) {
1140                 case PTD_STATE_QTD_DONE:
1141                         if ((usb_pipeint(qtd->urb->pipe)) &&
1142                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1143                                 qtd->actual_length =
1144                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1145                         else
1146                                 qtd->actual_length =
1147                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1148
1149                         qtd->status = QTD_XFER_COMPLETE;
1150                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1151                                                         is_short_bulk(qtd))
1152                                 qtd = NULL;
1153                         else
1154                                 qtd = list_entry(qtd->qtd_list.next,
1155                                                         typeof(*qtd), qtd_list);
1156
1157                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1158                         qh->ping = FROM_DW3_PING(ptd.dw3);
1159                         break;
1160
1161                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1162                         qtd->status = QTD_PAYLOAD_ALLOC;
1163                         ptd.dw0 |= DW0_VALID_BIT;
1164                         /* RL counter = ERR counter */
1165                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1166                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1167                         ptd.dw3 &= ~TO_DW3_CERR(3);
1168                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1169                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1170                         qh->ping = FROM_DW3_PING(ptd.dw3);
1171                         break;
1172
1173                 case PTD_STATE_URB_RETIRE:
1174                         qtd->status = QTD_RETIRE;
1175                         if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1176                                         (qtd->urb->status != -EPIPE) &&
1177                                         (qtd->urb->status != -EREMOTEIO)) {
1178                                 qh->tt_buffer_dirty = 1;
1179                                 if (usb_hub_clear_tt_buffer(qtd->urb))
1180                                         /* Clear failed; let's hope things work
1181                                            anyway */
1182                                         qh->tt_buffer_dirty = 0;
1183                         }
1184                         qtd = NULL;
1185                         qh->toggle = 0;
1186                         qh->ping = 0;
1187                         break;
1188
1189                 default:
1190                         WARN_ON(1);
1191                         continue;
1192                 }
1193
1194                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1195                         if (slots == priv->int_slots) {
1196                                 if (state == PTD_STATE_QTD_RELOAD)
1197                                         dev_err(hcd->self.controller,
1198                                                 "%s: PTD_STATE_QTD_RELOAD on "
1199                                                 "interrupt packet\n", __func__);
1200                                 if (state != PTD_STATE_QTD_RELOAD)
1201                                         create_ptd_int(qh, qtd, &ptd);
1202                         } else {
1203                                 if (state != PTD_STATE_QTD_RELOAD)
1204                                         create_ptd_atl(qh, qtd, &ptd);
1205                         }
1206
1207                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1208                                 qh, &ptd);
1209                 }
1210         }
1211
1212         if (modified)
1213                 schedule_ptds(hcd);
1214 }
1215
1216 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1217 {
1218         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1219         u32 imask;
1220         irqreturn_t irqret = IRQ_NONE;
1221
1222         spin_lock(&priv->lock);
1223
1224         if (!(hcd->state & HC_STATE_RUNNING))
1225                 goto leave;
1226
1227         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1228         if (unlikely(!imask))
1229                 goto leave;
1230         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1231
1232         priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1233         priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1234
1235         handle_done_ptds(hcd);
1236
1237         irqret = IRQ_HANDLED;
1238 leave:
1239         spin_unlock(&priv->lock);
1240
1241         return irqret;
1242 }
1243
1244 /*
1245  * Workaround for problem described in chip errata 2:
1246  *
1247  * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1248  * One solution suggested in the errata is to use SOF interrupts _instead_of_
1249  * ATL done interrupts (the "instead of" might be important since it seems
1250  * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1251  * to set the PTD's done bit in addition to not generating an interrupt!).
1252  *
1253  * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1254  * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1255  *
1256  * If we use SOF interrupts only, we get latency between ptd completion and the
1257  * actual handling. This is very noticeable in testusb runs which takes several
1258  * minutes longer without ATL interrupts.
1259  *
1260  * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1261  * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1262  * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1263  * completed and its done map bit is set.
1264  *
1265  * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1266  * not to cause too much lag when this HW bug occurs, while still hopefully
1267  * ensuring that the check does not falsely trigger.
1268  */
1269 #define SLOT_TIMEOUT 300
1270 #define SLOT_CHECK_PERIOD 200
1271 static struct timer_list errata2_timer;
1272
1273 static void errata2_function(unsigned long data)
1274 {
1275         struct usb_hcd *hcd = (struct usb_hcd *) data;
1276         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1277         int slot;
1278         struct ptd ptd;
1279         unsigned long spinflags;
1280
1281         spin_lock_irqsave(&priv->lock, spinflags);
1282
1283         for (slot = 0; slot < 32; slot++)
1284                 if (priv->atl_slots[slot].qh && time_after(jiffies,
1285                                         priv->atl_slots[slot].timestamp +
1286                                         SLOT_TIMEOUT * HZ / 1000)) {
1287                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1288                         if (!FROM_DW0_VALID(ptd.dw0) &&
1289                                         !FROM_DW3_ACTIVE(ptd.dw3))
1290                                 priv->atl_done_map |= 1 << slot;
1291                 }
1292
1293         if (priv->atl_done_map)
1294                 handle_done_ptds(hcd);
1295
1296         spin_unlock_irqrestore(&priv->lock, spinflags);
1297
1298         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1299         add_timer(&errata2_timer);
1300 }
1301
1302 static int isp1760_run(struct usb_hcd *hcd)
1303 {
1304         int retval;
1305         u32 temp;
1306         u32 command;
1307         u32 chipid;
1308
1309         hcd->uses_new_polling = 1;
1310
1311         hcd->state = HC_STATE_RUNNING;
1312
1313         /* Set PTD interrupt AND & OR maps */
1314         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1315         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1316         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1317         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1318         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1319         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1320         /* step 23 passed */
1321
1322         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1323         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1324
1325         command = reg_read32(hcd->regs, HC_USBCMD);
1326         command &= ~(CMD_LRESET|CMD_RESET);
1327         command |= CMD_RUN;
1328         reg_write32(hcd->regs, HC_USBCMD, command);
1329
1330         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1331         if (retval)
1332                 return retval;
1333
1334         /*
1335          * XXX
1336          * Spec says to write FLAG_CF as last config action, priv code grabs
1337          * the semaphore while doing so.
1338          */
1339         down_write(&ehci_cf_port_reset_rwsem);
1340         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1341
1342         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1343         up_write(&ehci_cf_port_reset_rwsem);
1344         if (retval)
1345                 return retval;
1346
1347         init_timer(&errata2_timer);
1348         errata2_timer.function = errata2_function;
1349         errata2_timer.data = (unsigned long) hcd;
1350         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1351         add_timer(&errata2_timer);
1352
1353         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1354         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1355                                         chipid & 0xffff, chipid >> 16);
1356
1357         /* PTD Register Init Part 2, Step 28 */
1358
1359         /* Setup registers controlling PTD checking */
1360         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1361         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1362         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1363         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1364         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1365         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1366         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1367                                                 ATL_BUF_FILL | INT_BUF_FILL);
1368
1369         /* GRR this is run-once init(), being done every time the HC starts.
1370          * So long as they're part of class devices, we can't do it init()
1371          * since the class device isn't created that early.
1372          */
1373         return 0;
1374 }
1375
1376 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1377 {
1378         qtd->data_buffer = databuffer;
1379
1380         if (len > MAX_PAYLOAD_SIZE)
1381                 len = MAX_PAYLOAD_SIZE;
1382         qtd->length = len;
1383
1384         return qtd->length;
1385 }
1386
1387 static void qtd_list_free(struct list_head *qtd_list)
1388 {
1389         struct isp1760_qtd *qtd, *qtd_next;
1390
1391         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1392                 list_del(&qtd->qtd_list);
1393                 qtd_free(qtd);
1394         }
1395 }
1396
1397 /*
1398  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1399  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1400  */
1401 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1402 static void packetize_urb(struct usb_hcd *hcd,
1403                 struct urb *urb, struct list_head *head, gfp_t flags)
1404 {
1405         struct isp1760_qtd *qtd;
1406         void *buf;
1407         int len, maxpacketsize;
1408         u8 packet_type;
1409
1410         /*
1411          * URBs map to sequences of QTDs:  one logical transaction
1412          */
1413
1414         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1415                 /* XXX This looks like usb storage / SCSI bug */
1416                 dev_err(hcd->self.controller,
1417                                 "buf is null, dma is %08lx len is %d\n",
1418                                 (long unsigned)urb->transfer_dma,
1419                                 urb->transfer_buffer_length);
1420                 WARN_ON(1);
1421         }
1422
1423         if (usb_pipein(urb->pipe))
1424                 packet_type = IN_PID;
1425         else
1426                 packet_type = OUT_PID;
1427
1428         if (usb_pipecontrol(urb->pipe)) {
1429                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1430                 if (!qtd)
1431                         goto cleanup;
1432                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1433                 list_add_tail(&qtd->qtd_list, head);
1434
1435                 /* for zero length DATA stages, STATUS is always IN */
1436                 if (urb->transfer_buffer_length == 0)
1437                         packet_type = IN_PID;
1438         }
1439
1440         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1441                                                 usb_pipeout(urb->pipe)));
1442
1443         /*
1444          * buffer gets wrapped in one or more qtds;
1445          * last one may be "short" (including zero len)
1446          * and may serve as a control status ack
1447          */
1448         buf = urb->transfer_buffer;
1449         len = urb->transfer_buffer_length;
1450
1451         for (;;) {
1452                 int this_qtd_len;
1453
1454                 qtd = qtd_alloc(flags, urb, packet_type);
1455                 if (!qtd)
1456                         goto cleanup;
1457                 this_qtd_len = qtd_fill(qtd, buf, len);
1458                 list_add_tail(&qtd->qtd_list, head);
1459
1460                 len -= this_qtd_len;
1461                 buf += this_qtd_len;
1462
1463                 if (len <= 0)
1464                         break;
1465         }
1466
1467         /*
1468          * control requests may need a terminating data "status" ack;
1469          * bulk ones may need a terminating short packet (zero length).
1470          */
1471         if (urb->transfer_buffer_length != 0) {
1472                 int one_more = 0;
1473
1474                 if (usb_pipecontrol(urb->pipe)) {
1475                         one_more = 1;
1476                         if (packet_type == IN_PID)
1477                                 packet_type = OUT_PID;
1478                         else
1479                                 packet_type = IN_PID;
1480                 } else if (usb_pipebulk(urb->pipe)
1481                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1482                                 && !(urb->transfer_buffer_length %
1483                                                         maxpacketsize)) {
1484                         one_more = 1;
1485                 }
1486                 if (one_more) {
1487                         qtd = qtd_alloc(flags, urb, packet_type);
1488                         if (!qtd)
1489                                 goto cleanup;
1490
1491                         /* never any data in such packets */
1492                         qtd_fill(qtd, NULL, 0);
1493                         list_add_tail(&qtd->qtd_list, head);
1494                 }
1495         }
1496
1497         return;
1498
1499 cleanup:
1500         qtd_list_free(head);
1501 }
1502
1503 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1504                 gfp_t mem_flags)
1505 {
1506         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1507         struct list_head *ep_queue;
1508         struct isp1760_qh *qh, *qhit;
1509         unsigned long spinflags;
1510         LIST_HEAD(new_qtds);
1511         int retval;
1512         int qh_in_queue;
1513
1514         switch (usb_pipetype(urb->pipe)) {
1515         case PIPE_CONTROL:
1516                 ep_queue = &priv->qh_list[QH_CONTROL];
1517                 break;
1518         case PIPE_BULK:
1519                 ep_queue = &priv->qh_list[QH_BULK];
1520                 break;
1521         case PIPE_INTERRUPT:
1522                 if (urb->interval < 0)
1523                         return -EINVAL;
1524                 /* FIXME: Check bandwidth  */
1525                 ep_queue = &priv->qh_list[QH_INTERRUPT];
1526                 break;
1527         case PIPE_ISOCHRONOUS:
1528                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1529                                                         "not yet supported\n",
1530                                                         __func__);
1531                 return -EPIPE;
1532         default:
1533                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1534                                                         __func__);
1535                 return -EPIPE;
1536         }
1537
1538         if (usb_pipein(urb->pipe))
1539                 urb->actual_length = 0;
1540
1541         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1542         if (list_empty(&new_qtds))
1543                 return -ENOMEM;
1544
1545         retval = 0;
1546         spin_lock_irqsave(&priv->lock, spinflags);
1547
1548         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1549                 retval = -ESHUTDOWN;
1550                 qtd_list_free(&new_qtds);
1551                 goto out;
1552         }
1553         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1554         if (retval) {
1555                 qtd_list_free(&new_qtds);
1556                 goto out;
1557         }
1558
1559         qh = urb->ep->hcpriv;
1560         if (qh) {
1561                 qh_in_queue = 0;
1562                 list_for_each_entry(qhit, ep_queue, qh_list) {
1563                         if (qhit == qh) {
1564                                 qh_in_queue = 1;
1565                                 break;
1566                         }
1567                 }
1568                 if (!qh_in_queue)
1569                         list_add_tail(&qh->qh_list, ep_queue);
1570         } else {
1571                 qh = qh_alloc(GFP_ATOMIC);
1572                 if (!qh) {
1573                         retval = -ENOMEM;
1574                         usb_hcd_unlink_urb_from_ep(hcd, urb);
1575                         qtd_list_free(&new_qtds);
1576                         goto out;
1577                 }
1578                 list_add_tail(&qh->qh_list, ep_queue);
1579                 urb->ep->hcpriv = qh;
1580         }
1581
1582         list_splice_tail(&new_qtds, &qh->qtd_list);
1583         schedule_ptds(hcd);
1584
1585 out:
1586         spin_unlock_irqrestore(&priv->lock, spinflags);
1587         return retval;
1588 }
1589
1590 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1591                 struct isp1760_qh *qh)
1592 {
1593         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1594         int skip_map;
1595
1596         WARN_ON(qh->slot == -1);
1597
1598         /* We need to forcefully reclaim the slot since some transfers never
1599            return, e.g. interrupt transfers and NAKed bulk transfers. */
1600         if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1601                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1602                 skip_map |= (1 << qh->slot);
1603                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1604                 priv->atl_slots[qh->slot].qh = NULL;
1605                 priv->atl_slots[qh->slot].qtd = NULL;
1606         } else {
1607                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1608                 skip_map |= (1 << qh->slot);
1609                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1610                 priv->int_slots[qh->slot].qh = NULL;
1611                 priv->int_slots[qh->slot].qtd = NULL;
1612         }
1613
1614         qh->slot = -1;
1615 }
1616
1617 /*
1618  * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1619  * any active transfer belonging to the urb in the process.
1620  */
1621 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1622                                                 struct isp1760_qtd *qtd)
1623 {
1624         struct urb *urb;
1625         int urb_was_running;
1626
1627         urb = qtd->urb;
1628         urb_was_running = 0;
1629         list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1630                 if (qtd->urb != urb)
1631                         break;
1632
1633                 if (qtd->status >= QTD_XFER_STARTED)
1634                         urb_was_running = 1;
1635                 if (last_qtd_of_urb(qtd, qh) &&
1636                                         (qtd->status >= QTD_XFER_COMPLETE))
1637                         urb_was_running = 0;
1638
1639                 if (qtd->status == QTD_XFER_STARTED)
1640                         kill_transfer(hcd, urb, qh);
1641                 qtd->status = QTD_RETIRE;
1642         }
1643
1644         if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1645                 qh->tt_buffer_dirty = 1;
1646                 if (usb_hub_clear_tt_buffer(urb))
1647                         /* Clear failed; let's hope things work anyway */
1648                         qh->tt_buffer_dirty = 0;
1649         }
1650 }
1651
1652 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1653                 int status)
1654 {
1655         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1656         unsigned long spinflags;
1657         struct isp1760_qh *qh;
1658         struct isp1760_qtd *qtd;
1659         int retval = 0;
1660
1661         spin_lock_irqsave(&priv->lock, spinflags);
1662         retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1663         if (retval)
1664                 goto out;
1665
1666         qh = urb->ep->hcpriv;
1667         if (!qh) {
1668                 retval = -EINVAL;
1669                 goto out;
1670         }
1671
1672         list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1673                 if (qtd->urb == urb) {
1674                         dequeue_urb_from_qtd(hcd, qh, qtd);
1675                         list_move(&qtd->qtd_list, &qh->qtd_list);
1676                         break;
1677                 }
1678
1679         urb->status = status;
1680         schedule_ptds(hcd);
1681
1682 out:
1683         spin_unlock_irqrestore(&priv->lock, spinflags);
1684         return retval;
1685 }
1686
1687 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1688                 struct usb_host_endpoint *ep)
1689 {
1690         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1691         unsigned long spinflags;
1692         struct isp1760_qh *qh, *qh_iter;
1693         int i;
1694
1695         spin_lock_irqsave(&priv->lock, spinflags);
1696
1697         qh = ep->hcpriv;
1698         if (!qh)
1699                 goto out;
1700
1701         WARN_ON(!list_empty(&qh->qtd_list));
1702
1703         for (i = 0; i < QH_END; i++)
1704                 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1705                         if (qh_iter == qh) {
1706                                 list_del(&qh_iter->qh_list);
1707                                 i = QH_END;
1708                                 break;
1709                         }
1710         qh_free(qh);
1711         ep->hcpriv = NULL;
1712
1713         schedule_ptds(hcd);
1714
1715 out:
1716         spin_unlock_irqrestore(&priv->lock, spinflags);
1717 }
1718
1719 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1720 {
1721         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1722         u32 temp, status = 0;
1723         u32 mask;
1724         int retval = 1;
1725         unsigned long flags;
1726
1727         /* if !PM, root hub timers won't get shut down ... */
1728         if (!HC_IS_RUNNING(hcd->state))
1729                 return 0;
1730
1731         /* init status to no-changes */
1732         buf[0] = 0;
1733         mask = PORT_CSC;
1734
1735         spin_lock_irqsave(&priv->lock, flags);
1736         temp = reg_read32(hcd->regs, HC_PORTSC1);
1737
1738         if (temp & PORT_OWNER) {
1739                 if (temp & PORT_CSC) {
1740                         temp &= ~PORT_CSC;
1741                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1742                         goto done;
1743                 }
1744         }
1745
1746         /*
1747          * Return status information even for ports with OWNER set.
1748          * Otherwise hub_wq wouldn't see the disconnect event when a
1749          * high-speed device is switched over to the companion
1750          * controller by the user.
1751          */
1752
1753         if ((temp & mask) != 0
1754                         || ((temp & PORT_RESUME) != 0
1755                                 && time_after_eq(jiffies,
1756                                         priv->reset_done))) {
1757                 buf [0] |= 1 << (0 + 1);
1758                 status = STS_PCD;
1759         }
1760         /* FIXME autosuspend idle root hubs */
1761 done:
1762         spin_unlock_irqrestore(&priv->lock, flags);
1763         return status ? retval : 0;
1764 }
1765
1766 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1767                 struct usb_hub_descriptor *desc)
1768 {
1769         int ports = HCS_N_PORTS(priv->hcs_params);
1770         u16 temp;
1771
1772         desc->bDescriptorType = 0x29;
1773         /* priv 1.0, 2.3.9 says 20ms max */
1774         desc->bPwrOn2PwrGood = 10;
1775         desc->bHubContrCurrent = 0;
1776
1777         desc->bNbrPorts = ports;
1778         temp = 1 + (ports / 8);
1779         desc->bDescLength = 7 + 2 * temp;
1780
1781         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1782         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1783         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1784
1785         /* per-port overcurrent reporting */
1786         temp = 0x0008;
1787         if (HCS_PPC(priv->hcs_params))
1788                 /* per-port power control */
1789                 temp |= 0x0001;
1790         else
1791                 /* no power switching */
1792                 temp |= 0x0002;
1793         desc->wHubCharacteristics = cpu_to_le16(temp);
1794 }
1795
1796 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1797
1798 static int check_reset_complete(struct usb_hcd *hcd, int index,
1799                 int port_status)
1800 {
1801         if (!(port_status & PORT_CONNECT))
1802                 return port_status;
1803
1804         /* if reset finished and it's still not enabled -- handoff */
1805         if (!(port_status & PORT_PE)) {
1806
1807                 dev_info(hcd->self.controller,
1808                                         "port %d full speed --> companion\n",
1809                                         index + 1);
1810
1811                 port_status |= PORT_OWNER;
1812                 port_status &= ~PORT_RWC_BITS;
1813                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1814
1815         } else
1816                 dev_info(hcd->self.controller, "port %d high speed\n",
1817                                                                 index + 1);
1818
1819         return port_status;
1820 }
1821
1822 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1823                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1824 {
1825         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1826         int ports = HCS_N_PORTS(priv->hcs_params);
1827         u32 temp, status;
1828         unsigned long flags;
1829         int retval = 0;
1830         unsigned selector;
1831
1832         /*
1833          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1834          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1835          * (track current state ourselves) ... blink for diagnostics,
1836          * power, "this is the one", etc.  EHCI spec supports this.
1837          */
1838
1839         spin_lock_irqsave(&priv->lock, flags);
1840         switch (typeReq) {
1841         case ClearHubFeature:
1842                 switch (wValue) {
1843                 case C_HUB_LOCAL_POWER:
1844                 case C_HUB_OVER_CURRENT:
1845                         /* no hub-wide feature/status flags */
1846                         break;
1847                 default:
1848                         goto error;
1849                 }
1850                 break;
1851         case ClearPortFeature:
1852                 if (!wIndex || wIndex > ports)
1853                         goto error;
1854                 wIndex--;
1855                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1856
1857                 /*
1858                  * Even if OWNER is set, so the port is owned by the
1859                  * companion controller, hub_wq needs to be able to clear
1860                  * the port-change status bits (especially
1861                  * USB_PORT_STAT_C_CONNECTION).
1862                  */
1863
1864                 switch (wValue) {
1865                 case USB_PORT_FEAT_ENABLE:
1866                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1867                         break;
1868                 case USB_PORT_FEAT_C_ENABLE:
1869                         /* XXX error? */
1870                         break;
1871                 case USB_PORT_FEAT_SUSPEND:
1872                         if (temp & PORT_RESET)
1873                                 goto error;
1874
1875                         if (temp & PORT_SUSPEND) {
1876                                 if ((temp & PORT_PE) == 0)
1877                                         goto error;
1878                                 /* resume signaling for 20 msec */
1879                                 temp &= ~(PORT_RWC_BITS);
1880                                 reg_write32(hcd->regs, HC_PORTSC1,
1881                                                         temp | PORT_RESUME);
1882                                 priv->reset_done = jiffies +
1883                                         msecs_to_jiffies(20);
1884                         }
1885                         break;
1886                 case USB_PORT_FEAT_C_SUSPEND:
1887                         /* we auto-clear this feature */
1888                         break;
1889                 case USB_PORT_FEAT_POWER:
1890                         if (HCS_PPC(priv->hcs_params))
1891                                 reg_write32(hcd->regs, HC_PORTSC1,
1892                                                         temp & ~PORT_POWER);
1893                         break;
1894                 case USB_PORT_FEAT_C_CONNECTION:
1895                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1896                         break;
1897                 case USB_PORT_FEAT_C_OVER_CURRENT:
1898                         /* XXX error ?*/
1899                         break;
1900                 case USB_PORT_FEAT_C_RESET:
1901                         /* GetPortStatus clears reset */
1902                         break;
1903                 default:
1904                         goto error;
1905                 }
1906                 reg_read32(hcd->regs, HC_USBCMD);
1907                 break;
1908         case GetHubDescriptor:
1909                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1910                         buf);
1911                 break;
1912         case GetHubStatus:
1913                 /* no hub-wide feature/status flags */
1914                 memset(buf, 0, 4);
1915                 break;
1916         case GetPortStatus:
1917                 if (!wIndex || wIndex > ports)
1918                         goto error;
1919                 wIndex--;
1920                 status = 0;
1921                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1922
1923                 /* wPortChange bits */
1924                 if (temp & PORT_CSC)
1925                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1926
1927
1928                 /* whoever resumes must GetPortStatus to complete it!! */
1929                 if (temp & PORT_RESUME) {
1930                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1931
1932                         /* Remote Wakeup received? */
1933                         if (!priv->reset_done) {
1934                                 /* resume signaling for 20 msec */
1935                                 priv->reset_done = jiffies
1936                                                 + msecs_to_jiffies(20);
1937                                 /* check the port again */
1938                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1939                         }
1940
1941                         /* resume completed? */
1942                         else if (time_after_eq(jiffies,
1943                                         priv->reset_done)) {
1944                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1945                                 priv->reset_done = 0;
1946
1947                                 /* stop resume signaling */
1948                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1949                                 reg_write32(hcd->regs, HC_PORTSC1,
1950                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1951                                 retval = handshake(hcd, HC_PORTSC1,
1952                                            PORT_RESUME, 0, 2000 /* 2msec */);
1953                                 if (retval != 0) {
1954                                         dev_err(hcd->self.controller,
1955                                                 "port %d resume error %d\n",
1956                                                 wIndex + 1, retval);
1957                                         goto error;
1958                                 }
1959                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1960                         }
1961                 }
1962
1963                 /* whoever resets must GetPortStatus to complete it!! */
1964                 if ((temp & PORT_RESET)
1965                                 && time_after_eq(jiffies,
1966                                         priv->reset_done)) {
1967                         status |= USB_PORT_STAT_C_RESET << 16;
1968                         priv->reset_done = 0;
1969
1970                         /* force reset to complete */
1971                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1972                         /* REVISIT:  some hardware needs 550+ usec to clear
1973                          * this bit; seems too long to spin routinely...
1974                          */
1975                         retval = handshake(hcd, HC_PORTSC1,
1976                                         PORT_RESET, 0, 750);
1977                         if (retval != 0) {
1978                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1979                                                 wIndex + 1, retval);
1980                                 goto error;
1981                         }
1982
1983                         /* see what we found out */
1984                         temp = check_reset_complete(hcd, wIndex,
1985                                         reg_read32(hcd->regs, HC_PORTSC1));
1986                 }
1987                 /*
1988                  * Even if OWNER is set, there's no harm letting hub_wq
1989                  * see the wPortStatus values (they should all be 0 except
1990                  * for PORT_POWER anyway).
1991                  */
1992
1993                 if (temp & PORT_OWNER)
1994                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1995
1996                 if (temp & PORT_CONNECT) {
1997                         status |= USB_PORT_STAT_CONNECTION;
1998                         /* status may be from integrated TT */
1999                         status |= USB_PORT_STAT_HIGH_SPEED;
2000                 }
2001                 if (temp & PORT_PE)
2002                         status |= USB_PORT_STAT_ENABLE;
2003                 if (temp & (PORT_SUSPEND|PORT_RESUME))
2004                         status |= USB_PORT_STAT_SUSPEND;
2005                 if (temp & PORT_RESET)
2006                         status |= USB_PORT_STAT_RESET;
2007                 if (temp & PORT_POWER)
2008                         status |= USB_PORT_STAT_POWER;
2009
2010                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2011                 break;
2012         case SetHubFeature:
2013                 switch (wValue) {
2014                 case C_HUB_LOCAL_POWER:
2015                 case C_HUB_OVER_CURRENT:
2016                         /* no hub-wide feature/status flags */
2017                         break;
2018                 default:
2019                         goto error;
2020                 }
2021                 break;
2022         case SetPortFeature:
2023                 selector = wIndex >> 8;
2024                 wIndex &= 0xff;
2025                 if (!wIndex || wIndex > ports)
2026                         goto error;
2027                 wIndex--;
2028                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2029                 if (temp & PORT_OWNER)
2030                         break;
2031
2032 /*              temp &= ~PORT_RWC_BITS; */
2033                 switch (wValue) {
2034                 case USB_PORT_FEAT_ENABLE:
2035                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2036                         break;
2037
2038                 case USB_PORT_FEAT_SUSPEND:
2039                         if ((temp & PORT_PE) == 0
2040                                         || (temp & PORT_RESET) != 0)
2041                                 goto error;
2042
2043                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2044                         break;
2045                 case USB_PORT_FEAT_POWER:
2046                         if (HCS_PPC(priv->hcs_params))
2047                                 reg_write32(hcd->regs, HC_PORTSC1,
2048                                                         temp | PORT_POWER);
2049                         break;
2050                 case USB_PORT_FEAT_RESET:
2051                         if (temp & PORT_RESUME)
2052                                 goto error;
2053                         /* line status bits may report this as low speed,
2054                          * which can be fine if this root hub has a
2055                          * transaction translator built in.
2056                          */
2057                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2058                                         && PORT_USB11(temp)) {
2059                                 temp |= PORT_OWNER;
2060                         } else {
2061                                 temp |= PORT_RESET;
2062                                 temp &= ~PORT_PE;
2063
2064                                 /*
2065                                  * caller must wait, then call GetPortStatus
2066                                  * usb 2.0 spec says 50 ms resets on root
2067                                  */
2068                                 priv->reset_done = jiffies +
2069                                         msecs_to_jiffies(50);
2070                         }
2071                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2072                         break;
2073                 default:
2074                         goto error;
2075                 }
2076                 reg_read32(hcd->regs, HC_USBCMD);
2077                 break;
2078
2079         default:
2080 error:
2081                 /* "stall" on error */
2082                 retval = -EPIPE;
2083         }
2084         spin_unlock_irqrestore(&priv->lock, flags);
2085         return retval;
2086 }
2087
2088 static int isp1760_get_frame(struct usb_hcd *hcd)
2089 {
2090         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2091         u32 fr;
2092
2093         fr = reg_read32(hcd->regs, HC_FRINDEX);
2094         return (fr >> 3) % priv->periodic_size;
2095 }
2096
2097 static void isp1760_stop(struct usb_hcd *hcd)
2098 {
2099         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2100         u32 temp;
2101
2102         del_timer(&errata2_timer);
2103
2104         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2105                         NULL, 0);
2106         mdelay(20);
2107
2108         spin_lock_irq(&priv->lock);
2109         ehci_reset(hcd);
2110         /* Disable IRQ */
2111         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2112         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2113         spin_unlock_irq(&priv->lock);
2114
2115         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2116 }
2117
2118 static void isp1760_shutdown(struct usb_hcd *hcd)
2119 {
2120         u32 command, temp;
2121
2122         isp1760_stop(hcd);
2123         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2124         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2125
2126         command = reg_read32(hcd->regs, HC_USBCMD);
2127         command &= ~CMD_RUN;
2128         reg_write32(hcd->regs, HC_USBCMD, command);
2129 }
2130
2131 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2132                                                 struct usb_host_endpoint *ep)
2133 {
2134         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2135         struct isp1760_qh *qh = ep->hcpriv;
2136         unsigned long spinflags;
2137
2138         if (!qh)
2139                 return;
2140
2141         spin_lock_irqsave(&priv->lock, spinflags);
2142         qh->tt_buffer_dirty = 0;
2143         schedule_ptds(hcd);
2144         spin_unlock_irqrestore(&priv->lock, spinflags);
2145 }
2146
2147
2148 static const struct hc_driver isp1760_hc_driver = {
2149         .description            = "isp1760-hcd",
2150         .product_desc           = "NXP ISP1760 USB Host Controller",
2151         .hcd_priv_size          = sizeof(struct isp1760_hcd *),
2152         .irq                    = isp1760_irq,
2153         .flags                  = HCD_MEMORY | HCD_USB2,
2154         .reset                  = isp1760_hc_setup,
2155         .start                  = isp1760_run,
2156         .stop                   = isp1760_stop,
2157         .shutdown               = isp1760_shutdown,
2158         .urb_enqueue            = isp1760_urb_enqueue,
2159         .urb_dequeue            = isp1760_urb_dequeue,
2160         .endpoint_disable       = isp1760_endpoint_disable,
2161         .get_frame_number       = isp1760_get_frame,
2162         .hub_status_data        = isp1760_hub_status_data,
2163         .hub_control            = isp1760_hub_control,
2164         .clear_tt_buffer_complete       = isp1760_clear_tt_buffer_complete,
2165 };
2166
2167 int __init isp1760_init_kmem_once(void)
2168 {
2169         urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2170                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2171                         SLAB_MEM_SPREAD, NULL);
2172
2173         if (!urb_listitem_cachep)
2174                 return -ENOMEM;
2175
2176         qtd_cachep = kmem_cache_create("isp1760_qtd",
2177                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2178                         SLAB_MEM_SPREAD, NULL);
2179
2180         if (!qtd_cachep)
2181                 return -ENOMEM;
2182
2183         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2184                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2185
2186         if (!qh_cachep) {
2187                 kmem_cache_destroy(qtd_cachep);
2188                 return -ENOMEM;
2189         }
2190
2191         return 0;
2192 }
2193
2194 void isp1760_deinit_kmem_cache(void)
2195 {
2196         kmem_cache_destroy(qtd_cachep);
2197         kmem_cache_destroy(qh_cachep);
2198         kmem_cache_destroy(urb_listitem_cachep);
2199 }
2200
2201 int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs,
2202                          struct resource *mem, int irq, unsigned long irqflags,
2203                          struct device *dev)
2204 {
2205         struct usb_hcd *hcd;
2206         int ret;
2207
2208         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2209         if (!hcd)
2210                 return -ENOMEM;
2211
2212         *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2213
2214         priv->hcd = hcd;
2215
2216         init_memory(priv);
2217
2218         hcd->irq = irq;
2219         hcd->regs = regs;
2220         hcd->rsrc_start = mem->start;
2221         hcd->rsrc_len = resource_size(mem);
2222
2223         ret = usb_add_hcd(hcd, irq, irqflags);
2224         if (ret)
2225                 goto error;
2226
2227         device_wakeup_enable(hcd->self.controller);
2228
2229         return 0;
2230
2231 error:
2232         usb_put_hcd(hcd);
2233         return ret;
2234 }
2235
2236 void isp1760_hcd_unregister(struct isp1760_hcd *priv)
2237 {
2238         usb_remove_hcd(priv->hcd);
2239         usb_put_hcd(priv->hcd);
2240 }