drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  12  *
  13  */
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/list.h>
  19 #include <linux/usb.h>
  20 #include <linux/usb/hcd.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/timer.h>
  26 #include <asm/unaligned.h>
  27 #include <asm/cacheflush.h>
  28
  29 #include "isp1760-hcd.h"
  30 #include "isp1760-regs.h"
  31
  32 static struct kmem_cache *qtd_cachep;
  33 static struct kmem_cache *qh_cachep;
  34 static struct kmem_cache *urb_listitem_cachep;
  35
  36 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
  37                 struct isp1760_qtd *qtd);
  38
  39 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  40 {
  41         return *(struct isp1760_hcd **)hcd->hcd_priv;
  42 }
  43
  44 /* urb state*/
  45 #define DELETE_URB              (0x0008)
  46 #define NO_TRANSFER_ACTIVE      (0xffffffff)
  47
  48 /* Philips Proprietary Transfer Descriptor (PTD) */
  49 typedef __u32 __bitwise __dw;
  50 struct ptd {
  51         __dw dw0;
  52         __dw dw1;
  53         __dw dw2;
  54         __dw dw3;
  55         __dw dw4;
  56         __dw dw5;
  57         __dw dw6;
  58         __dw dw7;
  59 };
  60 #define PTD_OFFSET              0x0400
  61 #define ISO_PTD_OFFSET          0x0400
  62 #define INT_PTD_OFFSET          0x0800
  63 #define ATL_PTD_OFFSET          0x0c00
  64 #define PAYLOAD_OFFSET          0x1000
  65
  66
  67 /* ATL */
  68 /* DW0 */
  69 #define DW0_VALID_BIT                   1
  70 #define FROM_DW0_VALID(x)               ((x) & 0x01)
  71 #define TO_DW0_LENGTH(x)                (((u32) x) << 3)
  72 #define TO_DW0_MAXPACKET(x)             (((u32) x) << 18)
  73 #define TO_DW0_MULTI(x)                 (((u32) x) << 29)
  74 #define TO_DW0_ENDPOINT(x)              (((u32) x) << 31)
  75 /* DW1 */
  76 #define TO_DW1_DEVICE_ADDR(x)           (((u32) x) << 3)
  77 #define TO_DW1_PID_TOKEN(x)             (((u32) x) << 10)
  78 #define DW1_TRANS_BULK                  ((u32) 2 << 12)
  79 #define DW1_TRANS_INT                   ((u32) 3 << 12)
  80 #define DW1_TRANS_SPLIT                 ((u32) 1 << 14)
  81 #define DW1_SE_USB_LOSPEED              ((u32) 2 << 16)
  82 #define TO_DW1_PORT_NUM(x)              (((u32) x) << 18)
  83 #define TO_DW1_HUB_NUM(x)               (((u32) x) << 25)
  84 /* DW2 */
  85 #define TO_DW2_DATA_START_ADDR(x)       (((u32) x) << 8)
  86 #define TO_DW2_RL(x)                    ((x) << 25)
  87 #define FROM_DW2_RL(x)                  (((x) >> 25) & 0xf)
  88 /* DW3 */
  89 #define FROM_DW3_NRBYTESTRANSFERRED(x)          ((x) & 0x7fff)
  90 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x)      ((x) & 0x07ff)
  91 #define TO_DW3_NAKCOUNT(x)              ((x) << 19)
  92 #define FROM_DW3_NAKCOUNT(x)            (((x) >> 19) & 0xf)
  93 #define TO_DW3_CERR(x)                  ((x) << 23)
  94 #define FROM_DW3_CERR(x)                (((x) >> 23) & 0x3)
  95 #define TO_DW3_DATA_TOGGLE(x)           ((x) << 25)
  96 #define FROM_DW3_DATA_TOGGLE(x)         (((x) >> 25) & 0x1)
  97 #define TO_DW3_PING(x)                  ((x) << 26)
  98 #define FROM_DW3_PING(x)                (((x) >> 26) & 0x1)
  99 #define DW3_ERROR_BIT                   (1 << 28)
 100 #define DW3_BABBLE_BIT                  (1 << 29)
 101 #define DW3_HALT_BIT                    (1 << 30)
 102 #define DW3_ACTIVE_BIT                  (1 << 31)
 103 #define FROM_DW3_ACTIVE(x)              (((x) >> 31) & 0x01)
 104
 105 #define INT_UNDERRUN                    (1 << 2)
 106 #define INT_BABBLE                      (1 << 1)
 107 #define INT_EXACT                       (1 << 0)
 108
 109 #define SETUP_PID       (2)
 110 #define IN_PID          (1)
 111 #define OUT_PID         (0)
 112
 113 /* Errata 1 */
 114 #define RL_COUNTER      (0)
 115 #define NAK_COUNTER     (0)
 116 #define ERR_COUNTER     (2)
 117
 118 struct isp1760_qtd {
 119         u8 packet_type;
 120         void *data_buffer;
 121         u32 payload_addr;
 122
 123         /* the rest is HCD-private */
 124         struct list_head qtd_list;
 125         struct urb *urb;
 126         size_t length;
 127         size_t actual_length;
 128
 129         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
 130         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
 131         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
 132                                 interrupt handler may touch this qtd! */
 133         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
 134         /* QTD_RETIRE:          transfer error/abort qtd */
 135 #define QTD_ENQUEUED            0
 136 #define QTD_PAYLOAD_ALLOC       1
 137 #define QTD_XFER_STARTED        2
 138 #define QTD_XFER_COMPLETE       3
 139 #define QTD_RETIRE              4
 140         u32 status;
 141 };
 142
 143 /* Queue head, one for each active endpoint */
 144 struct isp1760_qh {
 145         struct list_head qh_list;
 146         struct list_head qtd_list;
 147         u32 toggle;
 148         u32 ping;
 149         int slot;
 150         int tt_buffer_dirty;    /* See USB2.0 spec section 11.17.5 */
 151 };
 152
 153 struct urb_listitem {
 154         struct list_head urb_list;
 155         struct urb *urb;
 156 };
 157
 158 /*
 159  * Access functions for isp176x registers (addresses 0..0x03FF).
 160  */
 161 static u32 reg_read32(void __iomem *base, u32 reg)
 162 {
 163         return readl(base + reg);
 164 }
 165
 166 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 167 {
 168         writel(val, base + reg);
 169 }
 170
 171 /*
 172  * Access functions for isp176x memory (offset >= 0x0400).
 173  *
 174  * bank_reads8() reads memory locations prefetched by an earlier write to
 175  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 176  * bank optimizations, you should use the more generic mem_reads8() below.
 177  *
 178  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 179  * below.
 180  *
 181  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 182  * doesn't quite work because some people have to enforce 32-bit access
 183  */
 184 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 185                                                         __u32 *dst, u32 bytes)
 186 {
 187         __u32 __iomem *src;
 188         u32 val;
 189         __u8 *src_byteptr;
 190         __u8 *dst_byteptr;
 191
 192         src = src_base + (bank_addr | src_offset);
 193
 194         if (src_offset < PAYLOAD_OFFSET) {
 195                 while (bytes >= 4) {
 196                         *dst = le32_to_cpu(__raw_readl(src));
 197                         bytes -= 4;
 198                         src++;
 199                         dst++;
 200                 }
 201         } else {
 202                 while (bytes >= 4) {
 203                         *dst = __raw_readl(src);
 204                         bytes -= 4;
 205                         src++;
 206                         dst++;
 207                 }
 208         }
 209
 210         if (!bytes)
 211                 return;
 212
 213         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 214          * allocated.
 215          */
 216         if (src_offset < PAYLOAD_OFFSET)
 217                 val = le32_to_cpu(__raw_readl(src));
 218         else
 219                 val = __raw_readl(src);
 220
 221         dst_byteptr = (void *) dst;
 222         src_byteptr = (void *) &val;
 223         while (bytes > 0) {
 224                 *dst_byteptr = *src_byteptr;
 225                 dst_byteptr++;
 226                 src_byteptr++;
 227                 bytes--;
 228         }
 229 }
 230
 231 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 232                                                                 u32 bytes)
 233 {
 234         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 235         ndelay(90);
 236         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 237 }
 238
 239 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 240                                                 __u32 const *src, u32 bytes)
 241 {
 242         __u32 __iomem *dst;
 243
 244         dst = dst_base + dst_offset;
 245
 246         if (dst_offset < PAYLOAD_OFFSET) {
 247                 while (bytes >= 4) {
 248                         __raw_writel(cpu_to_le32(*src), dst);
 249                         bytes -= 4;
 250                         src++;
 251                         dst++;
 252                 }
 253         } else {
 254                 while (bytes >= 4) {
 255                         __raw_writel(*src, dst);
 256                         bytes -= 4;
 257                         src++;
 258                         dst++;
 259                 }
 260         }
 261
 262         if (!bytes)
 263                 return;
 264         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 265          * extra bytes should not be read by the HW.
 266          */
 267
 268         if (dst_offset < PAYLOAD_OFFSET)
 269                 __raw_writel(cpu_to_le32(*src), dst);
 270         else
 271                 __raw_writel(*src, dst);
 272 }
 273
 274 /*
 275  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 276  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 277  */
 278 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 279                                                                 struct ptd *ptd)
 280 {
 281         reg_write32(base, HC_MEMORY_REG,
 282                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 283         ndelay(90);
 284         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 285                                                 (void *) ptd, sizeof(*ptd));
 286 }
 287
 288 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 289                                                                 struct ptd *ptd)
 290 {
 291         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 292                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 293         /* Make sure dw0 gets written last (after other dw's and after payload)
 294            since it contains the enable bit */
 295         wmb();
 296         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 297                                                         sizeof(ptd->dw0));
 298 }
 299
 300
 301 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 302 static void init_memory(struct isp1760_hcd *priv)
 303 {
 304         int i, curr;
 305         u32 payload_addr;
 306
 307         payload_addr = PAYLOAD_OFFSET;
 308         for (i = 0; i < BLOCK_1_NUM; i++) {
 309                 priv->memory_pool[i].start = payload_addr;
 310                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 311                 priv->memory_pool[i].free = 1;
 312                 payload_addr += priv->memory_pool[i].size;
 313         }
 314
 315         curr = i;
 316         for (i = 0; i < BLOCK_2_NUM; i++) {
 317                 priv->memory_pool[curr + i].start = payload_addr;
 318                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 319                 priv->memory_pool[curr + i].free = 1;
 320                 payload_addr += priv->memory_pool[curr + i].size;
 321         }
 322
 323         curr = i;
 324         for (i = 0; i < BLOCK_3_NUM; i++) {
 325                 priv->memory_pool[curr + i].start = payload_addr;
 326                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 327                 priv->memory_pool[curr + i].free = 1;
 328                 payload_addr += priv->memory_pool[curr + i].size;
 329         }
 330
 331         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 332 }
 333
 334 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 335 {
 336         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 337         int i;
 338
 339         WARN_ON(qtd->payload_addr);
 340
 341         if (!qtd->length)
 342                 return;
 343
 344         for (i = 0; i < BLOCKS; i++) {
 345                 if (priv->memory_pool[i].size >= qtd->length &&
 346                                 priv->memory_pool[i].free) {
 347                         priv->memory_pool[i].free = 0;
 348                         qtd->payload_addr = priv->memory_pool[i].start;
 349                         return;
 350                 }
 351         }
 352 }
 353
 354 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 355 {
 356         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 357         int i;
 358
 359         if (!qtd->payload_addr)
 360                 return;
 361
 362         for (i = 0; i < BLOCKS; i++) {
 363                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 364                         WARN_ON(priv->memory_pool[i].free);
 365                         priv->memory_pool[i].free = 1;
 366                         qtd->payload_addr = 0;
 367                         return;
 368                 }
 369         }
 370
 371         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 372                                                 __func__, qtd->payload_addr);
 373         WARN_ON(1);
 374         qtd->payload_addr = 0;
 375 }
 376
 377 static int handshake(struct usb_hcd *hcd, u32 reg,
 378                       u32 mask, u32 done, int usec)
 379 {
 380         u32 result;
 381
 382         do {
 383                 result = reg_read32(hcd->regs, reg);
 384                 if (result == ~0)
 385                         return -ENODEV;
 386                 result &= mask;
 387                 if (result == done)
 388                         return 0;
 389                 udelay(1);
 390                 usec--;
 391         } while (usec > 0);
 392         return -ETIMEDOUT;
 393 }
 394
 395 /* reset a non-running (STS_HALT == 1) controller */
 396 static int ehci_reset(struct usb_hcd *hcd)
 397 {
 398         int retval;
 399         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 400
 401         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 402
 403         command |= CMD_RESET;
 404         reg_write32(hcd->regs, HC_USBCMD, command);
 405         hcd->state = HC_STATE_HALT;
 406         priv->next_statechange = jiffies;
 407         retval = handshake(hcd, HC_USBCMD,
 408                             CMD_RESET, 0, 250 * 1000);
 409         return retval;
 410 }
 411
 412 static struct isp1760_qh *qh_alloc(gfp_t flags)
 413 {
 414         struct isp1760_qh *qh;
 415
 416         qh = kmem_cache_zalloc(qh_cachep, flags);
 417         if (!qh)
 418                 return NULL;
 419
 420         INIT_LIST_HEAD(&qh->qh_list);
 421         INIT_LIST_HEAD(&qh->qtd_list);
 422         qh->slot = -1;
 423
 424         return qh;
 425 }
 426
 427 static void qh_free(struct isp1760_qh *qh)
 428 {
 429         WARN_ON(!list_empty(&qh->qtd_list));
 430         WARN_ON(qh->slot > -1);
 431         kmem_cache_free(qh_cachep, qh);
 432 }
 433
 434 /* one-time init, only for memory state */
 435 static int priv_init(struct usb_hcd *hcd)
 436 {
 437         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 438         u32                     hcc_params;
 439         int i;
 440
 441         spin_lock_init(&priv->lock);
 442
 443         for (i = 0; i < QH_END; i++)
 444                 INIT_LIST_HEAD(&priv->qh_list[i]);
 445
 446         /*
 447          * hw default: 1K periodic list heads, one per frame.
 448          * periodic_size can shrink by USBCMD update if hcc_params allows.
 449          */
 450         priv->periodic_size = DEFAULT_I_TDPS;
 451
 452         /* controllers may cache some of the periodic schedule ... */
 453         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 454         /* full frame cache */
 455         if (HCC_ISOC_CACHE(hcc_params))
 456                 priv->i_thresh = 8;
 457         else /* N microframes cached */
 458                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 459
 460         return 0;
 461 }
 462
 463 static int isp1760_hc_setup(struct usb_hcd *hcd)
 464 {
 465         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 466         int result;
 467         u32 scratch, hwmode;
 468
 469         /* low-level chip reset */
 470         if (priv->rst_gpio) {
 471                 gpiod_set_value_cansleep(priv->rst_gpio, 1);
 472                 mdelay(50);
 473                 gpiod_set_value_cansleep(priv->rst_gpio, 0);
 474         }
 475
 476         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 477         hwmode = HW_DATA_BUS_32BIT;
 478
 479         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 480                 hwmode &= ~HW_DATA_BUS_32BIT;
 481         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 482                 hwmode |= HW_ANA_DIGI_OC;
 483         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 484                 hwmode |= HW_DACK_POL_HIGH;
 485         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 486                 hwmode |= HW_DREQ_POL_HIGH;
 487         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 488                 hwmode |= HW_INTR_HIGH_ACT;
 489         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 490                 hwmode |= HW_INTR_EDGE_TRIG;
 491
 492         /*
 493          * We have to set this first in case we're in 16-bit mode.
 494          * Write it twice to ensure correct upper bits if switching
 495          * to 16-bit mode.
 496          */
 497         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 498         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 499
 500         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 501         /* Change bus pattern */
 502         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 503         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 504         if (scratch != 0xdeadbabe) {
 505                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 506                 return -ENODEV;
 507         }
 508
 509         /* pre reset */
 510         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 511         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 512         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 513         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 514
 515         /* reset */
 516         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 517         mdelay(100);
 518
 519         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 520         mdelay(100);
 521
 522         result = ehci_reset(hcd);
 523         if (result)
 524                 return result;
 525
 526         /* Step 11 passed */
 527
 528         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 529                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 530                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 531                            "analog" : "digital");
 532
 533         /* ATL reset */
 534         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 535         mdelay(10);
 536         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 537
 538         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 539
 540         /*
 541          * PORT 1 Control register of the ISP1760 is the OTG control
 542          * register on ISP1761. Since there is no OTG or device controller
 543          * support in this driver, we use port 1 as a "normal" USB host port on
 544          * both chips.
 545          */
 546         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 547         mdelay(10);
 548
 549         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 550
 551         return priv_init(hcd);
 552 }
 553
 554 static u32 base_to_chip(u32 base)
 555 {
 556         return ((base - 0x400) >> 3);
 557 }
 558
 559 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 560 {
 561         struct urb *urb;
 562
 563         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 564                 return 1;
 565
 566         urb = qtd->urb;
 567         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 568         return (qtd->urb != urb);
 569 }
 570
 571 /* magic numbers that can affect system performance */
 572 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 573 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 574 #define EHCI_TUNE_RL_TT         0
 575 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 576 #define EHCI_TUNE_MULT_TT       1
 577 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 578
 579 static void create_ptd_atl(struct isp1760_qh *qh,
 580                         struct isp1760_qtd *qtd, struct ptd *ptd)
 581 {
 582         u32 maxpacket;
 583         u32 multi;
 584         u32 rl = RL_COUNTER;
 585         u32 nak = NAK_COUNTER;
 586
 587         memset(ptd, 0, sizeof(*ptd));
 588
 589         /* according to 3.6.2, max packet len can not be > 0x400 */
 590         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 591                                                 usb_pipeout(qtd->urb->pipe));
 592         multi =  1 + ((maxpacket >> 11) & 0x3);
 593         maxpacket &= 0x7ff;
 594
 595         /* DW0 */
 596         ptd->dw0 = DW0_VALID_BIT;
 597         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 598         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 599         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 600
 601         /* DW1 */
 602         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 603         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 604         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 605
 606         if (usb_pipebulk(qtd->urb->pipe))
 607                 ptd->dw1 |= DW1_TRANS_BULK;
 608         else if  (usb_pipeint(qtd->urb->pipe))
 609                 ptd->dw1 |= DW1_TRANS_INT;
 610
 611         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 612                 /* split transaction */
 613
 614                 ptd->dw1 |= DW1_TRANS_SPLIT;
 615                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 616                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 617
 618                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 619                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 620
 621                 /* SE bit for Split INT transfers */
 622                 if (usb_pipeint(qtd->urb->pipe) &&
 623                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 624                         ptd->dw1 |= 2 << 16;
 625
 626                 rl = 0;
 627                 nak = 0;
 628         } else {
 629                 ptd->dw0 |= TO_DW0_MULTI(multi);
 630                 if (usb_pipecontrol(qtd->urb->pipe) ||
 631                                                 usb_pipebulk(qtd->urb->pipe))
 632                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 633         }
 634         /* DW2 */
 635         ptd->dw2 = 0;
 636         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 637         ptd->dw2 |= TO_DW2_RL(rl);
 638
 639         /* DW3 */
 640         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 641         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 642         if (usb_pipecontrol(qtd->urb->pipe)) {
 643                 if (qtd->data_buffer == qtd->urb->setup_packet)
 644                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 645                 else if (last_qtd_of_urb(qtd, qh))
 646                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 647         }
 648
 649         ptd->dw3 |= DW3_ACTIVE_BIT;
 650         /* Cerr */
 651         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 652 }
 653
 654 static void transform_add_int(struct isp1760_qh *qh,
 655                         struct isp1760_qtd *qtd, struct ptd *ptd)
 656 {
 657         u32 usof;
 658         u32 period;
 659
 660         /*
 661          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 662          * the algorithm from the original Philips driver code, which was
 663          * pretty much used in this driver before as well, is quite horrendous
 664          * and, i believe, incorrect. The code below follows the datasheet and
 665          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 666          * more reliable this way (fingers crossed...).
 667          */
 668
 669         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 670                 /* urb->interval is in units of microframes (1/8 ms) */
 671                 period = qtd->urb->interval >> 3;
 672
 673                 if (qtd->urb->interval > 4)
 674                         usof = 0x01; /* One bit set =>
 675                                                 interval 1 ms * uFrame-match */
 676                 else if (qtd->urb->interval > 2)
 677                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 678                 else if (qtd->urb->interval > 1)
 679                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 680                 else
 681                         usof = 0xff; /* All bits set => interval 1/8 ms */
 682         } else {
 683                 /* urb->interval is in units of frames (1 ms) */
 684                 period = qtd->urb->interval;
 685                 usof = 0x0f;            /* Execute Start Split on any of the
 686                                            four first uFrames */
 687
 688                 /*
 689                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 690                  * complete split needs to be sent. Valid only for IN." Also,
 691                  * "All bits can be set to one for every transfer." (p 82,
 692                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 693                  * that number come from? 0xff seems to work fine...
 694                  */
 695                 /* ptd->dw5 = 0x1c; */
 696                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 697         }
 698
 699         period = period >> 1;/* Ensure equal or shorter period than requested */
 700         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 701
 702         ptd->dw2 |= period;
 703         ptd->dw4 = usof;
 704 }
 705
 706 static void create_ptd_int(struct isp1760_qh *qh,
 707                         struct isp1760_qtd *qtd, struct ptd *ptd)
 708 {
 709         create_ptd_atl(qh, qtd, ptd);
 710         transform_add_int(qh, qtd, ptd);
 711 }
 712
 713 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 714 __releases(priv->lock)
 715 __acquires(priv->lock)
 716 {
 717         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 718
 719         if (!urb->unlinked) {
 720                 if (urb->status == -EINPROGRESS)
 721                         urb->status = 0;
 722         }
 723
 724         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 725                 void *ptr;
 726                 for (ptr = urb->transfer_buffer;
 727                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 728                      ptr += PAGE_SIZE)
 729                         flush_dcache_page(virt_to_page(ptr));
 730         }
 731
 732         /* complete() can reenter this HCD */
 733         usb_hcd_unlink_urb_from_ep(hcd, urb);
 734         spin_unlock(&priv->lock);
 735         usb_hcd_giveback_urb(hcd, urb, urb->status);
 736         spin_lock(&priv->lock);
 737 }
 738
 739 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 740                                                                 u8 packet_type)
 741 {
 742         struct isp1760_qtd *qtd;
 743
 744         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 745         if (!qtd)
 746                 return NULL;
 747
 748         INIT_LIST_HEAD(&qtd->qtd_list);
 749         qtd->urb = urb;
 750         qtd->packet_type = packet_type;
 751         qtd->status = QTD_ENQUEUED;
 752         qtd->actual_length = 0;
 753
 754         return qtd;
 755 }
 756
 757 static void qtd_free(struct isp1760_qtd *qtd)
 758 {
 759         WARN_ON(qtd->payload_addr);
 760         kmem_cache_free(qtd_cachep, qtd);
 761 }
 762
 763 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 764                                 struct isp1760_slotinfo *slots,
 765                                 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
 766                                 struct ptd *ptd)
 767 {
 768         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 769         int skip_map;
 770
 771         WARN_ON((slot < 0) || (slot > 31));
 772         WARN_ON(qtd->length && !qtd->payload_addr);
 773         WARN_ON(slots[slot].qtd);
 774         WARN_ON(slots[slot].qh);
 775         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 776
 777         /* Make sure done map has not triggered from some unlinked transfer */
 778         if (ptd_offset == ATL_PTD_OFFSET) {
 779                 priv->atl_done_map |= reg_read32(hcd->regs,
 780                                                 HC_ATL_PTD_DONEMAP_REG);
 781                 priv->atl_done_map &= ~(1 << slot);
 782         } else {
 783                 priv->int_done_map |= reg_read32(hcd->regs,
 784                                                 HC_INT_PTD_DONEMAP_REG);
 785                 priv->int_done_map &= ~(1 << slot);
 786         }
 787
 788         qh->slot = slot;
 789         qtd->status = QTD_XFER_STARTED;
 790         slots[slot].timestamp = jiffies;
 791         slots[slot].qtd = qtd;
 792         slots[slot].qh = qh;
 793         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 794
 795         if (ptd_offset == ATL_PTD_OFFSET) {
 796                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 797                 skip_map &= ~(1 << qh->slot);
 798                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 799         } else {
 800                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 801                 skip_map &= ~(1 << qh->slot);
 802                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 803         }
 804 }
 805
 806 static int is_short_bulk(struct isp1760_qtd *qtd)
 807 {
 808         return (usb_pipebulk(qtd->urb->pipe) &&
 809                                         (qtd->actual_length < qtd->length));
 810 }
 811
 812 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 813                                                 struct list_head *urb_list)
 814 {
 815         int last_qtd;
 816         struct isp1760_qtd *qtd, *qtd_next;
 817         struct urb_listitem *urb_listitem;
 818
 819         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 820                 if (qtd->status < QTD_XFER_COMPLETE)
 821                         break;
 822
 823                 last_qtd = last_qtd_of_urb(qtd, qh);
 824
 825                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 826                         qtd_next->status = QTD_RETIRE;
 827
 828                 if (qtd->status == QTD_XFER_COMPLETE) {
 829                         if (qtd->actual_length) {
 830                                 switch (qtd->packet_type) {
 831                                 case IN_PID:
 832                                         mem_reads8(hcd->regs, qtd->payload_addr,
 833                                                         qtd->data_buffer,
 834                                                         qtd->actual_length);
 835                                         /* Fall through (?) */
 836                                 case OUT_PID:
 837                                         qtd->urb->actual_length +=
 838                                                         qtd->actual_length;
 839                                         /* Fall through ... */
 840                                 case SETUP_PID:
 841                                         break;
 842                                 }
 843                         }
 844
 845                         if (is_short_bulk(qtd)) {
 846                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 847                                         qtd->urb->status = -EREMOTEIO;
 848                                 if (!last_qtd)
 849                                         qtd_next->status = QTD_RETIRE;
 850                         }
 851                 }
 852
 853                 if (qtd->payload_addr)
 854                         free_mem(hcd, qtd);
 855
 856                 if (last_qtd) {
 857                         if ((qtd->status == QTD_RETIRE) &&
 858                                         (qtd->urb->status == -EINPROGRESS))
 859                                 qtd->urb->status = -EPIPE;
 860                         /* Defer calling of urb_done() since it releases lock */
 861                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 862                                                                 GFP_ATOMIC);
 863                         if (unlikely(!urb_listitem))
 864                                 break; /* Try again on next call */
 865                         urb_listitem->urb = qtd->urb;
 866                         list_add_tail(&urb_listitem->urb_list, urb_list);
 867                 }
 868
 869                 list_del(&qtd->qtd_list);
 870                 qtd_free(qtd);
 871         }
 872 }
 873
 874 #define ENQUEUE_DEPTH   2
 875 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 876 {
 877         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 878         int ptd_offset;
 879         struct isp1760_slotinfo *slots;
 880         int curr_slot, free_slot;
 881         int n;
 882         struct ptd ptd;
 883         struct isp1760_qtd *qtd;
 884
 885         if (unlikely(list_empty(&qh->qtd_list))) {
 886                 WARN_ON(1);
 887                 return;
 888         }
 889
 890         /* Make sure this endpoint's TT buffer is clean before queueing ptds */
 891         if (qh->tt_buffer_dirty)
 892                 return;
 893
 894         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 895                                                         qtd_list)->urb->pipe)) {
 896                 ptd_offset = INT_PTD_OFFSET;
 897                 slots = priv->int_slots;
 898         } else {
 899                 ptd_offset = ATL_PTD_OFFSET;
 900                 slots = priv->atl_slots;
 901         }
 902
 903         free_slot = -1;
 904         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 905                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 906                         free_slot = curr_slot;
 907                 if (slots[curr_slot].qh == qh)
 908                         break;
 909         }
 910
 911         n = 0;
 912         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 913                 if (qtd->status == QTD_ENQUEUED) {
 914                         WARN_ON(qtd->payload_addr);
 915                         alloc_mem(hcd, qtd);
 916                         if ((qtd->length) && (!qtd->payload_addr))
 917                                 break;
 918
 919                         if ((qtd->length) &&
 920                             ((qtd->packet_type == SETUP_PID) ||
 921                              (qtd->packet_type == OUT_PID))) {
 922                                 mem_writes8(hcd->regs, qtd->payload_addr,
 923                                                 qtd->data_buffer, qtd->length);
 924                         }
 925
 926                         qtd->status = QTD_PAYLOAD_ALLOC;
 927                 }
 928
 929                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 930 /*
 931                         if ((curr_slot > 31) && (free_slot == -1))
 932                                 dev_dbg(hcd->self.controller, "%s: No slot "
 933                                         "available for transfer\n", __func__);
 934 */
 935                         /* Start xfer for this endpoint if not already done */
 936                         if ((curr_slot > 31) && (free_slot > -1)) {
 937                                 if (usb_pipeint(qtd->urb->pipe))
 938                                         create_ptd_int(qh, qtd, &ptd);
 939                                 else
 940                                         create_ptd_atl(qh, qtd, &ptd);
 941
 942                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 943                                                         slots, qtd, qh, &ptd);
 944                                 curr_slot = free_slot;
 945                         }
 946
 947                         n++;
 948                         if (n >= ENQUEUE_DEPTH)
 949                                 break;
 950                 }
 951         }
 952 }
 953
 954 static void schedule_ptds(struct usb_hcd *hcd)
 955 {
 956         struct isp1760_hcd *priv;
 957         struct isp1760_qh *qh, *qh_next;
 958         struct list_head *ep_queue;
 959         LIST_HEAD(urb_list);
 960         struct urb_listitem *urb_listitem, *urb_listitem_next;
 961         int i;
 962
 963         if (!hcd) {
 964                 WARN_ON(1);
 965                 return;
 966         }
 967
 968         priv = hcd_to_priv(hcd);
 969
 970         /*
 971          * check finished/retired xfers, transfer payloads, call urb_done()
 972          */
 973         for (i = 0; i < QH_END; i++) {
 974                 ep_queue = &priv->qh_list[i];
 975                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 976                         collect_qtds(hcd, qh, &urb_list);
 977                         if (list_empty(&qh->qtd_list))
 978                                 list_del(&qh->qh_list);
 979                 }
 980         }
 981
 982         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
 983                                                                 urb_list) {
 984                 isp1760_urb_done(hcd, urb_listitem->urb);
 985                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
 986         }
 987
 988         /*
 989          * Schedule packets for transfer.
 990          *
 991          * According to USB2.0 specification:
 992          *
 993          * 1st prio: interrupt xfers, up to 80 % of bandwidth
 994          * 2nd prio: control xfers
 995          * 3rd prio: bulk xfers
 996          *
 997          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
 998          * is very unclear on how to prioritize traffic):
 999          *
1000          * 1) Enqueue any queued control transfers, as long as payload chip mem
1001          *    and PTD ATL slots are available.
1002          * 2) Enqueue any queued INT transfers, as long as payload chip mem
1003          *    and PTD INT slots are available.
1004          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1005          *    and PTD ATL slots are available.
1006          *
1007          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1008          * conservation of chip mem and performance.
1009          *
1010          * I'm sure this scheme could be improved upon!
1011          */
1012         for (i = 0; i < QH_END; i++) {
1013                 ep_queue = &priv->qh_list[i];
1014                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1015                         enqueue_qtds(hcd, qh);
1016         }
1017 }
1018
1019 #define PTD_STATE_QTD_DONE      1
1020 #define PTD_STATE_QTD_RELOAD    2
1021 #define PTD_STATE_URB_RETIRE    3
1022
1023 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1024                                                                 struct urb *urb)
1025 {
1026         __dw dw4;
1027         int i;
1028
1029         dw4 = ptd->dw4;
1030         dw4 >>= 8;
1031
1032         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1033            need to handle these errors? Is it done in hardware? */
1034
1035         if (ptd->dw3 & DW3_HALT_BIT) {
1036
1037                 urb->status = -EPROTO; /* Default unknown error */
1038
1039                 for (i = 0; i < 8; i++) {
1040                         switch (dw4 & 0x7) {
1041                         case INT_UNDERRUN:
1042                                 dev_dbg(hcd->self.controller, "%s: underrun "
1043                                                 "during uFrame %d\n",
1044                                                 __func__, i);
1045                                 urb->status = -ECOMM; /* Could not write data */
1046                                 break;
1047                         case INT_EXACT:
1048                                 dev_dbg(hcd->self.controller, "%s: transaction "
1049                                                 "error during uFrame %d\n",
1050                                                 __func__, i);
1051                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1052                                                           error etc. */
1053                                 break;
1054                         case INT_BABBLE:
1055                                 dev_dbg(hcd->self.controller, "%s: babble "
1056                                                 "error during uFrame %d\n",
1057                                                 __func__, i);
1058                                 urb->status = -EOVERFLOW;
1059                                 break;
1060                         }
1061                         dw4 >>= 3;
1062                 }
1063
1064                 return PTD_STATE_URB_RETIRE;
1065         }
1066
1067         return PTD_STATE_QTD_DONE;
1068 }
1069
1070 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1071                                                                 struct urb *urb)
1072 {
1073         WARN_ON(!ptd);
1074         if (ptd->dw3 & DW3_HALT_BIT) {
1075                 if (ptd->dw3 & DW3_BABBLE_BIT)
1076                         urb->status = -EOVERFLOW;
1077                 else if (FROM_DW3_CERR(ptd->dw3))
1078                         urb->status = -EPIPE;  /* Stall */
1079                 else if (ptd->dw3 & DW3_ERROR_BIT)
1080                         urb->status = -EPROTO; /* XactErr */
1081                 else
1082                         urb->status = -EPROTO; /* Unknown */
1083 /*
1084                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1085                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1086                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1087                         __func__,
1088                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1089                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1090 */
1091                 return PTD_STATE_URB_RETIRE;
1092         }
1093
1094         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1095                 /* Transfer Error, *but* active and no HALT -> reload */
1096                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1097                 return PTD_STATE_QTD_RELOAD;
1098         }
1099
1100         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1101                 /*
1102                  * NAKs are handled in HW by the chip. Usually if the
1103                  * device is not able to send data fast enough.
1104                  * This happens mostly on slower hardware.
1105                  */
1106                 return PTD_STATE_QTD_RELOAD;
1107         }
1108
1109         return PTD_STATE_QTD_DONE;
1110 }
1111
1112 static void handle_done_ptds(struct usb_hcd *hcd)
1113 {
1114         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1115         struct ptd ptd;
1116         struct isp1760_qh *qh;
1117         int slot;
1118         int state;
1119         struct isp1760_slotinfo *slots;
1120         u32 ptd_offset;
1121         struct isp1760_qtd *qtd;
1122         int modified;
1123         int skip_map;
1124
1125         skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1126         priv->int_done_map &= ~skip_map;
1127         skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1128         priv->atl_done_map &= ~skip_map;
1129
1130         modified = priv->int_done_map || priv->atl_done_map;
1131
1132         while (priv->int_done_map || priv->atl_done_map) {
1133                 if (priv->int_done_map) {
1134                         /* INT ptd */
1135                         slot = __ffs(priv->int_done_map);
1136                         priv->int_done_map &= ~(1 << slot);
1137                         slots = priv->int_slots;
1138                         /* This should not trigger, and could be removed if
1139                            noone have any problems with it triggering: */
1140                         if (!slots[slot].qh) {
1141                                 WARN_ON(1);
1142                                 continue;
1143                         }
1144                         ptd_offset = INT_PTD_OFFSET;
1145                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1146                         state = check_int_transfer(hcd, &ptd,
1147                                                         slots[slot].qtd->urb);
1148                 } else {
1149                         /* ATL ptd */
1150                         slot = __ffs(priv->atl_done_map);
1151                         priv->atl_done_map &= ~(1 << slot);
1152                         slots = priv->atl_slots;
1153                         /* This should not trigger, and could be removed if
1154                            noone have any problems with it triggering: */
1155                         if (!slots[slot].qh) {
1156                                 WARN_ON(1);
1157                                 continue;
1158                         }
1159                         ptd_offset = ATL_PTD_OFFSET;
1160                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1161                         state = check_atl_transfer(hcd, &ptd,
1162                                                         slots[slot].qtd->urb);
1163                 }
1164
1165                 qtd = slots[slot].qtd;
1166                 slots[slot].qtd = NULL;
1167                 qh = slots[slot].qh;
1168                 slots[slot].qh = NULL;
1169                 qh->slot = -1;
1170
1171                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1172
1173                 switch (state) {
1174                 case PTD_STATE_QTD_DONE:
1175                         if ((usb_pipeint(qtd->urb->pipe)) &&
1176                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1177                                 qtd->actual_length =
1178                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1179                         else
1180                                 qtd->actual_length =
1181                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1182
1183                         qtd->status = QTD_XFER_COMPLETE;
1184                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1185                                                         is_short_bulk(qtd))
1186                                 qtd = NULL;
1187                         else
1188                                 qtd = list_entry(qtd->qtd_list.next,
1189                                                         typeof(*qtd), qtd_list);
1190
1191                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1192                         qh->ping = FROM_DW3_PING(ptd.dw3);
1193                         break;
1194
1195                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1196                         qtd->status = QTD_PAYLOAD_ALLOC;
1197                         ptd.dw0 |= DW0_VALID_BIT;
1198                         /* RL counter = ERR counter */
1199                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1200                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1201                         ptd.dw3 &= ~TO_DW3_CERR(3);
1202                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1203                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1204                         qh->ping = FROM_DW3_PING(ptd.dw3);
1205                         break;
1206
1207                 case PTD_STATE_URB_RETIRE:
1208                         qtd->status = QTD_RETIRE;
1209                         if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1210                                         (qtd->urb->status != -EPIPE) &&
1211                                         (qtd->urb->status != -EREMOTEIO)) {
1212                                 qh->tt_buffer_dirty = 1;
1213                                 if (usb_hub_clear_tt_buffer(qtd->urb))
1214                                         /* Clear failed; let's hope things work
1215                                            anyway */
1216                                         qh->tt_buffer_dirty = 0;
1217                         }
1218                         qtd = NULL;
1219                         qh->toggle = 0;
1220                         qh->ping = 0;
1221                         break;
1222
1223                 default:
1224                         WARN_ON(1);
1225                         continue;
1226                 }
1227
1228                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1229                         if (slots == priv->int_slots) {
1230                                 if (state == PTD_STATE_QTD_RELOAD)
1231                                         dev_err(hcd->self.controller,
1232                                                 "%s: PTD_STATE_QTD_RELOAD on "
1233                                                 "interrupt packet\n", __func__);
1234                                 if (state != PTD_STATE_QTD_RELOAD)
1235                                         create_ptd_int(qh, qtd, &ptd);
1236                         } else {
1237                                 if (state != PTD_STATE_QTD_RELOAD)
1238                                         create_ptd_atl(qh, qtd, &ptd);
1239                         }
1240
1241                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1242                                 qh, &ptd);
1243                 }
1244         }
1245
1246         if (modified)
1247                 schedule_ptds(hcd);
1248 }
1249
1250 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1251 {
1252         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1253         u32 imask;
1254         irqreturn_t irqret = IRQ_NONE;
1255
1256         spin_lock(&priv->lock);
1257
1258         if (!(hcd->state & HC_STATE_RUNNING))
1259                 goto leave;
1260
1261         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1262         if (unlikely(!imask))
1263                 goto leave;
1264         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1265
1266         priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1267         priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1268
1269         handle_done_ptds(hcd);
1270
1271         irqret = IRQ_HANDLED;
1272 leave:
1273         spin_unlock(&priv->lock);
1274
1275         return irqret;
1276 }
1277
1278 /*
1279  * Workaround for problem described in chip errata 2:
1280  *
1281  * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1282  * One solution suggested in the errata is to use SOF interrupts _instead_of_
1283  * ATL done interrupts (the "instead of" might be important since it seems
1284  * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1285  * to set the PTD's done bit in addition to not generating an interrupt!).
1286  *
1287  * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1288  * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1289  *
1290  * If we use SOF interrupts only, we get latency between ptd completion and the
1291  * actual handling. This is very noticeable in testusb runs which takes several
1292  * minutes longer without ATL interrupts.
1293  *
1294  * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1295  * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1296  * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1297  * completed and its done map bit is set.
1298  *
1299  * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1300  * not to cause too much lag when this HW bug occurs, while still hopefully
1301  * ensuring that the check does not falsely trigger.
1302  */
1303 #define SLOT_TIMEOUT 300
1304 #define SLOT_CHECK_PERIOD 200
1305 static struct timer_list errata2_timer;
1306
1307 static void errata2_function(unsigned long data)
1308 {
1309         struct usb_hcd *hcd = (struct usb_hcd *) data;
1310         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1311         int slot;
1312         struct ptd ptd;
1313         unsigned long spinflags;
1314
1315         spin_lock_irqsave(&priv->lock, spinflags);
1316
1317         for (slot = 0; slot < 32; slot++)
1318                 if (priv->atl_slots[slot].qh && time_after(jiffies,
1319                                         priv->atl_slots[slot].timestamp +
1320                                         SLOT_TIMEOUT * HZ / 1000)) {
1321                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1322                         if (!FROM_DW0_VALID(ptd.dw0) &&
1323                                         !FROM_DW3_ACTIVE(ptd.dw3))
1324                                 priv->atl_done_map |= 1 << slot;
1325                 }
1326
1327         if (priv->atl_done_map)
1328                 handle_done_ptds(hcd);
1329
1330         spin_unlock_irqrestore(&priv->lock, spinflags);
1331
1332         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1333         add_timer(&errata2_timer);
1334 }
1335
1336 static int isp1760_run(struct usb_hcd *hcd)
1337 {
1338         int retval;
1339         u32 temp;
1340         u32 command;
1341         u32 chipid;
1342
1343         hcd->uses_new_polling = 1;
1344
1345         hcd->state = HC_STATE_RUNNING;
1346
1347         /* Set PTD interrupt AND & OR maps */
1348         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1349         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1350         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1351         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1352         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1353         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1354         /* step 23 passed */
1355
1356         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1357         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1358
1359         command = reg_read32(hcd->regs, HC_USBCMD);
1360         command &= ~(CMD_LRESET|CMD_RESET);
1361         command |= CMD_RUN;
1362         reg_write32(hcd->regs, HC_USBCMD, command);
1363
1364         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1365         if (retval)
1366                 return retval;
1367
1368         /*
1369          * XXX
1370          * Spec says to write FLAG_CF as last config action, priv code grabs
1371          * the semaphore while doing so.
1372          */
1373         down_write(&ehci_cf_port_reset_rwsem);
1374         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1375
1376         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1377         up_write(&ehci_cf_port_reset_rwsem);
1378         if (retval)
1379                 return retval;
1380
1381         init_timer(&errata2_timer);
1382         errata2_timer.function = errata2_function;
1383         errata2_timer.data = (unsigned long) hcd;
1384         errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1385         add_timer(&errata2_timer);
1386
1387         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1388         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1389                                         chipid & 0xffff, chipid >> 16);
1390
1391         /* PTD Register Init Part 2, Step 28 */
1392
1393         /* Setup registers controlling PTD checking */
1394         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1395         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1396         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1397         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1398         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1399         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1400         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1401                                                 ATL_BUF_FILL | INT_BUF_FILL);
1402
1403         /* GRR this is run-once init(), being done every time the HC starts.
1404          * So long as they're part of class devices, we can't do it init()
1405          * since the class device isn't created that early.
1406          */
1407         return 0;
1408 }
1409
1410 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1411 {
1412         qtd->data_buffer = databuffer;
1413
1414         if (len > MAX_PAYLOAD_SIZE)
1415                 len = MAX_PAYLOAD_SIZE;
1416         qtd->length = len;
1417
1418         return qtd->length;
1419 }
1420
1421 static void qtd_list_free(struct list_head *qtd_list)
1422 {
1423         struct isp1760_qtd *qtd, *qtd_next;
1424
1425         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1426                 list_del(&qtd->qtd_list);
1427                 qtd_free(qtd);
1428         }
1429 }
1430
1431 /*
1432  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1433  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1434  */
1435 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1436 static void packetize_urb(struct usb_hcd *hcd,
1437                 struct urb *urb, struct list_head *head, gfp_t flags)
1438 {
1439         struct isp1760_qtd *qtd;
1440         void *buf;
1441         int len, maxpacketsize;
1442         u8 packet_type;
1443
1444         /*
1445          * URBs map to sequences of QTDs:  one logical transaction
1446          */
1447
1448         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1449                 /* XXX This looks like usb storage / SCSI bug */
1450                 dev_err(hcd->self.controller,
1451                                 "buf is null, dma is %08lx len is %d\n",
1452                                 (long unsigned)urb->transfer_dma,
1453                                 urb->transfer_buffer_length);
1454                 WARN_ON(1);
1455         }
1456
1457         if (usb_pipein(urb->pipe))
1458                 packet_type = IN_PID;
1459         else
1460                 packet_type = OUT_PID;
1461
1462         if (usb_pipecontrol(urb->pipe)) {
1463                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1464                 if (!qtd)
1465                         goto cleanup;
1466                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1467                 list_add_tail(&qtd->qtd_list, head);
1468
1469                 /* for zero length DATA stages, STATUS is always IN */
1470                 if (urb->transfer_buffer_length == 0)
1471                         packet_type = IN_PID;
1472         }
1473
1474         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1475                                                 usb_pipeout(urb->pipe)));
1476
1477         /*
1478          * buffer gets wrapped in one or more qtds;
1479          * last one may be "short" (including zero len)
1480          * and may serve as a control status ack
1481          */
1482         buf = urb->transfer_buffer;
1483         len = urb->transfer_buffer_length;
1484
1485         for (;;) {
1486                 int this_qtd_len;
1487
1488                 qtd = qtd_alloc(flags, urb, packet_type);
1489                 if (!qtd)
1490                         goto cleanup;
1491                 this_qtd_len = qtd_fill(qtd, buf, len);
1492                 list_add_tail(&qtd->qtd_list, head);
1493
1494                 len -= this_qtd_len;
1495                 buf += this_qtd_len;
1496
1497                 if (len <= 0)
1498                         break;
1499         }
1500
1501         /*
1502          * control requests may need a terminating data "status" ack;
1503          * bulk ones may need a terminating short packet (zero length).
1504          */
1505         if (urb->transfer_buffer_length != 0) {
1506                 int one_more = 0;
1507
1508                 if (usb_pipecontrol(urb->pipe)) {
1509                         one_more = 1;
1510                         if (packet_type == IN_PID)
1511                                 packet_type = OUT_PID;
1512                         else
1513                                 packet_type = IN_PID;
1514                 } else if (usb_pipebulk(urb->pipe)
1515                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1516                                 && !(urb->transfer_buffer_length %
1517                                                         maxpacketsize)) {
1518                         one_more = 1;
1519                 }
1520                 if (one_more) {
1521                         qtd = qtd_alloc(flags, urb, packet_type);
1522                         if (!qtd)
1523                                 goto cleanup;
1524
1525                         /* never any data in such packets */
1526                         qtd_fill(qtd, NULL, 0);
1527                         list_add_tail(&qtd->qtd_list, head);
1528                 }
1529         }
1530
1531         return;
1532
1533 cleanup:
1534         qtd_list_free(head);
1535 }
1536
1537 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1538                 gfp_t mem_flags)
1539 {
1540         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1541         struct list_head *ep_queue;
1542         struct isp1760_qh *qh, *qhit;
1543         unsigned long spinflags;
1544         LIST_HEAD(new_qtds);
1545         int retval;
1546         int qh_in_queue;
1547
1548         switch (usb_pipetype(urb->pipe)) {
1549         case PIPE_CONTROL:
1550                 ep_queue = &priv->qh_list[QH_CONTROL];
1551                 break;
1552         case PIPE_BULK:
1553                 ep_queue = &priv->qh_list[QH_BULK];
1554                 break;
1555         case PIPE_INTERRUPT:
1556                 if (urb->interval < 0)
1557                         return -EINVAL;
1558                 /* FIXME: Check bandwidth  */
1559                 ep_queue = &priv->qh_list[QH_INTERRUPT];
1560                 break;
1561         case PIPE_ISOCHRONOUS:
1562                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1563                                                         "not yet supported\n",
1564                                                         __func__);
1565                 return -EPIPE;
1566         default:
1567                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1568                                                         __func__);
1569                 return -EPIPE;
1570         }
1571
1572         if (usb_pipein(urb->pipe))
1573                 urb->actual_length = 0;
1574
1575         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1576         if (list_empty(&new_qtds))
1577                 return -ENOMEM;
1578
1579         retval = 0;
1580         spin_lock_irqsave(&priv->lock, spinflags);
1581
1582         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1583                 retval = -ESHUTDOWN;
1584                 qtd_list_free(&new_qtds);
1585                 goto out;
1586         }
1587         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1588         if (retval) {
1589                 qtd_list_free(&new_qtds);
1590                 goto out;
1591         }
1592
1593         qh = urb->ep->hcpriv;
1594         if (qh) {
1595                 qh_in_queue = 0;
1596                 list_for_each_entry(qhit, ep_queue, qh_list) {
1597                         if (qhit == qh) {
1598                                 qh_in_queue = 1;
1599                                 break;
1600                         }
1601                 }
1602                 if (!qh_in_queue)
1603                         list_add_tail(&qh->qh_list, ep_queue);
1604         } else {
1605                 qh = qh_alloc(GFP_ATOMIC);
1606                 if (!qh) {
1607                         retval = -ENOMEM;
1608                         usb_hcd_unlink_urb_from_ep(hcd, urb);
1609                         qtd_list_free(&new_qtds);
1610                         goto out;
1611                 }
1612                 list_add_tail(&qh->qh_list, ep_queue);
1613                 urb->ep->hcpriv = qh;
1614         }
1615
1616         list_splice_tail(&new_qtds, &qh->qtd_list);
1617         schedule_ptds(hcd);
1618
1619 out:
1620         spin_unlock_irqrestore(&priv->lock, spinflags);
1621         return retval;
1622 }
1623
1624 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1625                 struct isp1760_qh *qh)
1626 {
1627         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1628         int skip_map;
1629
1630         WARN_ON(qh->slot == -1);
1631
1632         /* We need to forcefully reclaim the slot since some transfers never
1633            return, e.g. interrupt transfers and NAKed bulk transfers. */
1634         if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1635                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1636                 skip_map |= (1 << qh->slot);
1637                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1638                 priv->atl_slots[qh->slot].qh = NULL;
1639                 priv->atl_slots[qh->slot].qtd = NULL;
1640         } else {
1641                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1642                 skip_map |= (1 << qh->slot);
1643                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1644                 priv->int_slots[qh->slot].qh = NULL;
1645                 priv->int_slots[qh->slot].qtd = NULL;
1646         }
1647
1648         qh->slot = -1;
1649 }
1650
1651 /*
1652  * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1653  * any active transfer belonging to the urb in the process.
1654  */
1655 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1656                                                 struct isp1760_qtd *qtd)
1657 {
1658         struct urb *urb;
1659         int urb_was_running;
1660
1661         urb = qtd->urb;
1662         urb_was_running = 0;
1663         list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1664                 if (qtd->urb != urb)
1665                         break;
1666
1667                 if (qtd->status >= QTD_XFER_STARTED)
1668                         urb_was_running = 1;
1669                 if (last_qtd_of_urb(qtd, qh) &&
1670                                         (qtd->status >= QTD_XFER_COMPLETE))
1671                         urb_was_running = 0;
1672
1673                 if (qtd->status == QTD_XFER_STARTED)
1674                         kill_transfer(hcd, urb, qh);
1675                 qtd->status = QTD_RETIRE;
1676         }
1677
1678         if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1679                 qh->tt_buffer_dirty = 1;
1680                 if (usb_hub_clear_tt_buffer(urb))
1681                         /* Clear failed; let's hope things work anyway */
1682                         qh->tt_buffer_dirty = 0;
1683         }
1684 }
1685
1686 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1687                 int status)
1688 {
1689         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1690         unsigned long spinflags;
1691         struct isp1760_qh *qh;
1692         struct isp1760_qtd *qtd;
1693         int retval = 0;
1694
1695         spin_lock_irqsave(&priv->lock, spinflags);
1696         retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1697         if (retval)
1698                 goto out;
1699
1700         qh = urb->ep->hcpriv;
1701         if (!qh) {
1702                 retval = -EINVAL;
1703                 goto out;
1704         }
1705
1706         list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1707                 if (qtd->urb == urb) {
1708                         dequeue_urb_from_qtd(hcd, qh, qtd);
1709                         list_move(&qtd->qtd_list, &qh->qtd_list);
1710                         break;
1711                 }
1712
1713         urb->status = status;
1714         schedule_ptds(hcd);
1715
1716 out:
1717         spin_unlock_irqrestore(&priv->lock, spinflags);
1718         return retval;
1719 }
1720
1721 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1722                 struct usb_host_endpoint *ep)
1723 {
1724         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1725         unsigned long spinflags;
1726         struct isp1760_qh *qh, *qh_iter;
1727         int i;
1728
1729         spin_lock_irqsave(&priv->lock, spinflags);
1730
1731         qh = ep->hcpriv;
1732         if (!qh)
1733                 goto out;
1734
1735         WARN_ON(!list_empty(&qh->qtd_list));
1736
1737         for (i = 0; i < QH_END; i++)
1738                 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1739                         if (qh_iter == qh) {
1740                                 list_del(&qh_iter->qh_list);
1741                                 i = QH_END;
1742                                 break;
1743                         }
1744         qh_free(qh);
1745         ep->hcpriv = NULL;
1746
1747         schedule_ptds(hcd);
1748
1749 out:
1750         spin_unlock_irqrestore(&priv->lock, spinflags);
1751 }
1752
1753 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1754 {
1755         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1756         u32 temp, status = 0;
1757         u32 mask;
1758         int retval = 1;
1759         unsigned long flags;
1760
1761         /* if !PM, root hub timers won't get shut down ... */
1762         if (!HC_IS_RUNNING(hcd->state))
1763                 return 0;
1764
1765         /* init status to no-changes */
1766         buf[0] = 0;
1767         mask = PORT_CSC;
1768
1769         spin_lock_irqsave(&priv->lock, flags);
1770         temp = reg_read32(hcd->regs, HC_PORTSC1);
1771
1772         if (temp & PORT_OWNER) {
1773                 if (temp & PORT_CSC) {
1774                         temp &= ~PORT_CSC;
1775                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1776                         goto done;
1777                 }
1778         }
1779
1780         /*
1781          * Return status information even for ports with OWNER set.
1782          * Otherwise hub_wq wouldn't see the disconnect event when a
1783          * high-speed device is switched over to the companion
1784          * controller by the user.
1785          */
1786
1787         if ((temp & mask) != 0
1788                         || ((temp & PORT_RESUME) != 0
1789                                 && time_after_eq(jiffies,
1790                                         priv->reset_done))) {
1791                 buf [0] |= 1 << (0 + 1);
1792                 status = STS_PCD;
1793         }
1794         /* FIXME autosuspend idle root hubs */
1795 done:
1796         spin_unlock_irqrestore(&priv->lock, flags);
1797         return status ? retval : 0;
1798 }
1799
1800 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1801                 struct usb_hub_descriptor *desc)
1802 {
1803         int ports = HCS_N_PORTS(priv->hcs_params);
1804         u16 temp;
1805
1806         desc->bDescriptorType = 0x29;
1807         /* priv 1.0, 2.3.9 says 20ms max */
1808         desc->bPwrOn2PwrGood = 10;
1809         desc->bHubContrCurrent = 0;
1810
1811         desc->bNbrPorts = ports;
1812         temp = 1 + (ports / 8);
1813         desc->bDescLength = 7 + 2 * temp;
1814
1815         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1816         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1817         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1818
1819         /* per-port overcurrent reporting */
1820         temp = 0x0008;
1821         if (HCS_PPC(priv->hcs_params))
1822                 /* per-port power control */
1823                 temp |= 0x0001;
1824         else
1825                 /* no power switching */
1826                 temp |= 0x0002;
1827         desc->wHubCharacteristics = cpu_to_le16(temp);
1828 }
1829
1830 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1831
1832 static int check_reset_complete(struct usb_hcd *hcd, int index,
1833                 int port_status)
1834 {
1835         if (!(port_status & PORT_CONNECT))
1836                 return port_status;
1837
1838         /* if reset finished and it's still not enabled -- handoff */
1839         if (!(port_status & PORT_PE)) {
1840
1841                 dev_info(hcd->self.controller,
1842                                         "port %d full speed --> companion\n",
1843                                         index + 1);
1844
1845                 port_status |= PORT_OWNER;
1846                 port_status &= ~PORT_RWC_BITS;
1847                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1848
1849         } else
1850                 dev_info(hcd->self.controller, "port %d high speed\n",
1851                                                                 index + 1);
1852
1853         return port_status;
1854 }
1855
1856 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1857                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1858 {
1859         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1860         int ports = HCS_N_PORTS(priv->hcs_params);
1861         u32 temp, status;
1862         unsigned long flags;
1863         int retval = 0;
1864         unsigned selector;
1865
1866         /*
1867          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1868          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1869          * (track current state ourselves) ... blink for diagnostics,
1870          * power, "this is the one", etc.  EHCI spec supports this.
1871          */
1872
1873         spin_lock_irqsave(&priv->lock, flags);
1874         switch (typeReq) {
1875         case ClearHubFeature:
1876                 switch (wValue) {
1877                 case C_HUB_LOCAL_POWER:
1878                 case C_HUB_OVER_CURRENT:
1879                         /* no hub-wide feature/status flags */
1880                         break;
1881                 default:
1882                         goto error;
1883                 }
1884                 break;
1885         case ClearPortFeature:
1886                 if (!wIndex || wIndex > ports)
1887                         goto error;
1888                 wIndex--;
1889                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1890
1891                 /*
1892                  * Even if OWNER is set, so the port is owned by the
1893                  * companion controller, hub_wq needs to be able to clear
1894                  * the port-change status bits (especially
1895                  * USB_PORT_STAT_C_CONNECTION).
1896                  */
1897
1898                 switch (wValue) {
1899                 case USB_PORT_FEAT_ENABLE:
1900                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1901                         break;
1902                 case USB_PORT_FEAT_C_ENABLE:
1903                         /* XXX error? */
1904                         break;
1905                 case USB_PORT_FEAT_SUSPEND:
1906                         if (temp & PORT_RESET)
1907                                 goto error;
1908
1909                         if (temp & PORT_SUSPEND) {
1910                                 if ((temp & PORT_PE) == 0)
1911                                         goto error;
1912                                 /* resume signaling for 20 msec */
1913                                 temp &= ~(PORT_RWC_BITS);
1914                                 reg_write32(hcd->regs, HC_PORTSC1,
1915                                                         temp | PORT_RESUME);
1916                                 priv->reset_done = jiffies +
1917                                         msecs_to_jiffies(20);
1918                         }
1919                         break;
1920                 case USB_PORT_FEAT_C_SUSPEND:
1921                         /* we auto-clear this feature */
1922                         break;
1923                 case USB_PORT_FEAT_POWER:
1924                         if (HCS_PPC(priv->hcs_params))
1925                                 reg_write32(hcd->regs, HC_PORTSC1,
1926                                                         temp & ~PORT_POWER);
1927                         break;
1928                 case USB_PORT_FEAT_C_CONNECTION:
1929                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1930                         break;
1931                 case USB_PORT_FEAT_C_OVER_CURRENT:
1932                         /* XXX error ?*/
1933                         break;
1934                 case USB_PORT_FEAT_C_RESET:
1935                         /* GetPortStatus clears reset */
1936                         break;
1937                 default:
1938                         goto error;
1939                 }
1940                 reg_read32(hcd->regs, HC_USBCMD);
1941                 break;
1942         case GetHubDescriptor:
1943                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1944                         buf);
1945                 break;
1946         case GetHubStatus:
1947                 /* no hub-wide feature/status flags */
1948                 memset(buf, 0, 4);
1949                 break;
1950         case GetPortStatus:
1951                 if (!wIndex || wIndex > ports)
1952                         goto error;
1953                 wIndex--;
1954                 status = 0;
1955                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1956
1957                 /* wPortChange bits */
1958                 if (temp & PORT_CSC)
1959                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1960
1961
1962                 /* whoever resumes must GetPortStatus to complete it!! */
1963                 if (temp & PORT_RESUME) {
1964                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1965
1966                         /* Remote Wakeup received? */
1967                         if (!priv->reset_done) {
1968                                 /* resume signaling for 20 msec */
1969                                 priv->reset_done = jiffies
1970                                                 + msecs_to_jiffies(20);
1971                                 /* check the port again */
1972                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1973                         }
1974
1975                         /* resume completed? */
1976                         else if (time_after_eq(jiffies,
1977                                         priv->reset_done)) {
1978                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1979                                 priv->reset_done = 0;
1980
1981                                 /* stop resume signaling */
1982                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1983                                 reg_write32(hcd->regs, HC_PORTSC1,
1984                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1985                                 retval = handshake(hcd, HC_PORTSC1,
1986                                            PORT_RESUME, 0, 2000 /* 2msec */);
1987                                 if (retval != 0) {
1988                                         dev_err(hcd->self.controller,
1989                                                 "port %d resume error %d\n",
1990                                                 wIndex + 1, retval);
1991                                         goto error;
1992                                 }
1993                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1994                         }
1995                 }
1996
1997                 /* whoever resets must GetPortStatus to complete it!! */
1998                 if ((temp & PORT_RESET)
1999                                 && time_after_eq(jiffies,
2000                                         priv->reset_done)) {
2001                         status |= USB_PORT_STAT_C_RESET << 16;
2002                         priv->reset_done = 0;
2003
2004                         /* force reset to complete */
2005                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
2006                         /* REVISIT:  some hardware needs 550+ usec to clear
2007                          * this bit; seems too long to spin routinely...
2008                          */
2009                         retval = handshake(hcd, HC_PORTSC1,
2010                                         PORT_RESET, 0, 750);
2011                         if (retval != 0) {
2012                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
2013                                                 wIndex + 1, retval);
2014                                 goto error;
2015                         }
2016
2017                         /* see what we found out */
2018                         temp = check_reset_complete(hcd, wIndex,
2019                                         reg_read32(hcd->regs, HC_PORTSC1));
2020                 }
2021                 /*
2022                  * Even if OWNER is set, there's no harm letting hub_wq
2023                  * see the wPortStatus values (they should all be 0 except
2024                  * for PORT_POWER anyway).
2025                  */
2026
2027                 if (temp & PORT_OWNER)
2028                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2029
2030                 if (temp & PORT_CONNECT) {
2031                         status |= USB_PORT_STAT_CONNECTION;
2032                         /* status may be from integrated TT */
2033                         status |= USB_PORT_STAT_HIGH_SPEED;
2034                 }
2035                 if (temp & PORT_PE)
2036                         status |= USB_PORT_STAT_ENABLE;
2037                 if (temp & (PORT_SUSPEND|PORT_RESUME))
2038                         status |= USB_PORT_STAT_SUSPEND;
2039                 if (temp & PORT_RESET)
2040                         status |= USB_PORT_STAT_RESET;
2041                 if (temp & PORT_POWER)
2042                         status |= USB_PORT_STAT_POWER;
2043
2044                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2045                 break;
2046         case SetHubFeature:
2047                 switch (wValue) {
2048                 case C_HUB_LOCAL_POWER:
2049                 case C_HUB_OVER_CURRENT:
2050                         /* no hub-wide feature/status flags */
2051                         break;
2052                 default:
2053                         goto error;
2054                 }
2055                 break;
2056         case SetPortFeature:
2057                 selector = wIndex >> 8;
2058                 wIndex &= 0xff;
2059                 if (!wIndex || wIndex > ports)
2060                         goto error;
2061                 wIndex--;
2062                 temp = reg_read32(hcd->regs, HC_PORTSC1);
2063                 if (temp & PORT_OWNER)
2064                         break;
2065
2066 /*              temp &= ~PORT_RWC_BITS; */
2067                 switch (wValue) {
2068                 case USB_PORT_FEAT_ENABLE:
2069                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2070                         break;
2071
2072                 case USB_PORT_FEAT_SUSPEND:
2073                         if ((temp & PORT_PE) == 0
2074                                         || (temp & PORT_RESET) != 0)
2075                                 goto error;
2076
2077                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2078                         break;
2079                 case USB_PORT_FEAT_POWER:
2080                         if (HCS_PPC(priv->hcs_params))
2081                                 reg_write32(hcd->regs, HC_PORTSC1,
2082                                                         temp | PORT_POWER);
2083                         break;
2084                 case USB_PORT_FEAT_RESET:
2085                         if (temp & PORT_RESUME)
2086                                 goto error;
2087                         /* line status bits may report this as low speed,
2088                          * which can be fine if this root hub has a
2089                          * transaction translator built in.
2090                          */
2091                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2092                                         && PORT_USB11(temp)) {
2093                                 temp |= PORT_OWNER;
2094                         } else {
2095                                 temp |= PORT_RESET;
2096                                 temp &= ~PORT_PE;
2097
2098                                 /*
2099                                  * caller must wait, then call GetPortStatus
2100                                  * usb 2.0 spec says 50 ms resets on root
2101                                  */
2102                                 priv->reset_done = jiffies +
2103                                         msecs_to_jiffies(50);
2104                         }
2105                         reg_write32(hcd->regs, HC_PORTSC1, temp);
2106                         break;
2107                 default:
2108                         goto error;
2109                 }
2110                 reg_read32(hcd->regs, HC_USBCMD);
2111                 break;
2112
2113         default:
2114 error:
2115                 /* "stall" on error */
2116                 retval = -EPIPE;
2117         }
2118         spin_unlock_irqrestore(&priv->lock, flags);
2119         return retval;
2120 }
2121
2122 static int isp1760_get_frame(struct usb_hcd *hcd)
2123 {
2124         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2125         u32 fr;
2126
2127         fr = reg_read32(hcd->regs, HC_FRINDEX);
2128         return (fr >> 3) % priv->periodic_size;
2129 }
2130
2131 static void isp1760_stop(struct usb_hcd *hcd)
2132 {
2133         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2134         u32 temp;
2135
2136         del_timer(&errata2_timer);
2137
2138         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2139                         NULL, 0);
2140         mdelay(20);
2141
2142         spin_lock_irq(&priv->lock);
2143         ehci_reset(hcd);
2144         /* Disable IRQ */
2145         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2146         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2147         spin_unlock_irq(&priv->lock);
2148
2149         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2150 }
2151
2152 static void isp1760_shutdown(struct usb_hcd *hcd)
2153 {
2154         u32 command, temp;
2155
2156         isp1760_stop(hcd);
2157         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2158         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2159
2160         command = reg_read32(hcd->regs, HC_USBCMD);
2161         command &= ~CMD_RUN;
2162         reg_write32(hcd->regs, HC_USBCMD, command);
2163 }
2164
2165 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2166                                                 struct usb_host_endpoint *ep)
2167 {
2168         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2169         struct isp1760_qh *qh = ep->hcpriv;
2170         unsigned long spinflags;
2171
2172         if (!qh)
2173                 return;
2174
2175         spin_lock_irqsave(&priv->lock, spinflags);
2176         qh->tt_buffer_dirty = 0;
2177         schedule_ptds(hcd);
2178         spin_unlock_irqrestore(&priv->lock, spinflags);
2179 }
2180
2181
2182 static const struct hc_driver isp1760_hc_driver = {
2183         .description            = "isp1760-hcd",
2184         .product_desc           = "NXP ISP1760 USB Host Controller",
2185         .hcd_priv_size          = sizeof(struct isp1760_hcd *),
2186         .irq                    = isp1760_irq,
2187         .flags                  = HCD_MEMORY | HCD_USB2,
2188         .reset                  = isp1760_hc_setup,
2189         .start                  = isp1760_run,
2190         .stop                   = isp1760_stop,
2191         .shutdown               = isp1760_shutdown,
2192         .urb_enqueue            = isp1760_urb_enqueue,
2193         .urb_dequeue            = isp1760_urb_dequeue,
2194         .endpoint_disable       = isp1760_endpoint_disable,
2195         .get_frame_number       = isp1760_get_frame,
2196         .hub_status_data        = isp1760_hub_status_data,
2197         .hub_control            = isp1760_hub_control,
2198         .clear_tt_buffer_complete       = isp1760_clear_tt_buffer_complete,
2199 };
2200
2201 int __init isp1760_init_kmem_once(void)
2202 {
2203         urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2204                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2205                         SLAB_MEM_SPREAD, NULL);
2206
2207         if (!urb_listitem_cachep)
2208                 return -ENOMEM;
2209
2210         qtd_cachep = kmem_cache_create("isp1760_qtd",
2211                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2212                         SLAB_MEM_SPREAD, NULL);
2213
2214         if (!qtd_cachep)
2215                 return -ENOMEM;
2216
2217         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2218                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2219
2220         if (!qh_cachep) {
2221                 kmem_cache_destroy(qtd_cachep);
2222                 return -ENOMEM;
2223         }
2224
2225         return 0;
2226 }
2227
2228 void isp1760_deinit_kmem_cache(void)
2229 {
2230         kmem_cache_destroy(qtd_cachep);
2231         kmem_cache_destroy(qh_cachep);
2232         kmem_cache_destroy(urb_listitem_cachep);
2233 }
2234
2235 int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
2236                      struct device *dev, unsigned int devflags)
2237 {
2238         struct usb_hcd *hcd = NULL;
2239         struct isp1760_hcd *priv;
2240         int ret;
2241
2242         if (usb_disabled())
2243                 return -ENODEV;
2244
2245         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2246         if (!priv)
2247                 return -ENOMEM;
2248
2249         /* prevent usb-core allocating DMA pages */
2250         dev->dma_mask = NULL;
2251
2252         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2253         if (!hcd)
2254                 return -ENOMEM;
2255
2256         priv->hcd = hcd;
2257         *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2258
2259         priv->devflags = devflags;
2260
2261         priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
2262         if (IS_ERR(priv->rst_gpio)) {
2263                 ret = PTR_ERR(priv->rst_gpio);
2264                 goto error;
2265         }
2266
2267         init_memory(priv);
2268         hcd->regs = devm_ioremap_resource(dev, mem);
2269         if (IS_ERR(hcd->regs)) {
2270                 ret = PTR_ERR(hcd->regs);
2271                 goto error;
2272         }
2273
2274         hcd->irq = irq;
2275         hcd->rsrc_start = mem->start;
2276         hcd->rsrc_len = resource_size(mem);
2277
2278         ret = usb_add_hcd(hcd, irq, irqflags);
2279         if (ret)
2280                 goto error;
2281         device_wakeup_enable(hcd->self.controller);
2282
2283         dev_set_drvdata(dev, priv);
2284
2285         return 0;
2286
2287 error:
2288         usb_put_hcd(hcd);
2289         return ret;
2290 }
2291
2292 void isp1760_unregister(struct device *dev)
2293 {
2294         struct isp1760_hcd *priv = dev_get_drvdata(dev);
2295         struct usb_hcd *hcd = priv->hcd;
2296
2297         usb_remove_hcd(hcd);
2298         usb_put_hcd(hcd);
2299 }
2300
2301 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2302 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2303 MODULE_LICENSE("GPL v2");