2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
14 #include <linux/gpio/consumer.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/usb.h>
20 #include <linux/usb/hcd.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
25 #include <linux/timer.h>
26 #include <asm/unaligned.h>
27 #include <asm/cacheflush.h>
29 #include "isp1760-hcd.h"
30 #include "isp1760-regs.h"
32 static struct kmem_cache *qtd_cachep;
33 static struct kmem_cache *qh_cachep;
34 static struct kmem_cache *urb_listitem_cachep;
36 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
37 struct isp1760_qtd *qtd);
39 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
41 return *(struct isp1760_hcd **)hcd->hcd_priv;
45 #define DELETE_URB (0x0008)
46 #define NO_TRANSFER_ACTIVE (0xffffffff)
48 /* Philips Proprietary Transfer Descriptor (PTD) */
49 typedef __u32 __bitwise __dw;
60 #define PTD_OFFSET 0x0400
61 #define ISO_PTD_OFFSET 0x0400
62 #define INT_PTD_OFFSET 0x0800
63 #define ATL_PTD_OFFSET 0x0c00
64 #define PAYLOAD_OFFSET 0x1000
69 #define DW0_VALID_BIT 1
70 #define FROM_DW0_VALID(x) ((x) & 0x01)
71 #define TO_DW0_LENGTH(x) (((u32) x) << 3)
72 #define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
73 #define TO_DW0_MULTI(x) (((u32) x) << 29)
74 #define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
76 #define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
77 #define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
78 #define DW1_TRANS_BULK ((u32) 2 << 12)
79 #define DW1_TRANS_INT ((u32) 3 << 12)
80 #define DW1_TRANS_SPLIT ((u32) 1 << 14)
81 #define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
82 #define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
83 #define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
85 #define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
86 #define TO_DW2_RL(x) ((x) << 25)
87 #define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
89 #define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
90 #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
91 #define TO_DW3_NAKCOUNT(x) ((x) << 19)
92 #define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
93 #define TO_DW3_CERR(x) ((x) << 23)
94 #define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
95 #define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
96 #define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
97 #define TO_DW3_PING(x) ((x) << 26)
98 #define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
99 #define DW3_ERROR_BIT (1 << 28)
100 #define DW3_BABBLE_BIT (1 << 29)
101 #define DW3_HALT_BIT (1 << 30)
102 #define DW3_ACTIVE_BIT (1 << 31)
103 #define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
105 #define INT_UNDERRUN (1 << 2)
106 #define INT_BABBLE (1 << 1)
107 #define INT_EXACT (1 << 0)
109 #define SETUP_PID (2)
114 #define RL_COUNTER (0)
115 #define NAK_COUNTER (0)
116 #define ERR_COUNTER (2)
123 /* the rest is HCD-private */
124 struct list_head qtd_list;
127 size_t actual_length;
129 /* QTD_ENQUEUED: waiting for transfer (inactive) */
130 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
131 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
132 interrupt handler may touch this qtd! */
133 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
134 /* QTD_RETIRE: transfer error/abort qtd */
135 #define QTD_ENQUEUED 0
136 #define QTD_PAYLOAD_ALLOC 1
137 #define QTD_XFER_STARTED 2
138 #define QTD_XFER_COMPLETE 3
143 /* Queue head, one for each active endpoint */
145 struct list_head qh_list;
146 struct list_head qtd_list;
150 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
153 struct urb_listitem {
154 struct list_head urb_list;
159 * Access functions for isp176x registers (addresses 0..0x03FF).
161 static u32 reg_read32(void __iomem *base, u32 reg)
163 return readl(base + reg);
166 static void reg_write32(void __iomem *base, u32 reg, u32 val)
168 writel(val, base + reg);
172 * Access functions for isp176x memory (offset >= 0x0400).
174 * bank_reads8() reads memory locations prefetched by an earlier write to
175 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
176 * bank optimizations, you should use the more generic mem_reads8() below.
178 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
181 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
182 * doesn't quite work because some people have to enforce 32-bit access
184 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
185 __u32 *dst, u32 bytes)
192 src = src_base + (bank_addr | src_offset);
194 if (src_offset < PAYLOAD_OFFSET) {
196 *dst = le32_to_cpu(__raw_readl(src));
203 *dst = __raw_readl(src);
213 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
216 if (src_offset < PAYLOAD_OFFSET)
217 val = le32_to_cpu(__raw_readl(src));
219 val = __raw_readl(src);
221 dst_byteptr = (void *) dst;
222 src_byteptr = (void *) &val;
224 *dst_byteptr = *src_byteptr;
231 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
234 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
236 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
239 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
240 __u32 const *src, u32 bytes)
244 dst = dst_base + dst_offset;
246 if (dst_offset < PAYLOAD_OFFSET) {
248 __raw_writel(cpu_to_le32(*src), dst);
255 __raw_writel(*src, dst);
264 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
265 * extra bytes should not be read by the HW.
268 if (dst_offset < PAYLOAD_OFFSET)
269 __raw_writel(cpu_to_le32(*src), dst);
271 __raw_writel(*src, dst);
275 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
276 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
278 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
281 reg_write32(base, HC_MEMORY_REG,
282 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
284 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
285 (void *) ptd, sizeof(*ptd));
288 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
291 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
292 &ptd->dw1, 7*sizeof(ptd->dw1));
293 /* Make sure dw0 gets written last (after other dw's and after payload)
294 since it contains the enable bit */
296 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
301 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
302 static void init_memory(struct isp1760_hcd *priv)
307 payload_addr = PAYLOAD_OFFSET;
308 for (i = 0; i < BLOCK_1_NUM; i++) {
309 priv->memory_pool[i].start = payload_addr;
310 priv->memory_pool[i].size = BLOCK_1_SIZE;
311 priv->memory_pool[i].free = 1;
312 payload_addr += priv->memory_pool[i].size;
316 for (i = 0; i < BLOCK_2_NUM; i++) {
317 priv->memory_pool[curr + i].start = payload_addr;
318 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
319 priv->memory_pool[curr + i].free = 1;
320 payload_addr += priv->memory_pool[curr + i].size;
324 for (i = 0; i < BLOCK_3_NUM; i++) {
325 priv->memory_pool[curr + i].start = payload_addr;
326 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
327 priv->memory_pool[curr + i].free = 1;
328 payload_addr += priv->memory_pool[curr + i].size;
331 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
334 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
336 struct isp1760_hcd *priv = hcd_to_priv(hcd);
339 WARN_ON(qtd->payload_addr);
344 for (i = 0; i < BLOCKS; i++) {
345 if (priv->memory_pool[i].size >= qtd->length &&
346 priv->memory_pool[i].free) {
347 priv->memory_pool[i].free = 0;
348 qtd->payload_addr = priv->memory_pool[i].start;
354 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
356 struct isp1760_hcd *priv = hcd_to_priv(hcd);
359 if (!qtd->payload_addr)
362 for (i = 0; i < BLOCKS; i++) {
363 if (priv->memory_pool[i].start == qtd->payload_addr) {
364 WARN_ON(priv->memory_pool[i].free);
365 priv->memory_pool[i].free = 1;
366 qtd->payload_addr = 0;
371 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
372 __func__, qtd->payload_addr);
374 qtd->payload_addr = 0;
377 static int handshake(struct usb_hcd *hcd, u32 reg,
378 u32 mask, u32 done, int usec)
383 result = reg_read32(hcd->regs, reg);
395 /* reset a non-running (STS_HALT == 1) controller */
396 static int ehci_reset(struct usb_hcd *hcd)
399 struct isp1760_hcd *priv = hcd_to_priv(hcd);
401 u32 command = reg_read32(hcd->regs, HC_USBCMD);
403 command |= CMD_RESET;
404 reg_write32(hcd->regs, HC_USBCMD, command);
405 hcd->state = HC_STATE_HALT;
406 priv->next_statechange = jiffies;
407 retval = handshake(hcd, HC_USBCMD,
408 CMD_RESET, 0, 250 * 1000);
412 static struct isp1760_qh *qh_alloc(gfp_t flags)
414 struct isp1760_qh *qh;
416 qh = kmem_cache_zalloc(qh_cachep, flags);
420 INIT_LIST_HEAD(&qh->qh_list);
421 INIT_LIST_HEAD(&qh->qtd_list);
427 static void qh_free(struct isp1760_qh *qh)
429 WARN_ON(!list_empty(&qh->qtd_list));
430 WARN_ON(qh->slot > -1);
431 kmem_cache_free(qh_cachep, qh);
434 /* one-time init, only for memory state */
435 static int priv_init(struct usb_hcd *hcd)
437 struct isp1760_hcd *priv = hcd_to_priv(hcd);
441 spin_lock_init(&priv->lock);
443 for (i = 0; i < QH_END; i++)
444 INIT_LIST_HEAD(&priv->qh_list[i]);
447 * hw default: 1K periodic list heads, one per frame.
448 * periodic_size can shrink by USBCMD update if hcc_params allows.
450 priv->periodic_size = DEFAULT_I_TDPS;
452 /* controllers may cache some of the periodic schedule ... */
453 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
454 /* full frame cache */
455 if (HCC_ISOC_CACHE(hcc_params))
457 else /* N microframes cached */
458 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
463 static int isp1760_hc_setup(struct usb_hcd *hcd)
465 struct isp1760_hcd *priv = hcd_to_priv(hcd);
469 /* low-level chip reset */
470 if (priv->rst_gpio) {
471 gpiod_set_value_cansleep(priv->rst_gpio, 1);
473 gpiod_set_value_cansleep(priv->rst_gpio, 0);
476 /* Setup HW Mode Control: This assumes a level active-low interrupt */
477 hwmode = HW_DATA_BUS_32BIT;
479 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
480 hwmode &= ~HW_DATA_BUS_32BIT;
481 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
482 hwmode |= HW_ANA_DIGI_OC;
483 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
484 hwmode |= HW_DACK_POL_HIGH;
485 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
486 hwmode |= HW_DREQ_POL_HIGH;
487 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
488 hwmode |= HW_INTR_HIGH_ACT;
489 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
490 hwmode |= HW_INTR_EDGE_TRIG;
493 * We have to set this first in case we're in 16-bit mode.
494 * Write it twice to ensure correct upper bits if switching
497 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
498 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
500 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
501 /* Change bus pattern */
502 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
503 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
504 if (scratch != 0xdeadbabe) {
505 dev_err(hcd->self.controller, "Scratch test failed.\n");
510 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
511 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
512 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
513 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
516 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
519 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
522 result = ehci_reset(hcd);
528 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
529 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
530 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
531 "analog" : "digital");
534 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
536 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
538 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
541 * PORT 1 Control register of the ISP1760 is the OTG control
542 * register on ISP1761. Since there is no OTG or device controller
543 * support in this driver, we use port 1 as a "normal" USB host port on
546 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
549 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
551 return priv_init(hcd);
554 static u32 base_to_chip(u32 base)
556 return ((base - 0x400) >> 3);
559 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
563 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
567 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
568 return (qtd->urb != urb);
571 /* magic numbers that can affect system performance */
572 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
573 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
574 #define EHCI_TUNE_RL_TT 0
575 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
576 #define EHCI_TUNE_MULT_TT 1
577 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
579 static void create_ptd_atl(struct isp1760_qh *qh,
580 struct isp1760_qtd *qtd, struct ptd *ptd)
585 u32 nak = NAK_COUNTER;
587 memset(ptd, 0, sizeof(*ptd));
589 /* according to 3.6.2, max packet len can not be > 0x400 */
590 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
591 usb_pipeout(qtd->urb->pipe));
592 multi = 1 + ((maxpacket >> 11) & 0x3);
596 ptd->dw0 = DW0_VALID_BIT;
597 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
598 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
599 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
602 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
603 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
604 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
606 if (usb_pipebulk(qtd->urb->pipe))
607 ptd->dw1 |= DW1_TRANS_BULK;
608 else if (usb_pipeint(qtd->urb->pipe))
609 ptd->dw1 |= DW1_TRANS_INT;
611 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
612 /* split transaction */
614 ptd->dw1 |= DW1_TRANS_SPLIT;
615 if (qtd->urb->dev->speed == USB_SPEED_LOW)
616 ptd->dw1 |= DW1_SE_USB_LOSPEED;
618 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
619 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
621 /* SE bit for Split INT transfers */
622 if (usb_pipeint(qtd->urb->pipe) &&
623 (qtd->urb->dev->speed == USB_SPEED_LOW))
629 ptd->dw0 |= TO_DW0_MULTI(multi);
630 if (usb_pipecontrol(qtd->urb->pipe) ||
631 usb_pipebulk(qtd->urb->pipe))
632 ptd->dw3 |= TO_DW3_PING(qh->ping);
636 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
637 ptd->dw2 |= TO_DW2_RL(rl);
640 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
641 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
642 if (usb_pipecontrol(qtd->urb->pipe)) {
643 if (qtd->data_buffer == qtd->urb->setup_packet)
644 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
645 else if (last_qtd_of_urb(qtd, qh))
646 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
649 ptd->dw3 |= DW3_ACTIVE_BIT;
651 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
654 static void transform_add_int(struct isp1760_qh *qh,
655 struct isp1760_qtd *qtd, struct ptd *ptd)
661 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
662 * the algorithm from the original Philips driver code, which was
663 * pretty much used in this driver before as well, is quite horrendous
664 * and, i believe, incorrect. The code below follows the datasheet and
665 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
666 * more reliable this way (fingers crossed...).
669 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
670 /* urb->interval is in units of microframes (1/8 ms) */
671 period = qtd->urb->interval >> 3;
673 if (qtd->urb->interval > 4)
674 usof = 0x01; /* One bit set =>
675 interval 1 ms * uFrame-match */
676 else if (qtd->urb->interval > 2)
677 usof = 0x22; /* Two bits set => interval 1/2 ms */
678 else if (qtd->urb->interval > 1)
679 usof = 0x55; /* Four bits set => interval 1/4 ms */
681 usof = 0xff; /* All bits set => interval 1/8 ms */
683 /* urb->interval is in units of frames (1 ms) */
684 period = qtd->urb->interval;
685 usof = 0x0f; /* Execute Start Split on any of the
686 four first uFrames */
689 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
690 * complete split needs to be sent. Valid only for IN." Also,
691 * "All bits can be set to one for every transfer." (p 82,
692 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
693 * that number come from? 0xff seems to work fine...
695 /* ptd->dw5 = 0x1c; */
696 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
699 period = period >> 1;/* Ensure equal or shorter period than requested */
700 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
706 static void create_ptd_int(struct isp1760_qh *qh,
707 struct isp1760_qtd *qtd, struct ptd *ptd)
709 create_ptd_atl(qh, qtd, ptd);
710 transform_add_int(qh, qtd, ptd);
713 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
714 __releases(priv->lock)
715 __acquires(priv->lock)
717 struct isp1760_hcd *priv = hcd_to_priv(hcd);
719 if (!urb->unlinked) {
720 if (urb->status == -EINPROGRESS)
724 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
726 for (ptr = urb->transfer_buffer;
727 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
729 flush_dcache_page(virt_to_page(ptr));
732 /* complete() can reenter this HCD */
733 usb_hcd_unlink_urb_from_ep(hcd, urb);
734 spin_unlock(&priv->lock);
735 usb_hcd_giveback_urb(hcd, urb, urb->status);
736 spin_lock(&priv->lock);
739 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
742 struct isp1760_qtd *qtd;
744 qtd = kmem_cache_zalloc(qtd_cachep, flags);
748 INIT_LIST_HEAD(&qtd->qtd_list);
750 qtd->packet_type = packet_type;
751 qtd->status = QTD_ENQUEUED;
752 qtd->actual_length = 0;
757 static void qtd_free(struct isp1760_qtd *qtd)
759 WARN_ON(qtd->payload_addr);
760 kmem_cache_free(qtd_cachep, qtd);
763 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
764 struct isp1760_slotinfo *slots,
765 struct isp1760_qtd *qtd, struct isp1760_qh *qh,
768 struct isp1760_hcd *priv = hcd_to_priv(hcd);
771 WARN_ON((slot < 0) || (slot > 31));
772 WARN_ON(qtd->length && !qtd->payload_addr);
773 WARN_ON(slots[slot].qtd);
774 WARN_ON(slots[slot].qh);
775 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
777 /* Make sure done map has not triggered from some unlinked transfer */
778 if (ptd_offset == ATL_PTD_OFFSET) {
779 priv->atl_done_map |= reg_read32(hcd->regs,
780 HC_ATL_PTD_DONEMAP_REG);
781 priv->atl_done_map &= ~(1 << slot);
783 priv->int_done_map |= reg_read32(hcd->regs,
784 HC_INT_PTD_DONEMAP_REG);
785 priv->int_done_map &= ~(1 << slot);
789 qtd->status = QTD_XFER_STARTED;
790 slots[slot].timestamp = jiffies;
791 slots[slot].qtd = qtd;
793 ptd_write(hcd->regs, ptd_offset, slot, ptd);
795 if (ptd_offset == ATL_PTD_OFFSET) {
796 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
797 skip_map &= ~(1 << qh->slot);
798 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
800 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
801 skip_map &= ~(1 << qh->slot);
802 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
806 static int is_short_bulk(struct isp1760_qtd *qtd)
808 return (usb_pipebulk(qtd->urb->pipe) &&
809 (qtd->actual_length < qtd->length));
812 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
813 struct list_head *urb_list)
816 struct isp1760_qtd *qtd, *qtd_next;
817 struct urb_listitem *urb_listitem;
819 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
820 if (qtd->status < QTD_XFER_COMPLETE)
823 last_qtd = last_qtd_of_urb(qtd, qh);
825 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
826 qtd_next->status = QTD_RETIRE;
828 if (qtd->status == QTD_XFER_COMPLETE) {
829 if (qtd->actual_length) {
830 switch (qtd->packet_type) {
832 mem_reads8(hcd->regs, qtd->payload_addr,
835 /* Fall through (?) */
837 qtd->urb->actual_length +=
839 /* Fall through ... */
845 if (is_short_bulk(qtd)) {
846 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
847 qtd->urb->status = -EREMOTEIO;
849 qtd_next->status = QTD_RETIRE;
853 if (qtd->payload_addr)
857 if ((qtd->status == QTD_RETIRE) &&
858 (qtd->urb->status == -EINPROGRESS))
859 qtd->urb->status = -EPIPE;
860 /* Defer calling of urb_done() since it releases lock */
861 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
863 if (unlikely(!urb_listitem))
864 break; /* Try again on next call */
865 urb_listitem->urb = qtd->urb;
866 list_add_tail(&urb_listitem->urb_list, urb_list);
869 list_del(&qtd->qtd_list);
874 #define ENQUEUE_DEPTH 2
875 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
877 struct isp1760_hcd *priv = hcd_to_priv(hcd);
879 struct isp1760_slotinfo *slots;
880 int curr_slot, free_slot;
883 struct isp1760_qtd *qtd;
885 if (unlikely(list_empty(&qh->qtd_list))) {
890 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
891 if (qh->tt_buffer_dirty)
894 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
895 qtd_list)->urb->pipe)) {
896 ptd_offset = INT_PTD_OFFSET;
897 slots = priv->int_slots;
899 ptd_offset = ATL_PTD_OFFSET;
900 slots = priv->atl_slots;
904 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
905 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
906 free_slot = curr_slot;
907 if (slots[curr_slot].qh == qh)
912 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
913 if (qtd->status == QTD_ENQUEUED) {
914 WARN_ON(qtd->payload_addr);
916 if ((qtd->length) && (!qtd->payload_addr))
920 ((qtd->packet_type == SETUP_PID) ||
921 (qtd->packet_type == OUT_PID))) {
922 mem_writes8(hcd->regs, qtd->payload_addr,
923 qtd->data_buffer, qtd->length);
926 qtd->status = QTD_PAYLOAD_ALLOC;
929 if (qtd->status == QTD_PAYLOAD_ALLOC) {
931 if ((curr_slot > 31) && (free_slot == -1))
932 dev_dbg(hcd->self.controller, "%s: No slot "
933 "available for transfer\n", __func__);
935 /* Start xfer for this endpoint if not already done */
936 if ((curr_slot > 31) && (free_slot > -1)) {
937 if (usb_pipeint(qtd->urb->pipe))
938 create_ptd_int(qh, qtd, &ptd);
940 create_ptd_atl(qh, qtd, &ptd);
942 start_bus_transfer(hcd, ptd_offset, free_slot,
943 slots, qtd, qh, &ptd);
944 curr_slot = free_slot;
948 if (n >= ENQUEUE_DEPTH)
954 static void schedule_ptds(struct usb_hcd *hcd)
956 struct isp1760_hcd *priv;
957 struct isp1760_qh *qh, *qh_next;
958 struct list_head *ep_queue;
960 struct urb_listitem *urb_listitem, *urb_listitem_next;
968 priv = hcd_to_priv(hcd);
971 * check finished/retired xfers, transfer payloads, call urb_done()
973 for (i = 0; i < QH_END; i++) {
974 ep_queue = &priv->qh_list[i];
975 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
976 collect_qtds(hcd, qh, &urb_list);
977 if (list_empty(&qh->qtd_list))
978 list_del(&qh->qh_list);
982 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
984 isp1760_urb_done(hcd, urb_listitem->urb);
985 kmem_cache_free(urb_listitem_cachep, urb_listitem);
989 * Schedule packets for transfer.
991 * According to USB2.0 specification:
993 * 1st prio: interrupt xfers, up to 80 % of bandwidth
994 * 2nd prio: control xfers
995 * 3rd prio: bulk xfers
997 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
998 * is very unclear on how to prioritize traffic):
1000 * 1) Enqueue any queued control transfers, as long as payload chip mem
1001 * and PTD ATL slots are available.
1002 * 2) Enqueue any queued INT transfers, as long as payload chip mem
1003 * and PTD INT slots are available.
1004 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
1005 * and PTD ATL slots are available.
1007 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
1008 * conservation of chip mem and performance.
1010 * I'm sure this scheme could be improved upon!
1012 for (i = 0; i < QH_END; i++) {
1013 ep_queue = &priv->qh_list[i];
1014 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
1015 enqueue_qtds(hcd, qh);
1019 #define PTD_STATE_QTD_DONE 1
1020 #define PTD_STATE_QTD_RELOAD 2
1021 #define PTD_STATE_URB_RETIRE 3
1023 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1032 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1033 need to handle these errors? Is it done in hardware? */
1035 if (ptd->dw3 & DW3_HALT_BIT) {
1037 urb->status = -EPROTO; /* Default unknown error */
1039 for (i = 0; i < 8; i++) {
1040 switch (dw4 & 0x7) {
1042 dev_dbg(hcd->self.controller, "%s: underrun "
1043 "during uFrame %d\n",
1045 urb->status = -ECOMM; /* Could not write data */
1048 dev_dbg(hcd->self.controller, "%s: transaction "
1049 "error during uFrame %d\n",
1051 urb->status = -EPROTO; /* timeout, bad CRC, PID
1055 dev_dbg(hcd->self.controller, "%s: babble "
1056 "error during uFrame %d\n",
1058 urb->status = -EOVERFLOW;
1064 return PTD_STATE_URB_RETIRE;
1067 return PTD_STATE_QTD_DONE;
1070 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1074 if (ptd->dw3 & DW3_HALT_BIT) {
1075 if (ptd->dw3 & DW3_BABBLE_BIT)
1076 urb->status = -EOVERFLOW;
1077 else if (FROM_DW3_CERR(ptd->dw3))
1078 urb->status = -EPIPE; /* Stall */
1079 else if (ptd->dw3 & DW3_ERROR_BIT)
1080 urb->status = -EPROTO; /* XactErr */
1082 urb->status = -EPROTO; /* Unknown */
1084 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1085 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1086 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1088 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1089 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1091 return PTD_STATE_URB_RETIRE;
1094 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1095 /* Transfer Error, *but* active and no HALT -> reload */
1096 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1097 return PTD_STATE_QTD_RELOAD;
1100 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1102 * NAKs are handled in HW by the chip. Usually if the
1103 * device is not able to send data fast enough.
1104 * This happens mostly on slower hardware.
1106 return PTD_STATE_QTD_RELOAD;
1109 return PTD_STATE_QTD_DONE;
1112 static void handle_done_ptds(struct usb_hcd *hcd)
1114 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1116 struct isp1760_qh *qh;
1119 struct isp1760_slotinfo *slots;
1121 struct isp1760_qtd *qtd;
1125 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1126 priv->int_done_map &= ~skip_map;
1127 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1128 priv->atl_done_map &= ~skip_map;
1130 modified = priv->int_done_map || priv->atl_done_map;
1132 while (priv->int_done_map || priv->atl_done_map) {
1133 if (priv->int_done_map) {
1135 slot = __ffs(priv->int_done_map);
1136 priv->int_done_map &= ~(1 << slot);
1137 slots = priv->int_slots;
1138 /* This should not trigger, and could be removed if
1139 noone have any problems with it triggering: */
1140 if (!slots[slot].qh) {
1144 ptd_offset = INT_PTD_OFFSET;
1145 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1146 state = check_int_transfer(hcd, &ptd,
1147 slots[slot].qtd->urb);
1150 slot = __ffs(priv->atl_done_map);
1151 priv->atl_done_map &= ~(1 << slot);
1152 slots = priv->atl_slots;
1153 /* This should not trigger, and could be removed if
1154 noone have any problems with it triggering: */
1155 if (!slots[slot].qh) {
1159 ptd_offset = ATL_PTD_OFFSET;
1160 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1161 state = check_atl_transfer(hcd, &ptd,
1162 slots[slot].qtd->urb);
1165 qtd = slots[slot].qtd;
1166 slots[slot].qtd = NULL;
1167 qh = slots[slot].qh;
1168 slots[slot].qh = NULL;
1171 WARN_ON(qtd->status != QTD_XFER_STARTED);
1174 case PTD_STATE_QTD_DONE:
1175 if ((usb_pipeint(qtd->urb->pipe)) &&
1176 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1177 qtd->actual_length =
1178 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1180 qtd->actual_length =
1181 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1183 qtd->status = QTD_XFER_COMPLETE;
1184 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1188 qtd = list_entry(qtd->qtd_list.next,
1189 typeof(*qtd), qtd_list);
1191 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1192 qh->ping = FROM_DW3_PING(ptd.dw3);
1195 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1196 qtd->status = QTD_PAYLOAD_ALLOC;
1197 ptd.dw0 |= DW0_VALID_BIT;
1198 /* RL counter = ERR counter */
1199 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1200 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1201 ptd.dw3 &= ~TO_DW3_CERR(3);
1202 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1203 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1204 qh->ping = FROM_DW3_PING(ptd.dw3);
1207 case PTD_STATE_URB_RETIRE:
1208 qtd->status = QTD_RETIRE;
1209 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1210 (qtd->urb->status != -EPIPE) &&
1211 (qtd->urb->status != -EREMOTEIO)) {
1212 qh->tt_buffer_dirty = 1;
1213 if (usb_hub_clear_tt_buffer(qtd->urb))
1214 /* Clear failed; let's hope things work
1216 qh->tt_buffer_dirty = 0;
1228 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1229 if (slots == priv->int_slots) {
1230 if (state == PTD_STATE_QTD_RELOAD)
1231 dev_err(hcd->self.controller,
1232 "%s: PTD_STATE_QTD_RELOAD on "
1233 "interrupt packet\n", __func__);
1234 if (state != PTD_STATE_QTD_RELOAD)
1235 create_ptd_int(qh, qtd, &ptd);
1237 if (state != PTD_STATE_QTD_RELOAD)
1238 create_ptd_atl(qh, qtd, &ptd);
1241 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1250 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1252 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1254 irqreturn_t irqret = IRQ_NONE;
1256 spin_lock(&priv->lock);
1258 if (!(hcd->state & HC_STATE_RUNNING))
1261 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1262 if (unlikely(!imask))
1264 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1266 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1267 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1269 handle_done_ptds(hcd);
1271 irqret = IRQ_HANDLED;
1273 spin_unlock(&priv->lock);
1279 * Workaround for problem described in chip errata 2:
1281 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1282 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1283 * ATL done interrupts (the "instead of" might be important since it seems
1284 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1285 * to set the PTD's done bit in addition to not generating an interrupt!).
1287 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1288 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1290 * If we use SOF interrupts only, we get latency between ptd completion and the
1291 * actual handling. This is very noticeable in testusb runs which takes several
1292 * minutes longer without ATL interrupts.
1294 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1295 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1296 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1297 * completed and its done map bit is set.
1299 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1300 * not to cause too much lag when this HW bug occurs, while still hopefully
1301 * ensuring that the check does not falsely trigger.
1303 #define SLOT_TIMEOUT 300
1304 #define SLOT_CHECK_PERIOD 200
1305 static struct timer_list errata2_timer;
1307 static void errata2_function(unsigned long data)
1309 struct usb_hcd *hcd = (struct usb_hcd *) data;
1310 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1313 unsigned long spinflags;
1315 spin_lock_irqsave(&priv->lock, spinflags);
1317 for (slot = 0; slot < 32; slot++)
1318 if (priv->atl_slots[slot].qh && time_after(jiffies,
1319 priv->atl_slots[slot].timestamp +
1320 SLOT_TIMEOUT * HZ / 1000)) {
1321 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1322 if (!FROM_DW0_VALID(ptd.dw0) &&
1323 !FROM_DW3_ACTIVE(ptd.dw3))
1324 priv->atl_done_map |= 1 << slot;
1327 if (priv->atl_done_map)
1328 handle_done_ptds(hcd);
1330 spin_unlock_irqrestore(&priv->lock, spinflags);
1332 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1333 add_timer(&errata2_timer);
1336 static int isp1760_run(struct usb_hcd *hcd)
1343 hcd->uses_new_polling = 1;
1345 hcd->state = HC_STATE_RUNNING;
1347 /* Set PTD interrupt AND & OR maps */
1348 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1349 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1350 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1351 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1352 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1353 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1354 /* step 23 passed */
1356 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1357 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1359 command = reg_read32(hcd->regs, HC_USBCMD);
1360 command &= ~(CMD_LRESET|CMD_RESET);
1362 reg_write32(hcd->regs, HC_USBCMD, command);
1364 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1370 * Spec says to write FLAG_CF as last config action, priv code grabs
1371 * the semaphore while doing so.
1373 down_write(&ehci_cf_port_reset_rwsem);
1374 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1376 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1377 up_write(&ehci_cf_port_reset_rwsem);
1381 init_timer(&errata2_timer);
1382 errata2_timer.function = errata2_function;
1383 errata2_timer.data = (unsigned long) hcd;
1384 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1385 add_timer(&errata2_timer);
1387 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1388 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1389 chipid & 0xffff, chipid >> 16);
1391 /* PTD Register Init Part 2, Step 28 */
1393 /* Setup registers controlling PTD checking */
1394 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1395 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1396 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1397 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1398 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1399 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1400 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1401 ATL_BUF_FILL | INT_BUF_FILL);
1403 /* GRR this is run-once init(), being done every time the HC starts.
1404 * So long as they're part of class devices, we can't do it init()
1405 * since the class device isn't created that early.
1410 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1412 qtd->data_buffer = databuffer;
1414 if (len > MAX_PAYLOAD_SIZE)
1415 len = MAX_PAYLOAD_SIZE;
1421 static void qtd_list_free(struct list_head *qtd_list)
1423 struct isp1760_qtd *qtd, *qtd_next;
1425 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1426 list_del(&qtd->qtd_list);
1432 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1433 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1435 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1436 static void packetize_urb(struct usb_hcd *hcd,
1437 struct urb *urb, struct list_head *head, gfp_t flags)
1439 struct isp1760_qtd *qtd;
1441 int len, maxpacketsize;
1445 * URBs map to sequences of QTDs: one logical transaction
1448 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1449 /* XXX This looks like usb storage / SCSI bug */
1450 dev_err(hcd->self.controller,
1451 "buf is null, dma is %08lx len is %d\n",
1452 (long unsigned)urb->transfer_dma,
1453 urb->transfer_buffer_length);
1457 if (usb_pipein(urb->pipe))
1458 packet_type = IN_PID;
1460 packet_type = OUT_PID;
1462 if (usb_pipecontrol(urb->pipe)) {
1463 qtd = qtd_alloc(flags, urb, SETUP_PID);
1466 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1467 list_add_tail(&qtd->qtd_list, head);
1469 /* for zero length DATA stages, STATUS is always IN */
1470 if (urb->transfer_buffer_length == 0)
1471 packet_type = IN_PID;
1474 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1475 usb_pipeout(urb->pipe)));
1478 * buffer gets wrapped in one or more qtds;
1479 * last one may be "short" (including zero len)
1480 * and may serve as a control status ack
1482 buf = urb->transfer_buffer;
1483 len = urb->transfer_buffer_length;
1488 qtd = qtd_alloc(flags, urb, packet_type);
1491 this_qtd_len = qtd_fill(qtd, buf, len);
1492 list_add_tail(&qtd->qtd_list, head);
1494 len -= this_qtd_len;
1495 buf += this_qtd_len;
1502 * control requests may need a terminating data "status" ack;
1503 * bulk ones may need a terminating short packet (zero length).
1505 if (urb->transfer_buffer_length != 0) {
1508 if (usb_pipecontrol(urb->pipe)) {
1510 if (packet_type == IN_PID)
1511 packet_type = OUT_PID;
1513 packet_type = IN_PID;
1514 } else if (usb_pipebulk(urb->pipe)
1515 && (urb->transfer_flags & URB_ZERO_PACKET)
1516 && !(urb->transfer_buffer_length %
1521 qtd = qtd_alloc(flags, urb, packet_type);
1525 /* never any data in such packets */
1526 qtd_fill(qtd, NULL, 0);
1527 list_add_tail(&qtd->qtd_list, head);
1534 qtd_list_free(head);
1537 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1540 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1541 struct list_head *ep_queue;
1542 struct isp1760_qh *qh, *qhit;
1543 unsigned long spinflags;
1544 LIST_HEAD(new_qtds);
1548 switch (usb_pipetype(urb->pipe)) {
1550 ep_queue = &priv->qh_list[QH_CONTROL];
1553 ep_queue = &priv->qh_list[QH_BULK];
1555 case PIPE_INTERRUPT:
1556 if (urb->interval < 0)
1558 /* FIXME: Check bandwidth */
1559 ep_queue = &priv->qh_list[QH_INTERRUPT];
1561 case PIPE_ISOCHRONOUS:
1562 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1563 "not yet supported\n",
1567 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1572 if (usb_pipein(urb->pipe))
1573 urb->actual_length = 0;
1575 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1576 if (list_empty(&new_qtds))
1580 spin_lock_irqsave(&priv->lock, spinflags);
1582 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1583 retval = -ESHUTDOWN;
1584 qtd_list_free(&new_qtds);
1587 retval = usb_hcd_link_urb_to_ep(hcd, urb);
1589 qtd_list_free(&new_qtds);
1593 qh = urb->ep->hcpriv;
1596 list_for_each_entry(qhit, ep_queue, qh_list) {
1603 list_add_tail(&qh->qh_list, ep_queue);
1605 qh = qh_alloc(GFP_ATOMIC);
1608 usb_hcd_unlink_urb_from_ep(hcd, urb);
1609 qtd_list_free(&new_qtds);
1612 list_add_tail(&qh->qh_list, ep_queue);
1613 urb->ep->hcpriv = qh;
1616 list_splice_tail(&new_qtds, &qh->qtd_list);
1620 spin_unlock_irqrestore(&priv->lock, spinflags);
1624 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1625 struct isp1760_qh *qh)
1627 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1630 WARN_ON(qh->slot == -1);
1632 /* We need to forcefully reclaim the slot since some transfers never
1633 return, e.g. interrupt transfers and NAKed bulk transfers. */
1634 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1635 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1636 skip_map |= (1 << qh->slot);
1637 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1638 priv->atl_slots[qh->slot].qh = NULL;
1639 priv->atl_slots[qh->slot].qtd = NULL;
1641 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1642 skip_map |= (1 << qh->slot);
1643 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1644 priv->int_slots[qh->slot].qh = NULL;
1645 priv->int_slots[qh->slot].qtd = NULL;
1652 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1653 * any active transfer belonging to the urb in the process.
1655 static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1656 struct isp1760_qtd *qtd)
1659 int urb_was_running;
1662 urb_was_running = 0;
1663 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1664 if (qtd->urb != urb)
1667 if (qtd->status >= QTD_XFER_STARTED)
1668 urb_was_running = 1;
1669 if (last_qtd_of_urb(qtd, qh) &&
1670 (qtd->status >= QTD_XFER_COMPLETE))
1671 urb_was_running = 0;
1673 if (qtd->status == QTD_XFER_STARTED)
1674 kill_transfer(hcd, urb, qh);
1675 qtd->status = QTD_RETIRE;
1678 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1679 qh->tt_buffer_dirty = 1;
1680 if (usb_hub_clear_tt_buffer(urb))
1681 /* Clear failed; let's hope things work anyway */
1682 qh->tt_buffer_dirty = 0;
1686 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1689 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1690 unsigned long spinflags;
1691 struct isp1760_qh *qh;
1692 struct isp1760_qtd *qtd;
1695 spin_lock_irqsave(&priv->lock, spinflags);
1696 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1700 qh = urb->ep->hcpriv;
1706 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1707 if (qtd->urb == urb) {
1708 dequeue_urb_from_qtd(hcd, qh, qtd);
1709 list_move(&qtd->qtd_list, &qh->qtd_list);
1713 urb->status = status;
1717 spin_unlock_irqrestore(&priv->lock, spinflags);
1721 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1722 struct usb_host_endpoint *ep)
1724 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1725 unsigned long spinflags;
1726 struct isp1760_qh *qh, *qh_iter;
1729 spin_lock_irqsave(&priv->lock, spinflags);
1735 WARN_ON(!list_empty(&qh->qtd_list));
1737 for (i = 0; i < QH_END; i++)
1738 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1739 if (qh_iter == qh) {
1740 list_del(&qh_iter->qh_list);
1750 spin_unlock_irqrestore(&priv->lock, spinflags);
1753 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1755 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1756 u32 temp, status = 0;
1759 unsigned long flags;
1761 /* if !PM, root hub timers won't get shut down ... */
1762 if (!HC_IS_RUNNING(hcd->state))
1765 /* init status to no-changes */
1769 spin_lock_irqsave(&priv->lock, flags);
1770 temp = reg_read32(hcd->regs, HC_PORTSC1);
1772 if (temp & PORT_OWNER) {
1773 if (temp & PORT_CSC) {
1775 reg_write32(hcd->regs, HC_PORTSC1, temp);
1781 * Return status information even for ports with OWNER set.
1782 * Otherwise hub_wq wouldn't see the disconnect event when a
1783 * high-speed device is switched over to the companion
1784 * controller by the user.
1787 if ((temp & mask) != 0
1788 || ((temp & PORT_RESUME) != 0
1789 && time_after_eq(jiffies,
1790 priv->reset_done))) {
1791 buf [0] |= 1 << (0 + 1);
1794 /* FIXME autosuspend idle root hubs */
1796 spin_unlock_irqrestore(&priv->lock, flags);
1797 return status ? retval : 0;
1800 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1801 struct usb_hub_descriptor *desc)
1803 int ports = HCS_N_PORTS(priv->hcs_params);
1806 desc->bDescriptorType = 0x29;
1807 /* priv 1.0, 2.3.9 says 20ms max */
1808 desc->bPwrOn2PwrGood = 10;
1809 desc->bHubContrCurrent = 0;
1811 desc->bNbrPorts = ports;
1812 temp = 1 + (ports / 8);
1813 desc->bDescLength = 7 + 2 * temp;
1815 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1816 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1817 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1819 /* per-port overcurrent reporting */
1821 if (HCS_PPC(priv->hcs_params))
1822 /* per-port power control */
1825 /* no power switching */
1827 desc->wHubCharacteristics = cpu_to_le16(temp);
1830 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1832 static int check_reset_complete(struct usb_hcd *hcd, int index,
1835 if (!(port_status & PORT_CONNECT))
1838 /* if reset finished and it's still not enabled -- handoff */
1839 if (!(port_status & PORT_PE)) {
1841 dev_info(hcd->self.controller,
1842 "port %d full speed --> companion\n",
1845 port_status |= PORT_OWNER;
1846 port_status &= ~PORT_RWC_BITS;
1847 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1850 dev_info(hcd->self.controller, "port %d high speed\n",
1856 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1857 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1859 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1860 int ports = HCS_N_PORTS(priv->hcs_params);
1862 unsigned long flags;
1867 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1868 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1869 * (track current state ourselves) ... blink for diagnostics,
1870 * power, "this is the one", etc. EHCI spec supports this.
1873 spin_lock_irqsave(&priv->lock, flags);
1875 case ClearHubFeature:
1877 case C_HUB_LOCAL_POWER:
1878 case C_HUB_OVER_CURRENT:
1879 /* no hub-wide feature/status flags */
1885 case ClearPortFeature:
1886 if (!wIndex || wIndex > ports)
1889 temp = reg_read32(hcd->regs, HC_PORTSC1);
1892 * Even if OWNER is set, so the port is owned by the
1893 * companion controller, hub_wq needs to be able to clear
1894 * the port-change status bits (especially
1895 * USB_PORT_STAT_C_CONNECTION).
1899 case USB_PORT_FEAT_ENABLE:
1900 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1902 case USB_PORT_FEAT_C_ENABLE:
1905 case USB_PORT_FEAT_SUSPEND:
1906 if (temp & PORT_RESET)
1909 if (temp & PORT_SUSPEND) {
1910 if ((temp & PORT_PE) == 0)
1912 /* resume signaling for 20 msec */
1913 temp &= ~(PORT_RWC_BITS);
1914 reg_write32(hcd->regs, HC_PORTSC1,
1915 temp | PORT_RESUME);
1916 priv->reset_done = jiffies +
1917 msecs_to_jiffies(20);
1920 case USB_PORT_FEAT_C_SUSPEND:
1921 /* we auto-clear this feature */
1923 case USB_PORT_FEAT_POWER:
1924 if (HCS_PPC(priv->hcs_params))
1925 reg_write32(hcd->regs, HC_PORTSC1,
1926 temp & ~PORT_POWER);
1928 case USB_PORT_FEAT_C_CONNECTION:
1929 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1931 case USB_PORT_FEAT_C_OVER_CURRENT:
1934 case USB_PORT_FEAT_C_RESET:
1935 /* GetPortStatus clears reset */
1940 reg_read32(hcd->regs, HC_USBCMD);
1942 case GetHubDescriptor:
1943 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1947 /* no hub-wide feature/status flags */
1951 if (!wIndex || wIndex > ports)
1955 temp = reg_read32(hcd->regs, HC_PORTSC1);
1957 /* wPortChange bits */
1958 if (temp & PORT_CSC)
1959 status |= USB_PORT_STAT_C_CONNECTION << 16;
1962 /* whoever resumes must GetPortStatus to complete it!! */
1963 if (temp & PORT_RESUME) {
1964 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1966 /* Remote Wakeup received? */
1967 if (!priv->reset_done) {
1968 /* resume signaling for 20 msec */
1969 priv->reset_done = jiffies
1970 + msecs_to_jiffies(20);
1971 /* check the port again */
1972 mod_timer(&hcd->rh_timer, priv->reset_done);
1975 /* resume completed? */
1976 else if (time_after_eq(jiffies,
1977 priv->reset_done)) {
1978 status |= USB_PORT_STAT_C_SUSPEND << 16;
1979 priv->reset_done = 0;
1981 /* stop resume signaling */
1982 temp = reg_read32(hcd->regs, HC_PORTSC1);
1983 reg_write32(hcd->regs, HC_PORTSC1,
1984 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1985 retval = handshake(hcd, HC_PORTSC1,
1986 PORT_RESUME, 0, 2000 /* 2msec */);
1988 dev_err(hcd->self.controller,
1989 "port %d resume error %d\n",
1990 wIndex + 1, retval);
1993 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1997 /* whoever resets must GetPortStatus to complete it!! */
1998 if ((temp & PORT_RESET)
1999 && time_after_eq(jiffies,
2000 priv->reset_done)) {
2001 status |= USB_PORT_STAT_C_RESET << 16;
2002 priv->reset_done = 0;
2004 /* force reset to complete */
2005 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
2006 /* REVISIT: some hardware needs 550+ usec to clear
2007 * this bit; seems too long to spin routinely...
2009 retval = handshake(hcd, HC_PORTSC1,
2010 PORT_RESET, 0, 750);
2012 dev_err(hcd->self.controller, "port %d reset error %d\n",
2013 wIndex + 1, retval);
2017 /* see what we found out */
2018 temp = check_reset_complete(hcd, wIndex,
2019 reg_read32(hcd->regs, HC_PORTSC1));
2022 * Even if OWNER is set, there's no harm letting hub_wq
2023 * see the wPortStatus values (they should all be 0 except
2024 * for PORT_POWER anyway).
2027 if (temp & PORT_OWNER)
2028 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
2030 if (temp & PORT_CONNECT) {
2031 status |= USB_PORT_STAT_CONNECTION;
2032 /* status may be from integrated TT */
2033 status |= USB_PORT_STAT_HIGH_SPEED;
2036 status |= USB_PORT_STAT_ENABLE;
2037 if (temp & (PORT_SUSPEND|PORT_RESUME))
2038 status |= USB_PORT_STAT_SUSPEND;
2039 if (temp & PORT_RESET)
2040 status |= USB_PORT_STAT_RESET;
2041 if (temp & PORT_POWER)
2042 status |= USB_PORT_STAT_POWER;
2044 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2048 case C_HUB_LOCAL_POWER:
2049 case C_HUB_OVER_CURRENT:
2050 /* no hub-wide feature/status flags */
2056 case SetPortFeature:
2057 selector = wIndex >> 8;
2059 if (!wIndex || wIndex > ports)
2062 temp = reg_read32(hcd->regs, HC_PORTSC1);
2063 if (temp & PORT_OWNER)
2066 /* temp &= ~PORT_RWC_BITS; */
2068 case USB_PORT_FEAT_ENABLE:
2069 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2072 case USB_PORT_FEAT_SUSPEND:
2073 if ((temp & PORT_PE) == 0
2074 || (temp & PORT_RESET) != 0)
2077 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2079 case USB_PORT_FEAT_POWER:
2080 if (HCS_PPC(priv->hcs_params))
2081 reg_write32(hcd->regs, HC_PORTSC1,
2084 case USB_PORT_FEAT_RESET:
2085 if (temp & PORT_RESUME)
2087 /* line status bits may report this as low speed,
2088 * which can be fine if this root hub has a
2089 * transaction translator built in.
2091 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2092 && PORT_USB11(temp)) {
2099 * caller must wait, then call GetPortStatus
2100 * usb 2.0 spec says 50 ms resets on root
2102 priv->reset_done = jiffies +
2103 msecs_to_jiffies(50);
2105 reg_write32(hcd->regs, HC_PORTSC1, temp);
2110 reg_read32(hcd->regs, HC_USBCMD);
2115 /* "stall" on error */
2118 spin_unlock_irqrestore(&priv->lock, flags);
2122 static int isp1760_get_frame(struct usb_hcd *hcd)
2124 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2127 fr = reg_read32(hcd->regs, HC_FRINDEX);
2128 return (fr >> 3) % priv->periodic_size;
2131 static void isp1760_stop(struct usb_hcd *hcd)
2133 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2136 del_timer(&errata2_timer);
2138 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2142 spin_lock_irq(&priv->lock);
2145 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2146 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2147 spin_unlock_irq(&priv->lock);
2149 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2152 static void isp1760_shutdown(struct usb_hcd *hcd)
2157 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2158 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2160 command = reg_read32(hcd->regs, HC_USBCMD);
2161 command &= ~CMD_RUN;
2162 reg_write32(hcd->regs, HC_USBCMD, command);
2165 static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2166 struct usb_host_endpoint *ep)
2168 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2169 struct isp1760_qh *qh = ep->hcpriv;
2170 unsigned long spinflags;
2175 spin_lock_irqsave(&priv->lock, spinflags);
2176 qh->tt_buffer_dirty = 0;
2178 spin_unlock_irqrestore(&priv->lock, spinflags);
2182 static const struct hc_driver isp1760_hc_driver = {
2183 .description = "isp1760-hcd",
2184 .product_desc = "NXP ISP1760 USB Host Controller",
2185 .hcd_priv_size = sizeof(struct isp1760_hcd *),
2187 .flags = HCD_MEMORY | HCD_USB2,
2188 .reset = isp1760_hc_setup,
2189 .start = isp1760_run,
2190 .stop = isp1760_stop,
2191 .shutdown = isp1760_shutdown,
2192 .urb_enqueue = isp1760_urb_enqueue,
2193 .urb_dequeue = isp1760_urb_dequeue,
2194 .endpoint_disable = isp1760_endpoint_disable,
2195 .get_frame_number = isp1760_get_frame,
2196 .hub_status_data = isp1760_hub_status_data,
2197 .hub_control = isp1760_hub_control,
2198 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
2201 int __init isp1760_init_kmem_once(void)
2203 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
2204 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2205 SLAB_MEM_SPREAD, NULL);
2207 if (!urb_listitem_cachep)
2210 qtd_cachep = kmem_cache_create("isp1760_qtd",
2211 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2212 SLAB_MEM_SPREAD, NULL);
2217 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2218 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2221 kmem_cache_destroy(qtd_cachep);
2228 void isp1760_deinit_kmem_cache(void)
2230 kmem_cache_destroy(qtd_cachep);
2231 kmem_cache_destroy(qh_cachep);
2232 kmem_cache_destroy(urb_listitem_cachep);
2235 int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
2236 struct device *dev, unsigned int devflags)
2238 struct usb_hcd *hcd = NULL;
2239 struct isp1760_hcd *priv;
2245 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2249 /* prevent usb-core allocating DMA pages */
2250 dev->dma_mask = NULL;
2252 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2257 *(struct isp1760_hcd **)hcd->hcd_priv = priv;
2259 priv->devflags = devflags;
2261 priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
2262 if (IS_ERR(priv->rst_gpio)) {
2263 ret = PTR_ERR(priv->rst_gpio);
2268 hcd->regs = devm_ioremap_resource(dev, mem);
2269 if (IS_ERR(hcd->regs)) {
2270 ret = PTR_ERR(hcd->regs);
2275 hcd->rsrc_start = mem->start;
2276 hcd->rsrc_len = resource_size(mem);
2278 ret = usb_add_hcd(hcd, irq, irqflags);
2281 device_wakeup_enable(hcd->self.controller);
2283 dev_set_drvdata(dev, priv);
2292 void isp1760_unregister(struct device *dev)
2294 struct isp1760_hcd *priv = dev_get_drvdata(dev);
2295 struct usb_hcd *hcd = priv->hcd;
2297 usb_remove_hcd(hcd);
2301 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2302 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2303 MODULE_LICENSE("GPL v2");