2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for tuning/monitoring */
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
71 struct ehci_hcd { /* one per controller */
72 /* glue to PCI and HCD framework */
73 struct ehci_caps __iomem *caps;
74 struct ehci_regs __iomem *regs;
75 struct ehci_dbg_port __iomem *debug;
77 __u32 hcs_params; /* cached register copy */
79 enum ehci_rh_state rh_state;
81 /* async schedule support */
82 struct ehci_qh *async;
83 struct ehci_qh *dummy; /* For AMD quirk use */
84 struct ehci_qh *reclaim;
85 struct ehci_qh *qh_scan_next;
86 unsigned scanning : 1;
88 /* periodic schedule support */
89 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
90 unsigned periodic_size;
91 __hc32 *periodic; /* hw periodic table */
92 dma_addr_t periodic_dma;
93 unsigned i_thresh; /* uframes HC might cache */
95 union ehci_shadow *pshadow; /* mirror hw periodic table */
96 int next_uframe; /* scan periodic, start here */
97 unsigned periodic_sched; /* periodic activity count */
98 unsigned uframe_periodic_max; /* max periodic time per uframe */
101 /* list of itds & sitds completed while clock_frame was still active */
102 struct list_head cached_itd_list;
103 struct list_head cached_sitd_list;
104 unsigned clock_frame;
106 /* per root hub port */
107 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
109 /* bit vectors (one bit per port) */
110 unsigned long bus_suspended; /* which ports were
111 already suspended at the start of a bus suspend */
112 unsigned long companion_ports; /* which ports are
113 dedicated to the companion controller */
114 unsigned long owned_ports; /* which ports are
115 owned by the companion during a bus suspend */
116 unsigned long port_c_suspend; /* which ports have
117 the change-suspend feature turned on */
118 unsigned long suspended_ports; /* which ports are
120 unsigned long resuming_ports; /* which ports have
123 /* per-HC memory pools (could be per-bus, but ...) */
124 struct dma_pool *qh_pool; /* qh per active urb */
125 struct dma_pool *qtd_pool; /* one or more per qh */
126 struct dma_pool *itd_pool; /* itd per iso urb */
127 struct dma_pool *sitd_pool; /* sitd per split iso urb */
129 struct timer_list iaa_watchdog;
130 struct timer_list watchdog;
131 unsigned long actions;
132 unsigned periodic_stamp;
133 unsigned random_frame;
134 unsigned long next_statechange;
135 ktime_t last_periodic_enable;
139 unsigned no_selective_suspend:1;
140 unsigned has_fsl_port_bug:1; /* FreeScale */
141 unsigned big_endian_mmio:1;
142 unsigned big_endian_desc:1;
143 unsigned big_endian_capbase:1;
144 unsigned has_amcc_usb23:1;
145 unsigned need_io_watchdog:1;
146 unsigned broken_periodic:1;
147 unsigned amd_pll_fix:1;
148 unsigned fs_i_thresh:1; /* Intel iso scheduling */
149 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
150 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
151 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
153 /* required for usb32 quirk */
154 #define OHCI_CTRL_HCFS (3 << 6)
155 #define OHCI_USB_OPER (2 << 6)
156 #define OHCI_USB_SUSPEND (3 << 6)
158 #define OHCI_HCCTRL_OFFSET 0x4
159 #define OHCI_HCCTRL_LEN 0x4
160 __hc32 *ohci_hcctrl_reg;
161 unsigned has_hostpc:1;
162 unsigned has_lpm:1; /* support link power management */
163 unsigned has_ppcd:1; /* support per-port change bits */
164 u8 sbrn; /* packed release number */
168 struct ehci_stats stats;
169 # define COUNT(x) do { (x)++; } while (0)
171 # define COUNT(x) do {} while (0)
176 struct dentry *debug_dir;
180 /* convert between an HCD pointer and the corresponding EHCI_HCD */
181 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
183 return (struct ehci_hcd *) (hcd->hcd_priv);
185 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
187 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
192 iaa_watchdog_start(struct ehci_hcd *ehci)
194 WARN_ON(timer_pending(&ehci->iaa_watchdog));
195 mod_timer(&ehci->iaa_watchdog,
196 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
199 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
201 del_timer(&ehci->iaa_watchdog);
204 enum ehci_timer_action {
211 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
213 clear_bit (action, &ehci->actions);
216 static void free_cached_lists(struct ehci_hcd *ehci);
218 /*-------------------------------------------------------------------------*/
220 #include <linux/usb/ehci_def.h>
222 /*-------------------------------------------------------------------------*/
224 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
227 * EHCI Specification 0.95 Section 3.5
228 * QTD: describe data transfer components (buffer, direction, ...)
229 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
231 * These are associated only with "QH" (Queue Head) structures,
232 * used with control, bulk, and interrupt transfers.
235 /* first part defined by EHCI spec */
236 __hc32 hw_next; /* see EHCI 3.5.1 */
237 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
238 __hc32 hw_token; /* see EHCI 3.5.3 */
239 #define QTD_TOGGLE (1 << 31) /* data toggle */
240 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
241 #define QTD_IOC (1 << 15) /* interrupt on complete */
242 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
243 #define QTD_PID(tok) (((tok)>>8) & 0x3)
244 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
245 #define QTD_STS_HALT (1 << 6) /* halted on error */
246 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
247 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
248 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
249 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
250 #define QTD_STS_STS (1 << 1) /* split transaction state */
251 #define QTD_STS_PING (1 << 0) /* issue PING? */
253 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
254 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
255 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
257 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
258 __hc32 hw_buf_hi [5]; /* Appendix B */
260 /* the rest is HCD-private */
261 dma_addr_t qtd_dma; /* qtd address */
262 struct list_head qtd_list; /* sw qtd list */
263 struct urb *urb; /* qtd's urb */
264 size_t length; /* length of buffer */
265 } __attribute__ ((aligned (32)));
267 /* mask NakCnt+T in qh->hw_alt_next */
268 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
270 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
272 /*-------------------------------------------------------------------------*/
274 /* type tag from {qh,itd,sitd,fstn}->hw_next */
275 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
278 * Now the following defines are not converted using the
279 * cpu_to_le32() macro anymore, since we have to support
280 * "dynamic" switching between be and le support, so that the driver
281 * can be used on one system with SoC EHCI controller using big-endian
282 * descriptors as well as a normal little-endian PCI EHCI controller.
284 /* values for that type tag */
285 #define Q_TYPE_ITD (0 << 1)
286 #define Q_TYPE_QH (1 << 1)
287 #define Q_TYPE_SITD (2 << 1)
288 #define Q_TYPE_FSTN (3 << 1)
290 /* next async queue entry, or pointer to interrupt/periodic QH */
291 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
293 /* for periodic/async schedules and qtd lists, mark end of list */
294 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
297 * Entries in periodic shadow table are pointers to one of four kinds
298 * of data structure. That's dictated by the hardware; a type tag is
299 * encoded in the low bits of the hardware's periodic schedule. Use
300 * Q_NEXT_TYPE to get the tag.
302 * For entries in the async schedule, the type tag always says "qh".
305 struct ehci_qh *qh; /* Q_TYPE_QH */
306 struct ehci_itd *itd; /* Q_TYPE_ITD */
307 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
308 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
309 __hc32 *hw_next; /* (all types) */
313 /*-------------------------------------------------------------------------*/
316 * EHCI Specification 0.95 Section 3.6
317 * QH: describes control/bulk/interrupt endpoints
318 * See Fig 3-7 "Queue Head Structure Layout".
320 * These appear in both the async and (for interrupt) periodic schedules.
323 /* first part defined by EHCI spec */
325 __hc32 hw_next; /* see EHCI 3.6.1 */
326 __hc32 hw_info1; /* see EHCI 3.6.2 */
327 #define QH_HEAD 0x00008000
328 __hc32 hw_info2; /* see EHCI 3.6.2 */
329 #define QH_SMASK 0x000000ff
330 #define QH_CMASK 0x0000ff00
331 #define QH_HUBADDR 0x007f0000
332 #define QH_HUBPORT 0x3f800000
333 #define QH_MULT 0xc0000000
334 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
336 /* qtd overlay (hardware parts of a struct ehci_qtd) */
341 __hc32 hw_buf_hi [5];
342 } __attribute__ ((aligned(32)));
345 struct ehci_qh_hw *hw;
346 /* the rest is HCD-private */
347 dma_addr_t qh_dma; /* address of qh */
348 union ehci_shadow qh_next; /* ptr to qh; or periodic */
349 struct list_head qtd_list; /* sw qtd list */
350 struct ehci_qtd *dummy;
351 struct ehci_qh *reclaim; /* next to reclaim */
353 struct ehci_hcd *ehci;
354 unsigned long unlink_time;
357 * Do NOT use atomic operations for QH refcounting. On some CPUs
358 * (PPC7448 for example), atomic operations cannot be performed on
359 * memory that is cache-inhibited (i.e. being used for DMA).
360 * Spinlocks are used to protect all QH fields.
365 u8 needs_rescan; /* Dequeue during giveback */
367 #define QH_STATE_LINKED 1 /* HC sees this */
368 #define QH_STATE_UNLINK 2 /* HC may still see this */
369 #define QH_STATE_IDLE 3 /* HC doesn't see this */
370 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
371 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
373 u8 xacterrs; /* XactErr retry counter */
374 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
376 /* periodic schedule info */
377 u8 usecs; /* intr bandwidth */
378 u8 gap_uf; /* uframes split/csplit gap */
379 u8 c_usecs; /* ... split completion bw */
380 u16 tt_usecs; /* tt downstream bandwidth */
381 unsigned short period; /* polling interval */
382 unsigned short start; /* where polling starts */
383 #define NO_FRAME ((unsigned short)~0) /* pick new start */
385 struct usb_device *dev; /* access to TT */
386 unsigned is_out:1; /* bulk or intr OUT */
387 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
390 /*-------------------------------------------------------------------------*/
392 /* description of one iso transaction (up to 3 KB data if highspeed) */
393 struct ehci_iso_packet {
394 /* These will be copied to iTD when scheduling */
395 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
396 __hc32 transaction; /* itd->hw_transaction[i] |= */
397 u8 cross; /* buf crosses pages */
398 /* for full speed OUT splits */
402 /* temporary schedule data for packets from iso urbs (both speeds)
403 * each packet is one logical usb transaction to the device (not TT),
404 * beginning at stream->next_uframe
406 struct ehci_iso_sched {
407 struct list_head td_list;
409 struct ehci_iso_packet packet [0];
413 * ehci_iso_stream - groups all (s)itds for this endpoint.
414 * acts like a qh would, if EHCI had them for ISO.
416 struct ehci_iso_stream {
417 /* first field matches ehci_hq, but is NULL */
418 struct ehci_qh_hw *hw;
423 struct list_head td_list; /* queued itds/sitds */
424 struct list_head free_list; /* list of unused itds/sitds */
425 struct usb_device *udev;
426 struct usb_host_endpoint *ep;
428 /* output of (re)scheduling */
432 /* the rest is derived from the endpoint descriptor,
433 * trusting urb->interval == f(epdesc->bInterval) and
434 * including the extra info for hw_bufp[0..2]
443 /* This is used to initialize iTD's hw_bufp fields */
448 /* this is used to initialize sITD's tt info */
452 /*-------------------------------------------------------------------------*/
455 * EHCI Specification 0.95 Section 3.3
456 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
458 * Schedule records for high speed iso xfers
461 /* first part defined by EHCI spec */
462 __hc32 hw_next; /* see EHCI 3.3.1 */
463 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
464 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
465 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
466 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
467 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
468 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
469 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
471 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
473 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
474 __hc32 hw_bufp_hi [7]; /* Appendix B */
476 /* the rest is HCD-private */
477 dma_addr_t itd_dma; /* for this itd */
478 union ehci_shadow itd_next; /* ptr to periodic q entry */
481 struct ehci_iso_stream *stream; /* endpoint's queue */
482 struct list_head itd_list; /* list of stream's itds */
484 /* any/all hw_transactions here may be used by that urb */
485 unsigned frame; /* where scheduled */
487 unsigned index[8]; /* in urb->iso_frame_desc */
488 } __attribute__ ((aligned (32)));
490 /*-------------------------------------------------------------------------*/
493 * EHCI Specification 0.95 Section 3.4
494 * siTD, aka split-transaction isochronous Transfer Descriptor
495 * ... describe full speed iso xfers through TT in hubs
496 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
499 /* first part defined by EHCI spec */
501 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
502 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
503 __hc32 hw_uframe; /* EHCI table 3-10 */
504 __hc32 hw_results; /* EHCI table 3-11 */
505 #define SITD_IOC (1 << 31) /* interrupt on completion */
506 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
507 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
508 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
509 #define SITD_STS_ERR (1 << 6) /* error from TT */
510 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
511 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
512 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
513 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
514 #define SITD_STS_STS (1 << 1) /* split transaction state */
516 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
518 __hc32 hw_buf [2]; /* EHCI table 3-12 */
519 __hc32 hw_backpointer; /* EHCI table 3-13 */
520 __hc32 hw_buf_hi [2]; /* Appendix B */
522 /* the rest is HCD-private */
524 union ehci_shadow sitd_next; /* ptr to periodic q entry */
527 struct ehci_iso_stream *stream; /* endpoint's queue */
528 struct list_head sitd_list; /* list of stream's sitds */
531 } __attribute__ ((aligned (32)));
533 /*-------------------------------------------------------------------------*/
536 * EHCI Specification 0.96 Section 3.7
537 * Periodic Frame Span Traversal Node (FSTN)
539 * Manages split interrupt transactions (using TT) that span frame boundaries
540 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
541 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
542 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
545 __hc32 hw_next; /* any periodic q entry */
546 __hc32 hw_prev; /* qh or EHCI_LIST_END */
548 /* the rest is HCD-private */
550 union ehci_shadow fstn_next; /* ptr to periodic q entry */
551 } __attribute__ ((aligned (32)));
553 /*-------------------------------------------------------------------------*/
555 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
557 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
558 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
560 #define ehci_prepare_ports_for_controller_resume(ehci) \
561 ehci_adjust_port_wakeup_flags(ehci, false, false);
563 /*-------------------------------------------------------------------------*/
565 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
568 * Some EHCI controllers have a Transaction Translator built into the
569 * root hub. This is a non-standard feature. Each controller will need
570 * to add code to the following inline functions, and call them as
571 * needed (mostly in root hub code).
574 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
576 /* Returns the speed of a device attached to a port on the root hub. */
577 static inline unsigned int
578 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
580 if (ehci_is_TDI(ehci)) {
581 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
585 return USB_PORT_STAT_LOW_SPEED;
588 return USB_PORT_STAT_HIGH_SPEED;
591 return USB_PORT_STAT_HIGH_SPEED;
596 #define ehci_is_TDI(e) (0)
598 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
601 /*-------------------------------------------------------------------------*/
603 #ifdef CONFIG_PPC_83xx
604 /* Some Freescale processors have an erratum in which the TT
605 * port number in the queue head was 0..N-1 instead of 1..N.
607 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
609 #define ehci_has_fsl_portno_bug(e) (0)
613 * While most USB host controllers implement their registers in
614 * little-endian format, a minority (celleb companion chip) implement
615 * them in big endian format.
617 * This attempts to support either format at compile time without a
618 * runtime penalty, or both formats with the additional overhead
619 * of checking a flag bit.
621 * ehci_big_endian_capbase is a special quirk for controllers that
622 * implement the HC capability registers as separate registers and not
623 * as fields of a 32-bit register.
626 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
627 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
628 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
630 #define ehci_big_endian_mmio(e) 0
631 #define ehci_big_endian_capbase(e) 0
635 * Big-endian read/write functions are arch-specific.
636 * Other arches can be added if/when they're needed.
638 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
639 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
640 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
643 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
644 __u32 __iomem * regs)
646 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
647 return ehci_big_endian_mmio(ehci) ?
655 static inline void ehci_writel(const struct ehci_hcd *ehci,
656 const unsigned int val, __u32 __iomem *regs)
658 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
659 ehci_big_endian_mmio(ehci) ?
660 writel_be(val, regs) :
668 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
669 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
670 * Other common bits are dependent on has_amcc_usb23 quirk flag.
673 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
677 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
679 hc_control |= OHCI_USB_OPER;
681 hc_control |= OHCI_USB_SUSPEND;
683 writel_be(hc_control, ehci->ohci_hcctrl_reg);
684 (void) readl_be(ehci->ohci_hcctrl_reg);
687 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
691 /*-------------------------------------------------------------------------*/
694 * The AMCC 440EPx not only implements its EHCI registers in big-endian
695 * format, but also its DMA data structures (descriptors).
697 * EHCI controllers accessed through PCI work normally (little-endian
698 * everywhere), so we won't bother supporting a BE-only mode for now.
700 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
701 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
704 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
706 return ehci_big_endian_desc(ehci)
707 ? (__force __hc32)cpu_to_be32(x)
708 : (__force __hc32)cpu_to_le32(x);
712 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
714 return ehci_big_endian_desc(ehci)
715 ? be32_to_cpu((__force __be32)x)
716 : le32_to_cpu((__force __le32)x);
719 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
721 return ehci_big_endian_desc(ehci)
722 ? be32_to_cpup((__force __be32 *)x)
723 : le32_to_cpup((__force __le32 *)x);
729 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
731 return cpu_to_le32(x);
735 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
737 return le32_to_cpu(x);
740 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
742 return le32_to_cpup(x);
747 /*-------------------------------------------------------------------------*/
751 /* For working around the MosChip frame-index-register bug */
752 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
756 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
758 return ehci_readl(ehci, &ehci->regs->frame_index);
763 /*-------------------------------------------------------------------------*/
766 #define STUB_DEBUG_FILES
769 /*-------------------------------------------------------------------------*/
771 #endif /* __LINUX_EHCI_HCD_H */