2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/usb.h>
25 #include <linux/usb/hcd.h>
28 #include "pci-quirks.h"
30 #define DRIVER_DESC "EHCI PCI platform driver"
32 static const char hcd_name[] = "ehci-pci";
34 /* defined here to avoid adding to pci_ids.h for single instance use */
35 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
37 /*-------------------------------------------------------------------------*/
38 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
39 static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
41 return pdev->vendor == PCI_VENDOR_ID_INTEL &&
42 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
46 * 0x84 is the offset of in/out threshold register,
47 * and it is the same offset as the register of 'hostpc'.
49 #define intel_quark_x1000_insnreg01 hostpc
51 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
52 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
54 /* called after powerup, by probe or system-pm "wakeup" */
55 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
59 /* we expect static quirk code to handle the "extended capabilities"
60 * (currently just BIOS handoff) allowed starting with EHCI 0.96
63 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
64 retval = pci_set_mwi(pdev);
66 ehci_dbg(ehci, "MWI active\n");
68 /* Reset the threshold limit */
69 if (is_intel_quark_x1000(pdev)) {
71 * For the Intel QUARK X1000, raise the I/O threshold to the
72 * maximum usable value in order to improve performance.
74 ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
75 ehci->regs->intel_quark_x1000_insnreg01);
81 /* called during probe() after chip reset completes */
82 static int ehci_pci_setup(struct usb_hcd *hcd)
84 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
85 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
86 struct pci_dev *p_smbus;
91 ehci->caps = hcd->regs;
94 * ehci_init() causes memory for DMA transfers to be
95 * allocated. Thus, any vendor-specific workarounds based on
96 * limiting the type of memory used for DMA transfers must
97 * happen before ehci_setup() is called.
99 * Most other workarounds can be done either before or after
100 * init and reset; they are located here too.
102 switch (pdev->vendor) {
103 case PCI_VENDOR_ID_TOSHIBA_2:
104 /* celleb's companion chip */
105 if (pdev->device == 0x01b5) {
106 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
107 ehci->big_endian_mmio = 1;
110 "unsupported big endian Toshiba quirk\n");
114 case PCI_VENDOR_ID_NVIDIA:
115 /* NVidia reports that certain chips don't handle
116 * QH, ITD, or SITD addresses above 2GB. (But TD,
117 * data buffer, and periodic schedule are normal.)
119 switch (pdev->device) {
120 case 0x003c: /* MCP04 */
121 case 0x005b: /* CK804 */
122 case 0x00d8: /* CK8 */
123 case 0x00e8: /* CK8S */
124 if (pci_set_consistent_dma_mask(pdev,
125 DMA_BIT_MASK(31)) < 0)
126 ehci_warn(ehci, "can't enable NVidia "
127 "workaround for >2GB RAM\n");
130 /* Some NForce2 chips have problems with selective suspend;
131 * fixed in newer silicon.
134 if (pdev->revision < 0xa4)
135 ehci->no_selective_suspend = 1;
139 case PCI_VENDOR_ID_INTEL:
140 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
143 case PCI_VENDOR_ID_TDI:
144 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
147 case PCI_VENDOR_ID_AMD:
149 if (usb_amd_find_chipset_info())
150 ehci->amd_pll_fix = 1;
151 /* AMD8111 EHCI doesn't work, according to AMD errata */
152 if (pdev->device == 0x7463) {
153 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
159 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
160 * read/write memory space which does not belong to it when
161 * there is NULL pointer with T-bit set to 1 in the frame list
162 * table. To avoid the issue, the frame list link pointer
163 * should always contain a valid pointer to a inactive qh.
165 if (pdev->device == 0x7808) {
166 ehci->use_dummy_qh = 1;
167 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
170 case PCI_VENDOR_ID_VIA:
171 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
174 /* The VT6212 defaults to a 1 usec EHCI sleep time which
175 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
176 * that sleep time use the conventional 10 usec.
178 pci_read_config_byte(pdev, 0x4b, &tmp);
181 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
184 case PCI_VENDOR_ID_ATI:
186 if (usb_amd_find_chipset_info())
187 ehci->amd_pll_fix = 1;
190 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
191 * read/write memory space which does not belong to it when
192 * there is NULL pointer with T-bit set to 1 in the frame list
193 * table. To avoid the issue, the frame list link pointer
194 * should always contain a valid pointer to a inactive qh.
196 if (pdev->device == 0x4396) {
197 ehci->use_dummy_qh = 1;
198 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
200 /* SB600 and old version of SB700 have a bug in EHCI controller,
201 * which causes usb devices lose response in some cases.
203 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
204 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
205 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
209 rev = p_smbus->revision;
210 if ((pdev->device == 0x4386) || (rev == 0x3a)
213 ehci_info(ehci, "applying AMD SB600/SB700 USB "
214 "freeze workaround\n");
215 pci_read_config_byte(pdev, 0x53, &tmp);
216 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
218 pci_dev_put(p_smbus);
221 case PCI_VENDOR_ID_NETMOS:
222 /* MosChip frame-index-register bug */
223 ehci_info(ehci, "applying MosChip frame-index workaround\n");
224 ehci->frame_index_bug = 1;
228 /* optional debug port, normally in the first BAR */
229 temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
231 pci_read_config_dword(pdev, temp, &temp);
233 if (((temp >> 13) & 7) == 1) {
234 u32 hcs_params = ehci_readl(ehci,
235 &ehci->caps->hcs_params);
238 ehci->debug = hcd->regs + temp;
239 temp = ehci_readl(ehci, &ehci->debug->control);
240 ehci_info(ehci, "debug port %d%s\n",
241 HCS_DEBUG_PORT(hcs_params),
242 (temp & DBGP_ENABLED) ? " IN USE" : "");
243 if (!(temp & DBGP_ENABLED))
248 retval = ehci_setup(hcd);
252 /* These workarounds need to be applied after ehci_setup() */
253 switch (pdev->vendor) {
254 case PCI_VENDOR_ID_NEC:
255 ehci->need_io_watchdog = 0;
257 case PCI_VENDOR_ID_INTEL:
258 ehci->need_io_watchdog = 0;
260 case PCI_VENDOR_ID_NVIDIA:
261 switch (pdev->device) {
262 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
263 * fetching device descriptors unless LPM is disabled.
264 * There are also intermittent problems enumerating
265 * devices with PPCD enabled.
268 ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
270 ehci->command &= ~CMD_PPCEE;
276 /* at least the Genesys GL880S needs fixup here */
277 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
279 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
280 ehci_dbg(ehci, "bogus port configuration: "
281 "cc=%d x pcc=%d < ports=%d\n",
282 HCS_N_CC(ehci->hcs_params),
283 HCS_N_PCC(ehci->hcs_params),
284 HCS_N_PORTS(ehci->hcs_params));
286 switch (pdev->vendor) {
287 case 0x17a0: /* GENESYS */
288 /* GL880S: should be PORTS=2 */
289 temp |= (ehci->hcs_params & ~0xf);
290 ehci->hcs_params = temp;
292 case PCI_VENDOR_ID_NVIDIA:
293 /* NF4: should be PCC=10 */
298 /* Serial Bus Release Number is at PCI 0x60 offset */
299 if (pdev->vendor == PCI_VENDOR_ID_STMICRO
300 && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
301 ; /* ConneXT has no sbrn register */
303 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
305 /* Keep this around for a while just in case some EHCI
306 * implementation uses legacy PCI PM support. This test
307 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
308 * been triggered by then.
310 if (!device_can_wakeup(&pdev->dev)) {
313 pci_read_config_word(pdev, 0x62, &port_wake);
314 if (port_wake & 0x0001) {
315 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
316 device_set_wakeup_capable(&pdev->dev, 1);
320 #ifdef CONFIG_PM_RUNTIME
321 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
322 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
325 retval = ehci_pci_reinit(ehci, pdev);
330 /*-------------------------------------------------------------------------*/
334 /* suspend/resume, section 4.3 */
336 /* These routines rely on the PCI bus glue
337 * to handle powerdown and wakeup, and currently also on
338 * transceivers that don't need any software attention to set up
339 * the right sort of wakeup.
340 * Also they depend on separate root hub suspend/resume.
343 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
345 return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
346 pdev->vendor == PCI_VENDOR_ID_INTEL &&
347 (pdev->device == 0x1E26 ||
348 pdev->device == 0x8C2D ||
349 pdev->device == 0x8C26 ||
350 pdev->device == 0x9C26);
353 static void ehci_enable_xhci_companion(void)
355 struct pci_dev *companion = NULL;
357 /* The xHCI and EHCI controllers are not on the same PCI slot */
358 for_each_pci_dev(companion) {
359 if (!usb_is_intel_switchable_xhci(companion))
361 usb_enable_xhci_ports(companion);
366 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
368 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
369 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
371 /* The BIOS on systems with the Intel Panther Point chipset may or may
372 * not support xHCI natively. That means that during system resume, it
373 * may switch the ports back to EHCI so that users can use their
374 * keyboard to select a kernel from GRUB after resume from hibernate.
376 * The BIOS is supposed to remember whether the OS had xHCI ports
377 * enabled before resume, and switch the ports back to xHCI when the
378 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
381 * Unconditionally switch the ports back to xHCI after a system resume.
382 * We can't tell whether the EHCI or xHCI controller will be resumed
383 * first, so we have to do the port switchover in both drivers. Writing
384 * a '1' to the port switchover registers should have no effect if the
385 * port was already switched over.
387 if (usb_is_intel_switchable_ehci(pdev))
388 ehci_enable_xhci_companion();
390 if (ehci_resume(hcd, hibernated) != 0)
391 (void) ehci_pci_reinit(ehci, pdev);
397 #define ehci_suspend NULL
398 #define ehci_pci_resume NULL
399 #endif /* CONFIG_PM */
401 static struct hc_driver __read_mostly ehci_pci_hc_driver;
403 static const struct ehci_driver_overrides pci_overrides __initconst = {
404 .reset = ehci_pci_setup,
407 /*-------------------------------------------------------------------------*/
409 /* PCI driver selection metadata; PCI hotplugging uses this */
410 static const struct pci_device_id pci_ids [] = { {
411 /* handle any USB 2.0 EHCI controller */
412 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
413 .driver_data = (unsigned long) &ehci_pci_hc_driver,
415 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
416 .driver_data = (unsigned long) &ehci_pci_hc_driver,
418 { /* end: all zeroes */ }
420 MODULE_DEVICE_TABLE(pci, pci_ids);
422 /* pci driver glue; this is a "new style" PCI driver module */
423 static struct pci_driver ehci_pci_driver = {
424 .name = (char *) hcd_name,
427 .probe = usb_hcd_pci_probe,
428 .remove = usb_hcd_pci_remove,
429 .shutdown = usb_hcd_pci_shutdown,
433 .pm = &usb_hcd_pci_pm_ops
438 static int __init ehci_pci_init(void)
443 pr_info("%s: " DRIVER_DESC "\n", hcd_name);
445 ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
447 /* Entries for the PCI suspend/resume callbacks are special */
448 ehci_pci_hc_driver.pci_suspend = ehci_suspend;
449 ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
451 return pci_register_driver(&ehci_pci_driver);
453 module_init(ehci_pci_init);
455 static void __exit ehci_pci_cleanup(void)
457 pci_unregister_driver(&ehci_pci_driver);
459 module_exit(ehci_pci_cleanup);
461 MODULE_DESCRIPTION(DRIVER_DESC);
462 MODULE_AUTHOR("David Brownell");
463 MODULE_AUTHOR("Alan Stern");
464 MODULE_LICENSE("GPL");