2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
25 /*-------------------------------------------------------------------------*/
27 /* called after powerup, by probe or system-pm "wakeup" */
28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
32 /* we expect static quirk code to handle the "extended capabilities"
33 * (currently just BIOS handoff) allowed starting with EHCI 0.96
36 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
37 retval = pci_set_mwi(pdev);
39 ehci_dbg(ehci, "MWI active\n");
44 static int ehci_quirk_amd_hudson(struct ehci_hcd *ehci)
46 struct pci_dev *amd_smbus_dev;
49 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
51 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
53 pci_dev_put(amd_smbus_dev);
58 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL);
61 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
62 if (rev < 0x11 || rev > 0x18) {
63 pci_dev_put(amd_smbus_dev);
70 amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
72 ehci_info(ehci, "QUIRK: Enable exception for AMD Hudson ASPM\n");
74 pci_dev_put(amd_smbus_dev);
80 /* called during probe() after chip reset completes */
81 static int ehci_pci_setup(struct usb_hcd *hcd)
83 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
84 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
85 struct pci_dev *p_smbus;
90 switch (pdev->vendor) {
91 case PCI_VENDOR_ID_TOSHIBA_2:
92 /* celleb's companion chip */
93 if (pdev->device == 0x01b5) {
94 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
95 ehci->big_endian_mmio = 1;
98 "unsupported big endian Toshiba quirk\n");
104 ehci->caps = hcd->regs;
105 ehci->regs = hcd->regs +
106 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
108 dbg_hcs_params(ehci, "reset");
109 dbg_hcc_params(ehci, "reset");
111 /* ehci_init() causes memory for DMA transfers to be
112 * allocated. Thus, any vendor-specific workarounds based on
113 * limiting the type of memory used for DMA transfers must
114 * happen before ehci_init() is called. */
115 switch (pdev->vendor) {
116 case PCI_VENDOR_ID_NVIDIA:
117 /* NVidia reports that certain chips don't handle
118 * QH, ITD, or SITD addresses above 2GB. (But TD,
119 * data buffer, and periodic schedule are normal.)
121 switch (pdev->device) {
122 case 0x003c: /* MCP04 */
123 case 0x005b: /* CK804 */
124 case 0x00d8: /* CK8 */
125 case 0x00e8: /* CK8S */
126 if (pci_set_consistent_dma_mask(pdev,
127 DMA_BIT_MASK(31)) < 0)
128 ehci_warn(ehci, "can't enable NVidia "
129 "workaround for >2GB RAM\n");
135 /* cache this readonly data; minimize chip reads */
136 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
138 if (ehci_quirk_amd_hudson(ehci))
139 ehci->amd_l1_fix = 1;
141 retval = ehci_halt(ehci);
145 /* data structure init */
146 retval = ehci_init(hcd);
150 switch (pdev->vendor) {
151 case PCI_VENDOR_ID_INTEL:
152 ehci->need_io_watchdog = 0;
153 if (pdev->device == 0x27cc) {
154 ehci->broken_periodic = 1;
155 ehci_info(ehci, "using broken periodic workaround\n");
158 case PCI_VENDOR_ID_TDI:
159 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
164 case PCI_VENDOR_ID_AMD:
165 /* AMD8111 EHCI doesn't work, according to AMD errata */
166 if (pdev->device == 0x7463) {
167 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
172 case PCI_VENDOR_ID_NVIDIA:
173 switch (pdev->device) {
174 /* Some NForce2 chips have problems with selective suspend;
175 * fixed in newer silicon.
178 if (pdev->revision < 0xa4)
179 ehci->no_selective_suspend = 1;
183 case PCI_VENDOR_ID_VIA:
184 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
187 /* The VT6212 defaults to a 1 usec EHCI sleep time which
188 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
189 * that sleep time use the conventional 10 usec.
191 pci_read_config_byte(pdev, 0x4b, &tmp);
194 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
197 case PCI_VENDOR_ID_ATI:
198 /* SB600 and old version of SB700 have a bug in EHCI controller,
199 * which causes usb devices lose response in some cases.
201 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
202 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
203 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
207 rev = p_smbus->revision;
208 if ((pdev->device == 0x4386) || (rev == 0x3a)
211 ehci_info(ehci, "applying AMD SB600/SB700 USB "
212 "freeze workaround\n");
213 pci_read_config_byte(pdev, 0x53, &tmp);
214 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
216 pci_dev_put(p_smbus);
221 /* optional debug port, normally in the first BAR */
222 temp = pci_find_capability(pdev, 0x0a);
224 pci_read_config_dword(pdev, temp, &temp);
226 if ((temp & (3 << 13)) == (1 << 13)) {
228 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
229 temp = ehci_readl(ehci, &ehci->debug->control);
230 ehci_info(ehci, "debug port %d%s\n",
231 HCS_DEBUG_PORT(ehci->hcs_params),
232 (temp & DBGP_ENABLED)
235 if (!(temp & DBGP_ENABLED))
242 /* at least the Genesys GL880S needs fixup here */
243 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
245 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
246 ehci_dbg(ehci, "bogus port configuration: "
247 "cc=%d x pcc=%d < ports=%d\n",
248 HCS_N_CC(ehci->hcs_params),
249 HCS_N_PCC(ehci->hcs_params),
250 HCS_N_PORTS(ehci->hcs_params));
252 switch (pdev->vendor) {
253 case 0x17a0: /* GENESYS */
254 /* GL880S: should be PORTS=2 */
255 temp |= (ehci->hcs_params & ~0xf);
256 ehci->hcs_params = temp;
258 case PCI_VENDOR_ID_NVIDIA:
259 /* NF4: should be PCC=10 */
264 /* Serial Bus Release Number is at PCI 0x60 offset */
265 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
267 /* Keep this around for a while just in case some EHCI
268 * implementation uses legacy PCI PM support. This test
269 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
270 * been triggered by then.
272 if (!device_can_wakeup(&pdev->dev)) {
275 pci_read_config_word(pdev, 0x62, &port_wake);
276 if (port_wake & 0x0001) {
277 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
278 device_set_wakeup_capable(&pdev->dev, 1);
282 #ifdef CONFIG_USB_SUSPEND
283 /* REVISIT: the controller works fine for wakeup iff the root hub
284 * itself is "globally" suspended, but usbcore currently doesn't
285 * understand such things.
287 * System suspend currently expects to be able to suspend the entire
288 * device tree, device-at-a-time. If we failed selective suspend
289 * reports, system suspend would fail; so the root hub code must claim
290 * success. That's lying to usbcore, and it matters for runtime
291 * PM scenarios with selective suspend and remote wakeup...
293 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
294 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
297 ehci_port_power(ehci, 1);
298 retval = ehci_pci_reinit(ehci, pdev);
303 /*-------------------------------------------------------------------------*/
307 /* suspend/resume, section 4.3 */
309 /* These routines rely on the PCI bus glue
310 * to handle powerdown and wakeup, and currently also on
311 * transceivers that don't need any software attention to set up
312 * the right sort of wakeup.
313 * Also they depend on separate root hub suspend/resume.
316 static int ehci_pci_suspend(struct usb_hcd *hcd)
318 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
322 if (time_before(jiffies, ehci->next_statechange))
325 /* Root hub was already suspended. Disable irq emission and
326 * mark HW unaccessible, bail out if RH has been resumed. Use
327 * the spinlock to properly synchronize with possible pending
328 * RH suspend or resume activity.
330 * This is still racy as hcd->state is manipulated outside of
331 * any locks =P But that will be a different fix.
333 spin_lock_irqsave (&ehci->lock, flags);
334 if (hcd->state != HC_STATE_SUSPENDED) {
338 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
339 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
341 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
343 spin_unlock_irqrestore (&ehci->lock, flags);
345 // could save FLADJ in case of Vaux power loss
346 // ... we'd only use it to handle clock skew
351 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
353 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
354 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
356 // maybe restore FLADJ
358 if (time_before(jiffies, ehci->next_statechange))
361 /* Mark hardware accessible again as we are out of D3 state by now */
362 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
364 /* If CF is still set and we aren't resuming from hibernation
365 * then we maintained PCI Vaux power.
366 * Just undo the effect of ehci_pci_suspend().
368 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
370 int mask = INTR_MASK;
372 if (!hcd->self.root_hub->do_remote_wakeup)
374 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
375 ehci_readl(ehci, &ehci->regs->intr_enable);
379 usb_root_hub_lost_power(hcd->self.root_hub);
381 /* Else reset, to cope with power loss or flush-to-storage
382 * style "resume" having let BIOS kick in during reboot.
384 (void) ehci_halt(ehci);
385 (void) ehci_reset(ehci);
386 (void) ehci_pci_reinit(ehci, pdev);
388 /* emptying the schedule aborts any urbs */
389 spin_lock_irq(&ehci->lock);
391 end_unlink_async(ehci);
393 spin_unlock_irq(&ehci->lock);
395 ehci_writel(ehci, ehci->command, &ehci->regs->command);
396 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
397 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
399 /* here we "know" root ports should always stay powered */
400 ehci_port_power(ehci, 1);
402 hcd->state = HC_STATE_SUSPENDED;
407 static const struct hc_driver ehci_pci_hc_driver = {
408 .description = hcd_name,
409 .product_desc = "EHCI Host Controller",
410 .hcd_priv_size = sizeof(struct ehci_hcd),
413 * generic hardware linkage
416 .flags = HCD_MEMORY | HCD_USB2,
419 * basic lifecycle operations
421 .reset = ehci_pci_setup,
424 .pci_suspend = ehci_pci_suspend,
425 .pci_resume = ehci_pci_resume,
428 .shutdown = ehci_shutdown,
431 * managing i/o requests and associated device resources
433 .urb_enqueue = ehci_urb_enqueue,
434 .urb_dequeue = ehci_urb_dequeue,
435 .endpoint_disable = ehci_endpoint_disable,
436 .endpoint_reset = ehci_endpoint_reset,
441 .get_frame_number = ehci_get_frame,
446 .hub_status_data = ehci_hub_status_data,
447 .hub_control = ehci_hub_control,
448 .bus_suspend = ehci_bus_suspend,
449 .bus_resume = ehci_bus_resume,
450 .relinquish_port = ehci_relinquish_port,
451 .port_handed_over = ehci_port_handed_over,
453 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
456 /*-------------------------------------------------------------------------*/
458 /* PCI driver selection metadata; PCI hotplugging uses this */
459 static const struct pci_device_id pci_ids [] = { {
460 /* handle any USB 2.0 EHCI controller */
461 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
462 .driver_data = (unsigned long) &ehci_pci_hc_driver,
464 { /* end: all zeroes */ }
466 MODULE_DEVICE_TABLE(pci, pci_ids);
468 /* pci driver glue; this is a "new style" PCI driver module */
469 static struct pci_driver ehci_pci_driver = {
470 .name = (char *) hcd_name,
473 .probe = usb_hcd_pci_probe,
474 .remove = usb_hcd_pci_remove,
475 .shutdown = usb_hcd_pci_shutdown,
477 #ifdef CONFIG_PM_SLEEP
479 .pm = &usb_hcd_pci_pm_ops