2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/ktime.h>
32 #include <linux/list.h>
33 #include <linux/interrupt.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/debugfs.h>
39 #include "../core/hcd.h"
41 #include <asm/byteorder.h>
44 #include <asm/system.h>
45 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
63 #define DRIVER_AUTHOR "David Brownell"
64 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
66 static const char hcd_name [] = "ehci_hcd";
76 /* magic numbers that can affect system performance */
77 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
78 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
79 #define EHCI_TUNE_RL_TT 0
80 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
81 #define EHCI_TUNE_MULT_TT 1
82 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
84 #define EHCI_IAA_MSECS 10 /* arbitrary */
85 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
86 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
87 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
89 /* Initial IRQ latency: faster than hw default */
90 static int log2_irq_thresh = 0; // 0 to 6
91 module_param (log2_irq_thresh, int, S_IRUGO);
92 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
94 /* initial park setting: slower than hw default */
95 static unsigned park = 0;
96 module_param (park, uint, S_IRUGO);
97 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
99 /* for flakey hardware, ignore overcurrent indicators */
100 static int ignore_oc = 0;
101 module_param (ignore_oc, bool, S_IRUGO);
102 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
104 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
106 /* for ASPM quirk of ISOC on AMD SB800 */
107 static struct pci_dev *amd_nb_dev;
109 /*-------------------------------------------------------------------------*/
112 #include "ehci-dbg.c"
114 /*-------------------------------------------------------------------------*/
117 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
119 /* Don't override timeouts which shrink or (later) disable
120 * the async ring; just the I/O watchdog. Note that if a
121 * SHRINK were pending, OFF would never be requested.
123 if (timer_pending(&ehci->watchdog)
124 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
128 if (!test_and_set_bit(action, &ehci->actions)) {
132 case TIMER_IO_WATCHDOG:
133 if (!ehci->need_io_watchdog)
137 case TIMER_ASYNC_OFF:
138 t = EHCI_ASYNC_JIFFIES;
140 /* case TIMER_ASYNC_SHRINK: */
142 /* add a jiffie since we synch against the
143 * 8 KHz uframe counter.
145 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
148 mod_timer(&ehci->watchdog, t + jiffies);
152 /*-------------------------------------------------------------------------*/
155 * handshake - spin reading hc until handshake completes or fails
156 * @ptr: address of hc register to be read
157 * @mask: bits to look at in result of read
158 * @done: value of those bits when handshake succeeds
159 * @usec: timeout in microseconds
161 * Returns negative errno, or zero on success
163 * Success happens when the "mask" bits have the specified value (hardware
164 * handshake done). There are two failure modes: "usec" have passed (major
165 * hardware flakeout), or the register reads as all-ones (hardware removed).
167 * That last failure should_only happen in cases like physical cardbus eject
168 * before driver shutdown. But it also seems to be caused by bugs in cardbus
169 * bridge shutdown: shutting down the bridge before the devices using it.
171 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
172 u32 mask, u32 done, int usec)
177 result = ehci_readl(ehci, ptr);
178 if (result == ~(u32)0) /* card removed */
189 /* force HC to halt state from unknown (EHCI spec section 2.3) */
190 static int ehci_halt (struct ehci_hcd *ehci)
192 u32 temp = ehci_readl(ehci, &ehci->regs->status);
194 /* disable any irqs left enabled by previous code */
195 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
197 if ((temp & STS_HALT) != 0)
200 temp = ehci_readl(ehci, &ehci->regs->command);
202 ehci_writel(ehci, temp, &ehci->regs->command);
203 return handshake (ehci, &ehci->regs->status,
204 STS_HALT, STS_HALT, 16 * 125);
207 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
208 u32 mask, u32 done, int usec)
212 error = handshake(ehci, ptr, mask, done, usec);
215 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
216 ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n",
217 ptr, mask, done, error);
223 /* put TDI/ARC silicon into EHCI mode */
224 static void tdi_reset (struct ehci_hcd *ehci)
226 u32 __iomem *reg_ptr;
229 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
230 tmp = ehci_readl(ehci, reg_ptr);
231 tmp |= USBMODE_CM_HC;
232 /* The default byte access to MMR space is LE after
233 * controller reset. Set the required endian mode
234 * for transfer buffers to match the host microprocessor
236 if (ehci_big_endian_mmio(ehci))
238 ehci_writel(ehci, tmp, reg_ptr);
241 /* reset a non-running (STS_HALT == 1) controller */
242 static int ehci_reset (struct ehci_hcd *ehci)
245 u32 command = ehci_readl(ehci, &ehci->regs->command);
247 /* If the EHCI debug controller is active, special care must be
248 * taken before and after a host controller reset */
249 if (ehci->debug && !dbgp_reset_prep())
252 command |= CMD_RESET;
253 dbg_cmd (ehci, "reset", command);
254 ehci_writel(ehci, command, &ehci->regs->command);
255 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
256 ehci->next_statechange = jiffies;
257 retval = handshake (ehci, &ehci->regs->command,
258 CMD_RESET, 0, 250 * 1000);
260 if (ehci->has_hostpc) {
261 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
262 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
263 ehci_writel(ehci, TXFIFO_DEFAULT,
264 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
269 if (ehci_is_TDI(ehci))
273 dbgp_external_startup();
278 /* idle the controller (from running) */
279 static void ehci_quiesce (struct ehci_hcd *ehci)
284 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
288 /* wait for any schedule enables/disables to take effect */
289 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
290 temp &= STS_ASS | STS_PSS;
291 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
292 STS_ASS | STS_PSS, temp, 16 * 125))
295 /* then disable anything that's still active */
296 temp = ehci_readl(ehci, &ehci->regs->command);
297 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
298 ehci_writel(ehci, temp, &ehci->regs->command);
300 /* hardware can take 16 microframes to turn off ... */
301 handshake_on_error_set_halt(ehci, &ehci->regs->status,
302 STS_ASS | STS_PSS, 0, 16 * 125);
305 /*-------------------------------------------------------------------------*/
307 static void end_unlink_async(struct ehci_hcd *ehci);
308 static void ehci_work(struct ehci_hcd *ehci);
310 #include "ehci-hub.c"
311 #include "ehci-mem.c"
313 #include "ehci-sched.c"
315 /*-------------------------------------------------------------------------*/
317 static void ehci_iaa_watchdog(unsigned long param)
319 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
322 spin_lock_irqsave (&ehci->lock, flags);
324 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
325 * So we need this watchdog, but must protect it against both
326 * (a) SMP races against real IAA firing and retriggering, and
327 * (b) clean HC shutdown, when IAA watchdog was pending.
330 && !timer_pending(&ehci->iaa_watchdog)
331 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
334 /* If we get here, IAA is *REALLY* late. It's barely
335 * conceivable that the system is so busy that CMD_IAAD
336 * is still legitimately set, so let's be sure it's
337 * clear before we read STS_IAA. (The HC should clear
338 * CMD_IAAD when it sets STS_IAA.)
340 cmd = ehci_readl(ehci, &ehci->regs->command);
342 ehci_writel(ehci, cmd & ~CMD_IAAD,
343 &ehci->regs->command);
345 /* If IAA is set here it either legitimately triggered
346 * before we cleared IAAD above (but _way_ late, so we'll
347 * still count it as lost) ... or a silicon erratum:
348 * - VIA seems to set IAA without triggering the IRQ;
349 * - IAAD potentially cleared without setting IAA.
351 status = ehci_readl(ehci, &ehci->regs->status);
352 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
353 COUNT (ehci->stats.lost_iaa);
354 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
357 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
359 end_unlink_async(ehci);
362 spin_unlock_irqrestore(&ehci->lock, flags);
365 static void ehci_watchdog(unsigned long param)
367 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
370 spin_lock_irqsave(&ehci->lock, flags);
372 /* stop async processing after it's idled a bit */
373 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
374 start_unlink_async (ehci, ehci->async);
376 /* ehci could run by timer, without IRQs ... */
379 spin_unlock_irqrestore (&ehci->lock, flags);
382 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
383 * The firmware seems to think that powering off is a wakeup event!
384 * This routine turns off remote wakeup and everything else, on all ports.
386 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
388 int port = HCS_N_PORTS(ehci->hcs_params);
391 ehci_writel(ehci, PORT_RWC_BITS,
392 &ehci->regs->port_status[port]);
396 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
397 * Should be called with ehci->lock held.
399 static void ehci_silence_controller(struct ehci_hcd *ehci)
402 ehci_turn_off_all_ports(ehci);
404 /* make BIOS/etc use companion controller during reboot */
405 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
407 /* unblock posted writes */
408 ehci_readl(ehci, &ehci->regs->configured_flag);
411 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
412 * This forcibly disables dma and IRQs, helping kexec and other cases
413 * where the next system software may expect clean state.
415 static void ehci_shutdown(struct usb_hcd *hcd)
417 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
419 del_timer_sync(&ehci->watchdog);
420 del_timer_sync(&ehci->iaa_watchdog);
422 spin_lock_irq(&ehci->lock);
423 ehci_silence_controller(ehci);
424 spin_unlock_irq(&ehci->lock);
427 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
431 if (!HCS_PPC (ehci->hcs_params))
434 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
435 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
436 (void) ehci_hub_control(ehci_to_hcd(ehci),
437 is_on ? SetPortFeature : ClearPortFeature,
440 /* Flush those writes */
441 ehci_readl(ehci, &ehci->regs->command);
445 /*-------------------------------------------------------------------------*/
448 * ehci_work is called from some interrupts, timers, and so on.
449 * it calls driver completion functions, after dropping ehci->lock.
451 static void ehci_work (struct ehci_hcd *ehci)
453 timer_action_done (ehci, TIMER_IO_WATCHDOG);
455 /* another CPU may drop ehci->lock during a schedule scan while
456 * it reports urb completions. this flag guards against bogus
457 * attempts at re-entrant schedule scanning.
463 if (ehci->next_uframe != -1)
464 scan_periodic (ehci);
467 /* the IO watchdog guards against hardware or driver bugs that
468 * misplace IRQs, and should let us run completely without IRQs.
469 * such lossage has been observed on both VT6202 and VT8235.
471 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
472 (ehci->async->qh_next.ptr != NULL ||
473 ehci->periodic_sched != 0))
474 timer_action (ehci, TIMER_IO_WATCHDOG);
478 * Called when the ehci_hcd module is removed.
480 static void ehci_stop (struct usb_hcd *hcd)
482 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
484 ehci_dbg (ehci, "stop\n");
486 /* no more interrupts ... */
487 del_timer_sync (&ehci->watchdog);
488 del_timer_sync(&ehci->iaa_watchdog);
490 spin_lock_irq(&ehci->lock);
491 if (HC_IS_RUNNING (hcd->state))
494 ehci_silence_controller(ehci);
496 spin_unlock_irq(&ehci->lock);
498 remove_companion_file(ehci);
499 remove_debug_files (ehci);
501 /* root hub is shut down separately (first, when possible) */
502 spin_lock_irq (&ehci->lock);
505 spin_unlock_irq (&ehci->lock);
506 ehci_mem_cleanup (ehci);
509 pci_dev_put(amd_nb_dev);
514 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
515 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
516 ehci->stats.lost_iaa);
517 ehci_dbg (ehci, "complete %ld unlink %ld\n",
518 ehci->stats.complete, ehci->stats.unlink);
521 dbg_status (ehci, "ehci_stop completed",
522 ehci_readl(ehci, &ehci->regs->status));
525 /* one-time init, only for memory state */
526 static int ehci_init(struct usb_hcd *hcd)
528 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
532 struct ehci_qh_hw *hw;
534 spin_lock_init(&ehci->lock);
537 * keep io watchdog by default, those good HCDs could turn off it later
539 ehci->need_io_watchdog = 1;
540 init_timer(&ehci->watchdog);
541 ehci->watchdog.function = ehci_watchdog;
542 ehci->watchdog.data = (unsigned long) ehci;
544 init_timer(&ehci->iaa_watchdog);
545 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
546 ehci->iaa_watchdog.data = (unsigned long) ehci;
548 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
551 * hw default: 1K periodic list heads, one per frame.
552 * periodic_size can shrink by USBCMD update if hcc_params allows.
554 ehci->periodic_size = DEFAULT_I_TDPS;
555 INIT_LIST_HEAD(&ehci->cached_itd_list);
556 INIT_LIST_HEAD(&ehci->cached_sitd_list);
558 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
559 /* periodic schedule size can be smaller than default */
560 switch (EHCI_TUNE_FLS) {
561 case 0: ehci->periodic_size = 1024; break;
562 case 1: ehci->periodic_size = 512; break;
563 case 2: ehci->periodic_size = 256; break;
567 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
570 /* controllers may cache some of the periodic schedule ... */
571 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
573 else // N microframes cached
574 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
576 ehci->reclaim = NULL;
577 ehci->next_uframe = -1;
578 ehci->clock_frame = -1;
581 * dedicate a qh for the async ring head, since we couldn't unlink
582 * a 'real' qh without stopping the async schedule [4.8]. use it
583 * as the 'reclamation list head' too.
584 * its dummy is used in hw_alt_next of many tds, to prevent the qh
585 * from automatically advancing to the next td after short reads.
587 ehci->async->qh_next.qh = NULL;
588 hw = ehci->async->hw;
589 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
590 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
591 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
592 hw->hw_qtd_next = EHCI_LIST_END(ehci);
593 ehci->async->qh_state = QH_STATE_LINKED;
594 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
596 /* clear interrupt enables, set irq latency */
597 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
599 temp = 1 << (16 + log2_irq_thresh);
600 if (HCC_CANPARK(hcc_params)) {
601 /* HW default park == 3, on hardware that supports it (like
602 * NVidia and ALI silicon), maximizes throughput on the async
603 * schedule by avoiding QH fetches between transfers.
605 * With fast usb storage devices and NForce2, "park" seems to
606 * make problems: throughput reduction (!), data errors...
609 park = min(park, (unsigned) 3);
613 ehci_dbg(ehci, "park %d\n", park);
615 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
616 /* periodic schedule size can be smaller than default */
618 temp |= (EHCI_TUNE_FLS << 2);
620 ehci->command = temp;
625 /* start HC running; it's halted, ehci_init() has been run (once) */
626 static int ehci_run (struct usb_hcd *hcd)
628 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
633 hcd->uses_new_polling = 1;
636 /* EHCI spec section 4.1 */
637 if ((retval = ehci_reset(ehci)) != 0) {
638 ehci_mem_cleanup(ehci);
641 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
642 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
645 * hcc_params controls whether ehci->regs->segment must (!!!)
646 * be used; it constrains QH/ITD/SITD and QTD locations.
647 * pci_pool consistent memory always uses segment zero.
648 * streaming mappings for I/O buffers, like pci_map_single(),
649 * can return segments above 4GB, if the device allows.
651 * NOTE: the dma mask is visible through dma_supported(), so
652 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
653 * Scsi_Host.highmem_io, and so forth. It's readonly to all
654 * host side drivers though.
656 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
657 if (HCC_64BIT_ADDR(hcc_params)) {
658 ehci_writel(ehci, 0, &ehci->regs->segment);
660 // this is deeply broken on almost all architectures
661 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
662 ehci_info(ehci, "enabled 64bit DMA\n");
667 // Philips, Intel, and maybe others need CMD_RUN before the
668 // root hub will detect new devices (why?); NEC doesn't
669 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
670 ehci->command |= CMD_RUN;
671 ehci_writel(ehci, ehci->command, &ehci->regs->command);
672 dbg_cmd (ehci, "init", ehci->command);
675 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
676 * are explicitly handed to companion controller(s), so no TT is
677 * involved with the root hub. (Except where one is integrated,
678 * and there's no companion controller unless maybe for USB OTG.)
680 * Turning on the CF flag will transfer ownership of all ports
681 * from the companions to the EHCI controller. If any of the
682 * companions are in the middle of a port reset at the time, it
683 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
684 * guarantees that no resets are in progress. After we set CF,
685 * a short delay lets the hardware catch up; new resets shouldn't
686 * be started before the port switching actions could complete.
688 down_write(&ehci_cf_port_reset_rwsem);
689 hcd->state = HC_STATE_RUNNING;
690 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
691 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
693 up_write(&ehci_cf_port_reset_rwsem);
694 ehci->last_periodic_enable = ktime_get_real();
696 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
698 "USB %x.%x started, EHCI %x.%02x%s\n",
699 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
700 temp >> 8, temp & 0xff,
701 ignore_oc ? ", overcurrent ignored" : "");
703 ehci_writel(ehci, INTR_MASK,
704 &ehci->regs->intr_enable); /* Turn On Interrupts */
706 /* GRR this is run-once init(), being done every time the HC starts.
707 * So long as they're part of class devices, we can't do it init()
708 * since the class device isn't created that early.
710 create_debug_files(ehci);
711 create_companion_file(ehci);
716 /*-------------------------------------------------------------------------*/
718 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
720 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
721 u32 status, masked_status, pcd_status = 0, cmd;
724 spin_lock (&ehci->lock);
726 status = ehci_readl(ehci, &ehci->regs->status);
728 /* e.g. cardbus physical eject */
729 if (status == ~(u32) 0) {
730 ehci_dbg (ehci, "device removed\n");
734 masked_status = status & INTR_MASK;
735 if (!masked_status) { /* irq sharing? */
736 spin_unlock(&ehci->lock);
740 /* clear (just) interrupts */
741 ehci_writel(ehci, masked_status, &ehci->regs->status);
742 cmd = ehci_readl(ehci, &ehci->regs->command);
746 /* unrequested/ignored: Frame List Rollover */
747 dbg_status (ehci, "irq", status);
750 /* INT, ERR, and IAA interrupt rates can be throttled */
752 /* normal [4.15.1.2] or error [4.15.1.1] completion */
753 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
754 if (likely ((status & STS_ERR) == 0))
755 COUNT (ehci->stats.normal);
757 COUNT (ehci->stats.error);
761 /* complete the unlinking of some qh [4.15.2.3] */
762 if (status & STS_IAA) {
763 /* guard against (alleged) silicon errata */
764 if (cmd & CMD_IAAD) {
765 ehci_writel(ehci, cmd & ~CMD_IAAD,
766 &ehci->regs->command);
767 ehci_dbg(ehci, "IAA with IAAD still set?\n");
770 COUNT(ehci->stats.reclaim);
771 end_unlink_async(ehci);
773 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
776 /* remote wakeup [4.3.1] */
777 if (status & STS_PCD) {
778 unsigned i = HCS_N_PORTS (ehci->hcs_params);
780 /* kick root hub later */
783 /* resume root hub? */
784 if (!(cmd & CMD_RUN))
785 usb_hcd_resume_root_hub(hcd);
788 int pstatus = ehci_readl(ehci,
789 &ehci->regs->port_status [i]);
791 if (pstatus & PORT_OWNER)
793 if (!(test_bit(i, &ehci->suspended_ports) &&
794 ((pstatus & PORT_RESUME) ||
795 !(pstatus & PORT_SUSPEND)) &&
796 (pstatus & PORT_PE) &&
797 ehci->reset_done[i] == 0))
800 /* start 20 msec resume signaling from this port,
801 * and make khubd collect PORT_STAT_C_SUSPEND to
802 * stop that signaling. Use 5 ms extra for safety,
803 * like usb_port_resume() does.
805 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
806 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
807 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
811 /* PCI errors [4.15.2.4] */
812 if (unlikely ((status & STS_FATAL) != 0)) {
813 ehci_err(ehci, "fatal error\n");
814 dbg_cmd(ehci, "fatal", cmd);
815 dbg_status(ehci, "fatal", status);
819 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
820 /* generic layer kills/unlinks all urbs, then
821 * uses ehci_stop to clean up the rest
828 spin_unlock (&ehci->lock);
830 usb_hcd_poll_rh_status(hcd);
834 /*-------------------------------------------------------------------------*/
837 * non-error returns are a promise to giveback() the urb later
838 * we drop ownership so next owner (or urb unlink) can get it
840 * urb + dev is in hcd.self.controller.urb_list
841 * we're queueing TDs onto software and hardware lists
843 * hcd-specific init for hcpriv hasn't been done yet
845 * NOTE: control, bulk, and interrupt share the same code to append TDs
846 * to a (possibly active) QH, and the same QH scanning code.
848 static int ehci_urb_enqueue (
853 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
854 struct list_head qtd_list;
856 INIT_LIST_HEAD (&qtd_list);
858 switch (usb_pipetype (urb->pipe)) {
860 /* qh_completions() code doesn't handle all the fault cases
861 * in multi-TD control transfers. Even 1KB is rare anyway.
863 if (urb->transfer_buffer_length > (16 * 1024))
866 /* case PIPE_BULK: */
868 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
870 return submit_async(ehci, urb, &qtd_list, mem_flags);
873 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
875 return intr_submit(ehci, urb, &qtd_list, mem_flags);
877 case PIPE_ISOCHRONOUS:
878 if (urb->dev->speed == USB_SPEED_HIGH)
879 return itd_submit (ehci, urb, mem_flags);
881 return sitd_submit (ehci, urb, mem_flags);
885 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
888 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
889 end_unlink_async(ehci);
891 /* If the QH isn't linked then there's nothing we can do
892 * unless we were called during a giveback, in which case
893 * qh_completions() has to deal with it.
895 if (qh->qh_state != QH_STATE_LINKED) {
896 if (qh->qh_state == QH_STATE_COMPLETING)
897 qh->needs_rescan = 1;
901 /* defer till later if busy */
903 struct ehci_qh *last;
905 for (last = ehci->reclaim;
907 last = last->reclaim)
909 qh->qh_state = QH_STATE_UNLINK_WAIT;
912 /* start IAA cycle */
914 start_unlink_async (ehci, qh);
917 /* remove from hardware lists
918 * completions normally happen asynchronously
921 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
923 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
928 spin_lock_irqsave (&ehci->lock, flags);
929 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
933 switch (usb_pipetype (urb->pipe)) {
934 // case PIPE_CONTROL:
937 qh = (struct ehci_qh *) urb->hcpriv;
940 switch (qh->qh_state) {
941 case QH_STATE_LINKED:
942 case QH_STATE_COMPLETING:
943 unlink_async(ehci, qh);
945 case QH_STATE_UNLINK:
946 case QH_STATE_UNLINK_WAIT:
947 /* already started */
950 /* QH might be waiting for a Clear-TT-Buffer */
951 qh_completions(ehci, qh);
957 qh = (struct ehci_qh *) urb->hcpriv;
960 switch (qh->qh_state) {
961 case QH_STATE_LINKED:
962 case QH_STATE_COMPLETING:
963 intr_deschedule (ehci, qh);
966 qh_completions (ehci, qh);
969 ehci_dbg (ehci, "bogus qh %p state %d\n",
975 case PIPE_ISOCHRONOUS:
978 // wait till next completion, do it then.
979 // completion irqs can wait up to 1024 msec,
983 spin_unlock_irqrestore (&ehci->lock, flags);
987 /*-------------------------------------------------------------------------*/
989 // bulk qh holds the data toggle
992 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
994 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
996 struct ehci_qh *qh, *tmp;
998 /* ASSERT: any requests/urbs are being unlinked */
999 /* ASSERT: nobody can be submitting urbs for this any more */
1002 spin_lock_irqsave (&ehci->lock, flags);
1007 /* endpoints can be iso streams. for now, we don't
1008 * accelerate iso completions ... so spin a while.
1010 if (qh->hw == NULL) {
1011 ehci_vdbg (ehci, "iso delay\n");
1015 if (!HC_IS_RUNNING (hcd->state))
1016 qh->qh_state = QH_STATE_IDLE;
1017 switch (qh->qh_state) {
1018 case QH_STATE_LINKED:
1019 case QH_STATE_COMPLETING:
1020 for (tmp = ehci->async->qh_next.qh;
1022 tmp = tmp->qh_next.qh)
1024 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1025 * may already be unlinked.
1028 unlink_async(ehci, qh);
1030 case QH_STATE_UNLINK: /* wait for hw to finish? */
1031 case QH_STATE_UNLINK_WAIT:
1033 spin_unlock_irqrestore (&ehci->lock, flags);
1034 schedule_timeout_uninterruptible(1);
1036 case QH_STATE_IDLE: /* fully unlinked */
1037 if (qh->clearing_tt)
1039 if (list_empty (&qh->qtd_list)) {
1043 /* else FALL THROUGH */
1045 /* caller was supposed to have unlinked any requests;
1046 * that's not our job. just leak this memory.
1048 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1049 qh, ep->desc.bEndpointAddress, qh->qh_state,
1050 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1055 spin_unlock_irqrestore (&ehci->lock, flags);
1060 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1062 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1064 int eptype = usb_endpoint_type(&ep->desc);
1065 int epnum = usb_endpoint_num(&ep->desc);
1066 int is_out = usb_endpoint_dir_out(&ep->desc);
1067 unsigned long flags;
1069 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1072 spin_lock_irqsave(&ehci->lock, flags);
1075 /* For Bulk and Interrupt endpoints we maintain the toggle state
1076 * in the hardware; the toggle bits in udev aren't used at all.
1077 * When an endpoint is reset by usb_clear_halt() we must reset
1078 * the toggle bit in the QH.
1081 usb_settoggle(qh->dev, epnum, is_out, 0);
1082 if (!list_empty(&qh->qtd_list)) {
1083 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1084 } else if (qh->qh_state == QH_STATE_LINKED ||
1085 qh->qh_state == QH_STATE_COMPLETING) {
1087 /* The toggle value in the QH can't be updated
1088 * while the QH is active. Unlink it now;
1089 * re-linking will call qh_refresh().
1091 if (eptype == USB_ENDPOINT_XFER_BULK)
1092 unlink_async(ehci, qh);
1094 intr_deschedule(ehci, qh);
1097 spin_unlock_irqrestore(&ehci->lock, flags);
1100 static int ehci_get_frame (struct usb_hcd *hcd)
1102 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1103 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1104 ehci->periodic_size;
1107 /*-------------------------------------------------------------------------*/
1109 MODULE_DESCRIPTION(DRIVER_DESC);
1110 MODULE_AUTHOR (DRIVER_AUTHOR);
1111 MODULE_LICENSE ("GPL");
1114 #include "ehci-pci.c"
1115 #define PCI_DRIVER ehci_pci_driver
1118 #ifdef CONFIG_USB_EHCI_FSL
1119 #include "ehci-fsl.c"
1120 #define PLATFORM_DRIVER ehci_fsl_driver
1123 #ifdef CONFIG_SOC_AU1200
1124 #include "ehci-au1xxx.c"
1125 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1128 #ifdef CONFIG_PPC_PS3
1129 #include "ehci-ps3.c"
1130 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1133 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1134 #include "ehci-ppc-of.c"
1135 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1138 #ifdef CONFIG_PLAT_ORION
1139 #include "ehci-orion.c"
1140 #define PLATFORM_DRIVER ehci_orion_driver
1143 #ifdef CONFIG_ARCH_IXP4XX
1144 #include "ehci-ixp4xx.c"
1145 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1148 #ifdef CONFIG_USB_W90X900_EHCI
1149 #include "ehci-w90x900.c"
1150 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1153 #ifdef CONFIG_ARCH_AT91
1154 #include "ehci-atmel.c"
1155 #define PLATFORM_DRIVER ehci_atmel_driver
1158 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1159 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
1160 #error "missing bus glue for ehci-hcd"
1163 static int __init ehci_hcd_init(void)
1170 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1171 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1172 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1173 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1174 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1175 " before uhci_hcd and ohci_hcd, not after\n");
1177 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1179 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1180 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1183 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1184 if (!ehci_debug_root) {
1190 #ifdef PLATFORM_DRIVER
1191 retval = platform_driver_register(&PLATFORM_DRIVER);
1197 retval = pci_register_driver(&PCI_DRIVER);
1202 #ifdef PS3_SYSTEM_BUS_DRIVER
1203 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1208 #ifdef OF_PLATFORM_DRIVER
1209 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1215 #ifdef OF_PLATFORM_DRIVER
1216 /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
1219 #ifdef PS3_SYSTEM_BUS_DRIVER
1220 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1224 pci_unregister_driver(&PCI_DRIVER);
1227 #ifdef PLATFORM_DRIVER
1228 platform_driver_unregister(&PLATFORM_DRIVER);
1232 debugfs_remove(ehci_debug_root);
1233 ehci_debug_root = NULL;
1236 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1239 module_init(ehci_hcd_init);
1241 static void __exit ehci_hcd_cleanup(void)
1243 #ifdef OF_PLATFORM_DRIVER
1244 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1246 #ifdef PLATFORM_DRIVER
1247 platform_driver_unregister(&PLATFORM_DRIVER);
1250 pci_unregister_driver(&PCI_DRIVER);
1252 #ifdef PS3_SYSTEM_BUS_DRIVER
1253 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1256 debugfs_remove(ehci_debug_root);
1258 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1260 module_exit(ehci_hcd_cleanup);