1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
25 #include <linux/slab.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
32 #include <plat/regs-usb-hsotg-phy.h>
33 #include <plat/regs-usb-hsotg.h>
34 #include <mach/regs-sys.h>
35 #include <plat/udc-hs.h>
37 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
41 * Unfortunately there seems to be a limit of the amount of data that can
42 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
43 * packets (which practially means 1 packet and 63 bytes of data) when the
46 * This means if we are wanting to move >127 bytes of data, we need to
47 * split the transactions up, but just doing one packet at a time does
48 * not work (this may be an implicit DATA0 PID on first packet of the
49 * transaction) and doing 2 packets is outside the controller's limits.
51 * If we try to lower the MPS size for EP0, then no transfers work properly
52 * for EP0, and the system will fail basic enumeration. As no cause for this
53 * has currently been found, we cannot support any large IN transfers for
56 #define EP0_MPS_LIMIT 64
62 * struct s3c_hsotg_ep - driver endpoint definition.
63 * @ep: The gadget layer representation of the endpoint.
64 * @name: The driver generated name for the endpoint.
65 * @queue: Queue of requests for this endpoint.
66 * @parent: Reference back to the parent device structure.
67 * @req: The current request that the endpoint is processing. This is
68 * used to indicate an request has been loaded onto the endpoint
69 * and has yet to be completed (maybe due to data move, or simply
70 * awaiting an ack from the core all the data has been completed).
71 * @debugfs: File entry for debugfs file for this endpoint.
72 * @lock: State lock to protect contents of endpoint.
73 * @dir_in: Set to true if this endpoint is of the IN direction, which
74 * means that it is sending data to the Host.
75 * @index: The index for the endpoint registers.
76 * @name: The name array passed to the USB core.
77 * @halted: Set if the endpoint has been halted.
78 * @periodic: Set if this is a periodic ep, such as Interrupt
79 * @sent_zlp: Set if we've sent a zero-length packet.
80 * @total_data: The total number of data bytes done.
81 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
82 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
83 * @last_load: The offset of data for the last start of request.
84 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
86 * This is the driver's state for each registered enpoint, allowing it
87 * to keep track of transactions that need doing. Each endpoint has a
88 * lock to protect the state, to try and avoid using an overall lock
89 * for the host controller as much as possible.
91 * For periodic IN endpoints, we have fifo_size and fifo_load to try
92 * and keep track of the amount of data in the periodic FIFO for each
93 * of these as we don't have a status register that tells us how much
98 struct list_head queue;
99 struct s3c_hsotg *parent;
100 struct s3c_hsotg_req *req;
101 struct dentry *debugfs;
105 unsigned long total_data;
106 unsigned int size_loaded;
107 unsigned int last_load;
108 unsigned int fifo_load;
109 unsigned short fifo_size;
111 unsigned char dir_in;
114 unsigned int halted:1;
115 unsigned int periodic:1;
116 unsigned int sent_zlp:1;
121 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
124 * struct s3c_hsotg - driver state.
125 * @dev: The parent device supplied to the probe function
126 * @driver: USB gadget driver
127 * @plat: The platform specific configuration data.
128 * @regs: The memory area mapped for accessing registers.
129 * @regs_res: The resource that was allocated when claiming register space.
130 * @irq: The IRQ number we are using
131 * @debug_root: root directrory for debugfs.
132 * @debug_file: main status file for debugfs.
133 * @debug_fifo: FIFO status file for debugfs.
134 * @ep0_reply: Request used for ep0 reply.
135 * @ep0_buff: Buffer for EP0 reply data, if needed.
136 * @ctrl_buff: Buffer for EP0 control requests.
137 * @ctrl_req: Request for EP0 control packets.
138 * @eps: The endpoints being supplied to the gadget framework
142 struct usb_gadget_driver *driver;
143 struct s3c_hsotg_plat *plat;
146 struct resource *regs_res;
149 struct dentry *debug_root;
150 struct dentry *debug_file;
151 struct dentry *debug_fifo;
153 struct usb_request *ep0_reply;
154 struct usb_request *ctrl_req;
158 struct usb_gadget gadget;
159 struct s3c_hsotg_ep eps[];
163 * struct s3c_hsotg_req - data transfer request
164 * @req: The USB gadget request
165 * @queue: The list of requests for the endpoint this is queued for.
166 * @in_progress: Has already had size/packets written to core
167 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
169 struct s3c_hsotg_req {
170 struct usb_request req;
171 struct list_head queue;
172 unsigned char in_progress;
173 unsigned char mapped;
176 /* conversion functions */
177 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
179 return container_of(req, struct s3c_hsotg_req, req);
182 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
184 return container_of(ep, struct s3c_hsotg_ep, ep);
187 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
189 return container_of(gadget, struct s3c_hsotg, gadget);
192 static inline void __orr32(void __iomem *ptr, u32 val)
194 writel(readl(ptr) | val, ptr);
197 static inline void __bic32(void __iomem *ptr, u32 val)
199 writel(readl(ptr) & ~val, ptr);
202 /* forward decleration of functions */
203 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
206 * using_dma - return the DMA status of the driver.
207 * @hsotg: The driver state.
209 * Return true if we're using DMA.
211 * Currently, we have the DMA support code worked into everywhere
212 * that needs it, but the AMBA DMA implementation in the hardware can
213 * only DMA from 32bit aligned addresses. This means that gadgets such
214 * as the CDC Ethernet cannot work as they often pass packets which are
217 * Unfortunately the choice to use DMA or not is global to the controller
218 * and seems to be only settable when the controller is being put through
219 * a core reset. This means we either need to fix the gadgets to take
220 * account of DMA alignment, or add bounce buffers (yuerk).
222 * Until this issue is sorted out, we always return 'false'.
224 static inline bool using_dma(struct s3c_hsotg *hsotg)
226 return false; /* support is not complete */
230 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
231 * @hsotg: The device state
232 * @ints: A bitmask of the interrupts to enable
234 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
236 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
239 new_gsintmsk = gsintmsk | ints;
241 if (new_gsintmsk != gsintmsk) {
242 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
243 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
248 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
249 * @hsotg: The device state
250 * @ints: A bitmask of the interrupts to enable
252 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
254 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
257 new_gsintmsk = gsintmsk & ~ints;
259 if (new_gsintmsk != gsintmsk)
260 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
264 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
265 * @hsotg: The device state
266 * @ep: The endpoint index
267 * @dir_in: True if direction is in.
268 * @en: The enable value, true to enable
270 * Set or clear the mask for an individual endpoint's interrupt
273 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
274 unsigned int ep, unsigned int dir_in,
284 local_irq_save(flags);
285 daint = readl(hsotg->regs + S3C_DAINTMSK);
290 writel(daint, hsotg->regs + S3C_DAINTMSK);
291 local_irq_restore(flags);
295 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
296 * @hsotg: The device instance.
298 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
306 /* the ryu 2.6.24 release ahs
307 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
308 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
309 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
310 hsotg->regs + S3C_GNPTXFSIZ);
313 /* set FIFO sizes to 2048/0x1C0 */
315 writel(2048, hsotg->regs + S3C_GRXFSIZ);
316 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
317 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
318 hsotg->regs + S3C_GNPTXFSIZ);
320 /* arange all the rest of the TX FIFOs, as some versions of this
321 * block have overlapping default addresses. This also ensures
322 * that if the settings have been changed, then they are set to
325 /* start at the end of the GNPTXFSIZ, rounded up */
329 /* currently we allocate TX FIFOs for all possible endpoints,
330 * and assume that they are all the same size. */
332 for (ep = 0; ep <= 15; ep++) {
334 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
337 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
340 /* according to p428 of the design guide, we need to ensure that
341 * all fifos are flushed before continuing */
343 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
344 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
346 /* wait until the fifos are both flushed */
349 val = readl(hsotg->regs + S3C_GRSTCTL);
351 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
354 if (--timeout == 0) {
356 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
363 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
367 * @ep: USB endpoint to allocate request for.
368 * @flags: Allocation flags
370 * Allocate a new USB request structure appropriate for the specified endpoint
372 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
375 struct s3c_hsotg_req *req;
377 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
381 INIT_LIST_HEAD(&req->queue);
383 req->req.dma = DMA_ADDR_INVALID;
388 * is_ep_periodic - return true if the endpoint is in periodic mode.
389 * @hs_ep: The endpoint to query.
391 * Returns true if the endpoint is in periodic mode, meaning it is being
392 * used for an Interrupt or ISO transfer.
394 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
396 return hs_ep->periodic;
400 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
401 * @hsotg: The device state.
402 * @hs_ep: The endpoint for the request
403 * @hs_req: The request being processed.
405 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
406 * of a request to ensure the buffer is ready for access by the caller.
408 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
409 struct s3c_hsotg_ep *hs_ep,
410 struct s3c_hsotg_req *hs_req)
412 struct usb_request *req = &hs_req->req;
413 enum dma_data_direction dir;
415 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
417 /* ignore this if we're not moving any data */
418 if (hs_req->req.length == 0)
421 if (hs_req->mapped) {
422 /* we mapped this, so unmap and remove the dma */
424 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
426 req->dma = DMA_ADDR_INVALID;
429 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
434 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
435 * @hsotg: The controller state.
436 * @hs_ep: The endpoint we're going to write for.
437 * @hs_req: The request to write data for.
439 * This is called when the TxFIFO has some space in it to hold a new
440 * transmission and we have something to give it. The actual setup of
441 * the data size is done elsewhere, so all we have to do is to actually
444 * The return value is zero if there is more space (or nothing was done)
445 * otherwise -ENOSPC is returned if the FIFO space was used up.
447 * This routine is only needed for PIO
449 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
450 struct s3c_hsotg_ep *hs_ep,
451 struct s3c_hsotg_req *hs_req)
453 bool periodic = is_ep_periodic(hs_ep);
454 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
455 int buf_pos = hs_req->req.actual;
456 int to_write = hs_ep->size_loaded;
461 to_write -= (buf_pos - hs_ep->last_load);
463 /* if there's nothing to write, get out early */
468 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
472 /* work out how much data was loaded so we can calculate
473 * how much data is left in the fifo. */
475 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
477 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
479 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
481 /* how much of the data has moved */
482 size_done = hs_ep->size_loaded - size_left;
484 /* how much data is left in the fifo */
485 can_write = hs_ep->fifo_load - size_done;
486 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
487 __func__, can_write);
489 can_write = hs_ep->fifo_size - can_write;
490 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
491 __func__, can_write);
493 if (can_write <= 0) {
494 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
498 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
500 "%s: no queue slots available (0x%08x)\n",
503 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
507 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
510 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
511 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
513 /* limit to 512 bytes of data, it seems at least on the non-periodic
514 * FIFO, requests of >512 cause the endpoint to get stuck with a
515 * fragment of the end of the transfer in it.
520 /* see if we can write data */
522 if (to_write > can_write) {
523 to_write = can_write;
524 pkt_round = to_write % hs_ep->ep.maxpacket;
526 /* Not sure, but we probably shouldn't be writing partial
527 * packets into the FIFO, so round the write down to an
528 * exact number of packets.
530 * Note, we do not currently check to see if we can ever
531 * write a full packet or not to the FIFO.
535 to_write -= pkt_round;
537 /* enable correct FIFO interrupt to alert us when there
538 * is more room left. */
540 s3c_hsotg_en_gsint(hsotg,
541 periodic ? S3C_GINTSTS_PTxFEmp :
542 S3C_GINTSTS_NPTxFEmp);
545 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
546 to_write, hs_req->req.length, can_write, buf_pos);
551 hs_req->req.actual = buf_pos + to_write;
552 hs_ep->total_data += to_write;
555 hs_ep->fifo_load += to_write;
557 to_write = DIV_ROUND_UP(to_write, 4);
558 data = hs_req->req.buf + buf_pos;
560 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
562 return (to_write >= can_write) ? -ENOSPC : 0;
566 * get_ep_limit - get the maximum data legnth for this endpoint
567 * @hs_ep: The endpoint
569 * Return the maximum data that can be queued in one go on a given endpoint
570 * so that transfers that are too long can be split.
572 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
574 int index = hs_ep->index;
579 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
580 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
583 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
585 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
592 /* we made the constant loading easier above by using +1 */
596 /* constrain by packet count if maxpkts*pktsize is greater
597 * than the length register size. */
599 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
600 maxsize = maxpkt * hs_ep->ep.maxpacket;
606 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
607 * @hsotg: The controller state.
608 * @hs_ep: The endpoint to process a request for
609 * @hs_req: The request to start.
610 * @continuing: True if we are doing more for the current request.
612 * Start the given request running by setting the endpoint registers
613 * appropriately, and writing any data to the FIFOs.
615 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
616 struct s3c_hsotg_ep *hs_ep,
617 struct s3c_hsotg_req *hs_req,
620 struct usb_request *ureq = &hs_req->req;
621 int index = hs_ep->index;
622 int dir_in = hs_ep->dir_in;
632 if (hs_ep->req && !continuing) {
633 dev_err(hsotg->dev, "%s: active request\n", __func__);
636 } else if (hs_ep->req != hs_req && continuing) {
638 "%s: continue different req\n", __func__);
644 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
645 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
647 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
648 __func__, readl(hsotg->regs + epctrl_reg), index,
649 hs_ep->dir_in ? "in" : "out");
651 length = ureq->length - ureq->actual;
655 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
656 ureq->buf, length, ureq->dma,
657 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
659 maxreq = get_ep_limit(hs_ep);
660 if (length > maxreq) {
661 int round = maxreq % hs_ep->ep.maxpacket;
663 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
664 __func__, length, maxreq, round);
666 /* round down to multiple of packets */
674 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
676 packets = 1; /* send one packet if length is zero. */
678 if (dir_in && index != 0)
679 epsize = S3C_DxEPTSIZ_MC(1);
683 if (index != 0 && ureq->zero) {
684 /* test for the packets being exactly right for the
687 if (length == (packets * hs_ep->ep.maxpacket))
691 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
692 epsize |= S3C_DxEPTSIZ_XferSize(length);
694 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
695 __func__, packets, length, ureq->length, epsize, epsize_reg);
697 /* store the request as the current one we're doing */
700 /* write size / packets */
701 writel(epsize, hsotg->regs + epsize_reg);
703 ctrl = readl(hsotg->regs + epctrl_reg);
705 if (ctrl & S3C_DxEPCTL_Stall) {
706 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
708 /* not sure what we can do here, if it is EP0 then we should
709 * get this cleared once the endpoint has transmitted the
710 * STALL packet, otherwise it needs to be cleared by the
715 if (using_dma(hsotg)) {
716 unsigned int dma_reg;
718 /* write DMA address to control register, buffer already
719 * synced by s3c_hsotg_ep_queue(). */
721 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
722 writel(ureq->dma, hsotg->regs + dma_reg);
724 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
725 __func__, ureq->dma, dma_reg);
728 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
729 ctrl |= S3C_DxEPCTL_USBActEp;
730 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
732 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
733 writel(ctrl, hsotg->regs + epctrl_reg);
735 /* set these, it seems that DMA support increments past the end
736 * of the packet buffer so we need to calculate the length from
737 * this information. */
738 hs_ep->size_loaded = length;
739 hs_ep->last_load = ureq->actual;
741 if (dir_in && !using_dma(hsotg)) {
742 /* set these anyway, we may need them for non-periodic in */
743 hs_ep->fifo_load = 0;
745 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
748 /* clear the INTknTXFEmpMsk when we start request, more as a aide
749 * to debugging to see what is going on. */
751 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
752 hsotg->regs + S3C_DIEPINT(index));
754 /* Note, trying to clear the NAK here causes problems with transmit
755 * on the S3C6400 ending up with the TXFIFO becomming full. */
757 /* check ep is enabled */
758 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
760 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
761 index, readl(hsotg->regs + epctrl_reg));
763 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
764 __func__, readl(hsotg->regs + epctrl_reg));
768 * s3c_hsotg_map_dma - map the DMA memory being used for the request
769 * @hsotg: The device state.
770 * @hs_ep: The endpoint the request is on.
771 * @req: The request being processed.
773 * We've been asked to queue a request, so ensure that the memory buffer
774 * is correctly setup for DMA. If we've been passed an extant DMA address
775 * then ensure the buffer has been synced to memory. If our buffer has no
776 * DMA memory, then we map the memory and mark our request to allow us to
777 * cleanup on completion.
779 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
780 struct s3c_hsotg_ep *hs_ep,
781 struct usb_request *req)
783 enum dma_data_direction dir;
784 struct s3c_hsotg_req *hs_req = our_req(req);
786 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
788 /* if the length is zero, ignore the DMA data */
789 if (hs_req->req.length == 0)
792 if (req->dma == DMA_ADDR_INVALID) {
795 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
797 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
801 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
804 dma_unmap_single(hsotg->dev, dma, req->length, dir);
811 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
818 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
819 __func__, req->buf, req->length);
824 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
827 struct s3c_hsotg_req *hs_req = our_req(req);
828 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
829 struct s3c_hsotg *hs = hs_ep->parent;
830 unsigned long irqflags;
833 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
834 ep->name, req, req->length, req->buf, req->no_interrupt,
835 req->zero, req->short_not_ok);
837 /* initialise status of the request */
838 INIT_LIST_HEAD(&hs_req->queue);
840 req->status = -EINPROGRESS;
842 /* if we're using DMA, sync the buffers as necessary */
844 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
849 spin_lock_irqsave(&hs_ep->lock, irqflags);
851 first = list_empty(&hs_ep->queue);
852 list_add_tail(&hs_req->queue, &hs_ep->queue);
855 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
857 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
862 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
863 struct usb_request *req)
865 struct s3c_hsotg_req *hs_req = our_req(req);
871 * s3c_hsotg_complete_oursetup - setup completion callback
872 * @ep: The endpoint the request was on.
873 * @req: The request completed.
875 * Called on completion of any requests the driver itself
876 * submitted that need cleaning up.
878 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
879 struct usb_request *req)
881 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
882 struct s3c_hsotg *hsotg = hs_ep->parent;
884 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
886 s3c_hsotg_ep_free_request(ep, req);
890 * ep_from_windex - convert control wIndex value to endpoint
891 * @hsotg: The driver state.
892 * @windex: The control request wIndex field (in host order).
894 * Convert the given wIndex into a pointer to an driver endpoint
895 * structure, or return NULL if it is not a valid endpoint.
897 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
900 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
901 int dir = (windex & USB_DIR_IN) ? 1 : 0;
902 int idx = windex & 0x7F;
907 if (idx > S3C_HSOTG_EPS)
910 if (idx && ep->dir_in != dir)
917 * s3c_hsotg_send_reply - send reply to control request
918 * @hsotg: The device state
920 * @buff: Buffer for request
921 * @length: Length of reply.
923 * Create a request and queue it on the given endpoint. This is useful as
924 * an internal method of sending replies to certain control requests, etc.
926 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
927 struct s3c_hsotg_ep *ep,
931 struct usb_request *req;
934 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
936 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
937 hsotg->ep0_reply = req;
939 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
943 req->buf = hsotg->ep0_buff;
944 req->length = length;
945 req->zero = 1; /* always do zero-length final transfer */
946 req->complete = s3c_hsotg_complete_oursetup;
949 memcpy(req->buf, buff, length);
953 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
955 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
963 * s3c_hsotg_process_req_status - process request GET_STATUS
964 * @hsotg: The device state
965 * @ctrl: USB control request
967 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
968 struct usb_ctrlrequest *ctrl)
970 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
971 struct s3c_hsotg_ep *ep;
975 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
978 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
982 switch (ctrl->bRequestType & USB_RECIP_MASK) {
983 case USB_RECIP_DEVICE:
984 reply = cpu_to_le16(0); /* bit 0 => self powered,
985 * bit 1 => remote wakeup */
988 case USB_RECIP_INTERFACE:
989 /* currently, the data result should be zero */
990 reply = cpu_to_le16(0);
993 case USB_RECIP_ENDPOINT:
994 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
998 reply = cpu_to_le16(ep->halted ? 1 : 0);
1005 if (le16_to_cpu(ctrl->wLength) != 2)
1008 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1010 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1017 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1020 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1021 * @hsotg: The device state
1022 * @ctrl: USB control request
1024 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1025 struct usb_ctrlrequest *ctrl)
1027 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1028 struct s3c_hsotg_ep *ep;
1030 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1031 __func__, set ? "SET" : "CLEAR");
1033 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1034 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1036 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1037 __func__, le16_to_cpu(ctrl->wIndex));
1041 switch (le16_to_cpu(ctrl->wValue)) {
1042 case USB_ENDPOINT_HALT:
1043 s3c_hsotg_ep_sethalt(&ep->ep, set);
1050 return -ENOENT; /* currently only deal with endpoint */
1056 * s3c_hsotg_process_control - process a control request
1057 * @hsotg: The device state
1058 * @ctrl: The control request received
1060 * The controller has received the SETUP phase of a control request, and
1061 * needs to work out what to do next (and whether to pass it on to the
1064 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1065 struct usb_ctrlrequest *ctrl)
1067 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1073 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1074 ctrl->bRequest, ctrl->bRequestType,
1075 ctrl->wValue, ctrl->wLength);
1077 /* record the direction of the request, for later use when enquing
1078 * packets onto EP0. */
1080 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1081 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1083 /* if we've no data with this request, then the last part of the
1084 * transaction is going to implicitly be IN. */
1085 if (ctrl->wLength == 0)
1088 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1089 switch (ctrl->bRequest) {
1090 case USB_REQ_SET_ADDRESS:
1091 dcfg = readl(hsotg->regs + S3C_DCFG);
1092 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1093 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1094 writel(dcfg, hsotg->regs + S3C_DCFG);
1096 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1098 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1101 case USB_REQ_GET_STATUS:
1102 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1105 case USB_REQ_CLEAR_FEATURE:
1106 case USB_REQ_SET_FEATURE:
1107 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1112 /* as a fallback, try delivering it to the driver to deal with */
1114 if (ret == 0 && hsotg->driver) {
1115 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1117 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1122 /* need to generate zlp in reply or take data */
1123 /* todo - deal with any data we might be sent? */
1124 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1128 /* the request is either unhandlable, or is not formatted correctly
1129 * so respond with a STALL for the status stage to indicate failure.
1136 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1137 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1139 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1140 * taken effect, so no need to clear later. */
1142 ctrl = readl(hsotg->regs + reg);
1143 ctrl |= S3C_DxEPCTL_Stall;
1144 ctrl |= S3C_DxEPCTL_CNAK;
1145 writel(ctrl, hsotg->regs + reg);
1148 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1149 ctrl, reg, readl(hsotg->regs + reg));
1151 /* don't belive we need to anything more to get the EP
1152 * to reply with a STALL packet */
1156 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1159 * s3c_hsotg_complete_setup - completion of a setup transfer
1160 * @ep: The endpoint the request was on.
1161 * @req: The request completed.
1163 * Called on completion of any requests the driver itself submitted for
1166 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1167 struct usb_request *req)
1169 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1170 struct s3c_hsotg *hsotg = hs_ep->parent;
1172 if (req->status < 0) {
1173 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1177 if (req->actual == 0)
1178 s3c_hsotg_enqueue_setup(hsotg);
1180 s3c_hsotg_process_control(hsotg, req->buf);
1184 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1185 * @hsotg: The device state.
1187 * Enqueue a request on EP0 if necessary to received any SETUP packets
1188 * received from the host.
1190 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1192 struct usb_request *req = hsotg->ctrl_req;
1193 struct s3c_hsotg_req *hs_req = our_req(req);
1196 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1200 req->buf = hsotg->ctrl_buff;
1201 req->complete = s3c_hsotg_complete_setup;
1203 if (!list_empty(&hs_req->queue)) {
1204 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1208 hsotg->eps[0].dir_in = 0;
1210 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1212 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1213 /* Don't think there's much we can do other than watch the
1219 * get_ep_head - return the first request on the endpoint
1220 * @hs_ep: The controller endpoint to get
1222 * Get the first request on the endpoint.
1224 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1226 if (list_empty(&hs_ep->queue))
1229 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1233 * s3c_hsotg_complete_request - complete a request given to us
1234 * @hsotg: The device state.
1235 * @hs_ep: The endpoint the request was on.
1236 * @hs_req: The request to complete.
1237 * @result: The result code (0 => Ok, otherwise errno)
1239 * The given request has finished, so call the necessary completion
1240 * if it has one and then look to see if we can start a new request
1243 * Note, expects the ep to already be locked as appropriate.
1245 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1246 struct s3c_hsotg_ep *hs_ep,
1247 struct s3c_hsotg_req *hs_req,
1253 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1257 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1258 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1260 /* only replace the status if we've not already set an error
1261 * from a previous transaction */
1263 if (hs_req->req.status == -EINPROGRESS)
1264 hs_req->req.status = result;
1267 list_del_init(&hs_req->queue);
1269 if (using_dma(hsotg))
1270 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1272 /* call the complete request with the locks off, just in case the
1273 * request tries to queue more work for this endpoint. */
1275 if (hs_req->req.complete) {
1276 spin_unlock(&hs_ep->lock);
1277 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1278 spin_lock(&hs_ep->lock);
1281 /* Look to see if there is anything else to do. Note, the completion
1282 * of the previous request may have caused a new request to be started
1283 * so be careful when doing this. */
1285 if (!hs_ep->req && result >= 0) {
1286 restart = !list_empty(&hs_ep->queue);
1288 hs_req = get_ep_head(hs_ep);
1289 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1295 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1296 * @hsotg: The device state.
1297 * @hs_ep: The endpoint the request was on.
1298 * @hs_req: The request to complete.
1299 * @result: The result code (0 => Ok, otherwise errno)
1301 * See s3c_hsotg_complete_request(), but called with the endpoint's
1304 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1305 struct s3c_hsotg_ep *hs_ep,
1306 struct s3c_hsotg_req *hs_req,
1309 unsigned long flags;
1311 spin_lock_irqsave(&hs_ep->lock, flags);
1312 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1313 spin_unlock_irqrestore(&hs_ep->lock, flags);
1317 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1318 * @hsotg: The device state.
1319 * @ep_idx: The endpoint index for the data
1320 * @size: The size of data in the fifo, in bytes
1322 * The FIFO status shows there is data to read from the FIFO for a given
1323 * endpoint, so sort out whether we need to read the data into a request
1324 * that has been made for that endpoint.
1326 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1328 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1329 struct s3c_hsotg_req *hs_req = hs_ep->req;
1330 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1336 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1339 dev_warn(hsotg->dev,
1340 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1341 __func__, size, ep_idx, epctl);
1343 /* dump the data from the FIFO, we've nothing we can do */
1344 for (ptr = 0; ptr < size; ptr += 4)
1350 spin_lock(&hs_ep->lock);
1353 read_ptr = hs_req->req.actual;
1354 max_req = hs_req->req.length - read_ptr;
1356 if (to_read > max_req) {
1357 /* more data appeared than we where willing
1358 * to deal with in this request.
1361 /* currently we don't deal this */
1365 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1366 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1368 hs_ep->total_data += to_read;
1369 hs_req->req.actual += to_read;
1370 to_read = DIV_ROUND_UP(to_read, 4);
1372 /* note, we might over-write the buffer end by 3 bytes depending on
1373 * alignment of the data. */
1374 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1376 spin_unlock(&hs_ep->lock);
1380 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1381 * @hsotg: The device instance
1382 * @req: The request currently on this endpoint
1384 * Generate a zero-length IN packet request for terminating a SETUP
1387 * Note, since we don't write any data to the TxFIFO, then it is
1388 * currently belived that we do not need to wait for any space in
1391 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1392 struct s3c_hsotg_req *req)
1397 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1401 if (req->req.length == 0) {
1402 hsotg->eps[0].sent_zlp = 1;
1403 s3c_hsotg_enqueue_setup(hsotg);
1407 hsotg->eps[0].dir_in = 1;
1408 hsotg->eps[0].sent_zlp = 1;
1410 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1412 /* issue a zero-sized packet to terminate this */
1413 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1414 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1416 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1417 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1418 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1419 ctrl |= S3C_DxEPCTL_USBActEp;
1420 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1424 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1425 * @hsotg: The device instance
1426 * @epnum: The endpoint received from
1427 * @was_setup: Set if processing a SetupDone event.
1429 * The RXFIFO has delivered an OutDone event, which means that the data
1430 * transfer for an OUT endpoint has been completed, either by a short
1431 * packet or by the finish of a transfer.
1433 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1434 int epnum, bool was_setup)
1436 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1437 struct s3c_hsotg_req *hs_req = hs_ep->req;
1438 struct usb_request *req = &hs_req->req;
1442 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1446 if (using_dma(hsotg)) {
1447 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1451 /* Calculate the size of the transfer by checking how much
1452 * is left in the endpoint size register and then working it
1453 * out from the amount we loaded for the transfer.
1455 * We need to do this as DMA pointers are always 32bit aligned
1456 * so may overshoot/undershoot the transfer.
1459 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1461 size_done = hs_ep->size_loaded - size_left;
1462 size_done += hs_ep->last_load;
1464 req->actual = size_done;
1467 if (req->actual < req->length && req->short_not_ok) {
1468 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1469 __func__, req->actual, req->length);
1471 /* todo - what should we return here? there's no one else
1472 * even bothering to check the status. */
1476 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1477 s3c_hsotg_send_zlp(hsotg, hs_req);
1480 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1484 * s3c_hsotg_read_frameno - read current frame number
1485 * @hsotg: The device instance
1487 * Return the current frame number
1489 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1493 dsts = readl(hsotg->regs + S3C_DSTS);
1494 dsts &= S3C_DSTS_SOFFN_MASK;
1495 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1501 * s3c_hsotg_handle_rx - RX FIFO has data
1502 * @hsotg: The device instance
1504 * The IRQ handler has detected that the RX FIFO has some data in it
1505 * that requires processing, so find out what is in there and do the
1508 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1509 * chunks, so if you have x packets received on an endpoint you'll get x
1510 * FIFO events delivered, each with a packet's worth of data in it.
1512 * When using DMA, we should not be processing events from the RXFIFO
1513 * as the actual data should be sent to the memory directly and we turn
1514 * on the completion interrupts to get notifications of transfer completion.
1516 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1518 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1519 u32 epnum, status, size;
1521 WARN_ON(using_dma(hsotg));
1523 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1524 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1526 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1527 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1530 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1531 __func__, grxstsr, size, epnum);
1533 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1535 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1536 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1537 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1540 case __status(S3C_GRXSTS_PktSts_OutDone):
1541 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1542 s3c_hsotg_read_frameno(hsotg));
1544 if (!using_dma(hsotg))
1545 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1548 case __status(S3C_GRXSTS_PktSts_SetupDone):
1550 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1551 s3c_hsotg_read_frameno(hsotg),
1552 readl(hsotg->regs + S3C_DOEPCTL(0)));
1554 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1557 case __status(S3C_GRXSTS_PktSts_OutRX):
1558 s3c_hsotg_rx_data(hsotg, epnum, size);
1561 case __status(S3C_GRXSTS_PktSts_SetupRX):
1563 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1564 s3c_hsotg_read_frameno(hsotg),
1565 readl(hsotg->regs + S3C_DOEPCTL(0)));
1567 s3c_hsotg_rx_data(hsotg, epnum, size);
1571 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1574 s3c_hsotg_dump(hsotg);
1580 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1581 * @mps: The maximum packet size in bytes.
1583 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1587 return S3C_D0EPCTL_MPS_64;
1589 return S3C_D0EPCTL_MPS_32;
1591 return S3C_D0EPCTL_MPS_16;
1593 return S3C_D0EPCTL_MPS_8;
1596 /* bad max packet size, warn and return invalid result */
1602 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1603 * @hsotg: The driver state.
1604 * @ep: The index number of the endpoint
1605 * @mps: The maximum packet size in bytes
1607 * Configure the maximum packet size for the given endpoint, updating
1608 * the hardware control registers to reflect this.
1610 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1611 unsigned int ep, unsigned int mps)
1613 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1614 void __iomem *regs = hsotg->regs;
1619 /* EP0 is a special case */
1620 mpsval = s3c_hsotg_ep0_mps(mps);
1624 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1630 hs_ep->ep.maxpacket = mps;
1632 /* update both the in and out endpoint controldir_ registers, even
1633 * if one of the directions may not be in use. */
1635 reg = readl(regs + S3C_DIEPCTL(ep));
1636 reg &= ~S3C_DxEPCTL_MPS_MASK;
1638 writel(reg, regs + S3C_DIEPCTL(ep));
1640 reg = readl(regs + S3C_DOEPCTL(ep));
1641 reg &= ~S3C_DxEPCTL_MPS_MASK;
1643 writel(reg, regs + S3C_DOEPCTL(ep));
1648 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1653 * s3c_hsotg_trytx - check to see if anything needs transmitting
1654 * @hsotg: The driver state
1655 * @hs_ep: The driver endpoint to check.
1657 * Check to see if there is a request that has data to send, and if so
1658 * make an attempt to write data into the FIFO.
1660 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1661 struct s3c_hsotg_ep *hs_ep)
1663 struct s3c_hsotg_req *hs_req = hs_ep->req;
1665 if (!hs_ep->dir_in || !hs_req)
1668 if (hs_req->req.actual < hs_req->req.length) {
1669 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1671 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1678 * s3c_hsotg_complete_in - complete IN transfer
1679 * @hsotg: The device state.
1680 * @hs_ep: The endpoint that has just completed.
1682 * An IN transfer has been completed, update the transfer's state and then
1683 * call the relevant completion routines.
1685 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1686 struct s3c_hsotg_ep *hs_ep)
1688 struct s3c_hsotg_req *hs_req = hs_ep->req;
1689 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1690 int size_left, size_done;
1693 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1697 /* Calculate the size of the transfer by checking how much is left
1698 * in the endpoint size register and then working it out from
1699 * the amount we loaded for the transfer.
1701 * We do this even for DMA, as the transfer may have incremented
1702 * past the end of the buffer (DMA transfers are always 32bit
1706 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1708 size_done = hs_ep->size_loaded - size_left;
1709 size_done += hs_ep->last_load;
1711 if (hs_req->req.actual != size_done)
1712 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1713 __func__, hs_req->req.actual, size_done);
1715 hs_req->req.actual = size_done;
1717 /* if we did all of the transfer, and there is more data left
1718 * around, then try restarting the rest of the request */
1720 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1721 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1722 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1724 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1728 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1729 * @hsotg: The driver state
1730 * @idx: The index for the endpoint (0..15)
1731 * @dir_in: Set if this is an IN endpoint
1733 * Process and clear any interrupt pending for an individual endpoint
1735 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1738 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1739 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1740 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1741 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1745 ints = readl(hsotg->regs + epint_reg);
1747 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1748 __func__, idx, dir_in ? "in" : "out", ints);
1750 if (ints & S3C_DxEPINT_XferCompl) {
1752 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1753 __func__, readl(hsotg->regs + epctl_reg),
1754 readl(hsotg->regs + epsiz_reg));
1756 /* we get OutDone from the FIFO, so we only need to look
1757 * at completing IN requests here */
1759 s3c_hsotg_complete_in(hsotg, hs_ep);
1762 s3c_hsotg_enqueue_setup(hsotg);
1763 } else if (using_dma(hsotg)) {
1764 /* We're using DMA, we need to fire an OutDone here
1765 * as we ignore the RXFIFO. */
1767 s3c_hsotg_handle_outdone(hsotg, idx, false);
1770 clear |= S3C_DxEPINT_XferCompl;
1773 if (ints & S3C_DxEPINT_EPDisbld) {
1774 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1775 clear |= S3C_DxEPINT_EPDisbld;
1778 if (ints & S3C_DxEPINT_AHBErr) {
1779 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1780 clear |= S3C_DxEPINT_AHBErr;
1783 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1784 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1786 if (using_dma(hsotg) && idx == 0) {
1787 /* this is the notification we've received a
1788 * setup packet. In non-DMA mode we'd get this
1789 * from the RXFIFO, instead we need to process
1790 * the setup here. */
1795 s3c_hsotg_handle_outdone(hsotg, 0, true);
1798 clear |= S3C_DxEPINT_Setup;
1801 if (ints & S3C_DxEPINT_Back2BackSetup) {
1802 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1803 clear |= S3C_DxEPINT_Back2BackSetup;
1807 /* not sure if this is important, but we'll clear it anyway
1809 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1810 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1812 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1815 /* this probably means something bad is happening */
1816 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1817 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1819 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1823 writel(clear, hsotg->regs + epint_reg);
1827 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1828 * @hsotg: The device state.
1830 * Handle updating the device settings after the enumeration phase has
1833 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1835 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1836 int ep0_mps = 0, ep_mps;
1838 /* This should signal the finish of the enumeration phase
1839 * of the USB handshaking, so we should now know what rate
1840 * we connected at. */
1842 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1844 /* note, since we're limited by the size of transfer on EP0, and
1845 * it seems IN transfers must be a even number of packets we do
1846 * not advertise a 64byte MPS on EP0. */
1848 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1849 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1850 case S3C_DSTS_EnumSpd_FS:
1851 case S3C_DSTS_EnumSpd_FS48:
1852 hsotg->gadget.speed = USB_SPEED_FULL;
1853 dev_info(hsotg->dev, "new device is full-speed\n");
1855 ep0_mps = EP0_MPS_LIMIT;
1859 case S3C_DSTS_EnumSpd_HS:
1860 dev_info(hsotg->dev, "new device is high-speed\n");
1861 hsotg->gadget.speed = USB_SPEED_HIGH;
1863 ep0_mps = EP0_MPS_LIMIT;
1867 case S3C_DSTS_EnumSpd_LS:
1868 hsotg->gadget.speed = USB_SPEED_LOW;
1869 dev_info(hsotg->dev, "new device is low-speed\n");
1871 /* note, we don't actually support LS in this driver at the
1872 * moment, and the documentation seems to imply that it isn't
1873 * supported by the PHYs on some of the devices.
1878 /* we should now know the maximum packet size for an
1879 * endpoint, so set the endpoints to a default value. */
1883 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1884 for (i = 1; i < S3C_HSOTG_EPS; i++)
1885 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1888 /* ensure after enumeration our EP0 is active */
1890 s3c_hsotg_enqueue_setup(hsotg);
1892 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1893 readl(hsotg->regs + S3C_DIEPCTL0),
1894 readl(hsotg->regs + S3C_DOEPCTL0));
1898 * kill_all_requests - remove all requests from the endpoint's queue
1899 * @hsotg: The device state.
1900 * @ep: The endpoint the requests may be on.
1901 * @result: The result code to use.
1902 * @force: Force removal of any current requests
1904 * Go through the requests on the given endpoint and mark them
1905 * completed with the given result code.
1907 static void kill_all_requests(struct s3c_hsotg *hsotg,
1908 struct s3c_hsotg_ep *ep,
1909 int result, bool force)
1911 struct s3c_hsotg_req *req, *treq;
1912 unsigned long flags;
1914 spin_lock_irqsave(&ep->lock, flags);
1916 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1917 /* currently, we can't do much about an already
1918 * running request on an in endpoint */
1920 if (ep->req == req && ep->dir_in && !force)
1923 s3c_hsotg_complete_request(hsotg, ep, req,
1927 spin_unlock_irqrestore(&ep->lock, flags);
1930 #define call_gadget(_hs, _entry) \
1931 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1932 (_hs)->driver && (_hs)->driver->_entry) \
1933 (_hs)->driver->_entry(&(_hs)->gadget);
1936 * s3c_hsotg_disconnect_irq - disconnect irq service
1937 * @hsotg: The device state.
1939 * A disconnect IRQ has been received, meaning that the host has
1940 * lost contact with the bus. Remove all current transactions
1941 * and signal the gadget driver that this has happened.
1943 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1947 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1948 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1950 call_gadget(hsotg, disconnect);
1954 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1955 * @hsotg: The device state:
1956 * @periodic: True if this is a periodic FIFO interrupt
1958 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1960 struct s3c_hsotg_ep *ep;
1963 /* look through for any more data to transmit */
1965 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1966 ep = &hsotg->eps[epno];
1971 if ((periodic && !ep->periodic) ||
1972 (!periodic && ep->periodic))
1975 ret = s3c_hsotg_trytx(hsotg, ep);
1981 static struct s3c_hsotg *our_hsotg;
1983 /* IRQ flags which will trigger a retry around the IRQ loop */
1984 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1985 S3C_GINTSTS_PTxFEmp | \
1989 * s3c_hsotg_irq - handle device interrupt
1990 * @irq: The IRQ number triggered
1991 * @pw: The pw value when registered the handler.
1993 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
1995 struct s3c_hsotg *hsotg = pw;
1996 int retry_count = 8;
2001 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2002 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2004 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2005 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2009 if (gintsts & S3C_GINTSTS_OTGInt) {
2010 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2012 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2014 writel(otgint, hsotg->regs + S3C_GOTGINT);
2015 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2018 if (gintsts & S3C_GINTSTS_DisconnInt) {
2019 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2020 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2022 s3c_hsotg_disconnect_irq(hsotg);
2025 if (gintsts & S3C_GINTSTS_SessReqInt) {
2026 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2027 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2030 if (gintsts & S3C_GINTSTS_EnumDone) {
2031 s3c_hsotg_irq_enumdone(hsotg);
2032 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2035 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2036 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2037 readl(hsotg->regs + S3C_DSTS),
2038 readl(hsotg->regs + S3C_GOTGCTL));
2040 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2043 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2044 u32 daint = readl(hsotg->regs + S3C_DAINT);
2045 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2046 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2049 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2051 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2053 s3c_hsotg_epint(hsotg, ep, 0);
2056 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2058 s3c_hsotg_epint(hsotg, ep, 1);
2061 writel(daint, hsotg->regs + S3C_DAINT);
2062 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2063 hsotg->regs + S3C_GINTSTS);
2066 if (gintsts & S3C_GINTSTS_USBRst) {
2067 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2068 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2069 readl(hsotg->regs + S3C_GNPTXSTS));
2071 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2073 /* it seems after a reset we can end up with a situation
2074 * where the TXFIFO still has data in it... try flushing
2075 * it to remove anything that may still be in it.
2079 writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
2080 hsotg->regs + S3C_GRSTCTL);
2082 dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
2083 readl(hsotg->regs + S3C_GNPTXSTS));
2086 s3c_hsotg_enqueue_setup(hsotg);
2088 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2091 /* check both FIFOs */
2093 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2094 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2096 /* Disable the interrupt to stop it happening again
2097 * unless one of these endpoint routines decides that
2098 * it needs re-enabling */
2100 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2101 s3c_hsotg_irq_fifoempty(hsotg, false);
2103 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2106 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2107 dev_dbg(hsotg->dev, "PTxFEmp\n");
2109 /* See note in S3C_GINTSTS_NPTxFEmp */
2111 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2112 s3c_hsotg_irq_fifoempty(hsotg, true);
2114 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2117 if (gintsts & S3C_GINTSTS_RxFLvl) {
2118 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2119 * we need to retry s3c_hsotg_handle_rx if this is still
2122 s3c_hsotg_handle_rx(hsotg);
2123 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2126 if (gintsts & S3C_GINTSTS_ModeMis) {
2127 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2128 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2131 if (gintsts & S3C_GINTSTS_USBSusp) {
2132 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2133 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2135 call_gadget(hsotg, suspend);
2138 if (gintsts & S3C_GINTSTS_WkUpInt) {
2139 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2140 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2142 call_gadget(hsotg, resume);
2145 if (gintsts & S3C_GINTSTS_ErlySusp) {
2146 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2147 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2150 /* these next two seem to crop-up occasionally causing the core
2151 * to shutdown the USB transfer, so try clearing them and logging
2154 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2155 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2157 s3c_hsotg_dump(hsotg);
2159 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2160 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2163 if (gintsts & S3C_GINTSTS_GINNakEff) {
2164 dev_info(hsotg->dev, "GINNakEff triggered\n");
2166 s3c_hsotg_dump(hsotg);
2168 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2169 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2172 /* if we've had fifo events, we should try and go around the
2173 * loop again to see if there's any point in returning yet. */
2175 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2182 * s3c_hsotg_ep_enable - enable the given endpoint
2183 * @ep: The USB endpint to configure
2184 * @desc: The USB endpoint descriptor to configure with.
2186 * This is called from the USB gadget code's usb_ep_enable().
2188 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2189 const struct usb_endpoint_descriptor *desc)
2191 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2192 struct s3c_hsotg *hsotg = hs_ep->parent;
2193 unsigned long flags;
2194 int index = hs_ep->index;
2202 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2203 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2204 desc->wMaxPacketSize, desc->bInterval);
2206 /* not to be called for EP0 */
2207 WARN_ON(index == 0);
2209 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2210 if (dir_in != hs_ep->dir_in) {
2211 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2215 mps = le16_to_cpu(desc->wMaxPacketSize);
2217 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2219 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2220 epctrl = readl(hsotg->regs + epctrl_reg);
2222 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2223 __func__, epctrl, epctrl_reg);
2225 spin_lock_irqsave(&hs_ep->lock, flags);
2227 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2228 epctrl |= S3C_DxEPCTL_MPS(mps);
2230 /* mark the endpoint as active, otherwise the core may ignore
2231 * transactions entirely for this endpoint */
2232 epctrl |= S3C_DxEPCTL_USBActEp;
2234 /* set the NAK status on the endpoint, otherwise we might try and
2235 * do something with data that we've yet got a request to process
2236 * since the RXFIFO will take data for an endpoint even if the
2237 * size register hasn't been set.
2240 epctrl |= S3C_DxEPCTL_SNAK;
2242 /* update the endpoint state */
2243 hs_ep->ep.maxpacket = mps;
2245 /* default, set to non-periodic */
2246 hs_ep->periodic = 0;
2248 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2249 case USB_ENDPOINT_XFER_ISOC:
2250 dev_err(hsotg->dev, "no current ISOC support\n");
2254 case USB_ENDPOINT_XFER_BULK:
2255 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2258 case USB_ENDPOINT_XFER_INT:
2260 /* Allocate our TxFNum by simply using the index
2261 * of the endpoint for the moment. We could do
2262 * something better if the host indicates how
2263 * many FIFOs we are expecting to use. */
2265 hs_ep->periodic = 1;
2266 epctrl |= S3C_DxEPCTL_TxFNum(index);
2269 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2272 case USB_ENDPOINT_XFER_CONTROL:
2273 epctrl |= S3C_DxEPCTL_EPType_Control;
2277 /* for non control endpoints, set PID to D0 */
2279 epctrl |= S3C_DxEPCTL_SetD0PID;
2281 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2284 writel(epctrl, hsotg->regs + epctrl_reg);
2285 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2286 __func__, readl(hsotg->regs + epctrl_reg));
2288 /* enable the endpoint interrupt */
2289 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2292 spin_unlock_irqrestore(&hs_ep->lock, flags);
2296 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2298 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2299 struct s3c_hsotg *hsotg = hs_ep->parent;
2300 int dir_in = hs_ep->dir_in;
2301 int index = hs_ep->index;
2302 unsigned long flags;
2306 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2308 if (ep == &hsotg->eps[0].ep) {
2309 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2313 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2315 /* terminate all requests with shutdown */
2316 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2318 spin_lock_irqsave(&hs_ep->lock, flags);
2320 ctrl = readl(hsotg->regs + epctrl_reg);
2321 ctrl &= ~S3C_DxEPCTL_EPEna;
2322 ctrl &= ~S3C_DxEPCTL_USBActEp;
2323 ctrl |= S3C_DxEPCTL_SNAK;
2325 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2326 writel(ctrl, hsotg->regs + epctrl_reg);
2328 /* disable endpoint interrupts */
2329 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2331 spin_unlock_irqrestore(&hs_ep->lock, flags);
2336 * on_list - check request is on the given endpoint
2337 * @ep: The endpoint to check.
2338 * @test: The request to test if it is on the endpoint.
2340 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2342 struct s3c_hsotg_req *req, *treq;
2344 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2352 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2354 struct s3c_hsotg_req *hs_req = our_req(req);
2355 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2356 struct s3c_hsotg *hs = hs_ep->parent;
2357 unsigned long flags;
2359 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2361 if (hs_req == hs_ep->req) {
2362 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2363 return -EINPROGRESS;
2366 spin_lock_irqsave(&hs_ep->lock, flags);
2368 if (!on_list(hs_ep, hs_req)) {
2369 spin_unlock_irqrestore(&hs_ep->lock, flags);
2373 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2374 spin_unlock_irqrestore(&hs_ep->lock, flags);
2379 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2381 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2382 struct s3c_hsotg *hs = hs_ep->parent;
2383 int index = hs_ep->index;
2384 unsigned long irqflags;
2388 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2390 spin_lock_irqsave(&hs_ep->lock, irqflags);
2392 /* write both IN and OUT control registers */
2394 epreg = S3C_DIEPCTL(index);
2395 epctl = readl(hs->regs + epreg);
2398 epctl |= S3C_DxEPCTL_Stall;
2400 epctl &= ~S3C_DxEPCTL_Stall;
2402 writel(epctl, hs->regs + epreg);
2404 epreg = S3C_DOEPCTL(index);
2405 epctl = readl(hs->regs + epreg);
2408 epctl |= S3C_DxEPCTL_Stall;
2410 epctl &= ~S3C_DxEPCTL_Stall;
2412 writel(epctl, hs->regs + epreg);
2414 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2419 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2420 .enable = s3c_hsotg_ep_enable,
2421 .disable = s3c_hsotg_ep_disable,
2422 .alloc_request = s3c_hsotg_ep_alloc_request,
2423 .free_request = s3c_hsotg_ep_free_request,
2424 .queue = s3c_hsotg_ep_queue,
2425 .dequeue = s3c_hsotg_ep_dequeue,
2426 .set_halt = s3c_hsotg_ep_sethalt,
2427 /* note, don't belive we have any call for the fifo routines */
2431 * s3c_hsotg_corereset - issue softreset to the core
2432 * @hsotg: The device state
2434 * Issue a soft reset to the core, and await the core finishing it.
2436 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2441 dev_dbg(hsotg->dev, "resetting core\n");
2443 /* issue soft reset */
2444 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2448 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2449 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2451 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2452 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2459 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2461 if (timeout-- < 0) {
2462 dev_info(hsotg->dev,
2463 "%s: reset failed, GRSTCTL=%08x\n",
2468 if (grstctl & S3C_GRSTCTL_CSftRst)
2471 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2474 break; /* reset done */
2477 dev_dbg(hsotg->dev, "reset successful\n");
2481 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2483 struct s3c_hsotg *hsotg = our_hsotg;
2487 printk(KERN_ERR "%s: called with no device\n", __func__);
2492 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2496 if (driver->speed != USB_SPEED_HIGH &&
2497 driver->speed != USB_SPEED_FULL) {
2498 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2501 if (!driver->bind || !driver->setup) {
2502 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2506 WARN_ON(hsotg->driver);
2508 driver->driver.bus = NULL;
2509 hsotg->driver = driver;
2510 hsotg->gadget.dev.driver = &driver->driver;
2511 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2512 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2514 ret = device_add(&hsotg->gadget.dev);
2516 dev_err(hsotg->dev, "failed to register gadget device\n");
2520 ret = driver->bind(&hsotg->gadget);
2522 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2524 hsotg->gadget.dev.driver = NULL;
2525 hsotg->driver = NULL;
2529 /* we must now enable ep0 ready for host detection and then
2530 * set configuration. */
2532 s3c_hsotg_corereset(hsotg);
2534 /* set the PLL on, remove the HNP/SRP and set the PHY */
2535 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2536 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2538 /* looks like soft-reset changes state of FIFOs */
2539 s3c_hsotg_init_fifo(hsotg);
2541 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2543 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2545 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2546 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2547 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2548 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2549 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2550 S3C_GINTSTS_ErlySusp,
2551 hsotg->regs + S3C_GINTMSK);
2553 if (using_dma(hsotg))
2554 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2555 S3C_GAHBCFG_HBstLen_Incr4,
2556 hsotg->regs + S3C_GAHBCFG);
2558 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2560 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2561 * up being flooded with interrupts if the host is polling the
2562 * endpoint to try and read data. */
2564 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2565 S3C_DIEPMSK_INTknEPMisMsk |
2566 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2567 hsotg->regs + S3C_DIEPMSK);
2569 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2570 * DMA mode we may need this. */
2571 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2572 S3C_DOEPMSK_EPDisbldMsk |
2573 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2574 S3C_DIEPMSK_TimeOUTMsk) : 0),
2575 hsotg->regs + S3C_DOEPMSK);
2577 writel(0, hsotg->regs + S3C_DAINTMSK);
2579 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2580 readl(hsotg->regs + S3C_DIEPCTL0),
2581 readl(hsotg->regs + S3C_DOEPCTL0));
2583 /* enable in and out endpoint interrupts */
2584 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2586 /* Enable the RXFIFO when in slave mode, as this is how we collect
2587 * the data. In DMA mode, we get events from the FIFO but also
2588 * things we cannot process, so do not use it. */
2589 if (!using_dma(hsotg))
2590 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2592 /* Enable interrupts for EP0 in and out */
2593 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2594 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2596 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2597 udelay(10); /* see openiboot */
2598 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2600 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2602 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2603 writing to the EPCTL register.. */
2605 /* set to read 1 8byte packet */
2606 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2607 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2609 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2610 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2611 S3C_DxEPCTL_USBActEp,
2612 hsotg->regs + S3C_DOEPCTL0);
2614 /* enable, but don't activate EP0in */
2615 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2616 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2618 s3c_hsotg_enqueue_setup(hsotg);
2620 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2621 readl(hsotg->regs + S3C_DIEPCTL0),
2622 readl(hsotg->regs + S3C_DOEPCTL0));
2624 /* clear global NAKs */
2625 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2626 hsotg->regs + S3C_DCTL);
2628 /* must be at-least 3ms to allow bus to see disconnect */
2631 /* remove the soft-disconnect and let's go */
2632 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2634 /* report to the user, and return */
2636 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2640 hsotg->driver = NULL;
2641 hsotg->gadget.dev.driver = NULL;
2644 EXPORT_SYMBOL(usb_gadget_register_driver);
2646 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2648 struct s3c_hsotg *hsotg = our_hsotg;
2654 if (!driver || driver != hsotg->driver || !driver->unbind)
2657 /* all endpoints should be shutdown */
2658 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2659 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2661 call_gadget(hsotg, disconnect);
2663 driver->unbind(&hsotg->gadget);
2664 hsotg->driver = NULL;
2665 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2667 device_del(&hsotg->gadget.dev);
2669 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2670 driver->driver.name);
2674 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2676 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2678 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2681 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2682 .get_frame = s3c_hsotg_gadget_getframe,
2686 * s3c_hsotg_initep - initialise a single endpoint
2687 * @hsotg: The device state.
2688 * @hs_ep: The endpoint to be initialised.
2689 * @epnum: The endpoint number
2691 * Initialise the given endpoint (as part of the probe and device state
2692 * creation) to give to the gadget driver. Setup the endpoint name, any
2693 * direction information and other state that may be required.
2695 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2696 struct s3c_hsotg_ep *hs_ep,
2704 else if ((epnum % 2) == 0) {
2711 hs_ep->index = epnum;
2713 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2715 INIT_LIST_HEAD(&hs_ep->queue);
2716 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2718 spin_lock_init(&hs_ep->lock);
2720 /* add to the list of endpoints known by the gadget driver */
2722 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2724 hs_ep->parent = hsotg;
2725 hs_ep->ep.name = hs_ep->name;
2726 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2727 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2729 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2730 * an OUT endpoint, we may as well do this if in future the
2731 * code is changed to make each endpoint's direction changeable.
2734 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2735 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
2737 /* if we're using dma, we need to set the next-endpoint pointer
2738 * to be something valid.
2741 if (using_dma(hsotg)) {
2742 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2743 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2744 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2749 * s3c_hsotg_otgreset - reset the OtG phy block
2750 * @hsotg: The host state.
2752 * Power up the phy, set the basic configuration and start the PHY.
2754 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2758 writel(0, S3C_PHYPWR);
2761 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2763 writel(osc | 0x10, S3C_PHYCLK);
2765 /* issue a full set of resets to the otg and core */
2767 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2768 udelay(20); /* at-least 10uS */
2769 writel(0, S3C_RSTCON);
2773 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2775 /* unmask subset of endpoint interrupts */
2777 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2778 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2779 hsotg->regs + S3C_DIEPMSK);
2781 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2782 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2783 hsotg->regs + S3C_DOEPMSK);
2785 writel(0, hsotg->regs + S3C_DAINTMSK);
2787 /* Be in disconnected state until gadget is registered */
2788 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2791 /* post global nak until we're ready */
2792 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2793 hsotg->regs + S3C_DCTL);
2798 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2799 readl(hsotg->regs + S3C_GRXFSIZ),
2800 readl(hsotg->regs + S3C_GNPTXFSIZ));
2802 s3c_hsotg_init_fifo(hsotg);
2804 /* set the PLL on, remove the HNP/SRP and set the PHY */
2805 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2806 hsotg->regs + S3C_GUSBCFG);
2808 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2809 hsotg->regs + S3C_GAHBCFG);
2812 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2814 struct device *dev = hsotg->dev;
2815 void __iomem *regs = hsotg->regs;
2819 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2820 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2821 readl(regs + S3C_DIEPMSK));
2823 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2824 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2826 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2827 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2829 /* show periodic fifo settings */
2831 for (idx = 1; idx <= 15; idx++) {
2832 val = readl(regs + S3C_DPTXFSIZn(idx));
2833 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2834 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2835 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2838 for (idx = 0; idx < 15; idx++) {
2840 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2841 readl(regs + S3C_DIEPCTL(idx)),
2842 readl(regs + S3C_DIEPTSIZ(idx)),
2843 readl(regs + S3C_DIEPDMA(idx)));
2845 val = readl(regs + S3C_DOEPCTL(idx));
2847 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2848 idx, readl(regs + S3C_DOEPCTL(idx)),
2849 readl(regs + S3C_DOEPTSIZ(idx)),
2850 readl(regs + S3C_DOEPDMA(idx)));
2854 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2855 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2860 * state_show - debugfs: show overall driver and device state.
2861 * @seq: The seq file to write to.
2862 * @v: Unused parameter.
2864 * This debugfs entry shows the overall state of the hardware and
2865 * some general information about each of the endpoints available
2868 static int state_show(struct seq_file *seq, void *v)
2870 struct s3c_hsotg *hsotg = seq->private;
2871 void __iomem *regs = hsotg->regs;
2874 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2875 readl(regs + S3C_DCFG),
2876 readl(regs + S3C_DCTL),
2877 readl(regs + S3C_DSTS));
2879 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2880 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2882 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2883 readl(regs + S3C_GINTMSK),
2884 readl(regs + S3C_GINTSTS));
2886 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2887 readl(regs + S3C_DAINTMSK),
2888 readl(regs + S3C_DAINT));
2890 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2891 readl(regs + S3C_GNPTXSTS),
2892 readl(regs + S3C_GRXSTSR));
2894 seq_printf(seq, "\nEndpoint status:\n");
2896 for (idx = 0; idx < 15; idx++) {
2899 in = readl(regs + S3C_DIEPCTL(idx));
2900 out = readl(regs + S3C_DOEPCTL(idx));
2902 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2905 in = readl(regs + S3C_DIEPTSIZ(idx));
2906 out = readl(regs + S3C_DOEPTSIZ(idx));
2908 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2911 seq_printf(seq, "\n");
2917 static int state_open(struct inode *inode, struct file *file)
2919 return single_open(file, state_show, inode->i_private);
2922 static const struct file_operations state_fops = {
2923 .owner = THIS_MODULE,
2926 .llseek = seq_lseek,
2927 .release = single_release,
2931 * fifo_show - debugfs: show the fifo information
2932 * @seq: The seq_file to write data to.
2933 * @v: Unused parameter.
2935 * Show the FIFO information for the overall fifo and all the
2936 * periodic transmission FIFOs.
2938 static int fifo_show(struct seq_file *seq, void *v)
2940 struct s3c_hsotg *hsotg = seq->private;
2941 void __iomem *regs = hsotg->regs;
2945 seq_printf(seq, "Non-periodic FIFOs:\n");
2946 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2948 val = readl(regs + S3C_GNPTXFSIZ);
2949 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2950 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2951 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2953 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2955 for (idx = 1; idx <= 15; idx++) {
2956 val = readl(regs + S3C_DPTXFSIZn(idx));
2958 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2959 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2960 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2966 static int fifo_open(struct inode *inode, struct file *file)
2968 return single_open(file, fifo_show, inode->i_private);
2971 static const struct file_operations fifo_fops = {
2972 .owner = THIS_MODULE,
2975 .llseek = seq_lseek,
2976 .release = single_release,
2980 static const char *decode_direction(int is_in)
2982 return is_in ? "in" : "out";
2986 * ep_show - debugfs: show the state of an endpoint.
2987 * @seq: The seq_file to write data to.
2988 * @v: Unused parameter.
2990 * This debugfs entry shows the state of the given endpoint (one is
2991 * registered for each available).
2993 static int ep_show(struct seq_file *seq, void *v)
2995 struct s3c_hsotg_ep *ep = seq->private;
2996 struct s3c_hsotg *hsotg = ep->parent;
2997 struct s3c_hsotg_req *req;
2998 void __iomem *regs = hsotg->regs;
2999 int index = ep->index;
3000 int show_limit = 15;
3001 unsigned long flags;
3003 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3004 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3006 /* first show the register state */
3008 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3009 readl(regs + S3C_DIEPCTL(index)),
3010 readl(regs + S3C_DOEPCTL(index)));
3012 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3013 readl(regs + S3C_DIEPDMA(index)),
3014 readl(regs + S3C_DOEPDMA(index)));
3016 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3017 readl(regs + S3C_DIEPINT(index)),
3018 readl(regs + S3C_DOEPINT(index)));
3020 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3021 readl(regs + S3C_DIEPTSIZ(index)),
3022 readl(regs + S3C_DOEPTSIZ(index)));
3024 seq_printf(seq, "\n");
3025 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3026 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3028 seq_printf(seq, "request list (%p,%p):\n",
3029 ep->queue.next, ep->queue.prev);
3031 spin_lock_irqsave(&ep->lock, flags);
3033 list_for_each_entry(req, &ep->queue, queue) {
3034 if (--show_limit < 0) {
3035 seq_printf(seq, "not showing more requests...\n");
3039 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3040 req == ep->req ? '*' : ' ',
3041 req, req->req.length, req->req.buf);
3042 seq_printf(seq, "%d done, res %d\n",
3043 req->req.actual, req->req.status);
3046 spin_unlock_irqrestore(&ep->lock, flags);
3051 static int ep_open(struct inode *inode, struct file *file)
3053 return single_open(file, ep_show, inode->i_private);
3056 static const struct file_operations ep_fops = {
3057 .owner = THIS_MODULE,
3060 .llseek = seq_lseek,
3061 .release = single_release,
3065 * s3c_hsotg_create_debug - create debugfs directory and files
3066 * @hsotg: The driver state
3068 * Create the debugfs files to allow the user to get information
3069 * about the state of the system. The directory name is created
3070 * with the same name as the device itself, in case we end up
3071 * with multiple blocks in future systems.
3073 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3075 struct dentry *root;
3078 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3079 hsotg->debug_root = root;
3081 dev_err(hsotg->dev, "cannot create debug root\n");
3085 /* create general state file */
3087 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3088 hsotg, &state_fops);
3090 if (IS_ERR(hsotg->debug_file))
3091 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3093 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3096 if (IS_ERR(hsotg->debug_fifo))
3097 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3099 /* create one file for each endpoint */
3101 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3102 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3104 ep->debugfs = debugfs_create_file(ep->name, 0444,
3105 root, ep, &ep_fops);
3107 if (IS_ERR(ep->debugfs))
3108 dev_err(hsotg->dev, "failed to create %s debug file\n",
3114 * s3c_hsotg_delete_debug - cleanup debugfs entries
3115 * @hsotg: The driver state
3117 * Cleanup (remove) the debugfs files for use on module exit.
3119 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3123 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3124 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3125 debugfs_remove(ep->debugfs);
3128 debugfs_remove(hsotg->debug_file);
3129 debugfs_remove(hsotg->debug_fifo);
3130 debugfs_remove(hsotg->debug_root);
3134 * s3c_hsotg_gate - set the hardware gate for the block
3135 * @pdev: The device we bound to
3138 * Set the hardware gate setting into the block. If we end up on
3139 * something other than an S3C64XX, then we might need to change this
3140 * to using a platform data callback, or some other mechanism.
3142 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3144 unsigned long flags;
3147 local_irq_save(flags);
3149 others = __raw_readl(S3C64XX_OTHERS);
3151 others |= S3C64XX_OTHERS_USBMASK;
3153 others &= ~S3C64XX_OTHERS_USBMASK;
3154 __raw_writel(others, S3C64XX_OTHERS);
3156 local_irq_restore(flags);
3159 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3161 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3163 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3164 struct device *dev = &pdev->dev;
3165 struct s3c_hsotg *hsotg;
3166 struct resource *res;
3171 plat = &s3c_hsotg_default_pdata;
3173 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3174 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3177 dev_err(dev, "cannot get memory\n");
3184 platform_set_drvdata(pdev, hsotg);
3186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3188 dev_err(dev, "cannot find register resource 0\n");
3193 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3195 if (!hsotg->regs_res) {
3196 dev_err(dev, "cannot reserve registers\n");
3201 hsotg->regs = ioremap(res->start, resource_size(res));
3203 dev_err(dev, "cannot map registers\n");
3208 ret = platform_get_irq(pdev, 0);
3210 dev_err(dev, "cannot find IRQ\n");
3216 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3218 dev_err(dev, "cannot claim IRQ\n");
3222 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3224 device_initialize(&hsotg->gadget.dev);
3226 dev_set_name(&hsotg->gadget.dev, "gadget");
3228 hsotg->gadget.is_dualspeed = 1;
3229 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3230 hsotg->gadget.name = dev_name(dev);
3232 hsotg->gadget.dev.parent = dev;
3233 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3235 /* setup endpoint information */
3237 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3238 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3240 /* allocate EP0 request */
3242 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3244 if (!hsotg->ctrl_req) {
3245 dev_err(dev, "failed to allocate ctrl req\n");
3249 /* reset the system */
3251 s3c_hsotg_gate(pdev, true);
3253 s3c_hsotg_otgreset(hsotg);
3254 s3c_hsotg_corereset(hsotg);
3255 s3c_hsotg_init(hsotg);
3257 /* initialise the endpoints now the core has been initialised */
3258 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3259 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3261 s3c_hsotg_create_debug(hsotg);
3263 s3c_hsotg_dump(hsotg);
3269 iounmap(hsotg->regs);
3272 release_resource(hsotg->regs_res);
3273 kfree(hsotg->regs_res);
3280 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3282 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3284 s3c_hsotg_delete_debug(hsotg);
3286 usb_gadget_unregister_driver(hsotg->driver);
3288 free_irq(hsotg->irq, hsotg);
3289 iounmap(hsotg->regs);
3291 release_resource(hsotg->regs_res);
3292 kfree(hsotg->regs_res);
3294 s3c_hsotg_gate(pdev, false);
3301 #define s3c_hsotg_suspend NULL
3302 #define s3c_hsotg_resume NULL
3305 static struct platform_driver s3c_hsotg_driver = {
3307 .name = "s3c-hsotg",
3308 .owner = THIS_MODULE,
3310 .probe = s3c_hsotg_probe,
3311 .remove = __devexit_p(s3c_hsotg_remove),
3312 .suspend = s3c_hsotg_suspend,
3313 .resume = s3c_hsotg_resume,
3316 static int __init s3c_hsotg_modinit(void)
3318 return platform_driver_register(&s3c_hsotg_driver);
3321 static void __exit s3c_hsotg_modexit(void)
3323 platform_driver_unregister(&s3c_hsotg_driver);
3326 module_init(s3c_hsotg_modinit);
3327 module_exit(s3c_hsotg_modexit);
3329 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3330 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3331 MODULE_LICENSE("GPL");
3332 MODULE_ALIAS("platform:s3c-hsotg");