2 * USB Gadget driver for LPC32xx
5 * Kevin Wells <kevin.wells@nxp.com>
7 * Roland Stigge <stigge@antcom.de>
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
13 * Note: This driver is based on original work done by Mike James for
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/init.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/proc_fs.h>
42 #include <linux/clk.h>
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/i2c.h>
46 #include <linux/kthread.h>
47 #include <linux/freezer.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/dmapool.h>
50 #include <linux/workqueue.h>
52 #include <linux/usb/isp1301.h>
54 #include <asm/byteorder.h>
55 #include <mach/hardware.h>
58 #include <asm/system.h>
60 #include <mach/platform.h>
61 #include <mach/irqs.h>
62 #include <mach/board.h>
63 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
64 #include <linux/seq_file.h>
68 * USB device configuration structure
70 typedef void (*usc_chg_event)(int);
71 struct lpc32xx_usbd_cfg {
72 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
73 usc_chg_event conn_chgb; /* Connection change event (optional) */
74 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
75 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
79 * controller driver data structures
82 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
83 #define NUM_ENDPOINTS 16
86 * IRQ indices make reading the code a little easier
90 #define IRQ_USB_DEVDMA 2
93 #define EP_OUT 0 /* RX (from host) */
94 #define EP_IN 1 /* TX (to host) */
96 /* Returns the interrupt mask for the selected hardware endpoint */
97 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
100 #define EP_ISO_TYPE 1
101 #define EP_BLK_TYPE 2
102 #define EP_CTL_TYPE 3
105 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
106 #define DATA_IN 1 /* Expect dev->host transfer */
107 #define DATA_OUT 2 /* Expect host->dev transfer */
109 /* DD (DMA Descriptor) structure, requires word alignment, this is already
110 * defined in the LPC32XX USB device header file, but this version is slightly
111 * modified to tag some work data with each DMA descriptor. */
112 struct lpc32xx_usbd_dd_gad {
117 u32 dd_iso_ps_mem_addr;
119 u32 iso_status[6]; /* 5 spare */
124 * Logical endpoint structure
128 struct list_head queue;
129 struct lpc32xx_udc *udc;
131 u32 hwep_num_base; /* Physical hardware EP */
132 u32 hwep_num; /* Maps to hardware endpoint */
144 const struct usb_endpoint_descriptor *desc;
148 * Common UDC structure
151 struct usb_gadget gadget;
152 struct usb_gadget_driver *driver;
153 struct platform_device *pdev;
157 struct i2c_client *isp1301_i2c_client;
159 /* Board and device specific */
160 struct lpc32xx_usbd_cfg *board;
163 void __iomem *udp_baseaddr;
165 struct clk *usb_pll_clk;
166 struct clk *usb_slv_clk;
171 struct dma_pool *dd_cache;
173 /* Common EP and control data */
175 u32 enabled_hwepints;
179 /* VBUS detection, pullup, and power flags */
185 /* Work queues related to I2C support */
186 struct work_struct pullup_job;
187 struct work_struct vbus_job;
188 struct work_struct power_job;
190 /* USB device peripheral - various */
191 struct lpc32xx_ep ep[NUM_ENDPOINTS];
197 atomic_t enabled_ep_cnt;
198 wait_queue_head_t ep_disable_wait_queue;
204 struct lpc32xx_request {
205 struct usb_request req;
206 struct list_head queue;
207 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
212 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
214 return container_of(g, struct lpc32xx_udc, gadget);
217 #define ep_dbg(epp, fmt, arg...) \
218 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
219 #define ep_err(epp, fmt, arg...) \
220 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
221 #define ep_info(epp, fmt, arg...) \
222 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
223 #define ep_warn(epp, fmt, arg...) \
224 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
226 #define UDCA_BUFF_SIZE (128)
228 /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
229 * be replaced with an inremap()ed pointer, see USB_OTG_CLK_CTRL()
231 #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
232 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON | OTG_CLOCK_ON | \
233 DEV_CLOCK_ON | I2C_CLOCK_ON)
235 /* USB_CTRL bit defines */
236 #define USB_SLAVE_HCLK_EN (1 << 24)
237 #define USB_HOST_NEED_CLK_EN (1 << 21)
238 #define USB_DEV_NEED_CLK_EN (1 << 22)
240 #define USB_OTG_CLK_CTRL(udc) ((udc)->udp_baseaddr + 0xFF4)
241 #define USB_OTG_CLK_STAT(udc) ((udc)->udp_baseaddr + 0xFF8)
243 /* USB_OTG_CLK_CTRL bit defines */
244 #define AHB_M_CLOCK_ON (1 << 4)
245 #define OTG_CLOCK_ON (1 << 3)
246 #define I2C_CLOCK_ON (1 << 2)
247 #define DEV_CLOCK_ON (1 << 1)
248 #define HOST_CLOCK_ON (1 << 0)
250 #define USB_OTG_STAT_CONTROL(udc) (udc->udp_baseaddr + 0x110)
252 /* USB_OTG_STAT_CONTROL bit defines */
253 #define TRANSPARENT_I2C_EN (1 << 7)
254 #define HOST_EN (1 << 0)
256 /**********************************************************************
257 * USB device controller register offsets
258 **********************************************************************/
260 #define USBD_DEVINTST(x) ((x) + 0x200)
261 #define USBD_DEVINTEN(x) ((x) + 0x204)
262 #define USBD_DEVINTCLR(x) ((x) + 0x208)
263 #define USBD_DEVINTSET(x) ((x) + 0x20C)
264 #define USBD_CMDCODE(x) ((x) + 0x210)
265 #define USBD_CMDDATA(x) ((x) + 0x214)
266 #define USBD_RXDATA(x) ((x) + 0x218)
267 #define USBD_TXDATA(x) ((x) + 0x21C)
268 #define USBD_RXPLEN(x) ((x) + 0x220)
269 #define USBD_TXPLEN(x) ((x) + 0x224)
270 #define USBD_CTRL(x) ((x) + 0x228)
271 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
272 #define USBD_EPINTST(x) ((x) + 0x230)
273 #define USBD_EPINTEN(x) ((x) + 0x234)
274 #define USBD_EPINTCLR(x) ((x) + 0x238)
275 #define USBD_EPINTSET(x) ((x) + 0x23C)
276 #define USBD_EPINTPRI(x) ((x) + 0x240)
277 #define USBD_REEP(x) ((x) + 0x244)
278 #define USBD_EPIND(x) ((x) + 0x248)
279 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
280 /* DMA support registers only below */
281 /* Set, clear, or get enabled state of the DMA request status. If
282 * enabled, an IN or OUT token will start a DMA transfer for the EP */
283 #define USBD_DMARST(x) ((x) + 0x250)
284 #define USBD_DMARCLR(x) ((x) + 0x254)
285 #define USBD_DMARSET(x) ((x) + 0x258)
286 /* DMA UDCA head pointer */
287 #define USBD_UDCAH(x) ((x) + 0x280)
288 /* EP DMA status, enable, and disable. This is used to specifically
289 * enabled or disable DMA for a specific EP */
290 #define USBD_EPDMAST(x) ((x) + 0x284)
291 #define USBD_EPDMAEN(x) ((x) + 0x288)
292 #define USBD_EPDMADIS(x) ((x) + 0x28C)
293 /* DMA master interrupts enable and pending interrupts */
294 #define USBD_DMAINTST(x) ((x) + 0x290)
295 #define USBD_DMAINTEN(x) ((x) + 0x294)
296 /* DMA end of transfer interrupt enable, disable, status */
297 #define USBD_EOTINTST(x) ((x) + 0x2A0)
298 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
299 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
300 /* New DD request interrupt enable, disable, status */
301 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
302 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
303 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
304 /* DMA error interrupt enable, disable, status */
305 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
306 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
307 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
309 /**********************************************************************
310 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
311 * USBD_DEVINTPRI register definitions
312 **********************************************************************/
313 #define USBD_ERR_INT (1 << 9)
314 #define USBD_EP_RLZED (1 << 8)
315 #define USBD_TXENDPKT (1 << 7)
316 #define USBD_RXENDPKT (1 << 6)
317 #define USBD_CDFULL (1 << 5)
318 #define USBD_CCEMPTY (1 << 4)
319 #define USBD_DEV_STAT (1 << 3)
320 #define USBD_EP_SLOW (1 << 2)
321 #define USBD_EP_FAST (1 << 1)
322 #define USBD_FRAME (1 << 0)
324 /**********************************************************************
325 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
326 * USBD_EPINTPRI register definitions
327 **********************************************************************/
328 /* End point selection macro (RX) */
329 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
331 /* End point selection macro (TX) */
332 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
334 /**********************************************************************
335 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
336 * USBD_EPDMAEN/USBD_EPDMADIS/
337 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
338 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
339 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
340 * register definitions
341 **********************************************************************/
342 /* Endpoint selection macro */
343 #define USBD_EP_SEL(e) (1 << (e))
345 /**********************************************************************
346 * SBD_DMAINTST/USBD_DMAINTEN
347 **********************************************************************/
348 #define USBD_SYS_ERR_INT (1 << 2)
349 #define USBD_NEW_DD_INT (1 << 1)
350 #define USBD_EOT_INT (1 << 0)
352 /**********************************************************************
353 * USBD_RXPLEN register definitions
354 **********************************************************************/
355 #define USBD_PKT_RDY (1 << 11)
356 #define USBD_DV (1 << 10)
357 #define USBD_PK_LEN_MASK 0x3FF
359 /**********************************************************************
360 * USBD_CTRL register definitions
361 **********************************************************************/
362 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
363 #define USBD_WR_EN (1 << 1)
364 #define USBD_RD_EN (1 << 0)
366 /**********************************************************************
367 * USBD_CMDCODE register definitions
368 **********************************************************************/
369 #define USBD_CMD_CODE(c) ((c) << 16)
370 #define USBD_CMD_PHASE(p) ((p) << 8)
372 /**********************************************************************
373 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
374 **********************************************************************/
375 #define USBD_DMAEP(e) (1 << (e))
377 /* DD (DMA Descriptor) structure, requires word alignment */
378 struct lpc32xx_usbd_dd {
383 u32 dd_iso_ps_mem_addr;
386 /* dd_setup bit defines */
387 #define DD_SETUP_ATLE_DMA_MODE 0x01
388 #define DD_SETUP_NEXT_DD_VALID 0x04
389 #define DD_SETUP_ISO_EP 0x10
390 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
391 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
393 /* dd_status bit defines */
394 #define DD_STATUS_DD_RETIRED 0x01
395 #define DD_STATUS_STS_MASK 0x1E
396 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
397 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
398 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
399 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
400 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
401 #define DD_STATUS_STS_SE 0x12 /* System error */
402 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
403 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
404 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
405 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
406 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
410 * Protocol engine bits below
413 /* Device Interrupt Bit Definitions */
414 #define FRAME_INT 0x00000001
415 #define EP_FAST_INT 0x00000002
416 #define EP_SLOW_INT 0x00000004
417 #define DEV_STAT_INT 0x00000008
418 #define CCEMTY_INT 0x00000010
419 #define CDFULL_INT 0x00000020
420 #define RxENDPKT_INT 0x00000040
421 #define TxENDPKT_INT 0x00000080
422 #define EP_RLZED_INT 0x00000100
423 #define ERR_INT 0x00000200
425 /* Rx & Tx Packet Length Definitions */
426 #define PKT_LNGTH_MASK 0x000003FF
427 #define PKT_DV 0x00000400
428 #define PKT_RDY 0x00000800
430 /* USB Control Definitions */
431 #define CTRL_RD_EN 0x00000001
432 #define CTRL_WR_EN 0x00000002
435 #define CMD_SET_ADDR 0x00D00500
436 #define CMD_CFG_DEV 0x00D80500
437 #define CMD_SET_MODE 0x00F30500
438 #define CMD_RD_FRAME 0x00F50500
439 #define DAT_RD_FRAME 0x00F50200
440 #define CMD_RD_TEST 0x00FD0500
441 #define DAT_RD_TEST 0x00FD0200
442 #define CMD_SET_DEV_STAT 0x00FE0500
443 #define CMD_GET_DEV_STAT 0x00FE0500
444 #define DAT_GET_DEV_STAT 0x00FE0200
445 #define CMD_GET_ERR_CODE 0x00FF0500
446 #define DAT_GET_ERR_CODE 0x00FF0200
447 #define CMD_RD_ERR_STAT 0x00FB0500
448 #define DAT_RD_ERR_STAT 0x00FB0200
449 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
450 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
451 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
452 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
453 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
454 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
455 #define CMD_CLR_BUF 0x00F20500
456 #define DAT_CLR_BUF 0x00F20200
457 #define CMD_VALID_BUF 0x00FA0500
459 /* Device Address Register Definitions */
460 #define DEV_ADDR_MASK 0x7F
463 /* Device Configure Register Definitions */
464 #define CONF_DVICE 0x01
466 /* Device Mode Register Definitions */
475 /* Device Status Register Definitions */
477 #define DEV_CON_CH 0x02
479 #define DEV_SUS_CH 0x08
482 /* Error Code Register Definitions */
483 #define ERR_EC_MASK 0x0F
486 /* Error Status Register Definitions */
488 #define ERR_UEPKT 0x02
489 #define ERR_DCRC 0x04
490 #define ERR_TIMOUT 0x08
492 #define ERR_B_OVRN 0x20
493 #define ERR_BTSTF 0x40
496 /* Endpoint Select Register Definitions */
497 #define EP_SEL_F 0x01
498 #define EP_SEL_ST 0x02
499 #define EP_SEL_STP 0x04
500 #define EP_SEL_PO 0x08
501 #define EP_SEL_EPN 0x10
502 #define EP_SEL_B_1_FULL 0x20
503 #define EP_SEL_B_2_FULL 0x40
505 /* Endpoint Status Register Definitions */
506 #define EP_STAT_ST 0x01
507 #define EP_STAT_DA 0x20
508 #define EP_STAT_RF_MO 0x40
509 #define EP_STAT_CND_ST 0x80
511 /* Clear Buffer Register Definitions */
512 #define CLR_BUF_PO 0x01
514 /* DMA Interrupt Bit Definitions */
516 #define NDD_REQ_INT 0x02
517 #define SYS_ERR_INT 0x04
519 #define DRIVER_VERSION "1.03"
520 static const char driver_name[] = "lpc32xx_udc";
524 * proc interface support
527 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
528 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
529 static const char debug_filename[] = "driver/udc";
531 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
533 struct lpc32xx_request *req;
536 seq_printf(s, "%12s, maxpacket %4d %3s",
537 ep->ep.name, ep->ep.maxpacket,
538 ep->is_in ? "in" : "out");
539 seq_printf(s, " type %4s", epnames[ep->eptype]);
540 seq_printf(s, " ints: %12d", ep->totalints);
542 if (list_empty(&ep->queue))
543 seq_printf(s, "\t(queue empty)\n");
545 list_for_each_entry(req, &ep->queue, queue) {
546 u32 length = req->req.actual;
548 seq_printf(s, "\treq %p len %d/%d buf %p\n",
550 req->req.length, req->req.buf);
555 static int proc_udc_show(struct seq_file *s, void *unused)
557 struct lpc32xx_udc *udc = s->private;
558 struct lpc32xx_ep *ep;
561 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
563 spin_lock_irqsave(&udc->lock, flags);
565 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
566 udc->vbus ? "present" : "off",
567 udc->enabled ? (udc->vbus ? "active" : "enabled") :
569 udc->selfpowered ? "self" : "VBUS",
570 udc->suspended ? ", suspended" : "",
571 udc->driver ? udc->driver->driver.name : "(none)");
573 if (udc->enabled && udc->vbus) {
574 proc_ep_show(s, &udc->ep[0]);
575 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
581 spin_unlock_irqrestore(&udc->lock, flags);
586 static int proc_udc_open(struct inode *inode, struct file *file)
588 return single_open(file, proc_udc_show, PDE(inode)->data);
591 static const struct file_operations proc_ops = {
592 .owner = THIS_MODULE,
593 .open = proc_udc_open,
596 .release = single_release,
599 static void create_debug_file(struct lpc32xx_udc *udc)
601 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
604 static void remove_debug_file(struct lpc32xx_udc *udc)
607 debugfs_remove(udc->pde);
611 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
612 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
615 /* Primary initialization sequence for the ISP1301 transceiver */
616 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
618 /* LPC32XX only supports DAT_SE0 USB mode */
619 /* This sequence is important */
621 /* Disable transparent UART mode first */
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
626 /* Set full speed and SE0 mode */
627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
628 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
629 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
630 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
633 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
635 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
636 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
637 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
638 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
640 /* Driver VBUS_DRV high or low depending on board setup */
641 if (udc->board->vbus_drv_pol != 0)
642 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
643 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
645 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
646 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
649 /* Bi-directional mode with suspend control
650 * Enable both pulldowns for now - the pullup will be enable when VBUS
652 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
653 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
654 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
655 ISP1301_I2C_OTG_CONTROL_1,
656 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
658 /* Discharge VBUS (just in case) */
659 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
660 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
662 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
663 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
666 /* Clear and enable VBUS high edge interrupt */
667 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
668 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
670 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
671 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
672 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
673 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
674 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
675 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
676 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
678 /* Enable usb_need_clk clock after transceiver is initialized */
679 writel((readl(USB_CTRL) | (1 << 22)), USB_CTRL);
681 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
682 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
683 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
684 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
685 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
686 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
689 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
690 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
693 /* Enable pullup for bus signalling */
694 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
695 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
697 /* Enable pullup for bus signalling */
698 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
699 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
703 static void pullup_work(struct work_struct *work)
705 struct lpc32xx_udc *udc =
706 container_of(work, struct lpc32xx_udc, pullup_job);
708 isp1301_pullup_set(udc);
711 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
714 if (en_pullup == udc->pullup)
717 udc->pullup = en_pullup;
719 isp1301_pullup_set(udc);
721 /* defer slow i2c pull up setting */
722 schedule_work(&udc->pullup_job);
726 /* Powers up or down the ISP1301 transceiver */
727 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
730 /* Power up ISP1301 - this ISP1301 will automatically wakeup
731 when VBUS is detected */
732 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
733 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
736 /* Power down ISP1301 */
737 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
738 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
741 static void power_work(struct work_struct *work)
743 struct lpc32xx_udc *udc =
744 container_of(work, struct lpc32xx_udc, power_job);
746 isp1301_set_powerstate(udc, udc->poweron);
752 * USB protocol engine command/data read/write helper functions
755 /* Issues a single command to the USB device state machine */
756 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
761 /* EP may lock on CLRI if this read isn't done */
762 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
766 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
768 /* Write command code */
769 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
771 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
772 USBD_CCEMPTY) == 0) && (to > 0)) {
783 /* Issues 2 commands (or command and data) to the USB device state machine */
784 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
787 udc_protocol_cmd_w(udc, cmd);
788 udc_protocol_cmd_w(udc, data);
791 /* Issues a single command to the USB device state machine and reads
793 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
798 /* Write a command and read data from the protocol engine */
799 writel((USBD_CDFULL | USBD_CCEMPTY),
800 USBD_DEVINTCLR(udc->udp_baseaddr));
802 /* Write command code */
803 udc_protocol_cmd_w(udc, cmd);
805 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
806 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
811 "Protocol engine didn't receive response (CDFULL)\n");
813 return readl(USBD_CMDDATA(udc->udp_baseaddr));
818 * USB device interrupt mask support functions
821 /* Enable one or more USB device interrupts */
822 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
824 udc->enabled_devints |= devmask;
825 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
828 /* Disable one or more USB device interrupts */
829 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
831 udc->enabled_devints &= ~mask;
832 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
835 /* Clear one or more USB device interrupts */
836 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
838 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
843 * Endpoint interrupt disable/enable functions
846 /* Enable one or more USB endpoint interrupts */
847 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
849 udc->enabled_hwepints |= (1 << hwep);
850 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
853 /* Disable one or more USB endpoint interrupts */
854 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
856 udc->enabled_hwepints &= ~(1 << hwep);
857 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
860 /* Clear one or more USB endpoint interrupts */
861 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
863 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
866 /* Enable DMA for the HW channel */
867 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
869 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
872 /* Disable DMA for the HW channel */
873 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
875 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
880 * Endpoint realize/unrealize functions
883 /* Before an endpoint can be used, it needs to be realized
884 * in the USB protocol engine - this realizes the endpoint.
885 * The interrupt (FIFO or DMA) is not enabled with this function */
886 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
891 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
892 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
893 udc->realized_eps |= (1 << hwep);
894 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
895 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
897 /* Wait until endpoint is realized in hardware */
898 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
899 USBD_EP_RLZED)) && (to > 0))
902 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
904 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
907 /* Unrealize an EP */
908 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
910 udc->realized_eps &= ~(1 << hwep);
911 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
916 * Endpoint support functions
919 /* Select and clear endpoint interrupt */
920 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
922 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
923 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
926 /* Disables the endpoint in the USB protocol engine */
927 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
929 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
930 DAT_WR_BYTE(EP_STAT_DA));
933 /* Stalls the endpoint - endpoint will return STALL */
934 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
936 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
937 DAT_WR_BYTE(EP_STAT_ST));
940 /* Clear stall or reset endpoint */
941 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
943 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
947 /* Select an endpoint for endpoint status, clear, validate */
948 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
950 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
955 * Endpoint buffer management functions
958 /* Clear the current endpoint's buffer */
959 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
961 udc_select_hwep(udc, hwep);
962 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
965 /* Validate the current endpoint's buffer */
966 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
968 udc_select_hwep(udc, hwep);
969 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
972 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
974 /* Clear EP interrupt */
975 uda_clear_hwepint(udc, hwep);
976 return udc_selep_clrint(udc, hwep);
984 /* Allocate a DMA Descriptor */
985 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
988 struct lpc32xx_usbd_dd_gad *dd;
990 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
991 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
998 /* Free a DMA Descriptor */
999 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
1001 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
1006 * USB setup and shutdown functions
1009 /* Enables or disables most of the USB system clocks when low power mode is
1010 * needed. Clocks are typically started on a connection event, and disabled
1011 * when a cable is disconnected */
1012 #define OTGOFF_CLK_MASK (AHB_M_CLOCK_ON | I2C_CLOCK_ON)
1013 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
1024 clk_enable(udc->usb_pll_clk);
1026 /* Enable the USB device clock */
1027 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1030 /* Set to enable all needed USB OTG clocks */
1031 writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc));
1033 while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) !=
1034 USB_CLOCK_MASK) && (to > 0))
1037 dev_dbg(udc->dev, "Cannot enable USB OTG clocking\n");
1044 /* Never disable the USB_HCLK during normal operation */
1046 /* 48MHz PLL dpwn */
1047 clk_disable(udc->usb_pll_clk);
1049 /* Enable the USB device clock */
1050 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1053 /* Set to enable all needed USB OTG clocks */
1054 writel(OTGOFF_CLK_MASK, USB_OTG_CLK_CTRL(udc));
1056 while (((readl(USB_OTG_CLK_STAT(udc)) &
1058 OTGOFF_CLK_MASK) && (to > 0))
1061 dev_dbg(udc->dev, "Cannot disable USB OTG clocking\n");
1065 /* Set/reset USB device address */
1066 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1068 /* Address will be latched at the end of the status phase, or
1069 latched immediately if function is called twice */
1070 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1071 DAT_WR_BYTE(DEV_EN | addr));
1074 /* Setup up a IN request for DMA transfer - this consists of determining the
1075 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1076 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1077 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1079 struct lpc32xx_request *req;
1080 u32 hwep = ep->hwep_num;
1082 ep->req_pending = 1;
1084 /* There will always be a request waiting here */
1085 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1087 /* Place the DD Descriptor into the UDCA */
1088 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1090 /* Enable DMA and interrupt for the HW EP */
1091 udc_ep_dma_enable(udc, hwep);
1093 /* Clear ZLP if last packet is not of MAXP size */
1094 if (req->req.length % ep->ep.maxpacket)
1100 /* Setup up a OUT request for DMA transfer - this consists of determining the
1101 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1102 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1103 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1105 struct lpc32xx_request *req;
1106 u32 hwep = ep->hwep_num;
1108 ep->req_pending = 1;
1110 /* There will always be a request waiting here */
1111 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1113 /* Place the DD Descriptor into the UDCA */
1114 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1116 /* Enable DMA and interrupt for the HW EP */
1117 udc_ep_dma_enable(udc, hwep);
1121 static void udc_disable(struct lpc32xx_udc *udc)
1125 /* Disable device */
1126 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1127 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1129 /* Disable all device interrupts (including EP0) */
1130 uda_disable_devint(udc, 0x3FF);
1132 /* Disable and reset all endpoint interrupts */
1133 for (i = 0; i < 32; i++) {
1134 uda_disable_hwepint(udc, i);
1135 uda_clear_hwepint(udc, i);
1136 udc_disable_hwep(udc, i);
1137 udc_unrealize_hwep(udc, i);
1138 udc->udca_v_base[i] = 0;
1140 /* Disable and clear all interrupts and DMA */
1141 udc_ep_dma_disable(udc, i);
1142 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1143 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1144 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1145 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1148 /* Disable DMA interrupts */
1149 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1151 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1154 static void udc_enable(struct lpc32xx_udc *udc)
1157 struct lpc32xx_ep *ep = &udc->ep[0];
1159 /* Start with known state */
1163 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1165 /* EP interrupts on high priority, FRAME interrupt on low priority */
1166 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1167 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1169 /* Clear any pending device interrupts */
1170 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1172 /* Setup UDCA - not yet used (DMA) */
1173 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1175 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1176 for (i = 0; i <= 1; i++) {
1177 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1178 uda_enable_hwepint(udc, i);
1179 udc_select_hwep(udc, i);
1180 udc_clrstall_hwep(udc, i);
1181 udc_clr_buffer_hwep(udc, i);
1184 /* Device interrupt setup */
1185 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1187 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1190 /* Set device address to 0 - called twice to force a latch in the USB
1191 engine without the need of a setup packet status closure */
1192 udc_set_address(udc, 0);
1193 udc_set_address(udc, 0);
1195 /* Enable master DMA interrupts */
1196 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1197 USBD_DMAINTEN(udc->udp_baseaddr));
1199 udc->dev_status = 0;
1204 * USB device board specific events handled via callbacks
1207 /* Connection change event - notify board function of change */
1208 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1210 /* Just notify of a connection change event (optional) */
1211 if (udc->board->conn_chgb != NULL)
1212 udc->board->conn_chgb(conn);
1215 /* Suspend/resume event - notify board function of change */
1216 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1218 /* Just notify of a Suspend/resume change event (optional) */
1219 if (udc->board->susp_chgb != NULL)
1220 udc->board->susp_chgb(conn);
1228 /* Remote wakeup enable/disable - notify board function of change */
1229 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1231 if (udc->board->rmwk_chgb != NULL)
1232 udc->board->rmwk_chgb(udc->dev_status &
1233 (1 << USB_DEVICE_REMOTE_WAKEUP));
1236 /* Reads data from FIFO, adjusts for alignment and data size */
1237 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1241 u32 *p32, tmp, cbytes;
1243 /* Use optimal data transfer method based on source address and size */
1244 switch (((u32) data) & 0x3) {
1245 case 0: /* 32-bit aligned */
1247 cbytes = (bytes & ~0x3);
1249 /* Copy 32-bit aligned data first */
1250 for (n = 0; n < cbytes; n += 4)
1251 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1253 /* Handle any remaining bytes */
1254 bl = bytes - cbytes;
1256 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1257 for (n = 0; n < bl; n++)
1258 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1263 case 1: /* 8-bit aligned */
1265 /* Each byte has to be handled independently */
1266 for (n = 0; n < bytes; n += 4) {
1267 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1273 for (i = 0; i < bl; i++)
1274 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1278 case 2: /* 16-bit aligned */
1280 cbytes = (bytes & ~0x3);
1282 /* Copy 32-bit sized objects first with 16-bit alignment */
1283 for (n = 0; n < cbytes; n += 4) {
1284 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1285 *p16++ = (u16)(tmp & 0xFFFF);
1286 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1289 /* Handle any remaining bytes */
1290 bl = bytes - cbytes;
1292 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1293 for (n = 0; n < bl; n++)
1294 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1300 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1301 * as EP0) that don't use DMA. This function should only be called if a packet
1302 * is known to be ready to read for the endpoint. Note that the endpoint must
1303 * be selected in the protocol engine prior to this call. */
1304 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1309 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1311 /* Setup read of endpoint */
1312 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1314 /* Wait until packet is ready */
1315 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1316 PKT_RDY) == 0) && (to > 0))
1319 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1321 /* Mask out count */
1322 tmp = tmpv & PKT_LNGTH_MASK;
1326 if ((tmp > 0) && (data != NULL))
1327 udc_pop_fifo(udc, (u8 *) data, tmp);
1329 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1331 /* Clear the buffer */
1332 udc_clr_buffer_hwep(udc, hwep);
1337 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1338 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1342 u32 *p32, tmp, cbytes;
1344 /* Use optimal data transfer method based on source address and size */
1345 switch (((u32) data) & 0x3) {
1346 case 0: /* 32-bit aligned */
1348 cbytes = (bytes & ~0x3);
1350 /* Copy 32-bit aligned data first */
1351 for (n = 0; n < cbytes; n += 4)
1352 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1354 /* Handle any remaining bytes */
1355 bl = bytes - cbytes;
1358 for (n = 0; n < bl; n++)
1359 tmp |= data[cbytes + n] << (n * 8);
1361 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1365 case 1: /* 8-bit aligned */
1367 /* Each byte has to be handled independently */
1368 for (n = 0; n < bytes; n += 4) {
1374 for (i = 0; i < bl; i++)
1375 tmp |= data[n + i] << (i * 8);
1377 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1381 case 2: /* 16-bit aligned */
1383 cbytes = (bytes & ~0x3);
1385 /* Copy 32-bit aligned data first */
1386 for (n = 0; n < cbytes; n += 4) {
1387 tmp = *p16++ & 0xFFFF;
1388 tmp |= (*p16++ & 0xFFFF) << 16;
1389 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1392 /* Handle any remaining bytes */
1393 bl = bytes - cbytes;
1396 for (n = 0; n < bl; n++)
1397 tmp |= data[cbytes + n] << (n * 8);
1399 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1405 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1406 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1407 * protocol engine prior to this call. */
1408 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1411 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1413 if ((bytes > 0) && (data == NULL))
1416 /* Setup write of endpoint */
1417 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1419 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1421 /* Need at least 1 byte to trigger TX */
1423 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1425 udc_stuff_fifo(udc, (u8 *) data, bytes);
1427 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1429 udc_val_buffer_hwep(udc, hwep);
1432 /* USB device reset - resets USB to a default state with just EP0
1434 static void uda_usb_reset(struct lpc32xx_udc *udc)
1437 /* Re-init device controller and EP0 */
1439 udc->gadget.speed = USB_SPEED_FULL;
1441 for (i = 1; i < NUM_ENDPOINTS; i++) {
1442 struct lpc32xx_ep *ep = &udc->ep[i];
1443 ep->req_pending = 0;
1447 /* Send a ZLP on EP0 */
1448 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1450 udc_write_hwep(udc, EP_IN, NULL, 0);
1453 /* Get current frame number */
1454 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1458 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1459 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1460 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1462 return (fhi << 8) | flo;
1465 /* Set the device as configured - enables all endpoints */
1466 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1468 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1471 /* Set the device as unconfigured - disables all endpoints */
1472 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1474 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1477 /* reinit == restore initial software state */
1478 static void udc_reinit(struct lpc32xx_udc *udc)
1482 INIT_LIST_HEAD(&udc->gadget.ep_list);
1483 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1485 for (i = 0; i < NUM_ENDPOINTS; i++) {
1486 struct lpc32xx_ep *ep = &udc->ep[i];
1489 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1491 ep->ep.maxpacket = ep->maxpacket;
1492 INIT_LIST_HEAD(&ep->queue);
1493 ep->req_pending = 0;
1496 udc->ep0state = WAIT_FOR_SETUP;
1499 /* Must be called with lock */
1500 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1502 struct lpc32xx_udc *udc = ep->udc;
1504 list_del_init(&req->queue);
1505 if (req->req.status == -EINPROGRESS)
1506 req->req.status = status;
1508 status = req->req.status;
1511 enum dma_data_direction direction;
1514 direction = DMA_TO_DEVICE;
1516 direction = DMA_FROM_DEVICE;
1519 dma_unmap_single(ep->udc->gadget.dev.parent,
1520 req->req.dma, req->req.length,
1525 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
1526 req->req.dma, req->req.length,
1530 udc_dd_free(udc, req->dd_desc_ptr);
1533 if (status && status != -ESHUTDOWN)
1534 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1536 ep->req_pending = 0;
1537 spin_unlock(&udc->lock);
1538 req->req.complete(&ep->ep, &req->req);
1539 spin_lock(&udc->lock);
1542 /* Must be called with lock */
1543 static void nuke(struct lpc32xx_ep *ep, int status)
1545 struct lpc32xx_request *req;
1547 while (!list_empty(&ep->queue)) {
1548 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1549 done(ep, req, status);
1552 if (ep->desc && status == -ESHUTDOWN) {
1553 uda_disable_hwepint(ep->udc, ep->hwep_num);
1554 udc_disable_hwep(ep->udc, ep->hwep_num);
1558 /* IN endpoint 0 transfer */
1559 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1561 struct lpc32xx_request *req;
1562 struct lpc32xx_ep *ep0 = &udc->ep[0];
1565 if (list_empty(&ep0->queue))
1566 /* Nothing to send */
1569 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1572 tsend = ts = req->req.length - req->req.actual;
1575 udc_ep0_send_zlp(udc);
1578 } else if (ts > ep0->ep.maxpacket)
1579 ts = ep0->ep.maxpacket; /* Just send what we can */
1581 /* Write data to the EP0 FIFO and start transfer */
1582 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1584 /* Increment data pointer */
1585 req->req.actual += ts;
1587 if (tsend >= ep0->ep.maxpacket)
1588 return 0; /* Stay in data transfer state */
1590 /* Transfer request is complete */
1591 udc->ep0state = WAIT_FOR_SETUP;
1596 /* OUT endpoint 0 transfer */
1597 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1599 struct lpc32xx_request *req;
1600 struct lpc32xx_ep *ep0 = &udc->ep[0];
1601 u32 tr, bufferspace;
1603 if (list_empty(&ep0->queue))
1606 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1610 if (req->req.length == 0) {
1611 /* Just dequeue request */
1613 udc->ep0state = WAIT_FOR_SETUP;
1617 /* Get data from FIFO */
1618 bufferspace = req->req.length - req->req.actual;
1619 if (bufferspace > ep0->ep.maxpacket)
1620 bufferspace = ep0->ep.maxpacket;
1622 /* Copy data to buffer */
1623 prefetchw(req->req.buf + req->req.actual);
1624 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1626 req->req.actual += bufferspace;
1628 if (tr < ep0->ep.maxpacket) {
1629 /* This is the last packet */
1631 udc->ep0state = WAIT_FOR_SETUP;
1639 /* Must be called with lock */
1640 static void stop_activity(struct lpc32xx_udc *udc)
1642 struct usb_gadget_driver *driver = udc->driver;
1645 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1648 udc->gadget.speed = USB_SPEED_UNKNOWN;
1651 for (i = 0; i < NUM_ENDPOINTS; i++) {
1652 struct lpc32xx_ep *ep = &udc->ep[i];
1653 nuke(ep, -ESHUTDOWN);
1656 spin_unlock(&udc->lock);
1657 driver->disconnect(&udc->gadget);
1658 spin_lock(&udc->lock);
1661 isp1301_pullup_enable(udc, 0, 0);
1667 * Activate or kill host pullup
1668 * Can be called with or without lock
1670 static void pullup(struct lpc32xx_udc *udc, int is_on)
1675 if (!udc->enabled || !udc->vbus)
1678 if (is_on != udc->pullup)
1679 isp1301_pullup_enable(udc, is_on, 0);
1682 /* Must be called without lock */
1683 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1685 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1686 struct lpc32xx_udc *udc = ep->udc;
1687 unsigned long flags;
1689 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1691 spin_lock_irqsave(&udc->lock, flags);
1693 nuke(ep, -ESHUTDOWN);
1695 /* restore the endpoint's pristine config */
1698 /* Clear all DMA statuses for this EP */
1699 udc_ep_dma_disable(udc, ep->hwep_num);
1700 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1701 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1702 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1703 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1705 /* Remove the DD pointer in the UDCA */
1706 udc->udca_v_base[ep->hwep_num] = 0;
1708 /* Disable and reset endpoint and interrupt */
1709 uda_clear_hwepint(udc, ep->hwep_num);
1710 udc_unrealize_hwep(udc, ep->hwep_num);
1714 spin_unlock_irqrestore(&udc->lock, flags);
1716 atomic_dec(&udc->enabled_ep_cnt);
1717 wake_up(&udc->ep_disable_wait_queue);
1722 /* Must be called without lock */
1723 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1724 const struct usb_endpoint_descriptor *desc)
1726 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1727 struct lpc32xx_udc *udc = ep->udc;
1730 unsigned long flags;
1732 /* Verify EP data */
1733 if ((!_ep) || (!ep) || (!desc) || (ep->desc) ||
1734 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1735 dev_dbg(udc->dev, "bad ep or descriptor\n");
1738 maxpacket = usb_endpoint_maxp(desc);
1739 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1740 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1744 /* Don't touch EP0 */
1745 if (ep->hwep_num_base == 0) {
1746 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1750 /* Is driver ready? */
1751 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1752 dev_dbg(udc->dev, "bogus device state\n");
1756 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1758 case USB_ENDPOINT_XFER_CONTROL:
1761 case USB_ENDPOINT_XFER_INT:
1762 if (maxpacket > ep->maxpacket) {
1764 "Bad INT endpoint maxpacket %d\n", maxpacket);
1769 case USB_ENDPOINT_XFER_BULK:
1770 switch (maxpacket) {
1779 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1784 case USB_ENDPOINT_XFER_ISOC:
1787 spin_lock_irqsave(&udc->lock, flags);
1789 /* Initialize endpoint to match the selected descriptor */
1790 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1792 ep->ep.maxpacket = maxpacket;
1794 /* Map hardware endpoint from base and direction */
1796 /* IN endpoints are offset 1 from the OUT endpoint */
1797 ep->hwep_num = ep->hwep_num_base + EP_IN;
1799 ep->hwep_num = ep->hwep_num_base;
1801 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1802 ep->hwep_num, maxpacket, (ep->is_in == 1));
1804 /* Realize the endpoint, interrupt is enabled later when
1805 * buffers are queued, IN EPs will NAK until buffers are ready */
1806 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1807 udc_clr_buffer_hwep(udc, ep->hwep_num);
1808 uda_disable_hwepint(udc, ep->hwep_num);
1809 udc_clrstall_hwep(udc, ep->hwep_num);
1811 /* Clear all DMA statuses for this EP */
1812 udc_ep_dma_disable(udc, ep->hwep_num);
1813 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1814 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1815 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1816 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1818 spin_unlock_irqrestore(&udc->lock, flags);
1820 atomic_inc(&udc->enabled_ep_cnt);
1825 * Allocate a USB request list
1826 * Can be called with or without lock
1828 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1831 struct lpc32xx_request *req;
1833 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1837 INIT_LIST_HEAD(&req->queue);
1842 * De-allocate a USB request list
1843 * Can be called with or without lock
1845 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1846 struct usb_request *_req)
1848 struct lpc32xx_request *req;
1850 req = container_of(_req, struct lpc32xx_request, req);
1851 BUG_ON(!list_empty(&req->queue));
1855 /* Must be called without lock */
1856 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1857 struct usb_request *_req, gfp_t gfp_flags)
1859 struct lpc32xx_request *req;
1860 struct lpc32xx_ep *ep;
1861 struct lpc32xx_udc *udc;
1862 unsigned long flags;
1865 req = container_of(_req, struct lpc32xx_request, req);
1866 ep = container_of(_ep, struct lpc32xx_ep, ep);
1868 if (!_req || !_req->complete || !_req->buf ||
1869 !list_empty(&req->queue))
1874 if (!_ep || (!ep->desc && ep->hwep_num_base != 0)) {
1875 dev_dbg(udc->dev, "invalid ep\n");
1880 if ((!udc) || (!udc->driver) ||
1881 (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1882 dev_dbg(udc->dev, "invalid device\n");
1887 enum dma_data_direction direction;
1888 struct lpc32xx_usbd_dd_gad *dd;
1890 /* Map DMA pointer */
1892 direction = DMA_TO_DEVICE;
1894 direction = DMA_FROM_DEVICE;
1896 if (req->req.dma == 0) {
1897 req->req.dma = dma_map_single(
1898 ep->udc->gadget.dev.parent,
1899 req->req.buf, req->req.length, direction);
1902 dma_sync_single_for_device(
1903 ep->udc->gadget.dev.parent, req->req.dma,
1904 req->req.length, direction);
1908 /* For the request, build a list of DDs */
1909 dd = udc_dd_alloc(udc);
1911 /* Error allocating DD */
1914 req->dd_desc_ptr = dd;
1916 /* Setup the DMA descriptor */
1917 dd->dd_next_phy = dd->dd_next_v = 0;
1918 dd->dd_buffer_addr = req->req.dma;
1921 /* Special handling for ISO EPs */
1922 if (ep->eptype == EP_ISO_TYPE) {
1923 dd->dd_setup = DD_SETUP_ISO_EP |
1924 DD_SETUP_PACKETLEN(0) |
1925 DD_SETUP_DMALENBYTES(1);
1926 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1928 dd->iso_status[0] = req->req.length;
1930 dd->iso_status[0] = 0;
1932 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1933 DD_SETUP_DMALENBYTES(req->req.length);
1936 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1937 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1939 spin_lock_irqsave(&udc->lock, flags);
1941 _req->status = -EINPROGRESS;
1943 req->send_zlp = _req->zero;
1945 /* Kickstart empty queues */
1946 if (list_empty(&ep->queue)) {
1947 list_add_tail(&req->queue, &ep->queue);
1949 if (ep->hwep_num_base == 0) {
1950 /* Handle expected data direction */
1952 /* IN packet to host */
1953 udc->ep0state = DATA_IN;
1954 status = udc_ep0_in_req(udc);
1956 /* OUT packet from host */
1957 udc->ep0state = DATA_OUT;
1958 status = udc_ep0_out_req(udc);
1960 } else if (ep->is_in) {
1961 /* IN packet to host and kick off transfer */
1962 if (!ep->req_pending)
1963 udc_ep_in_req_dma(udc, ep);
1965 /* OUT packet from host and kick off list */
1966 if (!ep->req_pending)
1967 udc_ep_out_req_dma(udc, ep);
1969 list_add_tail(&req->queue, &ep->queue);
1971 spin_unlock_irqrestore(&udc->lock, flags);
1973 return (status < 0) ? status : 0;
1976 /* Must be called without lock */
1977 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1979 struct lpc32xx_ep *ep;
1980 struct lpc32xx_request *req;
1981 unsigned long flags;
1983 ep = container_of(_ep, struct lpc32xx_ep, ep);
1984 if (!_ep || ep->hwep_num_base == 0)
1987 spin_lock_irqsave(&ep->udc->lock, flags);
1989 /* make sure it's actually queued on this endpoint */
1990 list_for_each_entry(req, &ep->queue, queue) {
1991 if (&req->req == _req)
1994 if (&req->req != _req) {
1995 spin_unlock_irqrestore(&ep->udc->lock, flags);
1999 done(ep, req, -ECONNRESET);
2001 spin_unlock_irqrestore(&ep->udc->lock, flags);
2006 /* Must be called without lock */
2007 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
2009 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2010 struct lpc32xx_udc *udc = ep->udc;
2011 unsigned long flags;
2013 if ((!ep) || (ep->desc == NULL) || (ep->hwep_num <= 1))
2016 /* Don't halt an IN EP */
2020 spin_lock_irqsave(&udc->lock, flags);
2024 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
2025 DAT_WR_BYTE(EP_STAT_ST));
2029 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
2033 spin_unlock_irqrestore(&udc->lock, flags);
2038 /* set the halt feature and ignores clear requests */
2039 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
2041 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2043 if (!_ep || !ep->udc)
2048 return usb_ep_set_halt(_ep);
2051 static const struct usb_ep_ops lpc32xx_ep_ops = {
2052 .enable = lpc32xx_ep_enable,
2053 .disable = lpc32xx_ep_disable,
2054 .alloc_request = lpc32xx_ep_alloc_request,
2055 .free_request = lpc32xx_ep_free_request,
2056 .queue = lpc32xx_ep_queue,
2057 .dequeue = lpc32xx_ep_dequeue,
2058 .set_halt = lpc32xx_ep_set_halt,
2059 .set_wedge = lpc32xx_ep_set_wedge,
2062 /* Send a ZLP on a non-0 IN EP */
2063 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2065 /* Clear EP status */
2066 udc_clearep_getsts(udc, ep->hwep_num);
2068 /* Send ZLP via FIFO mechanism */
2069 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
2073 * Handle EP completion for ZLP
2074 * This function will only be called when a delayed ZLP needs to be sent out
2075 * after a DMA transfer has filled both buffers.
2077 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2080 struct lpc32xx_request *req;
2082 if (ep->hwep_num <= 0)
2085 uda_clear_hwepint(udc, ep->hwep_num);
2087 /* If this interrupt isn't enabled, return now */
2088 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2091 /* Get endpoint status */
2092 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2095 * This should never happen, but protect against writing to the
2098 if (epstatus & EP_SEL_F)
2102 udc_send_in_zlp(udc, ep);
2103 uda_disable_hwepint(udc, ep->hwep_num);
2107 /* If there isn't a request waiting, something went wrong */
2108 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2112 /* Start another request if ready */
2113 if (!list_empty(&ep->queue)) {
2115 udc_ep_in_req_dma(udc, ep);
2117 udc_ep_out_req_dma(udc, ep);
2119 ep->req_pending = 0;
2124 /* DMA end of transfer completion */
2125 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2127 u32 status, epstatus;
2128 struct lpc32xx_request *req;
2129 struct lpc32xx_usbd_dd_gad *dd;
2131 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2135 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2137 ep_err(ep, "DMA interrupt on no req!\n");
2140 dd = req->dd_desc_ptr;
2142 /* DMA descriptor should always be retired for this call */
2143 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2144 ep_warn(ep, "DMA descriptor did not retire\n");
2147 udc_ep_dma_disable(udc, ep->hwep_num);
2148 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2149 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2152 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2153 (1 << ep->hwep_num)) {
2154 writel((1 << ep->hwep_num),
2155 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2156 ep_err(ep, "AHB critical error!\n");
2157 ep->req_pending = 0;
2159 /* The error could have occurred on a packet of a multipacket
2160 * transfer, so recovering the transfer is not possible. Close
2161 * the request with an error */
2162 done(ep, req, -ECONNABORTED);
2166 /* Handle the current DD's status */
2167 status = dd->dd_status;
2168 switch (status & DD_STATUS_STS_MASK) {
2169 case DD_STATUS_STS_NS:
2170 /* DD not serviced? This shouldn't happen! */
2171 ep->req_pending = 0;
2172 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2175 done(ep, req, -ECONNABORTED);
2178 case DD_STATUS_STS_BS:
2179 /* Interrupt only fires on EOT - This shouldn't happen! */
2180 ep->req_pending = 0;
2181 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2183 done(ep, req, -ECONNABORTED);
2186 case DD_STATUS_STS_NC:
2187 case DD_STATUS_STS_DUR:
2188 /* Really just a short packet, not an underrun */
2189 /* This is a good status and what we expect */
2193 /* Data overrun, system error, or unknown */
2194 ep->req_pending = 0;
2195 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2197 done(ep, req, -ECONNABORTED);
2201 /* ISO endpoints are handled differently */
2202 if (ep->eptype == EP_ISO_TYPE) {
2204 req->req.actual = req->req.length;
2206 req->req.actual = dd->iso_status[0] & 0xFFFF;
2208 req->req.actual += DD_STATUS_CURDMACNT(status);
2210 /* Send a ZLP if necessary. This will be done for non-int
2211 * packets which have a size that is a divisor of MAXP */
2212 if (req->send_zlp) {
2214 * If at least 1 buffer is available, send the ZLP now.
2215 * Otherwise, the ZLP send needs to be deferred until a
2216 * buffer is available.
2218 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2219 udc_clearep_getsts(udc, ep->hwep_num);
2220 uda_enable_hwepint(udc, ep->hwep_num);
2221 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2223 /* Let the EP interrupt handle the ZLP */
2226 udc_send_in_zlp(udc, ep);
2229 /* Transfer request is complete */
2232 /* Start another request if ready */
2233 udc_clearep_getsts(udc, ep->hwep_num);
2234 if (!list_empty((&ep->queue))) {
2236 udc_ep_in_req_dma(udc, ep);
2238 udc_ep_out_req_dma(udc, ep);
2240 ep->req_pending = 0;
2246 * Endpoint 0 functions
2249 static void udc_handle_dev(struct lpc32xx_udc *udc)
2253 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2254 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2258 else if (tmp & DEV_CON_CH)
2259 uda_power_event(udc, (tmp & DEV_CON));
2260 else if (tmp & DEV_SUS_CH) {
2261 if (tmp & DEV_SUS) {
2264 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2266 /* Power down transceiver */
2268 schedule_work(&udc->pullup_job);
2269 uda_resm_susp_event(udc, 1);
2271 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2272 udc->driver && udc->vbus) {
2273 uda_resm_susp_event(udc, 0);
2274 /* Power up transceiver */
2276 schedule_work(&udc->pullup_job);
2281 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2283 struct lpc32xx_ep *ep;
2284 u32 ep0buff = 0, tmp;
2286 switch (reqtype & USB_RECIP_MASK) {
2287 case USB_RECIP_INTERFACE:
2288 break; /* Not supported */
2290 case USB_RECIP_DEVICE:
2291 ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2292 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2293 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2296 case USB_RECIP_ENDPOINT:
2297 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2299 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS) || (tmp && !ep->desc))
2302 if (wIndex & USB_DIR_IN) {
2304 return -EOPNOTSUPP; /* Something's wrong */
2305 } else if (ep->is_in)
2306 return -EOPNOTSUPP; /* Not an IN endpoint */
2308 /* Get status of the endpoint */
2309 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2310 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2312 if (tmp & EP_SEL_ST)
2313 ep0buff = (1 << USB_ENDPOINT_HALT);
2323 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2328 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2330 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2331 struct usb_ctrlrequest ctrlpkt;
2333 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2335 /* Nuke previous transfers */
2338 /* Get setup packet */
2339 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2341 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2346 /* Native endianness */
2347 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2348 wValue = le16_to_cpu(ctrlpkt.wValue);
2349 wLength = le16_to_cpu(ctrlpkt.wLength);
2350 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2352 /* Set direction of EP0 */
2353 if (likely(reqtype & USB_DIR_IN))
2358 /* Handle SETUP packet */
2359 req = le16_to_cpu(ctrlpkt.bRequest);
2361 case USB_REQ_CLEAR_FEATURE:
2362 case USB_REQ_SET_FEATURE:
2364 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2365 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2366 goto stall; /* Nothing else handled */
2368 /* Tell board about event */
2369 if (req == USB_REQ_CLEAR_FEATURE)
2371 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2374 (1 << USB_DEVICE_REMOTE_WAKEUP);
2375 uda_remwkp_cgh(udc);
2378 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2379 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2380 if ((wValue != USB_ENDPOINT_HALT) ||
2381 (tmp >= NUM_ENDPOINTS))
2384 /* Find hardware endpoint from logical endpoint */
2390 if (req == USB_REQ_SET_FEATURE)
2391 udc_stall_hwep(udc, tmp);
2392 else if (!ep->wedge)
2393 udc_clrstall_hwep(udc, tmp);
2402 case USB_REQ_SET_ADDRESS:
2403 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2404 udc_set_address(udc, wValue);
2409 case USB_REQ_GET_STATUS:
2410 udc_get_status(udc, reqtype, wIndex);
2414 break; /* Let GadgetFS handle the descriptor instead */
2417 if (likely(udc->driver)) {
2418 /* device-2-host (IN) or no data setup command, process
2420 spin_unlock(&udc->lock);
2421 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2423 spin_lock(&udc->lock);
2424 if (req == USB_REQ_SET_CONFIGURATION) {
2425 /* Configuration is set after endpoints are realized */
2427 /* Set configuration */
2428 udc_set_device_configured(udc);
2430 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2431 DAT_WR_BYTE(AP_CLK |
2432 INAK_BI | INAK_II));
2434 /* Clear configuration */
2435 udc_set_device_unconfigured(udc);
2437 /* Disable NAK interrupts */
2438 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2439 DAT_WR_BYTE(AP_CLK));
2444 /* setup processing failed, force stall */
2446 "req %02x.%02x protocol STALL; stat %d\n",
2448 udc->ep0state = WAIT_FOR_SETUP;
2454 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2459 udc_stall_hwep(udc, EP_IN);
2463 udc_ep0_send_zlp(udc);
2467 /* IN endpoint 0 transfer */
2468 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2470 struct lpc32xx_ep *ep0 = &udc->ep[0];
2473 /* Clear EP interrupt */
2474 epstatus = udc_clearep_getsts(udc, EP_IN);
2476 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2480 /* Stalled? Clear stall and reset buffers */
2481 if (epstatus & EP_SEL_ST) {
2482 udc_clrstall_hwep(udc, EP_IN);
2483 nuke(ep0, -ECONNABORTED);
2484 udc->ep0state = WAIT_FOR_SETUP;
2488 /* Is a buffer available? */
2489 if (!(epstatus & EP_SEL_F)) {
2490 /* Handle based on current state */
2491 if (udc->ep0state == DATA_IN)
2492 udc_ep0_in_req(udc);
2494 /* Unknown state for EP0 oe end of DATA IN phase */
2495 nuke(ep0, -ECONNABORTED);
2496 udc->ep0state = WAIT_FOR_SETUP;
2501 /* OUT endpoint 0 transfer */
2502 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2504 struct lpc32xx_ep *ep0 = &udc->ep[0];
2507 /* Clear EP interrupt */
2508 epstatus = udc_clearep_getsts(udc, EP_OUT);
2511 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2516 if (epstatus & EP_SEL_ST) {
2517 udc_clrstall_hwep(udc, EP_OUT);
2518 nuke(ep0, -ECONNABORTED);
2519 udc->ep0state = WAIT_FOR_SETUP;
2523 /* A NAK may occur if a packet couldn't be received yet */
2524 if (epstatus & EP_SEL_EPN)
2526 /* Setup packet incoming? */
2527 if (epstatus & EP_SEL_STP) {
2529 udc->ep0state = WAIT_FOR_SETUP;
2532 /* Data available? */
2533 if (epstatus & EP_SEL_F)
2534 /* Handle based on current state */
2535 switch (udc->ep0state) {
2536 case WAIT_FOR_SETUP:
2537 udc_handle_ep0_setup(udc);
2541 udc_ep0_out_req(udc);
2545 /* Unknown state for EP0 */
2546 nuke(ep0, -ECONNABORTED);
2547 udc->ep0state = WAIT_FOR_SETUP;
2551 /* Must be called without lock */
2552 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2555 unsigned long flags;
2556 struct lpc32xx_udc *udc = to_udc(gadget);
2561 spin_lock_irqsave(&udc->lock, flags);
2563 frame = (int) udc_get_current_frame(udc);
2565 spin_unlock_irqrestore(&udc->lock, flags);
2570 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2575 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2577 struct lpc32xx_udc *udc = to_udc(gadget);
2579 /* Always self-powered */
2580 udc->selfpowered = (is_on != 0);
2586 * vbus is here! turn everything on that's ready
2587 * Must be called without lock
2589 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2591 unsigned long flags;
2592 struct lpc32xx_udc *udc = to_udc(gadget);
2594 spin_lock_irqsave(&udc->lock, flags);
2596 /* Doesn't need lock */
2598 udc_clk_set(udc, 1);
2600 pullup(udc, is_active);
2605 spin_unlock_irqrestore(&udc->lock, flags);
2607 * Wait for all the endpoints to disable,
2608 * before disabling clocks. Don't wait if
2609 * endpoints are not enabled.
2611 if (atomic_read(&udc->enabled_ep_cnt))
2612 wait_event_interruptible(udc->ep_disable_wait_queue,
2613 (atomic_read(&udc->enabled_ep_cnt) == 0));
2615 spin_lock_irqsave(&udc->lock, flags);
2617 udc_clk_set(udc, 0);
2620 spin_unlock_irqrestore(&udc->lock, flags);
2625 /* Can be called with or without lock */
2626 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2628 struct lpc32xx_udc *udc = to_udc(gadget);
2630 /* Doesn't need lock */
2636 static int lpc32xx_start(struct usb_gadget_driver *driver,
2637 int (*bind)(struct usb_gadget *));
2638 static int lpc32xx_stop(struct usb_gadget_driver *driver);
2640 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2641 .get_frame = lpc32xx_get_frame,
2642 .wakeup = lpc32xx_wakeup,
2643 .set_selfpowered = lpc32xx_set_selfpowered,
2644 .vbus_session = lpc32xx_vbus_session,
2645 .pullup = lpc32xx_pullup,
2646 .start = lpc32xx_start,
2647 .stop = lpc32xx_stop,
2650 static void nop_release(struct device *dev)
2652 /* nothing to free */
2655 static struct lpc32xx_udc controller = {
2657 .ops = &lpc32xx_udc_ops,
2658 .ep0 = &controller.ep[0].ep,
2659 .name = driver_name,
2661 .init_name = "gadget",
2662 .release = nop_release,
2668 .ops = &lpc32xx_ep_ops,
2673 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2675 .eptype = EP_CTL_TYPE,
2680 .ops = &lpc32xx_ep_ops,
2685 .hwep_num = 0, /* 2 or 3, will be set later */
2687 .eptype = EP_INT_TYPE,
2692 .ops = &lpc32xx_ep_ops,
2697 .hwep_num = 0, /* 4 or 5, will be set later */
2699 .eptype = EP_BLK_TYPE,
2704 .ops = &lpc32xx_ep_ops,
2709 .hwep_num = 0, /* 6 or 7, will be set later */
2711 .eptype = EP_ISO_TYPE,
2716 .ops = &lpc32xx_ep_ops,
2721 .hwep_num = 0, /* 8 or 9, will be set later */
2723 .eptype = EP_INT_TYPE,
2728 .ops = &lpc32xx_ep_ops,
2732 .hwep_num_base = 10,
2733 .hwep_num = 0, /* 10 or 11, will be set later */
2735 .eptype = EP_BLK_TYPE,
2740 .ops = &lpc32xx_ep_ops,
2744 .hwep_num_base = 12,
2745 .hwep_num = 0, /* 12 or 13, will be set later */
2747 .eptype = EP_ISO_TYPE,
2752 .ops = &lpc32xx_ep_ops,
2756 .hwep_num_base = 14,
2759 .eptype = EP_INT_TYPE,
2764 .ops = &lpc32xx_ep_ops,
2768 .hwep_num_base = 16,
2771 .eptype = EP_BLK_TYPE,
2776 .ops = &lpc32xx_ep_ops,
2780 .hwep_num_base = 18,
2783 .eptype = EP_ISO_TYPE,
2788 .ops = &lpc32xx_ep_ops,
2792 .hwep_num_base = 20,
2795 .eptype = EP_INT_TYPE,
2799 .name = "ep11-bulk",
2800 .ops = &lpc32xx_ep_ops,
2804 .hwep_num_base = 22,
2807 .eptype = EP_BLK_TYPE,
2812 .ops = &lpc32xx_ep_ops,
2816 .hwep_num_base = 24,
2819 .eptype = EP_ISO_TYPE,
2824 .ops = &lpc32xx_ep_ops,
2828 .hwep_num_base = 26,
2831 .eptype = EP_INT_TYPE,
2835 .name = "ep14-bulk",
2836 .ops = &lpc32xx_ep_ops,
2840 .hwep_num_base = 28,
2843 .eptype = EP_BLK_TYPE,
2847 .name = "ep15-bulk",
2848 .ops = &lpc32xx_ep_ops,
2852 .hwep_num_base = 30,
2855 .eptype = EP_BLK_TYPE,
2859 /* ISO and status interrupts */
2860 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2863 struct lpc32xx_udc *udc = _udc;
2865 spin_lock(&udc->lock);
2867 /* Read the device status register */
2868 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2870 devstat &= ~USBD_EP_FAST;
2871 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2872 devstat = devstat & udc->enabled_devints;
2874 /* Device specific handling needed? */
2875 if (devstat & USBD_DEV_STAT)
2876 udc_handle_dev(udc);
2878 /* Start of frame? (devstat & FRAME_INT):
2879 * The frame interrupt isn't really needed for ISO support,
2880 * as the driver will queue the necessary packets */
2883 if (devstat & ERR_INT) {
2884 /* All types of errors, from cable removal during transfer to
2885 * misc protocol and bit errors. These are mostly for just info,
2886 * as the USB hardware will work around these. If these errors
2887 * happen alot, something is wrong. */
2888 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2889 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2890 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2893 spin_unlock(&udc->lock);
2899 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2902 struct lpc32xx_udc *udc = _udc;
2904 spin_lock(&udc->lock);
2906 /* Read the device status register */
2907 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2910 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2912 /* Special handling for EP0 */
2913 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2915 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2916 udc_handle_ep0_in(udc);
2918 /* Handle EP0 OUT */
2919 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2920 udc_handle_ep0_out(udc);
2924 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2927 /* Handle other EP interrupts */
2928 for (i = 1; i < NUM_ENDPOINTS; i++) {
2929 if (tmp & (1 << udc->ep[i].hwep_num))
2930 udc_handle_eps(udc, &udc->ep[i]);
2934 spin_unlock(&udc->lock);
2939 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2941 struct lpc32xx_udc *udc = _udc;
2946 spin_lock(&udc->lock);
2948 /* Handle EP DMA EOT interrupts */
2949 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2950 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2951 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2952 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2953 for (i = 1; i < NUM_ENDPOINTS; i++) {
2954 if (tmp & (1 << udc->ep[i].hwep_num))
2955 udc_handle_dma_ep(udc, &udc->ep[i]);
2958 spin_unlock(&udc->lock);
2965 * VBUS detection, pullup handler, and Gadget cable state notification
2968 static void vbus_work(struct work_struct *work)
2971 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2974 if (udc->enabled != 0) {
2975 /* Discharge VBUS real quick */
2976 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2977 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2979 /* Give VBUS some time (100mS) to discharge */
2982 /* Disable VBUS discharge resistor */
2983 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2984 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2987 /* Clear interrupt */
2988 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2989 ISP1301_I2C_INTERRUPT_LATCH |
2990 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2992 /* Get the VBUS status from the transceiver */
2993 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2994 ISP1301_I2C_OTG_CONTROL_2);
2996 /* VBUS on or off? */
2997 if (value & OTG_B_SESS_VLD)
3003 if (udc->last_vbus != udc->vbus) {
3004 udc->last_vbus = udc->vbus;
3005 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
3009 /* Re-enable after completion */
3010 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
3013 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
3015 struct lpc32xx_udc *udc = _udc;
3017 /* Defer handling of VBUS IRQ to work queue */
3018 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
3019 schedule_work(&udc->vbus_job);
3024 static int lpc32xx_start(struct usb_gadget_driver *driver,
3025 int (*bind)(struct usb_gadget *))
3027 struct lpc32xx_udc *udc = &controller;
3030 if (!driver || driver->max_speed < USB_SPEED_FULL ||
3031 !bind || !driver->setup) {
3032 dev_err(udc->dev, "bad parameter.\n");
3037 dev_err(udc->dev, "UDC already has a gadget driver\n");
3041 udc->driver = driver;
3042 udc->gadget.dev.driver = &driver->driver;
3044 udc->selfpowered = 1;
3047 retval = bind(&udc->gadget);
3049 dev_err(udc->dev, "bind() returned %d\n", retval);
3051 udc->selfpowered = 0;
3053 udc->gadget.dev.driver = NULL;
3057 dev_dbg(udc->dev, "bound to %s\n", driver->driver.name);
3059 /* Force VBUS process once to check for cable insertion */
3060 udc->last_vbus = udc->vbus = 0;
3061 schedule_work(&udc->vbus_job);
3063 /* Do not re-enable ATX IRQ (3) */
3064 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
3065 enable_irq(udc->udp_irq[i]);
3070 static int lpc32xx_stop(struct usb_gadget_driver *driver)
3073 struct lpc32xx_udc *udc = &controller;
3075 if (!driver || driver != udc->driver || !driver->unbind)
3078 /* Disable USB pullup */
3079 isp1301_pullup_enable(udc, 0, 1);
3081 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3082 disable_irq(udc->udp_irq[i]);
3086 spin_lock(&udc->lock);
3088 spin_unlock(&udc->lock);
3091 * Wait for all the endpoints to disable,
3092 * before disabling clocks. Don't wait if
3093 * endpoints are not enabled.
3095 if (atomic_read(&udc->enabled_ep_cnt))
3096 wait_event_interruptible(udc->ep_disable_wait_queue,
3097 (atomic_read(&udc->enabled_ep_cnt) == 0));
3099 spin_lock(&udc->lock);
3100 udc_clk_set(udc, 0);
3101 spin_unlock(&udc->lock);
3107 driver->unbind(&udc->gadget);
3108 udc->gadget.dev.driver = NULL;
3111 dev_dbg(udc->dev, "unbound from %s\n", driver->driver.name);
3115 static void lpc32xx_udc_shutdown(struct platform_device *dev)
3117 /* Force disconnect on reboot */
3118 struct lpc32xx_udc *udc = &controller;
3124 * Callbacks to be overridden by options passed via OF (TODO)
3127 static void lpc32xx_usbd_conn_chg(int conn)
3129 /* Do nothing, it might be nice to enable an LED
3130 * based on conn state being !0 */
3133 static void lpc32xx_usbd_susp_chg(int susp)
3135 /* Device suspend if susp != 0 */
3138 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3140 /* Enable or disable USB remote wakeup */
3143 struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3145 .conn_chgb = &lpc32xx_usbd_conn_chg,
3146 .susp_chgb = &lpc32xx_usbd_susp_chg,
3147 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3151 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3153 static int __init lpc32xx_udc_probe(struct platform_device *pdev)
3155 struct device *dev = &pdev->dev;
3156 struct lpc32xx_udc *udc = &controller;
3158 struct resource *res;
3159 dma_addr_t dma_handle;
3160 struct device_node *isp1301_node;
3162 /* init software state */
3163 udc->gadget.dev.parent = dev;
3165 udc->dev = &pdev->dev;
3168 if (pdev->dev.of_node) {
3169 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3172 isp1301_node = NULL;
3175 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3176 if (!udc->isp1301_i2c_client)
3177 return -EPROBE_DEFER;
3179 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3180 udc->isp1301_i2c_client->addr);
3182 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3183 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3185 udc->board = &lpc32xx_usbddata;
3188 * Resources are mapped as follows:
3189 * IORESOURCE_MEM, base address and size of USB space
3190 * IORESOURCE_IRQ, USB device low priority interrupt number
3191 * IORESOURCE_IRQ, USB device high priority interrupt number
3192 * IORESOURCE_IRQ, USB device interrupt number
3193 * IORESOURCE_IRQ, USB transceiver interrupt number
3195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3199 spin_lock_init(&udc->lock);
3202 for (i = 0; i < 4; i++) {
3203 udc->udp_irq[i] = platform_get_irq(pdev, i);
3204 if (udc->udp_irq[i] < 0) {
3206 "irq resource %d not available!\n", i);
3207 return udc->udp_irq[i];
3211 udc->io_p_start = res->start;
3212 udc->io_p_size = resource_size(res);
3213 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3214 dev_err(udc->dev, "someone's using UDC memory\n");
3218 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3219 if (!udc->udp_baseaddr) {
3221 dev_err(udc->dev, "IO map failure\n");
3225 /* Enable AHB slave USB clock, needed for further USB clock control */
3226 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3228 /* Get required clocks */
3229 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3230 if (IS_ERR(udc->usb_pll_clk)) {
3231 dev_err(udc->dev, "failed to acquire USB PLL\n");
3232 retval = PTR_ERR(udc->usb_pll_clk);
3235 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3236 if (IS_ERR(udc->usb_slv_clk)) {
3237 dev_err(udc->dev, "failed to acquire USB device clock\n");
3238 retval = PTR_ERR(udc->usb_slv_clk);
3239 goto usb_clk_get_fail;
3242 /* Setup PLL clock to 48MHz */
3243 retval = clk_enable(udc->usb_pll_clk);
3245 dev_err(udc->dev, "failed to start USB PLL\n");
3246 goto pll_enable_fail;
3249 retval = clk_set_rate(udc->usb_pll_clk, 48000);
3251 dev_err(udc->dev, "failed to set USB clock rate\n");
3255 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3257 /* Enable USB device clock */
3258 retval = clk_enable(udc->usb_slv_clk);
3260 dev_err(udc->dev, "failed to start USB device clock\n");
3261 goto usb_clk_enable_fail;
3264 /* Set to enable all needed USB OTG clocks */
3265 writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc));
3268 while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) !=
3269 USB_CLOCK_MASK) && (i > 0))
3272 dev_dbg(udc->dev, "USB OTG clocks not correctly enabled\n");
3274 /* Setup deferred workqueue data */
3275 udc->poweron = udc->pullup = 0;
3276 INIT_WORK(&udc->pullup_job, pullup_work);
3277 INIT_WORK(&udc->vbus_job, vbus_work);
3279 INIT_WORK(&udc->power_job, power_work);
3282 /* All clocks are now on */
3285 isp1301_udc_configure(udc);
3286 /* Allocate memory for the UDCA */
3287 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3289 (GFP_KERNEL | GFP_DMA));
3290 if (!udc->udca_v_base) {
3291 dev_err(udc->dev, "error getting UDCA region\n");
3295 udc->udca_p_base = dma_handle;
3296 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3297 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3299 /* Setup the DD DMA memory pool */
3300 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3301 sizeof(struct lpc32xx_usbd_dd_gad),
3303 if (!udc->dd_cache) {
3304 dev_err(udc->dev, "error getting DD DMA region\n");
3306 goto dma_alloc_fail;
3309 /* Clear USB peripheral and initialize gadget endpoints */
3313 retval = device_register(&udc->gadget.dev);
3315 dev_err(udc->dev, "Device registration failure\n");
3316 goto dev_register_fail;
3319 /* Request IRQs - low and high priority USB device IRQs are routed to
3320 * the same handler, while the DMA interrupt is routed elsewhere */
3321 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3324 dev_err(udc->dev, "LP request irq %d failed\n",
3325 udc->udp_irq[IRQ_USB_LP]);
3328 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3331 dev_err(udc->dev, "HP request irq %d failed\n",
3332 udc->udp_irq[IRQ_USB_HP]);
3336 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3337 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3339 dev_err(udc->dev, "DEV request irq %d failed\n",
3340 udc->udp_irq[IRQ_USB_DEVDMA]);
3344 /* The transceiver interrupt is used for VBUS detection and will
3345 kick off the VBUS handler function */
3346 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3349 dev_err(udc->dev, "VBUS request irq %d failed\n",
3350 udc->udp_irq[IRQ_USB_ATX]);
3354 /* Initialize wait queue */
3355 init_waitqueue_head(&udc->ep_disable_wait_queue);
3356 atomic_set(&udc->enabled_ep_cnt, 0);
3358 /* Keep all IRQs disabled until GadgetFS starts up */
3359 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3360 disable_irq(udc->udp_irq[i]);
3362 retval = usb_add_gadget_udc(dev, &udc->gadget);
3364 goto add_gadget_fail;
3366 dev_set_drvdata(dev, udc);
3367 device_init_wakeup(dev, 1);
3368 create_debug_file(udc);
3370 /* Disable clocks for now */
3371 udc_clk_set(udc, 0);
3373 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3377 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3379 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3381 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3383 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3385 device_unregister(&udc->gadget.dev);
3387 dma_pool_destroy(udc->dd_cache);
3389 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3390 udc->udca_v_base, udc->udca_p_base);
3392 clk_disable(udc->usb_slv_clk);
3393 usb_clk_enable_fail:
3395 clk_disable(udc->usb_pll_clk);
3397 clk_put(udc->usb_slv_clk);
3399 clk_put(udc->usb_pll_clk);
3401 iounmap(udc->udp_baseaddr);
3403 release_mem_region(udc->io_p_start, udc->io_p_size);
3404 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3409 static int __devexit lpc32xx_udc_remove(struct platform_device *pdev)
3411 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3413 usb_del_gadget_udc(&udc->gadget);
3417 udc_clk_set(udc, 1);
3421 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3423 device_init_wakeup(&pdev->dev, 0);
3424 remove_debug_file(udc);
3426 dma_pool_destroy(udc->dd_cache);
3427 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3428 udc->udca_v_base, udc->udca_p_base);
3429 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3430 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3431 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3433 device_unregister(&udc->gadget.dev);
3435 clk_disable(udc->usb_slv_clk);
3436 clk_put(udc->usb_slv_clk);
3437 clk_disable(udc->usb_pll_clk);
3438 clk_put(udc->usb_pll_clk);
3439 iounmap(udc->udp_baseaddr);
3440 release_mem_region(udc->io_p_start, udc->io_p_size);
3446 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3449 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3452 /* Power down ISP */
3454 isp1301_set_powerstate(udc, 0);
3456 /* Disable clocking */
3457 udc_clk_set(udc, 0);
3459 /* Keep clock flag on, so we know to re-enable clocks
3463 /* Kill OTG and I2C clocks */
3464 writel(0, USB_OTG_CLK_CTRL(udc));
3465 while (((readl(USB_OTG_CLK_STAT(udc)) & OTGOFF_CLK_MASK) !=
3466 OTGOFF_CLK_MASK) && (to > 0))
3470 "USB OTG clocks not correctly enabled\n");
3472 /* Kill global USB clock */
3473 clk_disable(udc->usb_slv_clk);
3479 static int lpc32xx_udc_resume(struct platform_device *pdev)
3481 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3484 /* Enable global USB clock */
3485 clk_enable(udc->usb_slv_clk);
3487 /* Enable clocking */
3488 udc_clk_set(udc, 1);
3490 /* ISP back to normal power mode */
3492 isp1301_set_powerstate(udc, 1);
3498 #define lpc32xx_udc_suspend NULL
3499 #define lpc32xx_udc_resume NULL
3503 static struct of_device_id lpc32xx_udc_of_match[] = {
3504 { .compatible = "nxp,lpc3220-udc", },
3507 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3510 static struct platform_driver lpc32xx_udc_driver = {
3511 .remove = __devexit_p(lpc32xx_udc_remove),
3512 .shutdown = lpc32xx_udc_shutdown,
3513 .suspend = lpc32xx_udc_suspend,
3514 .resume = lpc32xx_udc_resume,
3516 .name = (char *) driver_name,
3517 .owner = THIS_MODULE,
3518 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3522 static int __init udc_init_module(void)
3524 return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe);
3526 module_init(udc_init_module);
3528 static void __exit udc_exit_module(void)
3530 platform_driver_unregister(&lpc32xx_udc_driver);
3532 module_exit(udc_exit_module);
3534 MODULE_DESCRIPTION("LPC32XX udc driver");
3535 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3536 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3537 MODULE_LICENSE("GPL");
3538 MODULE_ALIAS("platform:lpc32xx_udc");