1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
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32 * ========================================================================== */
34 #ifndef __DWC_OTG_REGS_H__
35 #define __DWC_OTG_REGS_H__
37 #include "dwc_otg_core_if.h"
42 * This file contains the data structures for accessing the DWC_otg core registers.
44 * The application interfaces with the HS OTG core by reading from and
45 * writing to the Control and Status Register (CSR) space through the
46 * AHB Slave interface. These registers are 32 bits wide, and the
47 * addresses are 32-bit-block aligned.
48 * CSRs are classified as follows:
49 * - Core Global Registers
50 * - Device Mode Registers
51 * - Device Global Registers
52 * - Device Endpoint Specific Registers
53 * - Host Mode Registers
54 * - Host Global Registers
56 * - Host Channel Specific Registers
58 * Only the Core Global registers can be accessed in both Device and
59 * Host modes. When the HS OTG core is operating in one mode, either
60 * Device or Host, the application must not access registers from the
61 * other mode. When the core switches from one mode to another, the
62 * registers in the new mode of operation must be reprogrammed as they
63 * would be after a power-on reset.
66 /****************************************************************************/
67 /** DWC_otg Core registers .
68 * The dwc_otg_core_global_regs structure defines the size
69 * and relative field offsets for the Core Global registers.
71 typedef struct dwc_otg_core_global_regs {
72 /** OTG Control and Status Register. <i>Offset: 000h</i> */
73 volatile uint32_t gotgctl;
74 /** OTG Interrupt Register. <i>Offset: 004h</i> */
75 volatile uint32_t gotgint;
76 /**Core AHB Configuration Register. <i>Offset: 008h</i> */
77 volatile uint32_t gahbcfg;
79 #define DWC_GLBINTRMASK 0x0001
80 #define DWC_DMAENABLE 0x0020
81 #define DWC_NPTXEMPTYLVL_EMPTY 0x0080
82 #define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
83 #define DWC_PTXEMPTYLVL_EMPTY 0x0100
84 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
86 /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
87 volatile uint32_t gusbcfg;
88 /**Core Reset Register. <i>Offset: 010h</i> */
89 volatile uint32_t grstctl;
90 /**Core Interrupt Register. <i>Offset: 014h</i> */
91 volatile uint32_t gintsts;
92 /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
93 volatile uint32_t gintmsk;
94 /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
95 volatile uint32_t grxstsr;
96 /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
97 volatile uint32_t grxstsp;
98 /**Receive FIFO Size Register. <i>Offset: 024h</i> */
99 volatile uint32_t grxfsiz;
100 /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
101 volatile uint32_t gnptxfsiz;
102 /**Non Periodic Transmit FIFO/Queue Status Register (Read
103 * Only). <i>Offset: 02Ch</i> */
104 volatile uint32_t gnptxsts;
105 /**I2C Access Register. <i>Offset: 030h</i> */
106 volatile uint32_t gi2cctl;
107 /**PHY Vendor Control Register. <i>Offset: 034h</i> */
108 volatile uint32_t gpvndctl;
109 /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
110 volatile uint32_t ggpio;
111 /**User ID Register. <i>Offset: 03Ch</i> */
112 volatile uint32_t guid;
113 /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
114 volatile uint32_t gsnpsid;
115 /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
116 volatile uint32_t ghwcfg1;
117 /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
118 volatile uint32_t ghwcfg2;
119 #define DWC_SLAVE_ONLY_ARCH 0
120 #define DWC_EXT_DMA_ARCH 1
121 #define DWC_INT_DMA_ARCH 2
123 #define DWC_MODE_HNP_SRP_CAPABLE 0
124 #define DWC_MODE_SRP_ONLY_CAPABLE 1
125 #define DWC_MODE_NO_HNP_SRP_CAPABLE 2
126 #define DWC_MODE_SRP_CAPABLE_DEVICE 3
127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
128 #define DWC_MODE_SRP_CAPABLE_HOST 5
129 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6
131 /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
132 volatile uint32_t ghwcfg3;
133 /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
134 volatile uint32_t ghwcfg4;
135 /** Core LPM Configuration register <i>Offset: 054h</i>*/
136 volatile uint32_t glpmcfg;
137 /** Global PowerDn Register <i>Offset: 058h</i> */
138 volatile uint32_t gpwrdn;
139 /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
140 volatile uint32_t gdfifocfg;
141 /** ADP Control Register <i>Offset: 060h</i> */
142 volatile uint32_t adpctl;
143 /** Reserved <i>Offset: 064h-0FFh</i> */
144 volatile uint32_t reserved39[39];
145 /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
146 volatile uint32_t hptxfsiz;
147 /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
148 otherwise Device Transmit FIFO#n Register.
149 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
150 volatile uint32_t dtxfsiz[15];
151 } dwc_otg_core_global_regs_t;
154 * This union represents the bit fields of the Core OTG Control
155 * and Status Register (GOTGCTL). Set the bits using the bit
156 * fields then write the <i>d32</i> value to the register.
158 typedef union gotgctl_data {
159 /** raw register data */
163 unsigned sesreqscs:1;
165 unsigned vbvalidoven:1;
166 unsigned vbvalidovval:1;
167 unsigned avalidoven:1;
168 unsigned avalidovval:1;
169 unsigned bvalidoven:1;
170 unsigned bvalidovval:1;
171 unsigned hstnegscs:1;
173 unsigned hstsethnpen:1;
175 unsigned reserved12_15:4;
181 unsigned reserved1:1;
182 unsigned multvalidbc:5;
184 unsigned reserved28_31:4;
189 * This union represents the bit fields of the Core OTG Interrupt Register
190 * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
191 * value to the register.
193 typedef union gotgint_data {
194 /** raw register data */
199 unsigned reserved0_1:2;
201 /** Session End Detected */
202 unsigned sesenddet:1;
204 unsigned reserved3_7:5;
206 /** Session Request Success Status Change */
207 unsigned sesreqsucstschng:1;
208 /** Host Negotiation Success Status Change */
209 unsigned hstnegsucstschng:1;
211 unsigned reserved10_16:7;
213 /** Host Negotiation Detected */
214 unsigned hstnegdet:1;
215 /** A-Device Timeout Change */
216 unsigned adevtoutchng:1;
219 /** Multi-Valued input changed */
222 unsigned reserved31_21:11;
228 * This union represents the bit fields of the Core AHB Configuration
229 * Register (GAHBCFG). Set/clear the bits using the bit fields then
230 * write the <i>d32</i> value to the register.
232 typedef union gahbcfg_data {
233 /** raw register data */
237 unsigned glblintrmsk:1;
238 #define DWC_GAHBCFG_GLBINT_ENABLE 1
240 unsigned hburstlen:4;
241 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
242 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
243 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
244 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
245 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
247 unsigned dmaenable:1;
248 #define DWC_GAHBCFG_DMAENABLE 1
250 unsigned nptxfemplvl_txfemplvl:1;
251 unsigned ptxfemplvl:1;
252 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
253 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
254 unsigned reserved9_20:12;
255 unsigned remmemsupp:1;
256 unsigned notialldmawrit:1;
257 unsigned ahbsingle:1;
258 unsigned reserved24_31:8;
263 * This union represents the bit fields of the Core USB Configuration
264 * Register (GUSBCFG). Set the bits using the bit fields then write
265 * the <i>d32</i> value to the register.
267 typedef union gusbcfg_data {
268 /** raw register data */
274 unsigned ulpi_utmi_sel:1;
280 unsigned usbtrdtim:4;
281 unsigned reserved1:1;
282 unsigned phylpwrclksel:1;
283 unsigned otgutmifssel:1;
284 unsigned ulpi_fsls:1;
285 unsigned ulpi_auto_res:1;
286 unsigned ulpi_clk_sus_m:1;
287 unsigned ulpi_ext_vbus_drv:1;
288 unsigned ulpi_int_vbus_indicator:1;
289 unsigned term_sel_dl_pulse:1;
290 unsigned indicator_complement:1;
291 unsigned indicator_pass_through:1;
292 unsigned ulpi_int_prot_dis:1;
293 unsigned ic_usb_cap:1;
294 unsigned ic_traffic_pull_remove:1;
295 unsigned tx_end_delay:1;
296 unsigned force_host_mode:1;
297 unsigned force_dev_mode:1;
298 unsigned reserved31:1;
303 * This union represents the bit fields of the Core Reset Register
304 * (GRSTCTL). Set/clear the bits using the bit fields then write the
305 * <i>d32</i> value to the register.
307 typedef union grstctl_data {
308 /** raw register data */
312 /** Core Soft Reset (CSftRst) (Device and Host)
314 * The application can flush the control logic in the
315 * entire core using this bit. This bit resets the
316 * pipelines in the AHB Clock domain as well as the
319 * The state machines are reset to an IDLE state, the
320 * control bits in the CSRs are cleared, all the
321 * transmit FIFOs and the receive FIFO are flushed.
323 * The status mask bits that control the generation of
324 * the interrupt, are cleared, to clear the
325 * interrupt. The interrupt status bits are not
326 * cleared, so the application can get the status of
327 * any events that occurred in the core after it has
330 * Any transactions on the AHB are terminated as soon
331 * as possible following the protocol. Any
332 * transactions on the USB are terminated immediately.
334 * The configuration settings in the CSRs are
335 * unchanged, so the software doesn't have to
336 * reprogram these registers (Device
337 * Configuration/Host Configuration/Core System
338 * Configuration/Core PHY Configuration).
340 * The application can write to this bit, any time it
341 * wants to reset the core. This is a self clearing
342 * bit and the core clears this bit after all the
343 * necessary logic is reset in the core, which may
344 * take several clocks, depending on the current state
350 * The application uses this bit to reset the control logic in
351 * the AHB clock domain. Only AHB clock domain pipelines are
355 /** Host Frame Counter Reset (Host Only)<br>
357 * The application can reset the (micro)frame number
358 * counter inside the core, using this bit. When the
359 * (micro)frame counter is reset, the subsequent SOF
360 * sent out by the core, will have a (micro)frame
364 /** In Token Sequence Learning Queue Flush
365 * (INTknQFlsh) (Device Only)
367 unsigned intknqflsh:1;
368 /** RxFIFO Flush (RxFFlsh) (Device and Host)
370 * The application can flush the entire Receive FIFO
371 * using this bit. The application must first
372 * ensure that the core is not in the middle of a
373 * transaction. The application should write into
374 * this bit, only after making sure that neither the
375 * DMA engine is reading from the RxFIFO nor the MAC
376 * is writing the data in to the FIFO. The
377 * application should wait until the bit is cleared
378 * before performing any other operations. This bit
379 * will takes 8 clocks (slowest of PHY or AHB clock)
383 /** TxFIFO Flush (TxFFlsh) (Device and Host).
385 * This bit is used to selectively flush a single or
386 * all transmit FIFOs. The application must first
387 * ensure that the core is not in the middle of a
388 * transaction. The application should write into
389 * this bit, only after making sure that neither the
390 * DMA engine is writing into the TxFIFO nor the MAC
391 * is reading the data out of the FIFO. The
392 * application should wait until the core clears this
393 * bit, before performing any operations. This bit
394 * will takes 8 clocks (slowest of PHY or AHB clock)
399 /** TxFIFO Number (TxFNum) (Device and Host).
401 * This is the FIFO number which needs to be flushed,
402 * using the TxFIFO Flush bit. This field should not
403 * be changed until the TxFIFO Flush bit is cleared by
405 * - 0x0 : Non Periodic TxFIFO Flush
406 * - 0x1 : Periodic TxFIFO #1 Flush in device mode
407 * or Periodic TxFIFO in host mode
408 * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
410 * - 0xF : Periodic TxFIFO #15 Flush in device mode
411 * - 0x10: Flush all the Transmit NonPeriodic and
412 * Transmit Periodic FIFOs in the core
416 unsigned reserved11_29:19;
417 /** DMA Request Signal. Indicated DMA request is in
418 * probress. Used for debug purpose. */
420 /** AHB Master Idle. Indicates the AHB Master State
421 * Machine is in IDLE condition. */
427 * This union represents the bit fields of the Core Interrupt Mask
428 * Register (GINTMSK). Set/clear the bits using the bit fields then
429 * write the <i>d32</i> value to the register.
431 typedef union gintmsk_data {
432 /** raw register data */
436 unsigned reserved0:1;
437 unsigned modemismatch:1;
440 unsigned rxstsqlvl:1;
441 unsigned nptxfempty:1;
442 unsigned ginnakeff:1;
443 unsigned goutnakeff:1;
444 unsigned ulpickint:1;
446 unsigned erlysuspend:1;
447 unsigned usbsuspend:1;
450 unsigned isooutdrop:1;
452 unsigned restoredone:1;
453 unsigned epmismatch:1;
455 unsigned outepintr:1;
456 unsigned incomplisoin:1;
457 unsigned incomplisoout:1;
462 unsigned ptxfempty:1;
463 unsigned lpmtranrcvd:1;
464 unsigned conidstschng:1;
465 unsigned disconnect:1;
466 unsigned sessreqintr:1;
471 * This union represents the bit fields of the Core Interrupt Register
472 * (GINTSTS). Set/clear the bits using the bit fields then write the
473 * <i>d32</i> value to the register.
475 typedef union gintsts_data {
476 /** raw register data */
478 #define DWC_SOF_INTR_MASK 0x0008
481 #define DWC_HOST_MODE 1
483 unsigned modemismatch:1;
486 unsigned rxstsqlvl:1;
487 unsigned nptxfempty:1;
488 unsigned ginnakeff:1;
489 unsigned goutnakeff:1;
490 unsigned ulpickint:1;
492 unsigned erlysuspend:1;
493 unsigned usbsuspend:1;
496 unsigned isooutdrop:1;
498 unsigned restoredone:1;
499 unsigned epmismatch:1;
501 unsigned outepintr:1;
502 unsigned incomplisoin:1;
503 unsigned incomplisoout:1;
508 unsigned ptxfempty:1;
509 unsigned lpmtranrcvd:1;
510 unsigned conidstschng:1;
511 unsigned disconnect:1;
512 unsigned sessreqintr:1;
518 * This union represents the bit fields in the Device Receive Status Read and
519 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
520 * element then read out the bits using the <i>b</i>it elements.
522 typedef union device_grxsts_data {
523 /** raw register data */
531 #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
532 #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
534 #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
535 #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
536 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
539 unsigned reserved25_31:7;
541 } device_grxsts_data_t;
544 * This union represents the bit fields in the Host Receive Status Read and
545 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
546 * element then read out the bits using the <i>b</i>it elements.
548 typedef union host_grxsts_data {
549 /** raw register data */
558 #define DWC_GRXSTS_PKTSTS_IN 0x2
559 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
560 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
561 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
563 unsigned reserved21_31:11;
565 } host_grxsts_data_t;
568 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
569 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
570 * then read out the bits using the <i>b</i>it elements.
572 typedef union fifosize_data {
573 /** raw register data */
577 unsigned startaddr:16;
583 * This union represents the bit fields in the Non-Periodic Transmit
584 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
585 * <i>d32</i> element then read out the bits using the <i>b</i>it
588 typedef union gnptxsts_data {
589 /** raw register data */
593 unsigned nptxfspcavail:16;
594 unsigned nptxqspcavail:8;
595 /** Top of the Non-Periodic Transmit Request Queue
596 * - bit 24 - Terminate (Last entry for the selected
598 * - bits 26:25 - Token Type
600 * - 2'b01 - Zero Length OUT
601 * - 2'b10 - PING/Complete Split
602 * - 2'b11 - Channel Halt
603 * - bits 30:27 - Channel/EP Number
605 unsigned nptxqtop_terminate:1;
606 unsigned nptxqtop_token:2;
607 unsigned nptxqtop_chnep:4;
613 * This union represents the bit fields in the Transmit
614 * FIFO Status Register (DTXFSTS). Read the register into the
615 * <i>d32</i> element then read out the bits using the <i>b</i>it
618 typedef union dtxfsts_data {
619 /** raw register data */
623 unsigned txfspcavail:16;
624 unsigned reserved:16;
629 * This union represents the bit fields in the I2C Control Register
630 * (I2CCTL). Read the register into the <i>d32</i> element then read out the
631 * bits using the <i>b</i>it elements.
633 typedef union gi2cctl_data {
634 /** raw register data */
643 unsigned i2csuspctl:1;
644 unsigned i2cdevaddr:2;
645 unsigned i2cdatse0:1;
653 * This union represents the bit fields in the PHY Vendor Control Register
654 * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
655 * bits using the <i>b</i>it elements.
657 typedef union gpvndctl_data {
658 /** raw register data */
664 unsigned regaddr16_21:6;
666 unsigned reserved23_24:2;
667 unsigned newregreq:1;
670 unsigned reserved28_30:3;
671 unsigned disulpidrvr:1;
676 * This union represents the bit fields in the General Purpose
677 * Input/Output Register (GGPIO).
678 * Read the register into the <i>d32</i> element then read out the
679 * bits using the <i>b</i>it elements.
681 typedef union ggpio_data {
682 /** raw register data */
692 * This union represents the bit fields in the User ID Register
693 * (GUID). Read the register into the <i>d32</i> element then read out the
694 * bits using the <i>b</i>it elements.
696 typedef union guid_data {
697 /** raw register data */
706 * This union represents the bit fields in the Synopsys ID Register
707 * (GSNPSID). Read the register into the <i>d32</i> element then read out the
708 * bits using the <i>b</i>it elements.
710 typedef union gsnpsid_data {
711 /** raw register data */
720 * This union represents the bit fields in the User HW Config1
721 * Register. Read the register into the <i>d32</i> element then read
722 * out the bits using the <i>b</i>it elements.
724 typedef union hwcfg1_data {
725 /** raw register data */
749 * This union represents the bit fields in the User HW Config2
750 * Register. Read the register into the <i>d32</i> element then read
751 * out the bits using the <i>b</i>it elements.
753 typedef union hwcfg2_data {
754 /** raw register data */
760 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
761 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
762 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
763 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
764 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
765 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
766 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
768 unsigned architecture:2;
769 unsigned point2point:1;
770 unsigned hs_phy_type:2;
771 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
772 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
773 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
774 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
776 unsigned fs_phy_type:2;
777 unsigned num_dev_ep:4;
778 unsigned num_host_chan:4;
779 unsigned perio_ep_supported:1;
780 unsigned dynamic_fifo:1;
781 unsigned multi_proc_int:1;
782 unsigned reserved21:1;
783 unsigned nonperio_tx_q_depth:2;
784 unsigned host_perio_tx_q_depth:2;
785 unsigned dev_token_q_depth:5;
786 unsigned otg_enable_ic_usb:1;
791 * This union represents the bit fields in the User HW Config3
792 * Register. Read the register into the <i>d32</i> element then read
793 * out the bits using the <i>b</i>it elements.
795 typedef union hwcfg3_data {
796 /** raw register data */
801 unsigned xfer_size_cntr_width:4;
802 unsigned packet_size_cntr_width:3;
805 unsigned vendor_ctrl_if:1;
806 unsigned optional_features:1;
807 unsigned synch_reset_type:1;
809 unsigned otg_enable_hsic:1;
810 unsigned bc_support:1;
811 unsigned otg_lpm_en:1;
812 unsigned dfifo_depth:16;
817 * This union represents the bit fields in the User HW Config4
818 * Register. Read the register into the <i>d32</i> element then read
819 * out the bits using the <i>b</i>it elements.
821 typedef union hwcfg4_data {
822 /** raw register data */
826 unsigned num_dev_perio_in_ep:4;
827 unsigned power_optimiz:1;
828 unsigned min_ahb_freq:1;
832 unsigned utmi_phy_data_width:2;
833 unsigned num_dev_mode_ctrl_ep:4;
834 unsigned iddig_filt_en:1;
835 unsigned vbus_valid_filt_en:1;
836 unsigned a_valid_filt_en:1;
837 unsigned b_valid_filt_en:1;
838 unsigned session_end_filt_en:1;
839 unsigned ded_fifo_en:1;
840 unsigned num_in_eps:4;
842 unsigned desc_dma_dyn:1;
847 * This union represents the bit fields of the Core LPM Configuration
848 * Register (GLPMCFG). Set the bits using bit fields then write
849 * the <i>d32</i> value to the register.
851 typedef union glpmctl_data {
852 /** raw register data */
856 /** LPM-Capable (LPMCap) (Device and Host)
857 * The application uses this bit to control
858 * the DWC_otg core LPM capabilities.
860 unsigned lpm_cap_en:1;
861 /** LPM response programmed by application (AppL1Res) (Device)
862 * Handshake response to LPM token pre-programmed
863 * by device application software.
865 unsigned appl_resp:1;
866 /** Host Initiated Resume Duration (HIRD) (Device and Host)
867 * In Host mode this field indicates the value of HIRD
868 * to be sent in an LPM transaction.
869 * In Device mode this field is updated with the
870 * Received LPM Token HIRD bmAttribute
871 * when an ACK/NYET/STALL response is sent
872 * to an LPM transaction.
875 /** RemoteWakeEnable (bRemoteWake) (Device and Host)
876 * In Host mode this bit indicates the value of remote
877 * wake up to be sent in wIndex field of LPM transaction.
878 * In Device mode this field is updated with the
879 * Received LPM Token bRemoteWake bmAttribute
880 * when an ACK/NYET/STALL response is sent
881 * to an LPM transaction.
883 unsigned rem_wkup_en:1;
884 /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
885 * The application uses this bit to control
886 * the utmi_sleep_n assertion to the PHY when in L1 state.
888 unsigned en_utmi_sleep:1;
889 /** HIRD Threshold (HIRD_Thres) (Device and Host)
891 unsigned hird_thres:5;
892 /** LPM Response (CoreL1Res) (Device and Host)
893 * In Host mode this bit contains handsake response to
895 * In Device mode the response of the core to
896 * LPM transaction received is reflected in these two bits.
897 - 0x0 : ERROR (No handshake response)
903 /** Port Sleep Status (SlpSts) (Device and Host)
904 * This bit is set as long as a Sleep condition
905 * is present on the USB bus.
907 unsigned prt_sleep_sts:1;
908 /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
909 * Indicates that the application or host
910 * can start resume from Sleep state.
912 unsigned sleep_state_resumeok:1;
913 /** LPM channel Index (LPM_Chnl_Indx) (Host)
914 * The channel number on which the LPM transaction
915 * has to be applied while sending
916 * an LPM transaction to the local device.
918 unsigned lpm_chan_index:4;
919 /** LPM Retry Count (LPM_Retry_Cnt) (Host)
920 * Number host retries that would be performed
921 * if the device response was not valid response.
923 unsigned retry_count:3;
924 /** Send LPM Transaction (SndLPM) (Host)
925 * When set by application software,
926 * an LPM transaction containing two tokens
930 /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
931 * Number of LPM Host Retries still remaining
932 * to be transmitted for the current LPM sequence
934 unsigned retry_count_sts:3;
935 /** Enable Best Effort Service Latency (BESL) (Device and Host)
936 * This bit enables the BESL features as defined in the LPM errata
940 unsigned reserved29:1;
941 /** In host mode once this bit is set, the host
942 * configures to drive the HSIC Idle state on the bus.
943 * It then waits for the device to initiate the Connect sequence.
944 * In device mode once this bit is set, the device waits for
945 * the HSIC Idle line state on the bus. Upon receving the Idle
946 * line state, it initiates the HSIC Connect sequence.
948 unsigned hsic_connect:1;
949 /** This bit overrides and functionally inverts
950 * the if_select_hsic input port signal.
952 unsigned inv_sel_hsic:1;
957 * This union represents the bit fields of the Core ADP Timer, Control and
958 * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
959 * the <i>d32</i> value to the register.
961 typedef union adpctl_data {
962 /** raw register data */
966 /** Probe Discharge (PRB_DSCHG)
967 * These bits set the times for TADP_DSCHG.
968 * These bits are defined as follows:
974 unsigned prb_dschg:2;
975 /** Probe Delta (PRB_DELTA)
976 * These bits set the resolution for RTIM value.
977 * The bits are defined in units of 32 kHz clock cycles as follows:
982 * For example if this value is chosen to 2'b01, it means that RTIM
983 * increments for every 3(three) 32Khz clock cycles.
985 unsigned prb_delta:2;
986 /** Probe Period (PRB_PER)
987 * These bits sets the TADP_PRD as shown in Figure 4 as follows:
988 * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
989 * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
990 * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
994 /** These bits capture the latest time it took for VBUS to ramp from
995 * VADP_SINK to VADP_PRB.
1000 * 0x7FF - 2048 cycles
1001 * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
1004 /** Enable Probe (EnaPrb)
1005 * When programmed to 1'b1, the core performs a probe operation.
1006 * This bit is valid only if OTG_Ver = 1'b1.
1009 /** Enable Sense (EnaSns)
1010 * When programmed to 1'b1, the core performs a Sense operation.
1011 * This bit is valid only if OTG_Ver = 1'b1.
1014 /** ADP Reset (ADPRes)
1015 * When set, ADP controller is reset.
1016 * This bit is valid only if OTG_Ver = 1'b1.
1019 /** ADP Enable (ADPEn)
1020 * When set, the core performs either ADP probing or sensing
1021 * based on EnaPrb or EnaSns.
1022 * This bit is valid only if OTG_Ver = 1'b1.
1025 /** ADP Probe Interrupt (ADP_PRB_INT)
1026 * When this bit is set, it means that the VBUS
1027 * voltage is greater than VADP_PRB or VADP_PRB is reached.
1028 * This bit is valid only if OTG_Ver = 1'b1.
1030 unsigned adp_prb_int:1;
1032 * ADP Sense Interrupt (ADP_SNS_INT)
1033 * When this bit is set, it means that the VBUS voltage is greater than
1034 * VADP_SNS value or VADP_SNS is reached.
1035 * This bit is valid only if OTG_Ver = 1'b1.
1037 unsigned adp_sns_int:1;
1038 /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
1039 * This bit is relevant only for an ADP probe.
1040 * When this bit is set, it means that the ramp time has
1041 * completed ie ADPCTL.RTIM has reached its terminal value
1042 * of 0x7FF. This is a debug feature that allows software
1043 * to read the ramp time after each cycle.
1044 * This bit is valid only if OTG_Ver = 1'b1.
1046 unsigned adp_tmout_int:1;
1047 /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
1048 * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
1049 * This bit is valid only if OTG_Ver = 1'b1.
1051 unsigned adp_prb_int_msk:1;
1052 /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
1053 * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
1054 * This bit is valid only if OTG_Ver = 1'b1.
1056 unsigned adp_sns_int_msk:1;
1057 /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
1058 * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
1059 * This bit is valid only if OTG_Ver = 1'b1.
1061 unsigned adp_tmout_int_msk:1;
1063 * 2'b00 - Read/Write Valid (updated by the core)
1070 unsigned reserved29_31:3;
1074 ////////////////////////////////////////////
1077 * Device Global Registers. <i>Offsets 800h-BFFh</i>
1079 * The following structures define the size and relative field offsets
1080 * for the Device Mode Registers.
1082 * <i>These registers are visible only in Device mode and must not be
1083 * accessed in Host mode, as the results are unknown.</i>
1085 typedef struct dwc_otg_dev_global_regs {
1086 /** Device Configuration Register. <i>Offset 800h</i> */
1087 volatile uint32_t dcfg;
1088 /** Device Control Register. <i>Offset: 804h</i> */
1089 volatile uint32_t dctl;
1090 /** Device Status Register (Read Only). <i>Offset: 808h</i> */
1091 volatile uint32_t dsts;
1092 /** Reserved. <i>Offset: 80Ch</i> */
1094 /** Device IN Endpoint Common Interrupt Mask
1095 * Register. <i>Offset: 810h</i> */
1096 volatile uint32_t diepmsk;
1097 /** Device OUT Endpoint Common Interrupt Mask
1098 * Register. <i>Offset: 814h</i> */
1099 volatile uint32_t doepmsk;
1100 /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
1101 volatile uint32_t daint;
1102 /** Device All Endpoints Interrupt Mask Register. <i>Offset:
1104 volatile uint32_t daintmsk;
1105 /** Device IN Token Queue Read Register-1 (Read Only).
1106 * <i>Offset: 820h</i> */
1107 volatile uint32_t dtknqr1;
1108 /** Device IN Token Queue Read Register-2 (Read Only).
1109 * <i>Offset: 824h</i> */
1110 volatile uint32_t dtknqr2;
1111 /** Device VBUS discharge Register. <i>Offset: 828h</i> */
1112 volatile uint32_t dvbusdis;
1113 /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
1114 volatile uint32_t dvbuspulse;
1115 /** Device IN Token Queue Read Register-3 (Read Only). /
1116 * Device Thresholding control register (Read/Write)
1117 * <i>Offset: 830h</i> */
1118 volatile uint32_t dtknqr3_dthrctl;
1119 /** Device IN Token Queue Read Register-4 (Read Only). /
1120 * Device IN EPs empty Inr. Mask Register (Read/Write)
1121 * <i>Offset: 834h</i> */
1122 volatile uint32_t dtknqr4_fifoemptymsk;
1123 /** Device Each Endpoint Interrupt Register (Read Only). /
1124 * <i>Offset: 838h</i> */
1125 volatile uint32_t deachint;
1126 /** Device Each Endpoint Interrupt mask Register (Read/Write). /
1127 * <i>Offset: 83Ch</i> */
1128 volatile uint32_t deachintmsk;
1129 /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
1130 * <i>Offset: 840h</i> */
1131 volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
1132 /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
1133 * <i>Offset: 880h</i> */
1134 volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
1135 } dwc_otg_device_global_regs_t;
1138 * This union represents the bit fields in the Device Configuration
1139 * Register. Read the register into the <i>d32</i> member then
1140 * set/clear the bits using the <i>b</i>it elements. Write the
1141 * <i>d32</i> member to the dcfg register.
1143 typedef union dcfg_data {
1144 /** raw register data */
1146 /** register bits */
1150 /** Non Zero Length Status OUT Handshake */
1151 unsigned nzstsouthshk:1;
1152 #define DWC_DCFG_SEND_STALL 1
1154 unsigned ena32khzs:1;
1155 /** Device Addresses */
1157 /** Periodic Frame Interval */
1158 unsigned perfrint:2;
1159 #define DWC_DCFG_FRAME_INTERVAL_80 0
1160 #define DWC_DCFG_FRAME_INTERVAL_85 1
1161 #define DWC_DCFG_FRAME_INTERVAL_90 2
1162 #define DWC_DCFG_FRAME_INTERVAL_95 3
1164 /** Enable Device OUT NAK for bulk in DDMA mode */
1165 unsigned endevoutnak:1;
1167 unsigned reserved14_17:4;
1168 /** In Endpoint Mis-match count */
1170 /** Enable Descriptor DMA in Device mode */
1172 unsigned perschintvl:2;
1173 unsigned resvalid:6;
1178 * This union represents the bit fields in the Device Control
1179 * Register. Read the register into the <i>d32</i> member then
1180 * set/clear the bits using the <i>b</i>it elements.
1182 typedef union dctl_data {
1183 /** raw register data */
1185 /** register bits */
1187 /** Remote Wakeup */
1188 unsigned rmtwkupsig:1;
1189 /** Soft Disconnect */
1190 unsigned sftdiscon:1;
1191 /** Global Non-Periodic IN NAK Status */
1192 unsigned gnpinnaksts:1;
1193 /** Global OUT NAK Status */
1194 unsigned goutnaksts:1;
1197 /** Set Global Non-Periodic IN NAK */
1198 unsigned sgnpinnak:1;
1199 /** Clear Global Non-Periodic IN NAK */
1200 unsigned cgnpinnak:1;
1201 /** Set Global OUT NAK */
1202 unsigned sgoutnak:1;
1203 /** Clear Global OUT NAK */
1204 unsigned cgoutnak:1;
1205 /** Power-On Programming Done */
1206 unsigned pwronprgdone:1;
1208 unsigned reserved:1;
1209 /** Global Multi Count */
1211 /** Ignore Frame Number for ISOC EPs */
1213 /** NAK on Babble */
1214 unsigned nakonbble:1;
1215 /** Enable Continue on BNA */
1216 unsigned encontonbna:1;
1217 /** Enable deep sleep besl reject feature*/
1218 unsigned besl_reject:1;
1220 unsigned reserved17_31:13;
1225 * This union represents the bit fields in the Device Status
1226 * Register. Read the register into the <i>d32</i> member then
1227 * set/clear the bits using the <i>b</i>it elements.
1229 typedef union dsts_data {
1230 /** raw register data */
1232 /** register bits */
1234 /** Suspend Status */
1236 /** Enumerated Speed */
1238 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
1239 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
1240 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
1241 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
1242 /** Erratic Error */
1243 unsigned errticerr:1;
1244 unsigned reserved4_7:4;
1245 /** Frame or Microframe Number of the received SOF */
1247 unsigned reserved22_31:10;
1252 * This union represents the bit fields in the Device IN EP Interrupt
1253 * Register and the Device IN EP Common Mask Register.
1255 * - Read the register into the <i>d32</i> member then set/clear the
1256 * bits using the <i>b</i>it elements.
1258 typedef union diepint_data {
1259 /** raw register data */
1261 /** register bits */
1263 /** Transfer complete mask */
1264 unsigned xfercompl:1;
1265 /** Endpoint disable mask */
1266 unsigned epdisabled:1;
1267 /** AHB Error mask */
1269 /** TimeOUT Handshake mask (non-ISOC EPs) */
1271 /** IN Token received with TxF Empty mask */
1272 unsigned intktxfemp:1;
1273 /** IN Token Received with EP mismatch mask */
1274 unsigned intknepmis:1;
1275 /** IN Endpoint NAK Effective mask */
1276 unsigned inepnakeff:1;
1278 unsigned emptyintr:1;
1280 unsigned txfifoundrn:1;
1282 /** BNA Interrupt mask */
1285 unsigned reserved10_12:3;
1286 /** BNA Interrupt mask */
1289 unsigned reserved14_31:18;
1294 * This union represents the bit fields in the Device IN EP
1295 * Common/Dedicated Interrupt Mask Register.
1297 typedef union diepint_data diepmsk_data_t;
1300 * This union represents the bit fields in the Device OUT EP Interrupt
1301 * Registerand Device OUT EP Common Interrupt Mask Register.
1303 * - Read the register into the <i>d32</i> member then set/clear the
1304 * bits using the <i>b</i>it elements.
1306 typedef union doepint_data {
1307 /** raw register data */
1309 /** register bits */
1311 /** Transfer complete */
1312 unsigned xfercompl:1;
1313 /** Endpoint disable */
1314 unsigned epdisabled:1;
1317 /** Setup Phase Done (contorl EPs) */
1319 /** OUT Token Received when Endpoint Disabled */
1320 unsigned outtknepdis:1;
1322 unsigned stsphsercvd:1;
1323 /** Back-to-Back SETUP Packets Received */
1324 unsigned back2backsetup:1;
1326 unsigned reserved7:1;
1327 /** OUT packet Error */
1328 unsigned outpkterr:1;
1329 /** BNA Interrupt */
1332 unsigned reserved10:1;
1333 /** Packet Drop Status */
1334 unsigned pktdrpsts:1;
1335 /** Babble Interrupt */
1337 /** NAK Interrupt */
1339 /** NYET Interrupt */
1341 /** Bit indicating setup packet received */
1344 unsigned reserved16_31:16;
1349 * This union represents the bit fields in the Device OUT EP
1350 * Common/Dedicated Interrupt Mask Register.
1352 typedef union doepint_data doepmsk_data_t;
1355 * This union represents the bit fields in the Device All EP Interrupt
1356 * and Mask Registers.
1357 * - Read the register into the <i>d32</i> member then set/clear the
1358 * bits using the <i>b</i>it elements.
1360 typedef union daint_data {
1361 /** raw register data */
1363 /** register bits */
1365 /** IN Endpoint bits */
1367 /** OUT Endpoint bits */
1371 /** IN Endpoint bits */
1388 /** OUT Endpoint bits */
1409 * This union represents the bit fields in the Device IN Token Queue
1411 * - Read the register into the <i>d32</i> member.
1412 * - READ-ONLY Register
1414 typedef union dtknq1_data {
1415 /** raw register data */
1417 /** register bits */
1419 /** In Token Queue Write Pointer */
1420 unsigned intknwptr:5;
1422 unsigned reserved05_06:2;
1423 /** write pointer has wrapped. */
1424 unsigned wrap_bit:1;
1425 /** EP Numbers of IN Tokens 0 ... 4 */
1426 unsigned epnums0_5:24;
1431 * This union represents Threshold control Register
1432 * - Read and write the register into the <i>d32</i> member.
1433 * - READ-WRITABLE Register
1435 typedef union dthrctl_data {
1436 /** raw register data */
1438 /** register bits */
1440 /** non ISO Tx Thr. Enable */
1441 unsigned non_iso_thr_en:1;
1442 /** ISO Tx Thr. Enable */
1443 unsigned iso_thr_en:1;
1444 /** Tx Thr. Length */
1445 unsigned tx_thr_len:9;
1446 /** AHB Threshold ratio */
1447 unsigned ahb_thr_ratio:2;
1449 unsigned reserved13_15:3;
1450 /** Rx Thr. Enable */
1451 unsigned rx_thr_en:1;
1452 /** Rx Thr. Length */
1453 unsigned rx_thr_len:9;
1454 unsigned reserved26:1;
1455 /** Arbiter Parking Enable*/
1456 unsigned arbprken:1;
1458 unsigned reserved28_31:4;
1463 * Device Logical IN Endpoint-Specific Registers. <i>Offsets
1466 * There will be one set of endpoint registers per logical endpoint
1469 * <i>These registers are visible only in Device mode and must not be
1470 * accessed in Host mode, as the results are unknown.</i>
1472 typedef struct dwc_otg_dev_in_ep_regs {
1473 /** Device IN Endpoint Control Register. <i>Offset:900h +
1474 * (ep_num * 20h) + 00h</i> */
1475 volatile uint32_t diepctl;
1476 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
1477 uint32_t reserved04;
1478 /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
1479 * (ep_num * 20h) + 08h</i> */
1480 volatile uint32_t diepint;
1481 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
1482 uint32_t reserved0C;
1483 /** Device IN Endpoint Transfer Size
1484 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
1485 volatile uint32_t dieptsiz;
1486 /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
1487 * (ep_num * 20h) + 14h</i> */
1488 volatile uint32_t diepdma;
1489 /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
1490 * (ep_num * 20h) + 18h</i> */
1491 volatile uint32_t dtxfsts;
1492 /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
1493 * (ep_num * 20h) + 1Ch</i> */
1494 volatile uint32_t diepdmab;
1495 } dwc_otg_dev_in_ep_regs_t;
1498 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
1501 * There will be one set of endpoint registers per logical endpoint
1504 * <i>These registers are visible only in Device mode and must not be
1505 * accessed in Host mode, as the results are unknown.</i>
1507 typedef struct dwc_otg_dev_out_ep_regs {
1508 /** Device OUT Endpoint Control Register. <i>Offset:B00h +
1509 * (ep_num * 20h) + 00h</i> */
1510 volatile uint32_t doepctl;
1511 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
1512 uint32_t reserved04;
1513 /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
1514 * (ep_num * 20h) + 08h</i> */
1515 volatile uint32_t doepint;
1516 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
1517 uint32_t reserved0C;
1518 /** Device OUT Endpoint Transfer Size Register. <i>Offset:
1519 * B00h + (ep_num * 20h) + 10h</i> */
1520 volatile uint32_t doeptsiz;
1521 /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
1522 * + (ep_num * 20h) + 14h</i> */
1523 volatile uint32_t doepdma;
1524 /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
1526 /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
1527 * + (ep_num * 20h) + 1Ch</i> */
1529 } dwc_otg_dev_out_ep_regs_t;
1532 * This union represents the bit fields in the Device EP Control
1533 * Register. Read the register into the <i>d32</i> member then
1534 * set/clear the bits using the <i>b</i>it elements.
1536 typedef union depctl_data {
1537 /** raw register data */
1539 /** register bits */
1541 /** Maximum Packet Size
1543 * IN/OUT EP0 - 2 bits
1549 #define DWC_DEP0CTL_MPS_64 0
1550 #define DWC_DEP0CTL_MPS_32 1
1551 #define DWC_DEP0CTL_MPS_16 2
1552 #define DWC_DEP0CTL_MPS_8 3
1556 * OUT EPn/OUT EP0 - reserved */
1559 /** USB Active Endpoint */
1560 unsigned usbactep:1;
1562 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
1563 * This field contains the PID of the packet going to
1564 * be received or transmitted on this endpoint. The
1565 * application should program the PID of the first
1566 * packet going to be received or transmitted on this
1567 * endpoint , after the endpoint is
1568 * activated. Application use the SetD1PID and
1569 * SetD0PID fields of this register to program either
1572 * The encoding for this field is
1583 * 2'b01: Isochronous
1585 * 2'b11: Interrupt */
1590 * IN EPn/IN EP0 - reserved */
1593 /** Stall Handshake */
1598 * OUT EPn/OUT EP0 - reserved */
1605 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
1606 * Writing to this field sets the Endpoint DPID (DPID)
1607 * field in this register to DATA0. Set Even
1608 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
1609 * Writing to this field sets the Even/Odd
1610 * (micro)frame (EO_FrNum) field to even (micro)
1613 unsigned setd0pid:1;
1614 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
1615 * Writing to this field sets the Endpoint DPID (DPID)
1616 * field in this register to DATA1 Set Odd
1617 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
1618 * Writing to this field sets the Even/Odd
1619 * (micro)frame (EO_FrNum) field to odd (micro) frame.
1621 unsigned setd1pid:1;
1623 /** Endpoint Disable */
1625 /** Endpoint Enable */
1631 * This union represents the bit fields in the Device EP Transfer
1632 * Size Register. Read the register into the <i>d32</i> member then
1633 * set/clear the bits using the <i>b</i>it elements.
1635 typedef union deptsiz_data {
1636 /** raw register data */
1638 /** register bits */
1640 /** Transfer size */
1641 unsigned xfersize:19;
1642 /** Max packet count for EP (pow(2,10)-1) */
1643 #define MAX_PKT_CNT 1023
1646 /** Multi Count - Periodic IN endpoints */
1648 unsigned reserved:1;
1653 * This union represents the bit fields in the Device EP 0 Transfer
1654 * Size Register. Read the register into the <i>d32</i> member then
1655 * set/clear the bits using the <i>b</i>it elements.
1657 typedef union deptsiz0_data {
1658 /** raw register data */
1660 /** register bits */
1662 /** Transfer size */
1663 unsigned xfersize:7;
1665 unsigned reserved7_18:12;
1669 unsigned reserved21_28:8;
1670 /**Setup Packet Count (DOEPTSIZ0 Only) */
1672 unsigned reserved31;
1676 /////////////////////////////////////////////////
1677 // DMA Descriptor Specific Structures
1680 /** Buffer status definitions */
1682 #define BS_HOST_READY 0x0
1683 #define BS_DMA_BUSY 0x1
1684 #define BS_DMA_DONE 0x2
1685 #define BS_HOST_BUSY 0x3
1687 /** Receive/Transmit status definitions */
1689 #define RTS_SUCCESS 0x0
1690 #define RTS_BUFFLUSH 0x1
1691 #define RTS_RESERVED 0x2
1692 #define RTS_BUFERR 0x3
1695 * This union represents the bit fields in the DMA Descriptor
1696 * status quadlet. Read the quadlet into the <i>d32</i> member then
1697 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
1698 * <i>b_iso_in</i> elements.
1700 typedef union dev_dma_desc_sts {
1701 /** raw register data */
1705 /** Received number of bytes */
1707 /** NAK bit - only for OUT EPs */
1709 unsigned reserved17_22:6;
1710 /** Multiple Transfer - only for OUT EPs */
1712 /** Setup Packet received - only for OUT EPs */
1714 /** Interrupt On Complete */
1720 /** Receive Status */
1722 /** Buffer Status */
1726 //#ifdef DWC_EN_ISOC
1727 /** iso out quadlet bits */
1729 /** Received number of bytes */
1730 unsigned rxbytes:11;
1732 unsigned reserved11:1;
1734 unsigned framenum:11;
1735 /** Received ISO Data PID */
1737 /** Interrupt On Complete */
1743 /** Receive Status */
1745 /** Buffer Status */
1749 /** iso in quadlet bits */
1751 /** Transmited number of bytes */
1752 unsigned txbytes:12;
1754 unsigned framenum:11;
1755 /** Transmited ISO Data PID */
1757 /** Interrupt On Complete */
1763 /** Transmit Status */
1765 /** Buffer Status */
1768 //#endif /* DWC_EN_ISOC */
1769 } dev_dma_desc_sts_t;
1772 * DMA Descriptor structure
1774 * DMA Descriptor structure contains two quadlets:
1775 * Status quadlet and Data buffer pointer.
1777 typedef struct dwc_otg_dev_dma_desc {
1778 /** DMA Descriptor status quadlet */
1779 dev_dma_desc_sts_t status;
1780 /** DMA Descriptor data buffer pointer */
1782 } dwc_otg_dev_dma_desc_t;
1785 * The dwc_otg_dev_if structure contains information needed to manage
1786 * the DWC_otg controller acting in device mode. It represents the
1787 * programming view of the device-specific aspects of the controller.
1789 typedef struct dwc_otg_dev_if {
1790 /** Pointer to device Global registers.
1791 * Device Global Registers starting at offset 800h
1793 dwc_otg_device_global_regs_t *dev_global_regs;
1794 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
1797 * Device Logical IN Endpoint-Specific Registers 900h-AFCh
1799 dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
1800 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
1801 #define DWC_EP_REG_OFFSET 0x20
1803 /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
1804 dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
1805 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
1807 /* Device configuration information */
1808 uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
1809 uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
1810 uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
1812 /** Size of periodic FIFOs (Bytes) */
1813 uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
1815 /** Size of Tx FIFOs (Bytes) */
1816 uint16_t tx_fifo_size[MAX_TX_FIFOS];
1818 /** Thresholding enable flags and length varaiables **/
1820 uint16_t iso_tx_thr_en;
1821 uint16_t non_iso_tx_thr_en;
1823 uint16_t rx_thr_length;
1824 uint16_t tx_thr_length;
1827 * Pointers to the DMA Descriptors for EP0 Control
1828 * transfers (virtual and physical)
1831 /** 2 descriptors for SETUP packets */
1832 dwc_dma_t dma_setup_desc_addr[2];
1833 dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
1835 /** Pointer to Descriptor with latest SETUP packet */
1836 dwc_otg_dev_dma_desc_t *psetup;
1838 /** Index of current SETUP handler descriptor */
1839 uint32_t setup_desc_index;
1841 /** Descriptor for Data In or Status In phases */
1842 dwc_dma_t dma_in_desc_addr;
1843 dwc_otg_dev_dma_desc_t *in_desc_addr;
1845 /** Descriptor for Data Out or Status Out phases */
1846 dwc_dma_t dma_out_desc_addr;
1847 dwc_otg_dev_dma_desc_t *out_desc_addr;
1849 /** Setup Packet Detected - if set clear NAK when queueing */
1851 /** Isoc ep pointer on which incomplete happens */
1856 /////////////////////////////////////////////////
1857 // Host Mode Register Structures
1860 * The Host Global Registers structure defines the size and relative
1861 * field offsets for the Host Mode Global Registers. Host Global
1862 * Registers offsets 400h-7FFh.
1864 typedef struct dwc_otg_host_global_regs {
1865 /** Host Configuration Register. <i>Offset: 400h</i> */
1866 volatile uint32_t hcfg;
1867 /** Host Frame Interval Register. <i>Offset: 404h</i> */
1868 volatile uint32_t hfir;
1869 /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
1870 volatile uint32_t hfnum;
1871 /** Reserved. <i>Offset: 40Ch</i> */
1872 uint32_t reserved40C;
1873 /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
1874 volatile uint32_t hptxsts;
1875 /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
1876 volatile uint32_t haint;
1877 /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
1878 volatile uint32_t haintmsk;
1879 /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
1880 volatile uint32_t hflbaddr;
1881 } dwc_otg_host_global_regs_t;
1884 * This union represents the bit fields in the Host Configuration Register.
1885 * Read the register into the <i>d32</i> member then set/clear the bits using
1886 * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
1888 typedef union hcfg_data {
1889 /** raw register data */
1892 /** register bits */
1894 /** FS/LS Phy Clock Select */
1895 unsigned fslspclksel:2;
1896 #define DWC_HCFG_30_60_MHZ 0
1897 #define DWC_HCFG_48_MHZ 1
1898 #define DWC_HCFG_6_MHZ 2
1900 /** FS/LS Only Support */
1901 unsigned fslssupp:1;
1902 unsigned reserved3_6:4;
1903 /** Enable 32-KHz Suspend Mode */
1904 unsigned ena32khzs:1;
1905 /** Resume Validation Periiod */
1906 unsigned resvalid:8;
1907 unsigned reserved16_22:7;
1908 /** Enable Scatter/gather DMA in Host mode */
1910 /** Frame List Entries */
1911 unsigned frlisten:2;
1912 /** Enable Periodic Scheduling */
1913 unsigned perschedena:1;
1914 unsigned reserved27_30:4;
1915 unsigned modechtimen:1;
1920 * This union represents the bit fields in the Host Frame Remaing/Number
1923 typedef union hfir_data {
1924 /** raw register data */
1927 /** register bits */
1930 unsigned hfirrldctrl:1;
1931 unsigned reserved:15;
1936 * This union represents the bit fields in the Host Frame Remaing/Number
1939 typedef union hfnum_data {
1940 /** raw register data */
1943 /** register bits */
1946 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
1951 typedef union hptxsts_data {
1952 /** raw register data */
1955 /** register bits */
1957 unsigned ptxfspcavail:16;
1958 unsigned ptxqspcavail:8;
1959 /** Top of the Periodic Transmit Request Queue
1960 * - bit 24 - Terminate (last entry for the selected channel)
1961 * - bits 26:25 - Token Type
1962 * - 2'b00 - Zero length
1965 * - bits 30:27 - Channel Number
1966 * - bit 31 - Odd/even microframe
1968 unsigned ptxqtop_terminate:1;
1969 unsigned ptxqtop_token:2;
1970 unsigned ptxqtop_chnum:4;
1971 unsigned ptxqtop_odd:1;
1976 * This union represents the bit fields in the Host Port Control and Status
1977 * Register. Read the register into the <i>d32</i> member then set/clear the
1978 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1981 typedef union hprt0_data {
1982 /** raw register data */
1984 /** register bits */
1986 unsigned prtconnsts:1;
1987 unsigned prtconndet:1;
1989 unsigned prtenchng:1;
1990 unsigned prtovrcurract:1;
1991 unsigned prtovrcurrchng:1;
1995 unsigned reserved9:1;
1996 unsigned prtlnsts:2;
1998 unsigned prttstctl:4;
2000 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
2001 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
2002 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2
2003 unsigned reserved19_31:13;
2008 * This union represents the bit fields in the Host All Interrupt
2011 typedef union haint_data {
2012 /** raw register data */
2014 /** register bits */
2032 unsigned reserved:16;
2037 unsigned reserved:16;
2042 * This union represents the bit fields in the Host All Interrupt
2045 typedef union haintmsk_data {
2046 /** raw register data */
2048 /** register bits */
2066 unsigned reserved:16;
2071 unsigned reserved:16;
2076 * Host Channel Specific Registers. <i>500h-5FCh</i>
2078 typedef struct dwc_otg_hc_regs {
2079 /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
2080 volatile uint32_t hcchar;
2081 /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
2082 volatile uint32_t hcsplt;
2083 /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
2084 volatile uint32_t hcint;
2085 /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
2086 volatile uint32_t hcintmsk;
2087 /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
2088 volatile uint32_t hctsiz;
2089 /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
2090 volatile uint32_t hcdma;
2091 volatile uint32_t reserved;
2092 /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
2093 volatile uint32_t hcdmab;
2094 } dwc_otg_hc_regs_t;
2097 * This union represents the bit fields in the Host Channel Characteristics
2098 * Register. Read the register into the <i>d32</i> member then set/clear the
2099 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
2102 typedef union hcchar_data {
2103 /** raw register data */
2106 /** register bits */
2108 /** Maximum packet size in bytes */
2111 /** Endpoint number */
2114 /** 0: OUT, 1: IN */
2117 unsigned reserved:1;
2119 /** 0: Full/high speed device, 1: Low speed device */
2122 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
2125 /** Packets per frame for periodic transfers. 0 is reserved. */
2126 unsigned multicnt:2;
2128 /** Device address */
2132 * Frame to transmit periodic transaction.
2137 /** Channel disable */
2140 /** Channel enable */
2145 typedef union hcsplt_data {
2146 /** raw register data */
2149 /** register bits */
2157 /** Transaction Position */
2159 #define DWC_HCSPLIT_XACTPOS_MID 0
2160 #define DWC_HCSPLIT_XACTPOS_END 1
2161 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
2162 #define DWC_HCSPLIT_XACTPOS_ALL 3
2164 /** Do Complete Split */
2165 unsigned compsplt:1;
2168 unsigned reserved:14;
2176 * This union represents the bit fields in the Host All Interrupt
2179 typedef union hcint_data {
2180 /** raw register data */
2182 /** register bits */
2184 /** Transfer Complete */
2185 unsigned xfercomp:1;
2186 /** Channel Halted */
2190 /** STALL Response Received */
2192 /** NAK Response Received */
2194 /** ACK Response Received */
2196 /** NYET Response Received */
2198 /** Transaction Err */
2202 /** Frame Overrun */
2203 unsigned frmovrun:1;
2204 /** Data Toggle Error */
2205 unsigned datatglerr:1;
2206 /** Buffer Not Available (only for DDMA mode) */
2208 /** Exessive transaction error (only for DDMA mode) */
2209 unsigned xcs_xact:1;
2210 /** Frame List Rollover interrupt */
2211 unsigned frm_list_roll:1;
2213 unsigned reserved14_31:18;
2218 * This union represents the bit fields in the Host Channel Interrupt Mask
2219 * Register. Read the register into the <i>d32</i> member then set/clear the
2220 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
2221 * hcintmsk register.
2223 typedef union hcintmsk_data {
2224 /** raw register data */
2227 /** register bits */
2229 unsigned xfercompl:1;
2238 unsigned frmovrun:1;
2239 unsigned datatglerr:1;
2241 unsigned xcs_xact:1;
2242 unsigned frm_list_roll:1;
2243 unsigned reserved14_31:18;
2248 * This union represents the bit fields in the Host Channel Transfer Size
2249 * Register. Read the register into the <i>d32</i> member then set/clear the
2250 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
2254 typedef union hctsiz_data {
2255 /** raw register data */
2258 /** register bits */
2260 /** Total transfer size in bytes */
2261 unsigned xfersize:19;
2263 /** Data packets to transfer */
2267 * Packet ID for next data packet
2271 * 3: MDATA (non-Control), SETUP (Control)
2274 #define DWC_HCTSIZ_DATA0 0
2275 #define DWC_HCTSIZ_DATA1 2
2276 #define DWC_HCTSIZ_DATA2 1
2277 #define DWC_HCTSIZ_MDATA 3
2278 #define DWC_HCTSIZ_SETUP 3
2280 /** Do PING protocol when 1 */
2284 /** register bits */
2286 /** Scheduling information */
2289 /** Number of transfer descriptors.
2292 * 256 only for HS isochronous endpoint.
2296 /** Data packets to transfer */
2297 unsigned reserved16_28:13;
2300 * Packet ID for next data packet
2304 * 3: MDATA (non-Control)
2308 /** Do PING protocol when 1 */
2314 * This union represents the bit fields in the Host DMA Address
2315 * Register used in Descriptor DMA mode.
2317 typedef union hcdma_data {
2318 /** raw register data */
2320 /** register bits */
2322 unsigned reserved0_2:3;
2323 /** Current Transfer Descriptor. Not used for ISOC */
2325 /** Start Address of Descriptor List */
2326 unsigned dma_addr:21;
2331 * This union represents the bit fields in the DMA Descriptor
2332 * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
2333 * set/clear the bits using the <i>b</i>it elements.
2335 typedef union host_dma_desc_sts {
2336 /** raw register data */
2340 /* for non-isochronous */
2342 /** Number of bytes */
2343 unsigned n_bytes:17;
2344 /** QTD offset to jump when Short Packet received - only for IN EPs */
2345 unsigned qtd_offset:6;
2347 * Set to request the core to jump to alternate QTD if
2348 * Short Packet received - only for IN EPs
2352 * Setup Packet bit. When set indicates that buffer contains
2356 /** Interrupt On Complete */
2360 unsigned reserved27:1;
2363 #define DMA_DESC_STS_PKTERR 1
2364 unsigned reserved30:1;
2368 /* for isochronous */
2370 /** Number of bytes */
2371 unsigned n_bytes:12;
2372 unsigned reserved12_24:13;
2373 /** Interrupt On Complete */
2375 unsigned reserved26_27:2;
2378 unsigned reserved30:1;
2382 } host_dma_desc_sts_t;
2384 #define MAX_DMA_DESC_SIZE 131071
2385 #define MAX_DMA_DESC_NUM_GENERIC 64
2386 #define MAX_DMA_DESC_NUM_HS_ISOC 256
2387 #define MAX_FRLIST_EN_NUM 64
2389 * Host-mode DMA Descriptor structure
2391 * DMA Descriptor structure contains two quadlets:
2392 * Status quadlet and Data buffer pointer.
2394 typedef struct dwc_otg_host_dma_desc {
2395 /** DMA Descriptor status quadlet */
2396 host_dma_desc_sts_t status;
2397 /** DMA Descriptor data buffer pointer */
2399 } dwc_otg_host_dma_desc_t;
2401 /** OTG Host Interface Structure.
2403 * The OTG Host Interface Structure structure contains information
2404 * needed to manage the DWC_otg controller acting in host mode. It
2405 * represents the programming view of the host-specific aspects of the
2408 typedef struct dwc_otg_host_if {
2409 /** Host Global Registers starting at offset 400h.*/
2410 dwc_otg_host_global_regs_t *host_global_regs;
2411 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
2413 /** Host Port 0 Control and Status Register */
2414 volatile uint32_t *hprt0;
2415 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
2417 /** Host Channel Specific Registers at offsets 500h-5FCh. */
2418 dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
2419 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
2420 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
2422 /* Host configuration information */
2423 /** Number of Host Channels (range: 1-16) */
2424 uint8_t num_host_channels;
2425 /** Periodic EPs supported (0: no, 1: yes) */
2426 uint8_t perio_eps_supported;
2427 /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
2428 uint16_t perio_tx_fifo_size;
2430 } dwc_otg_host_if_t;
2433 * This union represents the bit fields in the Power and Clock Gating Control
2434 * Register. Read the register into the <i>d32</i> member then set/clear the
2435 * bits using the <i>b</i>it elements.
2437 typedef union pcgcctl_data {
2438 /** raw register data */
2441 /** register bits */
2444 unsigned stoppclk:1;
2446 unsigned gatehclk:1;
2449 /** Reset Power Down Modules */
2450 unsigned rstpdwnmodule:1;
2452 unsigned reserved:1;
2453 /** Enable Sleep Clock Gating (Enbl_L1Gating) */
2454 unsigned enbl_sleep_gating:1;
2455 /** PHY In Sleep (PhySleep) */
2456 unsigned phy_in_sleep:1;
2458 unsigned deep_sleep:1;
2459 unsigned resetaftsusp:1;
2460 unsigned restoremode:1;
2461 unsigned enbl_extnd_hiber:1;
2462 unsigned extnd_hiber_pwrclmp:1;
2463 unsigned extnd_hiber_switch:1;
2464 unsigned ess_reg_restored:1;
2465 unsigned prt_clk_sel:2;
2466 unsigned port_power:1;
2467 unsigned max_xcvrselect:2;
2468 unsigned max_termsel:1;
2469 unsigned mac_dev_addr:7;
2470 unsigned p2hd_dev_enum_spd:2;
2471 unsigned p2hd_prt_spd:2;
2472 unsigned if_dev_mode:1;
2477 * This union represents the bit fields in the Global Data FIFO Software
2478 * Configuration Register. Read the register into the <i>d32</i> member then
2479 * set/clear the bits using the <i>b</i>it elements.
2481 typedef union gdfifocfg_data {
2482 /* raw register data */
2484 /** register bits */
2486 /** OTG Data FIFO depth */
2487 unsigned gdfifocfg:16;
2488 /** Start address of EP info controller */
2489 unsigned epinfobase:16;
2494 * This union represents the bit fields in the Global Power Down Register
2495 * Register. Read the register into the <i>d32</i> member then set/clear the
2496 * bits using the <i>b</i>it elements.
2498 typedef union gpwrdn_data {
2499 /* raw register data */
2502 /** register bits */
2504 /** PMU Interrupt Select */
2505 unsigned pmuintsel:1;
2510 /** Power Down Clamp */
2511 unsigned pwrdnclmp:1;
2512 /** Power Down Reset */
2513 unsigned pwrdnrstn:1;
2514 /** Power Down Switch */
2515 unsigned pwrdnswtch:1;
2517 unsigned dis_vbus:1;
2518 /** Line State Change */
2519 unsigned lnstschng:1;
2520 /** Line state change mask */
2521 unsigned lnstchng_msk:1;
2522 /** Reset Detected */
2524 /** Reset Detect mask */
2525 unsigned rst_det_msk:1;
2526 /** Disconnect Detected */
2527 unsigned disconn_det:1;
2528 /** Disconnect Detect mask */
2529 unsigned disconn_det_msk:1;
2530 /** Connect Detected*/
2531 unsigned connect_det:1;
2532 /** Connect Detected Mask*/
2533 unsigned connect_det_msk:1;
2536 /** SRP Detect mask */
2537 unsigned srp_det_msk:1;
2538 /** Status Change Interrupt */
2539 unsigned sts_chngint:1;
2540 /** Status Change Interrupt Mask */
2541 unsigned sts_chngint_msk:1;
2543 unsigned linestate:2;
2544 /** Indicates current mode(status of IDDIG signal) */
2546 /** B Session Valid signal status*/
2547 unsigned bsessvld:1;
2548 /** ADP Event Detected */
2550 /** Multi Valued ID pin */
2551 unsigned mult_val_id_bc:5;
2552 /** Reserved 24_31 */
2553 unsigned reserved29_31:3;