1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
35 #include "dwc_otg_hcd.h"
36 #include "dwc_otg_regs.h"
37 #include <linux/usb.h>
38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
39 #include <../drivers/usb/core/hcd.h>
41 #include <linux/usb/hcd.h>
44 * This file contains the implementation of the HCD Interrupt handlers.
47 /** This function handles interrupts for the HCD. */
48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
52 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
53 gintsts_data_t gintsts;
55 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
58 if (dwc_otg_check_haps_status(core_if) == -1 ) {
59 DWC_WARN("HAPS is disconnected");
63 /* Exit from ISR if core is hibernated */
64 if (core_if->hibernation_suspend == 1) {
67 DWC_SPINLOCK(dwc_otg_hcd->lock);
68 /* Check if HOST Mode */
69 if (dwc_otg_is_host_mode(core_if)) {
70 gintsts.d32 = dwc_otg_read_core_intr(core_if);
72 DWC_SPINUNLOCK(dwc_otg_hcd->lock);
76 /* Don't print debug message in the interrupt handler on SOF */
78 if (gintsts.d32 != DWC_SOF_INTR_MASK)
80 DWC_DEBUGPL(DBG_HCD, "\n");
85 if (gintsts.d32 != DWC_SOF_INTR_MASK)
88 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
92 if (gintsts.b.sofintr) {
93 retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
95 if (gintsts.b.rxstsqlvl) {
97 dwc_otg_hcd_handle_rx_status_q_level_intr
100 if (gintsts.b.nptxfempty) {
102 dwc_otg_hcd_handle_np_tx_fifo_empty_intr
105 if (gintsts.b.i2cintr) {
106 /** @todo Implement i2cintr handler. */
108 if (gintsts.b.portintr) {
109 retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
111 if (gintsts.b.hcintr) {
112 retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
114 if (gintsts.b.ptxfempty) {
116 dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
121 if (gintsts.d32 != DWC_SOF_INTR_MASK)
125 "DWC OTG HCD Finished Servicing Interrupts\n");
126 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
127 DWC_READ_REG32(&global_regs->gintsts));
128 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
129 DWC_READ_REG32(&global_regs->gintmsk));
135 if (gintsts.d32 != DWC_SOF_INTR_MASK)
137 DWC_DEBUGPL(DBG_HCD, "\n");
141 DWC_SPINUNLOCK(dwc_otg_hcd->lock);
145 #ifdef DWC_TRACK_MISSED_SOFS
146 #warning Compiling code to track missed SOFs
147 #define FRAME_NUM_ARRAY_SIZE 1000
149 * This function is for debug only.
151 static inline void track_missed_sofs(uint16_t curr_frame_number)
153 static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
154 static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
155 static int frame_num_idx = 0;
156 static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
157 static int dumped_frame_num_array = 0;
159 if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
160 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
162 frame_num_array[frame_num_idx] = curr_frame_number;
163 last_frame_num_array[frame_num_idx++] = last_frame_num;
165 } else if (!dumped_frame_num_array) {
167 DWC_PRINTF("Frame Last Frame\n");
168 DWC_PRINTF("----- ----------\n");
169 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
170 DWC_PRINTF("0x%04x 0x%04x\n",
171 frame_num_array[i], last_frame_num_array[i]);
173 dumped_frame_num_array = 1;
175 last_frame_num = curr_frame_number;
180 * Handles the start-of-frame interrupt in host mode. Non-periodic
181 * transactions may be queued to the DWC_otg controller for the current
182 * (micro)frame. Periodic transactions may be queued to the controller for the
185 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
188 dwc_list_link_t *qh_entry;
190 dwc_otg_transaction_type_e tr_type;
191 gintsts_data_t gintsts = {.d32 = 0 };
194 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
197 DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
199 hcd->frame_number = hfnum.b.frnum;
202 hcd->frrem_accum += hfnum.b.frrem;
203 hcd->frrem_samples++;
206 #ifdef DWC_TRACK_MISSED_SOFS
207 track_missed_sofs(hcd->frame_number);
209 /* Determine whether any periodic QHs should be executed. */
210 qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
211 while (qh_entry != &hcd->periodic_sched_inactive) {
212 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
213 qh_entry = qh_entry->next;
214 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
216 * Move QH to the ready list to be executed next
219 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
223 tr_type = dwc_otg_hcd_select_transactions(hcd);
224 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
225 dwc_otg_hcd_queue_transactions(hcd, tr_type);
228 /* Clear interrupt */
229 gintsts.b.sofintr = 1;
230 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
235 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
236 * least one packet in the Rx FIFO. The packets are moved from the FIFO to
237 * memory if the DWC_otg controller is operating in Slave mode. */
238 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
240 host_grxsts_data_t grxsts;
243 DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
246 DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
248 hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
250 DWC_ERROR("Unable to get corresponding channel\n");
255 DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
256 DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
257 DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
259 DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
261 switch (grxsts.b.pktsts) {
262 case DWC_GRXSTS_PKTSTS_IN:
263 /* Read the data into the host buffer. */
264 if (grxsts.b.bcnt > 0) {
265 dwc_otg_read_packet(dwc_otg_hcd->core_if,
266 hc->xfer_buff, grxsts.b.bcnt);
268 /* Update the HC fields for the next packet received. */
269 hc->xfer_count += grxsts.b.bcnt;
270 hc->xfer_buff += grxsts.b.bcnt;
273 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
274 case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
275 case DWC_GRXSTS_PKTSTS_CH_HALTED:
276 /* Handled in interrupt, just ignore data */
279 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
287 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
288 * data packets may be written to the FIFO for OUT transfers. More requests
289 * may be written to the non-periodic request queue for IN transfers. This
290 * interrupt is enabled only in Slave mode. */
291 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
293 DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
294 dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
295 DWC_OTG_TRANSACTION_NON_PERIODIC);
299 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
300 * packets may be written to the FIFO for OUT transfers. More requests may be
301 * written to the periodic request queue for IN transfers. This interrupt is
302 * enabled only in Slave mode. */
303 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
305 DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
306 dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
307 DWC_OTG_TRANSACTION_PERIODIC);
311 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd);
312 /** There are multiple conditions that can cause a port interrupt. This function
313 * determines which interrupt conditions have occurred and handles them
315 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
319 hprt0_data_t hprt0_modify;
320 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
321 struct usb_bus *bus = hcd_to_bus(hcd);
323 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
324 hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
326 /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
329 hprt0_modify.b.prtena = 0;
330 hprt0_modify.b.prtconndet = 0;
331 hprt0_modify.b.prtenchng = 0;
332 hprt0_modify.b.prtovrcurrchng = 0;
334 /* Port Connect Detected
335 * Set flag and clear if detected */
336 if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
337 // Dont modify port status if we are in hibernation state
338 hprt0_modify.b.prtconndet = 1;
339 hprt0_modify.b.prtenchng = 1;
340 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
341 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
345 if (hprt0.b.prtconndet) {
346 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
347 if (dwc_otg_hcd->core_if->adp_enable &&
348 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
349 DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
350 DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
351 dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
352 /* TODO - check if this is required, as
353 * host initialization was already performed
354 * after initial ADP probing
356 /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
357 dwc_otg_core_init(dwc_otg_hcd->core_if);
358 dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
359 cil_hcd_start(dwc_otg_hcd->core_if);*/
361 hprt0_data_t hprt0_local;
362 /* check if root hub is in suspend state
363 * if root hub in suspend, resume it.
365 if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED) ) {
366 DWC_PRINTF("%s: hcd->state = %d, hcd->flags = %ld\n",
367 __func__, hcd->state, hcd->flags);
368 usb_hcd_resume_root_hub(hcd);
370 DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
371 "Port Connect Detected--\n", hprt0.d32);
372 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
373 dwc_otg_hcd->flags.b.port_connect_status = 1;
374 hprt0_modify.b.prtconndet = 1;
376 if (dwc_otg_hcd->core_if->otg_ver && (dwc_otg_hcd->core_if->test_mode == 7)) {
377 hprt0_local.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
378 hprt0_local.b.prtrst = 1;
379 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_local.d32);
381 hprt0.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
383 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
386 /* B-Device has connected, Delete the connection timer. */
387 DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
389 /* The Hub driver asserts a reset when it sees port connect
390 * status change flag */
394 /* Port Enable Changed
395 * Clear if detected - Set internal flag if disabled */
396 if (hprt0.b.prtenchng) {
397 DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
398 "Port Enable Changed--\n", hprt0.d32);
399 hprt0_modify.b.prtenchng = 1;
400 if (hprt0.b.prtena == 1) {
403 dwc_otg_core_params_t *params =
404 dwc_otg_hcd->core_if->core_params;
405 dwc_otg_core_global_regs_t *global_regs =
406 dwc_otg_hcd->core_if->core_global_regs;
407 dwc_otg_host_if_t *host_if =
408 dwc_otg_hcd->core_if->host_if;
410 /* Every time when port enables calculate
413 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
414 hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
415 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
417 /* Check if we need to adjust the PHY clock speed for
418 * low power and adjust it */
419 if (params->host_support_fs_ls_low_power) {
420 gusbcfg_data_t usbcfg;
423 DWC_READ_REG32(&global_regs->gusbcfg);
425 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
427 DWC_HPRT0_PRTSPD_FULL_SPEED) {
432 if (usbcfg.b.phylpwrclksel == 0) {
433 /* Set PHY low power clock select for FS/LS devices */
434 usbcfg.b.phylpwrclksel = 1;
436 (&global_regs->gusbcfg,
443 (&host_if->host_global_regs->hcfg);
445 if (hprt0.b.prtspd ==
446 DWC_HPRT0_PRTSPD_LOW_SPEED
447 && params->host_ls_low_power_phy_clk
449 DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
453 "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
454 if (hcfg.b.fslspclksel !=
459 (&host_if->host_global_regs->hcfg,
466 "FS_PHY programming HCFG to 48 MHz ()\n");
467 if (hcfg.b.fslspclksel !=
472 (&host_if->host_global_regs->hcfg,
481 if (usbcfg.b.phylpwrclksel == 1) {
482 usbcfg.b.phylpwrclksel = 0;
484 (&global_regs->gusbcfg,
491 DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
496 /* Port has been enabled set the reset change flag */
497 dwc_otg_hcd->flags.b.port_reset_change = 1;
500 dwc_otg_hcd->flags.b.port_enable_change = 1;
505 /** Overcurrent Change Interrupt */
506 if (hprt0.b.prtovrcurrchng) {
507 DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
508 "Port Overcurrent Changed--\n", hprt0.d32);
509 dwc_otg_hcd->flags.b.port_over_current_change = 1;
510 hprt0_modify.b.prtovrcurrchng = 1;
514 /* Clear Port Interrupts */
515 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
520 /** This interrupt indicates that one or more host channels has a pending
521 * interrupt. There are multiple conditions that can cause each host channel
522 * interrupt. This function determines which conditions have occurred for each
523 * host channel interrupt and handles them appropriately. */
524 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
530 /* Clear appropriate bits in HCINTn to clear the interrupt bit in
533 haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
535 for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
536 if (haint.b2.chint & (1 << i)) {
537 retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
545 * Gets the actual length of a transfer after the transfer halts. _halt_status
546 * holds the reason for the halt.
548 * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
549 * *short_read is set to 1 upon return if less than the requested
550 * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
551 * return. short_read may also be NULL on entry, in which case it remains
554 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
555 dwc_otg_hc_regs_t * hc_regs,
557 dwc_otg_halt_status_e halt_status,
560 hctsiz_data_t hctsiz;
563 if (short_read != NULL) {
566 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
568 if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
570 length = hc->xfer_len - hctsiz.b.xfersize;
571 if (short_read != NULL) {
572 *short_read = (hctsiz.b.xfersize != 0);
574 } else if (hc->qh->do_split) {
575 length = qtd->ssplit_out_xfer_count;
577 length = hc->xfer_len;
581 * Must use the hctsiz.pktcnt field to determine how much data
582 * has been transferred. This field reflects the number of
583 * packets that have been transferred via the USB. This is
584 * always an integral number of packets if the transfer was
585 * halted before its normal completion. (Can't use the
586 * hctsiz.xfersize field because that reflects the number of
587 * bytes transferred via the AHB, not the USB).
590 (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
597 * Updates the state of the URB after a Transfer Complete interrupt on the
598 * host channel. Updates the actual_length field of the URB based on the
599 * number of bytes transferred via the host channel. Sets the URB status
600 * if the data transfer is finished.
602 * @return 1 if the data transfer specified by the URB is completely finished,
605 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
606 dwc_otg_hc_regs_t * hc_regs,
607 dwc_otg_hcd_urb_t * urb,
615 xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
616 DWC_OTG_HC_XFER_COMPLETE,
620 /* non DWORD-aligned buffer case handling. */
621 if (hc->align_buff && xfer_length && hc->ep_is_in) {
622 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
626 urb->actual_length += xfer_length;
628 if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
629 (urb->flags & URB_SEND_ZERO_PACKET)
630 && (urb->actual_length == urb->length)
631 && !(urb->length % hc->max_packet)) {
633 } else if (short_read || urb->actual_length >= urb->length) {
640 hctsiz_data_t hctsiz;
641 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
642 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
643 __func__, (hc->ep_is_in ? "IN" : "OUT"),
645 DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
646 DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
648 DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
650 DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
652 DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
653 short_read, xfer_done);
661 * Save the starting data toggle for the next transfer. The data toggle is
662 * saved in the QH for non-control transfers and it's saved in the QTD for
665 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
666 dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
668 hctsiz_data_t hctsiz;
669 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
671 if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
672 dwc_otg_qh_t *qh = hc->qh;
673 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
674 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
676 qh->data_toggle = DWC_OTG_HC_PID_DATA1;
679 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
680 qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
682 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
688 * Updates the state of an Isochronous URB when the transfer is stopped for
689 * any reason. The fields of the current entry in the frame descriptor array
690 * are set based on the transfer state and the input _halt_status. Completes
691 * the Isochronous URB if all the URB frames have been completed.
693 * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
694 * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
696 static dwc_otg_halt_status_e
697 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
699 dwc_otg_hc_regs_t * hc_regs,
700 dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
702 dwc_otg_hcd_urb_t *urb = qtd->urb;
703 dwc_otg_halt_status_e ret_val = halt_status;
704 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
706 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
707 switch (halt_status) {
708 case DWC_OTG_HC_XFER_COMPLETE:
709 frame_desc->status = 0;
710 frame_desc->actual_length =
711 get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
713 /* non DWORD-aligned buffer case handling. */
714 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
715 dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
716 hc->qh->dw_align_buf, frame_desc->actual_length);
720 case DWC_OTG_HC_XFER_FRAME_OVERRUN:
723 frame_desc->status = -DWC_E_NO_STREAM_RES;
725 frame_desc->status = -DWC_E_COMMUNICATION;
727 frame_desc->actual_length = 0;
729 case DWC_OTG_HC_XFER_BABBLE_ERR:
731 frame_desc->status = -DWC_E_OVERFLOW;
732 /* Don't need to update actual_length in this case. */
734 case DWC_OTG_HC_XFER_XACT_ERR:
736 frame_desc->status = -DWC_E_PROTOCOL;
737 frame_desc->actual_length =
738 get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
740 /* non DWORD-aligned buffer case handling. */
741 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
742 dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
743 hc->qh->dw_align_buf, frame_desc->actual_length);
745 /* Skip whole frame */
746 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
747 hc->ep_is_in && hcd->core_if->dma_enable) {
748 qtd->complete_split = 0;
749 qtd->isoc_split_offset = 0;
754 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
757 if (++qtd->isoc_frame_index == urb->packet_count) {
759 * urb->status is not used for isoc transfers.
760 * The individual frame_desc statuses are used instead.
762 hcd->fops->complete(hcd, urb->priv, urb, 0);
763 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
765 ret_val = DWC_OTG_HC_XFER_COMPLETE;
771 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
772 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
773 * still linked to the QH, the QH is added to the end of the inactive
774 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
775 * schedule if no more QTDs are linked to the QH.
777 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
779 int continue_split = 0;
782 DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
784 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
786 if (qtd->complete_split) {
788 } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
789 qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
794 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
799 dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
803 * Releases a host channel for use by other transfers. Attempts to select and
804 * queue more transactions since at least one host channel is available.
806 * @param hcd The HCD state structure.
807 * @param hc The host channel to release.
808 * @param qtd The QTD associated with the host channel. This QTD may be freed
809 * if the transfer is complete or an error has occurred.
810 * @param halt_status Reason the channel is being released. This status
811 * determines the actions taken by this function.
813 static void release_channel(dwc_otg_hcd_t * hcd,
816 dwc_otg_halt_status_e halt_status)
818 dwc_otg_transaction_type_e tr_type;
821 DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n",
822 __func__, hc->hc_num, halt_status);
824 if(halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE){
825 if(((uint32_t) qtd & 0xf0000000)==0){
826 DWC_PRINTF("%s error: qtd %p, status %d 0!!!\n", __func__, qtd, halt_status);
830 if(((uint32_t) qtd & 0x80000000)==0){
831 DWC_PRINTF("%s error: qtd %p, status %d 1!!!\n", __func__, qtd, halt_status);
835 if(((uint32_t) qtd->urb & 0xf0000000)==0){
836 DWC_PRINTF("%s qtd %p urb %p, status %d\n", __func__, qtd, qtd->urb, halt_status);
841 switch (halt_status) {
842 case DWC_OTG_HC_XFER_URB_COMPLETE:
845 case DWC_OTG_HC_XFER_AHB_ERR:
846 case DWC_OTG_HC_XFER_STALL:
847 case DWC_OTG_HC_XFER_BABBLE_ERR:
850 case DWC_OTG_HC_XFER_XACT_ERR:
851 if (qtd->error_count >= 3) {
852 DWC_DEBUGPL(DBG_HCDV,
853 " Complete URB with transaction error\n");
855 qtd->urb->status = -DWC_E_PROTOCOL;
856 hcd->fops->complete(hcd, qtd->urb->priv,
857 qtd->urb, -DWC_E_PROTOCOL);
862 case DWC_OTG_HC_XFER_URB_DEQUEUE:
864 * The QTD has already been removed and the QH has been
865 * deactivated. Don't want to do anything except release the
866 * host channel and try to queue more transfers.
869 case DWC_OTG_HC_XFER_NO_HALT_STATUS:
872 case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
873 DWC_DEBUGPL(DBG_HCDV,
874 " Complete URB with I/O error\n");
876 qtd->urb->status = -DWC_E_IO;
877 hcd->fops->complete(hcd, qtd->urb->priv,
878 qtd->urb, -DWC_E_IO);
885 deactivate_qh(hcd, hc->qh, free_qtd);
889 * Release the host channel for use by other transfers. The cleanup
890 * function clears the channel interrupt enables and conditions, so
891 * there's no need to clear the Channel Halted interrupt separately.
893 dwc_otg_hc_cleanup(hcd->core_if, hc);
894 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
896 switch (hc->ep_type) {
897 case DWC_OTG_EP_TYPE_CONTROL:
898 case DWC_OTG_EP_TYPE_BULK:
899 hcd->non_periodic_channels--;
904 * Don't release reservations for periodic channels here.
905 * That's done when a periodic transfer is descheduled (i.e.
906 * when the QH is removed from the periodic schedule).
911 /* Try to queue more transfers now that there's a free channel. */
912 tr_type = dwc_otg_hcd_select_transactions(hcd);
913 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
914 dwc_otg_hcd_queue_transactions(hcd, tr_type);
919 * Halts a host channel. If the channel cannot be halted immediately because
920 * the request queue is full, this function ensures that the FIFO empty
921 * interrupt for the appropriate queue is enabled so that the halt request can
922 * be queued when there is space in the request queue.
924 * This function may also be called in DMA mode. In that case, the channel is
925 * simply released since the core always halts the channel automatically in
928 static void halt_channel(dwc_otg_hcd_t * hcd,
930 dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
932 if (hcd->core_if->dma_enable) {
933 release_channel(hcd, hc, qtd, halt_status);
937 /* Slave mode processing... */
938 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
940 if (hc->halt_on_queue) {
941 gintmsk_data_t gintmsk = {.d32 = 0 };
942 dwc_otg_core_global_regs_t *global_regs;
943 global_regs = hcd->core_if->core_global_regs;
945 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
946 hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
948 * Make sure the Non-periodic Tx FIFO empty interrupt
949 * is enabled so that the non-periodic schedule will
952 gintmsk.b.nptxfempty = 1;
953 DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
956 * Move the QH from the periodic queued schedule to
957 * the periodic assigned schedule. This allows the
958 * halt to be queued when the periodic schedule is
961 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
962 &hc->qh->qh_list_entry);
965 * Make sure the Periodic Tx FIFO Empty interrupt is
966 * enabled so that the periodic schedule will be
969 gintmsk.b.ptxfempty = 1;
970 DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
976 * Performs common cleanup for non-periodic transfers after a Transfer
977 * Complete interrupt. This function should be called after any endpoint type
978 * specific handling is finished to release the host channel.
980 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
982 dwc_otg_hc_regs_t * hc_regs,
984 dwc_otg_halt_status_e halt_status)
988 qtd->error_count = 0;
990 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
993 * Got a NYET on the last transaction of the transfer. This
994 * means that the endpoint should be in the PING state at the
995 * beginning of the next transfer.
997 hc->qh->ping_state = 1;
998 clear_hc_int(hc_regs, nyet);
1002 * Always halt and release the host channel to make it available for
1003 * more transfers. There may still be more phases for a control
1004 * transfer or more data packets for a bulk transfer at this point,
1005 * but the host channel is still halted. A channel will be reassigned
1006 * to the transfer when the non-periodic schedule is processed after
1007 * the channel is released. This allows transactions to be queued
1008 * properly via dwc_otg_hcd_queue_transactions, which also enables the
1009 * Tx FIFO Empty interrupt if necessary.
1013 * IN transfers in Slave mode require an explicit disable to
1014 * halt the channel. (In DMA mode, this call simply releases
1017 halt_channel(hcd, hc, qtd, halt_status);
1020 * The channel is automatically disabled by the core for OUT
1021 * transfers in Slave mode.
1023 release_channel(hcd, hc, qtd, halt_status);
1028 * Performs common cleanup for periodic transfers after a Transfer Complete
1029 * interrupt. This function should be called after any endpoint type specific
1030 * handling is finished to release the host channel.
1032 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
1034 dwc_otg_hc_regs_t * hc_regs,
1035 dwc_otg_qtd_t * qtd,
1036 dwc_otg_halt_status_e halt_status)
1038 hctsiz_data_t hctsiz;
1039 qtd->error_count = 0;
1041 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1042 if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1043 /* Core halts channel in these cases. */
1044 release_channel(hcd, hc, qtd, halt_status);
1046 /* Flush any outstanding requests from the Tx queue. */
1047 halt_channel(hcd, hc, qtd, halt_status);
1051 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
1053 dwc_otg_hc_regs_t * hc_regs,
1054 dwc_otg_qtd_t * qtd)
1057 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1058 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1060 len = get_actual_xfer_length(hc, hc_regs, qtd,
1061 DWC_OTG_HC_XFER_COMPLETE, NULL);
1064 qtd->complete_split = 0;
1065 qtd->isoc_split_offset = 0;
1068 frame_desc->actual_length += len;
1070 if (hc->align_buff && len)
1071 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1072 qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1073 qtd->isoc_split_offset += len;
1075 if (frame_desc->length == frame_desc->actual_length) {
1076 frame_desc->status = 0;
1077 qtd->isoc_frame_index++;
1078 qtd->complete_split = 0;
1079 qtd->isoc_split_offset = 0;
1082 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1083 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1084 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1086 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1089 return 1; /* Indicates that channel released */
1093 * Handles a host channel Transfer Complete interrupt. This handler may be
1094 * called in either DMA mode or Slave mode.
1096 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
1098 dwc_otg_hc_regs_t * hc_regs,
1099 dwc_otg_qtd_t * qtd)
1102 dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1103 dwc_otg_hcd_urb_t *urb;
1106 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1107 "Transfer Complete--\n", hc->hc_num);
1109 if(((uint32_t) qtd & 0xf0000000)==0){
1110 DWC_PRINTF("%s qtd %p\n", __func__, qtd);
1111 release_channel(hcd, hc, qtd, hc->halt_status);
1116 if(((uint32_t)urb & 0xf0000000)==0){
1117 DWC_PRINTF("%s qtd %p, urb %p\n", __func__, qtd, urb);
1118 release_channel(hcd, hc, qtd, hc->halt_status);
1122 pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1124 if (hcd->core_if->dma_desc_enable) {
1125 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1126 if (pipe_type == UE_ISOCHRONOUS) {
1127 /* Do not disable the interrupt, just clear it */
1128 clear_hc_int(hc_regs, xfercomp);
1131 goto handle_xfercomp_done;
1135 * Handle xfer complete on CSPLIT.
1138 if (hc->qh->do_split) {
1139 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1140 && hcd->core_if->dma_enable) {
1141 if (qtd->complete_split
1142 && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1144 goto handle_xfercomp_done;
1146 qtd->complete_split = 0;
1150 /* Update the QTD and URB states. */
1151 switch (pipe_type) {
1153 switch (qtd->control_phase) {
1154 case DWC_OTG_CONTROL_SETUP:
1155 if (urb->length > 0) {
1156 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1158 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1160 DWC_DEBUGPL(DBG_HCDV,
1161 " Control setup transaction done\n");
1162 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1164 case DWC_OTG_CONTROL_DATA:{
1166 update_urb_state_xfer_comp(hc, hc_regs, urb,
1168 if (urb_xfer_done) {
1169 qtd->control_phase =
1170 DWC_OTG_CONTROL_STATUS;
1171 DWC_DEBUGPL(DBG_HCDV,
1172 " Control data transfer done\n");
1174 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1176 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1179 case DWC_OTG_CONTROL_STATUS:
1180 DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
1181 if (urb->status == -DWC_E_IN_PROGRESS) {
1184 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1185 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1189 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1192 DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
1194 update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1195 if (urb_xfer_done) {
1196 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1197 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1199 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1202 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1203 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1206 DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
1208 update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1211 * Interrupt URB is done on the first transfer complete
1214 if (urb_xfer_done) {
1215 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1216 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1218 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1221 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1222 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1224 case UE_ISOCHRONOUS:
1225 DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
1226 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1228 update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1229 DWC_OTG_HC_XFER_COMPLETE);
1231 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1235 handle_xfercomp_done:
1236 disable_hc_int(hc_regs, xfercompl);
1242 * Handles a host channel STALL interrupt. This handler may be called in
1243 * either DMA mode or Slave mode.
1245 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
1247 dwc_otg_hc_regs_t * hc_regs,
1248 dwc_otg_qtd_t * qtd)
1250 dwc_otg_hcd_urb_t *urb = qtd->urb;
1251 int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1253 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1254 "STALL Received--\n", hc->hc_num);
1256 if (hcd->core_if->dma_desc_enable) {
1257 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
1258 goto handle_stall_done;
1261 if (pipe_type == UE_CONTROL) {
1262 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1265 if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1266 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1268 * USB protocol requires resetting the data toggle for bulk
1269 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1270 * setup command is issued to the endpoint. Anticipate the
1271 * CLEAR_FEATURE command since a STALL has occurred and reset
1272 * the data toggle now.
1274 hc->qh->data_toggle = 0;
1277 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1280 disable_hc_int(hc_regs, stall);
1286 * Updates the state of the URB when a transfer has been stopped due to an
1287 * abnormal condition before the transfer completes. Modifies the
1288 * actual_length field of the URB to reflect the number of bytes that have
1289 * actually been transferred via the host channel.
1291 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
1292 dwc_otg_hc_regs_t * hc_regs,
1293 dwc_otg_hcd_urb_t * urb,
1294 dwc_otg_qtd_t * qtd,
1295 dwc_otg_halt_status_e halt_status)
1297 uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1299 /* non DWORD-aligned buffer case handling. */
1300 if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1301 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1305 urb->actual_length += bytes_transferred;
1309 hctsiz_data_t hctsiz;
1310 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1311 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1312 __func__, (hc->ep_is_in ? "IN" : "OUT"),
1314 DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
1315 hc->start_pkt_count);
1316 DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1317 DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
1318 DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
1320 DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
1321 urb->actual_length);
1322 DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
1329 * Handles a host channel NAK interrupt. This handler may be called in either
1330 * DMA mode or Slave mode.
1332 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
1334 dwc_otg_hc_regs_t * hc_regs,
1335 dwc_otg_qtd_t * qtd)
1337 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1338 "NAK Received--\n", hc->hc_num);
1341 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1342 * interrupt. Re-start the SSPLIT transfer.
1345 if (hc->complete_split) {
1346 qtd->error_count = 0;
1348 qtd->complete_split = 0;
1349 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1350 goto handle_nak_done;
1353 switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1356 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1358 * NAK interrupts are enabled on bulk/control IN
1359 * transfers in DMA mode for the sole purpose of
1360 * resetting the error count after a transaction error
1361 * occurs. The core will continue transferring data.
1363 qtd->error_count = 0;
1364 goto handle_nak_done;
1368 * NAK interrupts normally occur during OUT transfers in DMA
1369 * or Slave mode. For IN transfers, more requests will be
1370 * queued as request queue space is available.
1372 qtd->error_count = 0;
1374 if (!hc->qh->ping_state) {
1375 update_urb_state_xfer_intr(hc, hc_regs,
1377 DWC_OTG_HC_XFER_NAK);
1378 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1380 if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1381 hc->qh->ping_state = 1;
1385 * Halt the channel so the transfer can be re-started from
1386 * the appropriate point or the PING protocol will
1389 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1392 qtd->error_count = 0;
1393 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1395 case UE_ISOCHRONOUS:
1396 /* Should never get called for isochronous transfers. */
1397 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1402 disable_hc_int(hc_regs, nak);
1408 * Handles a host channel ACK interrupt. This interrupt is enabled when
1409 * performing the PING protocol in Slave mode, when errors occur during
1410 * either Slave mode or DMA mode, and during Start Split transactions.
1412 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
1414 dwc_otg_hc_regs_t * hc_regs,
1415 dwc_otg_qtd_t * qtd)
1417 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1418 "ACK Received--\n", hc->hc_num);
1422 * Handle ACK on SSPLIT.
1423 * ACK should not occur in CSPLIT.
1425 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1426 qtd->ssplit_out_xfer_count = hc->xfer_len;
1428 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1429 /* Don't need complete for isochronous out transfers. */
1430 qtd->complete_split = 1;
1434 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1435 switch (hc->xact_pos) {
1436 case DWC_HCSPLIT_XACTPOS_ALL:
1438 case DWC_HCSPLIT_XACTPOS_END:
1439 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1440 qtd->isoc_split_offset = 0;
1442 case DWC_HCSPLIT_XACTPOS_BEGIN:
1443 case DWC_HCSPLIT_XACTPOS_MID:
1445 * For BEGIN or MID, calculate the length for
1446 * the next microframe to determine the correct
1447 * SSPLIT token, either MID or END.
1450 struct dwc_otg_hcd_iso_packet_desc
1455 iso_descs[qtd->isoc_frame_index];
1456 qtd->isoc_split_offset += 188;
1458 if ((frame_desc->length -
1459 qtd->isoc_split_offset) <= 188) {
1460 qtd->isoc_split_pos =
1461 DWC_HCSPLIT_XACTPOS_END;
1463 qtd->isoc_split_pos =
1464 DWC_HCSPLIT_XACTPOS_MID;
1471 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1474 qtd->error_count = 0;
1476 if (hc->qh->ping_state) {
1477 hc->qh->ping_state = 0;
1479 * Halt the channel so the transfer can be re-started
1480 * from the appropriate point. This only happens in
1481 * Slave mode. In DMA mode, the ping_state is cleared
1482 * when the transfer is started because the core
1483 * automatically executes the PING, then the transfer.
1485 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1490 * If the ACK occurred when _not_ in the PING state, let the channel
1491 * continue transferring data after clearing the error count.
1494 disable_hc_int(hc_regs, ack);
1500 * Handles a host channel NYET interrupt. This interrupt should only occur on
1501 * Bulk and Control OUT endpoints and for complete split transactions. If a
1502 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1503 * handled in the xfercomp interrupt handler, not here. This handler may be
1504 * called in either DMA mode or Slave mode.
1506 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
1508 dwc_otg_hc_regs_t * hc_regs,
1509 dwc_otg_qtd_t * qtd)
1511 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1512 "NYET Received--\n", hc->hc_num);
1516 * re-do the CSPLIT immediately on non-periodic
1518 if (hc->do_split && hc->complete_split) {
1519 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1520 && hcd->core_if->dma_enable) {
1521 qtd->complete_split = 0;
1522 qtd->isoc_split_offset = 0;
1523 if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1524 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1525 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1528 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1529 goto handle_nyet_done;
1532 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1533 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1534 int frnum = dwc_otg_hcd_get_frame_number(hcd);
1536 if (dwc_full_frame_num(frnum) !=
1537 dwc_full_frame_num(hc->qh->sched_frame)) {
1539 * No longer in the same full speed frame.
1540 * Treat this as a transaction error.
1543 /** @todo Fix system performance so this can
1544 * be treated as an error. Right now complete
1545 * splits cannot be scheduled precisely enough
1546 * due to other system activity, so this error
1547 * occurs regularly in Slave mode.
1551 qtd->complete_split = 0;
1552 halt_channel(hcd, hc, qtd,
1553 DWC_OTG_HC_XFER_XACT_ERR);
1554 /** @todo add support for isoc release */
1555 goto handle_nyet_done;
1559 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1560 goto handle_nyet_done;
1563 hc->qh->ping_state = 1;
1564 qtd->error_count = 0;
1566 update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1567 DWC_OTG_HC_XFER_NYET);
1568 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1571 * Halt the channel and re-start the transfer so the PING
1572 * protocol will start.
1574 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1577 disable_hc_int(hc_regs, nyet);
1582 * Handles a host channel babble interrupt. This handler may be called in
1583 * either DMA mode or Slave mode.
1585 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
1587 dwc_otg_hc_regs_t * hc_regs,
1588 dwc_otg_qtd_t * qtd)
1590 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1591 "Babble Error--\n", hc->hc_num);
1593 if (hcd->core_if->dma_desc_enable) {
1594 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1595 DWC_OTG_HC_XFER_BABBLE_ERR);
1596 goto handle_babble_done;
1599 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1600 hcd->fops->complete(hcd, qtd->urb->priv,
1601 qtd->urb, -DWC_E_OVERFLOW);
1602 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1604 dwc_otg_halt_status_e halt_status;
1605 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1606 DWC_OTG_HC_XFER_BABBLE_ERR);
1607 halt_channel(hcd, hc, qtd, halt_status);
1611 disable_hc_int(hc_regs, bblerr);
1616 * Handles a host channel AHB error interrupt. This handler is only called in
1619 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
1621 dwc_otg_hc_regs_t * hc_regs,
1622 dwc_otg_qtd_t * qtd)
1624 hcchar_data_t hcchar;
1625 hcsplt_data_t hcsplt;
1626 hctsiz_data_t hctsiz;
1628 char *pipetype, *speed;
1630 dwc_otg_hcd_urb_t *urb = qtd->urb;
1632 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1633 "AHB Error--\n", hc->hc_num);
1635 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1636 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1637 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1638 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1640 DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1641 DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1642 DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1643 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1644 DWC_ERROR(" Device address: %d\n",
1645 dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1646 DWC_ERROR(" Endpoint: %d, %s\n",
1647 dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1648 (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1650 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1652 pipetype = "CONTROL";
1658 pipetype = "INTERRUPT";
1660 case UE_ISOCHRONOUS:
1661 pipetype = "ISOCHRONOUS";
1664 pipetype = "UNKNOWN";
1668 DWC_ERROR(" Endpoint type: %s\n", pipetype);
1670 switch (hc->speed) {
1671 case DWC_OTG_EP_SPEED_HIGH:
1674 case DWC_OTG_EP_SPEED_FULL:
1677 case DWC_OTG_EP_SPEED_LOW:
1685 DWC_ERROR(" Speed: %s\n", speed);
1687 DWC_ERROR(" Max packet size: %d\n",
1688 dwc_otg_hcd_get_mps(&urb->pipe_info));
1689 DWC_ERROR(" Data buffer length: %d\n", urb->length);
1690 DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
1691 urb->buf, (void *)urb->dma);
1692 DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
1693 urb->setup_packet, (void *)urb->setup_dma);
1694 DWC_ERROR(" Interval: %d\n", urb->interval);
1696 /* Core haltes the channel for Descriptor DMA mode */
1697 if (hcd->core_if->dma_desc_enable) {
1698 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1699 DWC_OTG_HC_XFER_AHB_ERR);
1700 goto handle_ahberr_done;
1703 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1706 * Force a channel halt. Don't call halt_channel because that won't
1707 * write to the HCCHARn register in DMA mode to force the halt.
1709 dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1711 disable_hc_int(hc_regs, ahberr);
1716 * Handles a host channel transaction error interrupt. This handler may be
1717 * called in either DMA mode or Slave mode.
1719 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
1721 dwc_otg_hc_regs_t * hc_regs,
1722 dwc_otg_qtd_t * qtd)
1724 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1725 "Transaction Error--\n", hc->hc_num);
1727 if (hcd->core_if->dma_desc_enable) {
1728 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1729 DWC_OTG_HC_XFER_XACT_ERR);
1730 goto handle_xacterr_done;
1733 switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1737 if (!hc->qh->ping_state) {
1739 update_urb_state_xfer_intr(hc, hc_regs,
1741 DWC_OTG_HC_XFER_XACT_ERR);
1742 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1743 if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1744 hc->qh->ping_state = 1;
1749 * Halt the channel so the transfer can be re-started from
1750 * the appropriate point or the PING protocol will start.
1752 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1756 if (hc->do_split && hc->complete_split) {
1757 qtd->complete_split = 0;
1759 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1761 case UE_ISOCHRONOUS:
1763 dwc_otg_halt_status_e halt_status;
1765 update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1766 DWC_OTG_HC_XFER_XACT_ERR);
1768 halt_channel(hcd, hc, qtd, halt_status);
1772 handle_xacterr_done:
1773 disable_hc_int(hc_regs, xacterr);
1779 * Handles a host channel frame overrun interrupt. This handler may be called
1780 * in either DMA mode or Slave mode.
1782 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
1784 dwc_otg_hc_regs_t * hc_regs,
1785 dwc_otg_qtd_t * qtd)
1787 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1788 "Frame Overrun--\n", hc->hc_num);
1790 switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1795 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1797 case UE_ISOCHRONOUS:
1799 dwc_otg_halt_status_e halt_status;
1801 update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1802 DWC_OTG_HC_XFER_FRAME_OVERRUN);
1804 halt_channel(hcd, hc, qtd, halt_status);
1809 disable_hc_int(hc_regs, frmovrun);
1815 * Handles a host channel data toggle error interrupt. This handler may be
1816 * called in either DMA mode or Slave mode.
1818 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
1820 dwc_otg_hc_regs_t * hc_regs,
1821 dwc_otg_qtd_t * qtd)
1823 DWC_ERROR("--Host Channel %d Interrupt: "
1824 "Data Toggle Error--\n", hc->hc_num);
1826 qtd->error_count += 3;//Complete the error URB immediately
1828 DWC_ERROR("Data Toggle Error on OUT transfer,"
1829 "channel %d\n", hc->hc_num);
1831 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1832 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1833 clear_hc_int(hc_regs,chhltd);
1840 * This function is for debug only. It checks that a valid halt status is set
1841 * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1842 * taken and a warning is issued.
1843 * @return 1 if halt status is ok, 0 otherwise.
1845 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
1847 dwc_otg_hc_regs_t * hc_regs,
1848 dwc_otg_qtd_t * qtd)
1850 hcchar_data_t hcchar;
1851 hctsiz_data_t hctsiz;
1853 hcintmsk_data_t hcintmsk;
1854 hcsplt_data_t hcsplt;
1856 if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1858 * This code is here only as a check. This condition should
1859 * never happen. Ignore the halt if it does occur.
1861 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1862 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1863 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1864 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1865 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1867 ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1868 "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1869 "hcint 0x%08x, hcintmsk 0x%08x, "
1870 "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1871 hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1872 hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1874 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1875 __func__, hc->hc_num);
1877 clear_hc_int(hc_regs, chhltd);
1882 * This code is here only as a check. hcchar.chdis should
1883 * never be set when the halt interrupt occurs. Halt the
1884 * channel again if it does occur.
1886 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1887 if (hcchar.b.chdis) {
1888 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1889 "hcchar 0x%08x, trying to halt again\n",
1890 __func__, hcchar.d32);
1891 clear_hc_int(hc_regs, chhltd);
1892 hc->halt_pending = 0;
1893 halt_channel(hcd, hc, qtd, hc->halt_status);
1902 * Handles a host Channel Halted interrupt in DMA mode. This handler
1903 * determines the reason the channel halted and proceeds accordingly.
1905 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
1907 dwc_otg_hc_regs_t * hc_regs,
1908 dwc_otg_qtd_t * qtd)
1911 hcintmsk_data_t hcintmsk;
1912 int out_nak_enh = 0;
1914 /* For core with OUT NAK enhancement, the flow for high-
1915 * speed CONTROL/BULK OUT is handled a little differently.
1917 if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1918 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1919 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1920 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1925 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1926 (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1927 && !hcd->core_if->dma_desc_enable)) {
1929 * Just release the channel. A dequeue can happen on a
1930 * transfer timeout. In the case of an AHB Error, the channel
1931 * was forced to halt because there's no way to gracefully
1934 if (hcd->core_if->dma_desc_enable)
1935 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1938 release_channel(hcd, hc, qtd, hc->halt_status);
1942 /* Read the HCINTn register to determine the cause for the halt. */
1943 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1944 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1946 if (hcint.b.xfercomp) {
1947 /** @todo This is here because of a possible hardware bug. Spec
1948 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1949 * interrupt w/ACK bit set should occur, but I only see the
1950 * XFERCOMP bit, even with it masked out. This is a workaround
1951 * for that behavior. Should fix this when hardware is fixed.
1953 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1954 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1956 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1957 } else if (hcint.b.stall) {
1958 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1959 } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1961 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1962 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1963 qtd->error_count = 0;
1965 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1970 * Must handle xacterr before nak or ack. Could get a xacterr
1971 * at the same time as either of these on a BULK/CONTROL OUT
1972 * that started with a PING. The xacterr takes precedence.
1974 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1975 } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1976 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1977 } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1978 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1979 } else if (hcint.b.bblerr) {
1980 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1981 } else if (hcint.b.frmovrun) {
1982 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1983 } else if(hcint.b.datatglerr){
1984 handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
1986 else if (!out_nak_enh) {
1989 * Must handle nyet before nak or ack. Could get a nyet at the
1990 * same time as either of those on a BULK/CONTROL OUT that
1991 * started with a PING. The nyet takes precedence.
1993 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1994 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1996 * If nak is not masked, it's because a non-split IN transfer
1997 * is in an error state. In that case, the nak is handled by
1998 * the nak interrupt handler, not here. Handle nak here for
1999 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2000 * rewinding the buffer pointer.
2002 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2003 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2005 * If ack is not masked, it's because a non-split IN transfer
2006 * is in an error state. In that case, the ack is handled by
2007 * the ack interrupt handler, not here. Handle ack here for
2008 * split transfers. Start splits halt on ACK.
2010 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2012 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2013 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2015 * A periodic transfer halted with no other channel
2016 * interrupts set. Assume it was halted by the core
2017 * because it could not be completed in its scheduled
2022 ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2023 __func__, hc->hc_num);
2025 halt_channel(hcd, hc, qtd,
2026 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2029 ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2030 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2031 __func__, hc->hc_num, hcint.d32,
2032 DWC_READ_REG32(&hcd->
2033 core_if->core_global_regs->
2035 clear_hc_int(hc_regs,chhltd);
2040 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2042 if(!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
2043 clear_hc_int(hc_regs,chhltd);
2048 * Handles a host channel Channel Halted interrupt.
2050 * In slave mode, this handler is called only when the driver specifically
2051 * requests a halt. This occurs during handling other host channel interrupts
2052 * (e.g. nak, xacterr, stall, nyet, etc.).
2054 * In DMA mode, this is the interrupt that occurs when the core has finished
2055 * processing a transfer on a channel. Other host channel interrupts (except
2056 * ahberr) are disabled in DMA mode.
2058 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
2060 dwc_otg_hc_regs_t * hc_regs,
2061 dwc_otg_qtd_t * qtd)
2063 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2064 "Channel Halted--\n", hc->hc_num);
2066 if (hcd->core_if->dma_enable) {
2067 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2070 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2074 release_channel(hcd, hc, qtd, hc->halt_status);
2080 /** Handles interrupt for a specific Host Channel */
2081 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
2085 hcintmsk_data_t hcintmsk;
2087 dwc_otg_hc_regs_t *hc_regs;
2090 DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2092 hc = dwc_otg_hcd->hc_ptr_array[num];
2093 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2094 qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2096 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2097 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2098 DWC_DEBUGPL(DBG_HCDV,
2099 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2100 hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2101 hcint.d32 = hcint.d32 & hcintmsk.d32;
2103 if (!dwc_otg_hcd->core_if->dma_enable) {
2104 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2109 if (hcint.b.chhltd) {
2110 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2112 if (hcint.b.xfercomp) {
2114 handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2116 * If NYET occurred at same time as Xfer Complete, the NYET is
2117 * handled by the Xfer Complete interrupt handler. Don't want
2118 * to call the NYET interrupt handler in this case.
2122 if (hcint.b.ahberr) {
2123 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2125 if (hcint.b.stall) {
2126 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2129 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2133 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2136 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2138 if (hcint.b.xacterr) {
2139 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2141 if (hcint.b.bblerr) {
2142 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2144 if (hcint.b.frmovrun) {
2146 handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2148 if (hcint.b.datatglerr) {
2150 handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2156 #endif /* DWC_DEVICE_ONLY */