drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
  39 #include <../drivers/usb/core/hcd.h>
  40 #else
  41 #include <linux/usb/hcd.h>
  42 #endif
  43 /** @file
  44  * This file contains the implementation of the HCD Interrupt handlers.
  45  */
  46
  47 /** This function handles interrupts for the HCD. */
  48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
  49 {
  50         int retval = 0;
  51         dwc_irqflags_t flags;
  52
  53         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  54         gintsts_data_t gintsts;
  55 #ifdef DEBUG
  56         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  57 #endif
  58
  59         if (dwc_otg_check_haps_status(core_if) == -1 ) {
  60                 DWC_WARN("HAPS is disconnected");
  61                 return retval;
  62         }
  63
  64         /* Exit from ISR if core is hibernated */
  65         if (core_if->hibernation_suspend == 1) {
  66                 return retval;
  67         }
  68         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
  69         /* Check if HOST Mode */
  70         if (dwc_otg_is_host_mode(core_if)) {
  71                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  72                 if (!gintsts.d32) {
  73                         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
  74                         return 0;
  75                 }
  76 #ifdef DEBUG
  77                 /* Don't print debug message in the interrupt handler on SOF */
  78 #ifndef DEBUG_SOF
  79                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  80 #endif
  81                         DWC_DEBUGPL(DBG_HCD, "\n");
  82 #endif
  83
  84 #ifdef DEBUG
  85 #ifndef DEBUG_SOF
  86                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  87 #endif
  88                         DWC_DEBUGPL(DBG_HCD,
  89                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  90                                     gintsts.d32);
  91 #endif
  92
  93                 if (gintsts.b.sofintr) {
  94                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  95                 }
  96                 if (gintsts.b.rxstsqlvl) {
  97                         retval |=
  98                             dwc_otg_hcd_handle_rx_status_q_level_intr
  99                             (dwc_otg_hcd);
 100                 }
 101                 if (gintsts.b.nptxfempty) {
 102                         retval |=
 103                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 104                             (dwc_otg_hcd);
 105                 }
 106                 if (gintsts.b.i2cintr) {
 107                         /** @todo Implement i2cintr handler. */
 108                 }
 109                 if (gintsts.b.portintr) {
 110                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 111                 }
 112                 if (gintsts.b.hcintr) {
 113                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 114                 }
 115                 if (gintsts.b.ptxfempty) {
 116                         retval |=
 117                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 118                             (dwc_otg_hcd);
 119                 }
 120 #ifdef DEBUG
 121 #ifndef DEBUG_SOF
 122                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 123 #endif
 124                 {
 125                         DWC_DEBUGPL(DBG_HCD,
 126                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 127                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 128                                     DWC_READ_REG32(&global_regs->gintsts));
 129                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 130                                     DWC_READ_REG32(&global_regs->gintmsk));
 131                 }
 132 #endif
 133
 134 #ifdef DEBUG
 135 #ifndef DEBUG_SOF
 136                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 137 #endif
 138                         DWC_DEBUGPL(DBG_HCD, "\n");
 139 #endif
 140
 141         }
 142         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
 143         return retval;
 144 }
 145
 146 #ifdef DWC_TRACK_MISSED_SOFS
 147 #warning Compiling code to track missed SOFs
 148 #define FRAME_NUM_ARRAY_SIZE 1000
 149 /**
 150  * This function is for debug only.
 151  */
 152 static inline void track_missed_sofs(uint16_t curr_frame_number)
 153 {
 154         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 155         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 156         static int frame_num_idx = 0;
 157         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 158         static int dumped_frame_num_array = 0;
 159
 160         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 161                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 162                     curr_frame_number) {
 163                         frame_num_array[frame_num_idx] = curr_frame_number;
 164                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 165                 }
 166         } else if (!dumped_frame_num_array) {
 167                 int i;
 168                 DWC_PRINTF("Frame     Last Frame\n");
 169                 DWC_PRINTF("-----     ----------\n");
 170                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 171                         DWC_PRINTF("0x%04x    0x%04x\n",
 172                                    frame_num_array[i], last_frame_num_array[i]);
 173                 }
 174                 dumped_frame_num_array = 1;
 175         }
 176         last_frame_num = curr_frame_number;
 177 }
 178 #endif
 179
 180 /**
 181  * Handles the start-of-frame interrupt in host mode. Non-periodic
 182  * transactions may be queued to the DWC_otg controller for the current
 183  * (micro)frame. Periodic transactions may be queued to the controller for the
 184  * next (micro)frame.
 185  */
 186 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
 187 {
 188         hfnum_data_t hfnum;
 189         dwc_list_link_t *qh_entry;
 190         dwc_otg_qh_t *qh;
 191         dwc_otg_transaction_type_e tr_type;
 192         gintsts_data_t gintsts = {.d32 = 0 };
 193
 194         hfnum.d32 =
 195             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 196
 197 #ifdef DEBUG_SOF
 198         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 199 #endif
 200         hcd->frame_number = hfnum.b.frnum;
 201
 202 #ifdef DEBUG
 203         hcd->frrem_accum += hfnum.b.frrem;
 204         hcd->frrem_samples++;
 205 #endif
 206
 207 #ifdef DWC_TRACK_MISSED_SOFS
 208         track_missed_sofs(hcd->frame_number);
 209 #endif
 210         /* Determine whether any periodic QHs should be executed. */
 211         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 212         while (qh_entry != &hcd->periodic_sched_inactive) {
 213                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 214                 qh_entry = qh_entry->next;
 215                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 216                         /*
 217                          * Move QH to the ready list to be executed next
 218                          * (micro)frame.
 219                          */
 220                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 221                                            &qh->qh_list_entry);
 222                 }
 223         }
 224         tr_type = dwc_otg_hcd_select_transactions(hcd);
 225         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 226                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 227         }
 228
 229         /* Clear interrupt */
 230         gintsts.b.sofintr = 1;
 231         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 232
 233         return 1;
 234 }
 235
 236 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 237  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 238  * memory if the DWC_otg controller is operating in Slave mode. */
 239 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 240 {
 241         host_grxsts_data_t grxsts;
 242         dwc_hc_t *hc = NULL;
 243
 244         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 245
 246         grxsts.d32 =
 247             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 248
 249         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 250         if (!hc) {
 251                 DWC_ERROR("Unable to get corresponding channel\n");
 252                 return 0;
 253         }
 254
 255         /* Packet Status */
 256         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 257         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 258         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 259                     hc->data_pid_start);
 260         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 261
 262         switch (grxsts.b.pktsts) {
 263         case DWC_GRXSTS_PKTSTS_IN:
 264                 /* Read the data into the host buffer. */
 265                 if (grxsts.b.bcnt > 0) {
 266                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 267                                             hc->xfer_buff, grxsts.b.bcnt);
 268
 269                         /* Update the HC fields for the next packet received. */
 270                         hc->xfer_count += grxsts.b.bcnt;
 271                         hc->xfer_buff += grxsts.b.bcnt;
 272                 }
 273
 274         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 275         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 276         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 277                 /* Handled in interrupt, just ignore data */
 278                 break;
 279         default:
 280                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 281                           grxsts.b.pktsts);
 282                 break;
 283         }
 284
 285         return 1;
 286 }
 287
 288 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 289  * data packets may be written to the FIFO for OUT transfers. More requests
 290  * may be written to the non-periodic request queue for IN transfers. This
 291  * interrupt is enabled only in Slave mode. */
 292 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 293 {
 294         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 295         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 296                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 297         return 1;
 298 }
 299
 300 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 301  * packets may be written to the FIFO for OUT transfers. More requests may be
 302  * written to the periodic request queue for IN transfers. This interrupt is
 303  * enabled only in Slave mode. */
 304 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 305 {
 306         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 307         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 308                                        DWC_OTG_TRANSACTION_PERIODIC);
 309         return 1;
 310 }
 311
 312 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd);
 313 /** There are multiple conditions that can cause a port interrupt. This function
 314  * determines which interrupt conditions have occurred and handles them
 315  * appropriately. */
 316 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 317 {
 318         int retval = 0;
 319         hprt0_data_t hprt0;
 320         hprt0_data_t hprt0_modify;
 321         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 322         struct usb_bus *bus = hcd_to_bus(hcd);
 323
 324         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 325         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 326
 327         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 328          * GINTSTS */
 329
 330         hprt0_modify.b.prtena = 0;
 331         hprt0_modify.b.prtconndet = 0;
 332         hprt0_modify.b.prtenchng = 0;
 333         hprt0_modify.b.prtovrcurrchng = 0;
 334
 335         /* Port Connect Detected
 336          * Set flag and clear if detected */
 337         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 338                 // Dont modify port status if we are in hibernation state
 339                 hprt0_modify.b.prtconndet = 1;
 340                 hprt0_modify.b.prtenchng = 1;
 341                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 342                 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 343                 return retval;
 344         }
 345
 346         if (hprt0.b.prtconndet) {
 347                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 348                 if (dwc_otg_hcd->core_if->adp_enable &&
 349                                 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 350                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 351                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
 352                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 353                         /* TODO - check if this is required, as
 354                          * host initialization was already performed
 355                          * after initial ADP probing
 356                          */
 357                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 358                         dwc_otg_core_init(dwc_otg_hcd->core_if);
 359                         dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 360                         cil_hcd_start(dwc_otg_hcd->core_if);*/
 361                 } else {
 362                         hprt0_data_t hprt0_local;
 363                         /* check if root hub is in suspend state
 364                          * if root hub in suspend, resume it.
 365                          */
 366                         if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED) ) {
 367                                 DWC_PRINTF("%s: hcd->state = %d, hcd->flags = %ld\n",
 368                                                 __func__, hcd->state, hcd->flags);
 369                                 usb_hcd_resume_root_hub(hcd);
 370                         }
 371                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 372                                     "Port Connect Detected--\n", hprt0.d32);
 373                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 374                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 375                         hprt0_modify.b.prtconndet = 1;
 376                         /* PET testing */
 377                         if (dwc_otg_hcd->core_if->otg_ver && (dwc_otg_hcd->core_if->test_mode == 7)) {
 378                                 hprt0_local.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 379                                 hprt0_local.b.prtrst = 1;
 380                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_local.d32);
 381                                 dwc_mdelay(60);
 382                                 hprt0.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 383                                 hprt0.b.prtrst = 0;
 384                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 385                         }
 386
 387                         /* B-Device has connected, Delete the connection timer. */
 388                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 389                 }
 390                 /* The Hub driver asserts a reset when it sees port connect
 391                  * status change flag */
 392                 retval |= 1;
 393         }
 394
 395         /* Port Enable Changed
 396          * Clear if detected - Set internal flag if disabled */
 397         if (hprt0.b.prtenchng) {
 398                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 399                             "Port Enable Changed--\n", hprt0.d32);
 400                 hprt0_modify.b.prtenchng = 1;
 401                 if (hprt0.b.prtena == 1) {
 402                         hfir_data_t hfir;
 403                         int do_reset = 0;
 404                         dwc_otg_core_params_t *params =
 405                             dwc_otg_hcd->core_if->core_params;
 406                         dwc_otg_core_global_regs_t *global_regs =
 407                             dwc_otg_hcd->core_if->core_global_regs;
 408                         dwc_otg_host_if_t *host_if =
 409                             dwc_otg_hcd->core_if->host_if;
 410
 411                         /* Every time when port enables calculate
 412                          * HFIR.FrInterval
 413                          */
 414                         hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
 415                         hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
 416                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
 417
 418                         /* Check if we need to adjust the PHY clock speed for
 419                          * low power and adjust it */
 420                         if (params->host_support_fs_ls_low_power) {
 421                                 gusbcfg_data_t usbcfg;
 422
 423                                 usbcfg.d32 =
 424                                     DWC_READ_REG32(&global_regs->gusbcfg);
 425
 426                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 427                                     || hprt0.b.prtspd ==
 428                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 429                                         /*
 430                                          * Low power
 431                                          */
 432                                         hcfg_data_t hcfg;
 433                                         if (usbcfg.b.phylpwrclksel == 0) {
 434                                                 /* Set PHY low power clock select for FS/LS devices */
 435                                                 usbcfg.b.phylpwrclksel = 1;
 436                                                 DWC_WRITE_REG32
 437                                                     (&global_regs->gusbcfg,
 438                                                      usbcfg.d32);
 439                                                 do_reset = 1;
 440                                         }
 441
 442                                         hcfg.d32 =
 443                                             DWC_READ_REG32
 444                                             (&host_if->host_global_regs->hcfg);
 445
 446                                         if (hprt0.b.prtspd ==
 447                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 448                                             && params->host_ls_low_power_phy_clk
 449                                             ==
 450                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
 451                                         {
 452                                                 /* 6 MHZ */
 453                                                 DWC_DEBUGPL(DBG_CIL,
 454                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 455                                                 if (hcfg.b.fslspclksel !=
 456                                                     DWC_HCFG_6_MHZ) {
 457                                                         hcfg.b.fslspclksel =
 458                                                             DWC_HCFG_6_MHZ;
 459                                                         DWC_WRITE_REG32
 460                                                             (&host_if->host_global_regs->hcfg,
 461                                                              hcfg.d32);
 462                                                         do_reset = 1;
 463                                                 }
 464                                         } else {
 465                                                 /* 48 MHZ */
 466                                                 DWC_DEBUGPL(DBG_CIL,
 467                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 468                                                 if (hcfg.b.fslspclksel !=
 469                                                     DWC_HCFG_48_MHZ) {
 470                                                         hcfg.b.fslspclksel =
 471                                                             DWC_HCFG_48_MHZ;
 472                                                         DWC_WRITE_REG32
 473                                                             (&host_if->host_global_regs->hcfg,
 474                                                              hcfg.d32);
 475                                                         do_reset = 1;
 476                                                 }
 477                                         }
 478                                 } else {
 479                                         /*
 480                                          * Not low power
 481                                          */
 482                                         if (usbcfg.b.phylpwrclksel == 1) {
 483                                                 usbcfg.b.phylpwrclksel = 0;
 484                                                 DWC_WRITE_REG32
 485                                                     (&global_regs->gusbcfg,
 486                                                      usbcfg.d32);
 487                                                 do_reset = 1;
 488                                         }
 489                                 }
 490
 491                                 if (do_reset) {
 492                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
 493                                 }
 494                         }
 495
 496                         if (!do_reset) {
 497                                 /* Port has been enabled set the reset change flag */
 498                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 499                         }
 500                 } else {
 501                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 502                 }
 503                 retval |= 1;
 504         }
 505
 506         /** Overcurrent Change Interrupt */
 507         if (hprt0.b.prtovrcurrchng) {
 508                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 509                             "Port Overcurrent Changed--\n", hprt0.d32);
 510                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 511                 hprt0_modify.b.prtovrcurrchng = 1;
 512                 retval |= 1;
 513         }
 514
 515         /* Clear Port Interrupts */
 516         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 517
 518         return retval;
 519 }
 520
 521 /** This interrupt indicates that one or more host channels has a pending
 522  * interrupt. There are multiple conditions that can cause each host channel
 523  * interrupt. This function determines which conditions have occurred for each
 524  * host channel interrupt and handles them appropriately. */
 525 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 526 {
 527         int i;
 528         int retval = 0;
 529         haint_data_t haint;
 530
 531         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 532          * GINTSTS */
 533
 534         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 535
 536         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 537                 if (haint.b2.chint & (1 << i)) {
 538                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 539                 }
 540         }
 541
 542         return retval;
 543 }
 544
 545 /**
 546  * Gets the actual length of a transfer after the transfer halts. _halt_status
 547  * holds the reason for the halt.
 548  *
 549  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 550  * *short_read is set to 1 upon return if less than the requested
 551  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 552  * return. short_read may also be NULL on entry, in which case it remains
 553  * unchanged.
 554  */
 555 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
 556                                        dwc_otg_hc_regs_t * hc_regs,
 557                                        dwc_otg_qtd_t * qtd,
 558                                        dwc_otg_halt_status_e halt_status,
 559                                        int *short_read)
 560 {
 561         hctsiz_data_t hctsiz;
 562         uint32_t length;
 563
 564         if (short_read != NULL) {
 565                 *short_read = 0;
 566         }
 567         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 568
 569         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 570                 if (hc->ep_is_in) {
 571                         length = hc->xfer_len - hctsiz.b.xfersize;
 572                         if (short_read != NULL) {
 573                                 *short_read = (hctsiz.b.xfersize != 0);
 574                         }
 575                 } else if (hc->qh->do_split) {
 576                         length = qtd->ssplit_out_xfer_count;
 577                 } else {
 578                         length = hc->xfer_len;
 579                 }
 580         } else {
 581                 /*
 582                  * Must use the hctsiz.pktcnt field to determine how much data
 583                  * has been transferred. This field reflects the number of
 584                  * packets that have been transferred via the USB. This is
 585                  * always an integral number of packets if the transfer was
 586                  * halted before its normal completion. (Can't use the
 587                  * hctsiz.xfersize field because that reflects the number of
 588                  * bytes transferred via the AHB, not the USB).
 589                  */
 590                 length =
 591                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 592         }
 593
 594         return length;
 595 }
 596
 597 /**
 598  * Updates the state of the URB after a Transfer Complete interrupt on the
 599  * host channel. Updates the actual_length field of the URB based on the
 600  * number of bytes transferred via the host channel. Sets the URB status
 601  * if the data transfer is finished.
 602  *
 603  * @return 1 if the data transfer specified by the URB is completely finished,
 604  * 0 otherwise.
 605  */
 606 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
 607                                       dwc_otg_hc_regs_t * hc_regs,
 608                                       dwc_otg_hcd_urb_t * urb,
 609                                       dwc_otg_qtd_t * qtd)
 610 {
 611         int xfer_done = 0;
 612         int short_read = 0;
 613
 614         int xfer_length;
 615
 616         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 617                                              DWC_OTG_HC_XFER_COMPLETE,
 618                                              &short_read);
 619
 620
 621         /* non DWORD-aligned buffer case handling. */
 622         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 623                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 624                            xfer_length);
 625         }
 626
 627         urb->actual_length += xfer_length;
 628
 629         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 630             (urb->flags & URB_SEND_ZERO_PACKET)
 631             && (urb->actual_length == urb->length)
 632             && !(urb->length % hc->max_packet)) {
 633                 xfer_done = 0;
 634         } else if (short_read || urb->actual_length >= urb->length) {
 635                 xfer_done = 1;
 636                 urb->status = 0;
 637         }
 638
 639 #ifdef DEBUG
 640         {
 641                 hctsiz_data_t hctsiz;
 642                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 643                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 644                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 645                             hc->hc_num);
 646                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 647                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 648                             hctsiz.b.xfersize);
 649                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 650                             urb->length);
 651                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 652                             urb->actual_length);
 653                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 654                             short_read, xfer_done);
 655         }
 656 #endif
 657
 658         return xfer_done;
 659 }
 660
 661 /*
 662  * Save the starting data toggle for the next transfer. The data toggle is
 663  * saved in the QH for non-control transfers and it's saved in the QTD for
 664  * control transfers.
 665  */
 666 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
 667                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
 668 {
 669         hctsiz_data_t hctsiz;
 670         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 671
 672         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 673                 dwc_otg_qh_t *qh = hc->qh;
 674                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 675                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 676                 } else {
 677                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 678                 }
 679         } else {
 680                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 681                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 682                 } else {
 683                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 684                 }
 685         }
 686 }
 687
 688 /**
 689  * Updates the state of an Isochronous URB when the transfer is stopped for
 690  * any reason. The fields of the current entry in the frame descriptor array
 691  * are set based on the transfer state and the input _halt_status. Completes
 692  * the Isochronous URB if all the URB frames have been completed.
 693  *
 694  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 695  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 696  */
 697 static dwc_otg_halt_status_e
 698 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
 699                       dwc_hc_t * hc,
 700                       dwc_otg_hc_regs_t * hc_regs,
 701                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 702 {
 703         dwc_otg_hcd_urb_t *urb = qtd->urb;
 704         dwc_otg_halt_status_e ret_val = halt_status;
 705         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 706
 707         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 708         switch (halt_status) {
 709         case DWC_OTG_HC_XFER_COMPLETE:
 710                 frame_desc->status = 0;
 711                 frame_desc->actual_length =
 712                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 713
 714                 /* non DWORD-aligned buffer case handling. */
 715                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 716                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 717                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 718                 }
 719
 720                 break;
 721         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 722                 urb->error_count++;
 723                 if (hc->ep_is_in) {
 724                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 725                 } else {
 726                         frame_desc->status = -DWC_E_COMMUNICATION;
 727                 }
 728                 frame_desc->actual_length = 0;
 729                 break;
 730         case DWC_OTG_HC_XFER_BABBLE_ERR:
 731                 urb->error_count++;
 732                 frame_desc->status = -DWC_E_OVERFLOW;
 733                 /* Don't need to update actual_length in this case. */
 734                 break;
 735         case DWC_OTG_HC_XFER_XACT_ERR:
 736                 urb->error_count++;
 737                 frame_desc->status = -DWC_E_PROTOCOL;
 738                 frame_desc->actual_length =
 739                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 740
 741                 /* non DWORD-aligned buffer case handling. */
 742                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 743                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 744                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 745                 }
 746                 /* Skip whole frame */
 747                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 748                     hc->ep_is_in && hcd->core_if->dma_enable) {
 749                         qtd->complete_split = 0;
 750                         qtd->isoc_split_offset = 0;
 751                 }
 752
 753                 break;
 754         default:
 755                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 756                 break;
 757         }
 758         if (++qtd->isoc_frame_index == urb->packet_count) {
 759                 /*
 760                  * urb->status is not used for isoc transfers.
 761                  * The individual frame_desc statuses are used instead.
 762                  */
 763                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 764                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 765         } else {
 766                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 767         }
 768         return ret_val;
 769 }
 770
 771 /**
 772  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 773  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 774  * still linked to the QH, the QH is added to the end of the inactive
 775  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 776  * schedule if no more QTDs are linked to the QH.
 777  */
 778 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
 779 {
 780         int continue_split = 0;
 781         dwc_otg_qtd_t *qtd;
 782
 783         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 784
 785         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 786
 787         if (qtd->complete_split) {
 788                 continue_split = 1;
 789         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 790                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 791                 continue_split = 1;
 792         }
 793
 794         if (free_qtd) {
 795                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 796                 continue_split = 0;
 797         }
 798
 799         qh->channel = NULL;
 800         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 801 }
 802
 803 /**
 804  * Releases a host channel for use by other transfers. Attempts to select and
 805  * queue more transactions since at least one host channel is available.
 806  *
 807  * @param hcd The HCD state structure.
 808  * @param hc The host channel to release.
 809  * @param qtd The QTD associated with the host channel. This QTD may be freed
 810  * if the transfer is complete or an error has occurred.
 811  * @param halt_status Reason the channel is being released. This status
 812  * determines the actions taken by this function.
 813  */
 814 static void release_channel(dwc_otg_hcd_t * hcd,
 815                             dwc_hc_t * hc,
 816                             dwc_otg_qtd_t * qtd,
 817                             dwc_otg_halt_status_e halt_status)
 818 {
 819         dwc_otg_transaction_type_e tr_type;
 820         int free_qtd;
 821
 822         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 823                     __func__, hc->hc_num, halt_status);
 824
 825         if(halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE){
 826                 if(((uint32_t) qtd & 0xf0000000)==0){
 827                         DWC_PRINTF("%s error: qtd %p, status %d 0!!!\n", __func__, qtd, halt_status);
 828                         goto cleanup;
 829                 }
 830
 831                 if(((uint32_t) qtd & 0x80000000)==0){
 832                         DWC_PRINTF("%s error: qtd %p, status %d 1!!!\n", __func__, qtd, halt_status);
 833                         goto cleanup;
 834                 }
 835
 836                 if(((uint32_t) qtd->urb & 0xf0000000)==0){
 837                         DWC_PRINTF("%s qtd %p urb %p, status %d\n", __func__, qtd, qtd->urb, halt_status);
 838                         goto cleanup;
 839                 }
 840         }
 841
 842         switch (halt_status) {
 843         case DWC_OTG_HC_XFER_URB_COMPLETE:
 844                 free_qtd = 1;
 845                 break;
 846         case DWC_OTG_HC_XFER_AHB_ERR:
 847         case DWC_OTG_HC_XFER_STALL:
 848         case DWC_OTG_HC_XFER_BABBLE_ERR:
 849                 free_qtd = 1;
 850                 break;
 851         case DWC_OTG_HC_XFER_XACT_ERR:
 852                 if (qtd->error_count >= 3) {
 853                         DWC_DEBUGPL(DBG_HCDV,
 854                                     "  Complete URB with transaction error\n");
 855                         free_qtd = 1;
 856                         qtd->urb->status = -DWC_E_PROTOCOL;
 857                         hcd->fops->complete(hcd, qtd->urb->priv,
 858                                             qtd->urb, -DWC_E_PROTOCOL);
 859                 } else {
 860                         free_qtd = 0;
 861                 }
 862                 break;
 863         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 864                 /*
 865                  * The QTD has already been removed and the QH has been
 866                  * deactivated. Don't want to do anything except release the
 867                  * host channel and try to queue more transfers.
 868                  */
 869                 goto cleanup;
 870         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 871                 free_qtd = 0;
 872                 break;
 873         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 874                 DWC_DEBUGPL(DBG_HCDV,
 875                         "  Complete URB with I/O error\n");
 876                 free_qtd = 1;
 877                 qtd->urb->status = -DWC_E_IO;
 878                 hcd->fops->complete(hcd, qtd->urb->priv,
 879                         qtd->urb, -DWC_E_IO);
 880                 break;
 881         default:
 882                 free_qtd = 0;
 883                 break;
 884         }
 885
 886         deactivate_qh(hcd, hc->qh, free_qtd);
 887
 888 cleanup:
 889         /*
 890          * Release the host channel for use by other transfers. The cleanup
 891          * function clears the channel interrupt enables and conditions, so
 892          * there's no need to clear the Channel Halted interrupt separately.
 893          */
 894         dwc_otg_hc_cleanup(hcd->core_if, hc);
 895         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 896
 897         switch (hc->ep_type) {
 898         case DWC_OTG_EP_TYPE_CONTROL:
 899         case DWC_OTG_EP_TYPE_BULK:
 900                 hcd->non_periodic_channels--;
 901                 break;
 902
 903         default:
 904                 /*
 905                  * Don't release reservations for periodic channels here.
 906                  * That's done when a periodic transfer is descheduled (i.e.
 907                  * when the QH is removed from the periodic schedule).
 908                  */
 909                 break;
 910         }
 911
 912         /* Try to queue more transfers now that there's a free channel. */
 913         tr_type = dwc_otg_hcd_select_transactions(hcd);
 914         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 915                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 916         }
 917 }
 918
 919 /**
 920  * Halts a host channel. If the channel cannot be halted immediately because
 921  * the request queue is full, this function ensures that the FIFO empty
 922  * interrupt for the appropriate queue is enabled so that the halt request can
 923  * be queued when there is space in the request queue.
 924  *
 925  * This function may also be called in DMA mode. In that case, the channel is
 926  * simply released since the core always halts the channel automatically in
 927  * DMA mode.
 928  */
 929 static void halt_channel(dwc_otg_hcd_t * hcd,
 930                          dwc_hc_t * hc,
 931                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 932 {
 933         if (hcd->core_if->dma_enable) {
 934                 release_channel(hcd, hc, qtd, halt_status);
 935                 return;
 936         }
 937
 938         /* Slave mode processing... */
 939         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 940
 941         if (hc->halt_on_queue) {
 942                 gintmsk_data_t gintmsk = {.d32 = 0 };
 943                 dwc_otg_core_global_regs_t *global_regs;
 944                 global_regs = hcd->core_if->core_global_regs;
 945
 946                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 947                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 948                         /*
 949                          * Make sure the Non-periodic Tx FIFO empty interrupt
 950                          * is enabled so that the non-periodic schedule will
 951                          * be processed.
 952                          */
 953                         gintmsk.b.nptxfempty = 1;
 954                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 955                 } else {
 956                         /*
 957                          * Move the QH from the periodic queued schedule to
 958                          * the periodic assigned schedule. This allows the
 959                          * halt to be queued when the periodic schedule is
 960                          * processed.
 961                          */
 962                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 963                                            &hc->qh->qh_list_entry);
 964
 965                         /*
 966                          * Make sure the Periodic Tx FIFO Empty interrupt is
 967                          * enabled so that the periodic schedule will be
 968                          * processed.
 969                          */
 970                         gintmsk.b.ptxfempty = 1;
 971                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 972                 }
 973         }
 974 }
 975
 976 /**
 977  * Performs common cleanup for non-periodic transfers after a Transfer
 978  * Complete interrupt. This function should be called after any endpoint type
 979  * specific handling is finished to release the host channel.
 980  */
 981 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
 982                                        dwc_hc_t * hc,
 983                                        dwc_otg_hc_regs_t * hc_regs,
 984                                        dwc_otg_qtd_t * qtd,
 985                                        dwc_otg_halt_status_e halt_status)
 986 {
 987         hcint_data_t hcint;
 988
 989         qtd->error_count = 0;
 990
 991         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
 992         if (hcint.b.nyet) {
 993                 /*
 994                  * Got a NYET on the last transaction of the transfer. This
 995                  * means that the endpoint should be in the PING state at the
 996                  * beginning of the next transfer.
 997                  */
 998                 hc->qh->ping_state = 1;
 999                 clear_hc_int(hc_regs, nyet);
1000         }
1001
1002         /*
1003          * Always halt and release the host channel to make it available for
1004          * more transfers. There may still be more phases for a control
1005          * transfer or more data packets for a bulk transfer at this point,
1006          * but the host channel is still halted. A channel will be reassigned
1007          * to the transfer when the non-periodic schedule is processed after
1008          * the channel is released. This allows transactions to be queued
1009          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1010          * Tx FIFO Empty interrupt if necessary.
1011          */
1012         if (hc->ep_is_in) {
1013                 /*
1014                  * IN transfers in Slave mode require an explicit disable to
1015                  * halt the channel. (In DMA mode, this call simply releases
1016                  * the channel.)
1017                  */
1018                 halt_channel(hcd, hc, qtd, halt_status);
1019         } else {
1020                 /*
1021                  * The channel is automatically disabled by the core for OUT
1022                  * transfers in Slave mode.
1023                  */
1024                 release_channel(hcd, hc, qtd, halt_status);
1025         }
1026 }
1027
1028 /**
1029  * Performs common cleanup for periodic transfers after a Transfer Complete
1030  * interrupt. This function should be called after any endpoint type specific
1031  * handling is finished to release the host channel.
1032  */
1033 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
1034                                    dwc_hc_t * hc,
1035                                    dwc_otg_hc_regs_t * hc_regs,
1036                                    dwc_otg_qtd_t * qtd,
1037                                    dwc_otg_halt_status_e halt_status)
1038 {
1039         hctsiz_data_t hctsiz;
1040         qtd->error_count = 0;
1041
1042         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1043         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1044                 /* Core halts channel in these cases. */
1045                 release_channel(hcd, hc, qtd, halt_status);
1046         } else {
1047                 /* Flush any outstanding requests from the Tx queue. */
1048                 halt_channel(hcd, hc, qtd, halt_status);
1049         }
1050 }
1051
1052 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
1053                                              dwc_hc_t * hc,
1054                                              dwc_otg_hc_regs_t * hc_regs,
1055                                              dwc_otg_qtd_t * qtd)
1056 {
1057         uint32_t len;
1058         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1059         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1060
1061         len = get_actual_xfer_length(hc, hc_regs, qtd,
1062                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1063
1064         if (!len) {
1065                 qtd->complete_split = 0;
1066                 qtd->isoc_split_offset = 0;
1067                 return 0;
1068         }
1069         frame_desc->actual_length += len;
1070
1071         if (hc->align_buff && len)
1072                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1073                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1074         qtd->isoc_split_offset += len;
1075
1076         if (frame_desc->length == frame_desc->actual_length) {
1077                 frame_desc->status = 0;
1078                 qtd->isoc_frame_index++;
1079                 qtd->complete_split = 0;
1080                 qtd->isoc_split_offset = 0;
1081         }
1082
1083         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1084                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1085                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1086         } else {
1087                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1088         }
1089
1090         return 1;               /* Indicates that channel released */
1091 }
1092
1093 /**
1094  * Handles a host channel Transfer Complete interrupt. This handler may be
1095  * called in either DMA mode or Slave mode.
1096  */
1097 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
1098                                        dwc_hc_t * hc,
1099                                        dwc_otg_hc_regs_t * hc_regs,
1100                                        dwc_otg_qtd_t * qtd)
1101 {
1102         int urb_xfer_done;
1103         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1104         dwc_otg_hcd_urb_t *urb;
1105         int pipe_type;
1106
1107         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1108                     "Transfer Complete--\n", hc->hc_num);
1109
1110         if(((uint32_t) qtd & 0xf0000000)==0){
1111                 DWC_PRINTF("%s qtd %p\n", __func__, qtd);
1112                 release_channel(hcd, hc, qtd, hc->halt_status);
1113                 return 1;
1114         }
1115
1116         urb = qtd->urb;
1117         if(((uint32_t)urb & 0xf0000000)==0){
1118                 DWC_PRINTF("%s qtd %p, urb %p\n", __func__, qtd, urb);
1119                 release_channel(hcd, hc, qtd, hc->halt_status);
1120                 return 1;
1121         }
1122
1123         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1124
1125         if (hcd->core_if->dma_desc_enable) {
1126                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1127                 if (pipe_type == UE_ISOCHRONOUS) {
1128                         /* Do not disable the interrupt, just clear it */
1129                         clear_hc_int(hc_regs, xfercomp);
1130                         return 1;
1131                 }
1132                 goto handle_xfercomp_done;
1133         }
1134
1135         /*
1136          * Handle xfer complete on CSPLIT.
1137          */
1138
1139         if (hc->qh->do_split) {
1140                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1141                     && hcd->core_if->dma_enable) {
1142                         if (qtd->complete_split
1143                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1144                                                              qtd))
1145                                 goto handle_xfercomp_done;
1146                 } else {
1147                         qtd->complete_split = 0;
1148                 }
1149         }
1150
1151         /* Update the QTD and URB states. */
1152         switch (pipe_type) {
1153         case UE_CONTROL:
1154                 switch (qtd->control_phase) {
1155                 case DWC_OTG_CONTROL_SETUP:
1156                         if (urb->length > 0) {
1157                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1158                         } else {
1159                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1160                         }
1161                         DWC_DEBUGPL(DBG_HCDV,
1162                                     "  Control setup transaction done\n");
1163                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1164                         break;
1165                 case DWC_OTG_CONTROL_DATA:{
1166                                 urb_xfer_done =
1167                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1168                                                                qtd);
1169                                 if (urb_xfer_done) {
1170                                         qtd->control_phase =
1171                                             DWC_OTG_CONTROL_STATUS;
1172                                         DWC_DEBUGPL(DBG_HCDV,
1173                                                     "  Control data transfer done\n");
1174                                 } else {
1175                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1176                                 }
1177                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1178                                 break;
1179                         }
1180                 case DWC_OTG_CONTROL_STATUS:
1181                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1182                         if (urb->status == -DWC_E_IN_PROGRESS) {
1183                                 urb->status = 0;
1184                         }
1185                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1186                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1187                         break;
1188                 }
1189
1190                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1191                 break;
1192         case UE_BULK:
1193                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1194                 urb_xfer_done =
1195                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1196                 if (urb_xfer_done) {
1197                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1198                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1199                 } else {
1200                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1201                 }
1202
1203                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1204                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1205                 break;
1206         case UE_INTERRUPT:
1207                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1208                 urb_xfer_done =
1209                         update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1210
1211                 /*
1212                  * Interrupt URB is done on the first transfer complete
1213                  * interrupt.
1214                  */
1215                 if (urb_xfer_done) {
1216                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1217                                 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1218                 } else {
1219                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1220                 }
1221
1222                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1223                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1224                 break;
1225         case UE_ISOCHRONOUS:
1226                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1227                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1228                         halt_status =
1229                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1230                                                   DWC_OTG_HC_XFER_COMPLETE);
1231                 }
1232                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1233                 break;
1234         }
1235
1236 handle_xfercomp_done:
1237         disable_hc_int(hc_regs, xfercompl);
1238
1239         return 1;
1240 }
1241
1242 /**
1243  * Handles a host channel STALL interrupt. This handler may be called in
1244  * either DMA mode or Slave mode.
1245  */
1246 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
1247                                     dwc_hc_t * hc,
1248                                     dwc_otg_hc_regs_t * hc_regs,
1249                                     dwc_otg_qtd_t * qtd)
1250 {
1251         dwc_otg_hcd_urb_t *urb = qtd->urb;
1252         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1253
1254         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1255                     "STALL Received--\n", hc->hc_num);
1256
1257         if (hcd->core_if->dma_desc_enable) {
1258                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
1259                 goto handle_stall_done;
1260         }
1261
1262         if (pipe_type == UE_CONTROL) {
1263                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1264         }
1265
1266         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1267                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1268                 /*
1269                  * USB protocol requires resetting the data toggle for bulk
1270                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1271                  * setup command is issued to the endpoint. Anticipate the
1272                  * CLEAR_FEATURE command since a STALL has occurred and reset
1273                  * the data toggle now.
1274                  */
1275                 hc->qh->data_toggle = 0;
1276         }
1277
1278         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1279
1280 handle_stall_done:
1281         disable_hc_int(hc_regs, stall);
1282
1283         return 1;
1284 }
1285
1286 /*
1287  * Updates the state of the URB when a transfer has been stopped due to an
1288  * abnormal condition before the transfer completes. Modifies the
1289  * actual_length field of the URB to reflect the number of bytes that have
1290  * actually been transferred via the host channel.
1291  */
1292 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
1293                                        dwc_otg_hc_regs_t * hc_regs,
1294                                        dwc_otg_hcd_urb_t * urb,
1295                                        dwc_otg_qtd_t * qtd,
1296                                        dwc_otg_halt_status_e halt_status)
1297 {
1298         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1299                                                             halt_status, NULL);
1300         /* non DWORD-aligned buffer case handling. */
1301         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1302                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1303                            bytes_transferred);
1304         }
1305
1306         urb->actual_length += bytes_transferred;
1307
1308 #ifdef DEBUG
1309         {
1310                 hctsiz_data_t hctsiz;
1311                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1312                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1313                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1314                             hc->hc_num);
1315                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1316                             hc->start_pkt_count);
1317                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1318                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1319                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1320                             bytes_transferred);
1321                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1322                             urb->actual_length);
1323                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1324                             urb->length);
1325         }
1326 #endif
1327 }
1328
1329 /**
1330  * Handles a host channel NAK interrupt. This handler may be called in either
1331  * DMA mode or Slave mode.
1332  */
1333 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
1334                                   dwc_hc_t * hc,
1335                                   dwc_otg_hc_regs_t * hc_regs,
1336                                   dwc_otg_qtd_t * qtd)
1337 {
1338         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1339                     "NAK Received--\n", hc->hc_num);
1340
1341         /*
1342          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1343          * interrupt.  Re-start the SSPLIT transfer.
1344          */
1345         if (hc->do_split) {
1346                 if (hc->complete_split) {
1347                         qtd->error_count = 0;
1348                 }
1349                 qtd->complete_split = 0;
1350                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1351                 goto handle_nak_done;
1352         }
1353
1354         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1355         case UE_CONTROL:
1356         case UE_BULK:
1357                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1358                         /*
1359                          * NAK interrupts are enabled on bulk/control IN
1360                          * transfers in DMA mode for the sole purpose of
1361                          * resetting the error count after a transaction error
1362                          * occurs. The core will continue transferring data.
1363                          */
1364                         qtd->error_count = 0;
1365                         goto handle_nak_done;
1366                 }
1367
1368                 /*
1369                  * NAK interrupts normally occur during OUT transfers in DMA
1370                  * or Slave mode. For IN transfers, more requests will be
1371                  * queued as request queue space is available.
1372                  */
1373                 qtd->error_count = 0;
1374
1375                 if (!hc->qh->ping_state) {
1376                         update_urb_state_xfer_intr(hc, hc_regs,
1377                                                    qtd->urb, qtd,
1378                                                    DWC_OTG_HC_XFER_NAK);
1379                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1380
1381                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1382                                 hc->qh->ping_state = 1;
1383                 }
1384
1385                 /*
1386                  * Halt the channel so the transfer can be re-started from
1387                  * the appropriate point or the PING protocol will
1388                  * start/continue.
1389                  */
1390                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1391                 break;
1392         case UE_INTERRUPT:
1393                 qtd->error_count = 0;
1394                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1395                 break;
1396         case UE_ISOCHRONOUS:
1397                 /* Should never get called for isochronous transfers. */
1398                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1399                 break;
1400         }
1401
1402 handle_nak_done:
1403         disable_hc_int(hc_regs, nak);
1404
1405         return 1;
1406 }
1407
1408 /**
1409  * Handles a host channel ACK interrupt. This interrupt is enabled when
1410  * performing the PING protocol in Slave mode, when errors occur during
1411  * either Slave mode or DMA mode, and during Start Split transactions.
1412  */
1413 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
1414                                   dwc_hc_t * hc,
1415                                   dwc_otg_hc_regs_t * hc_regs,
1416                                   dwc_otg_qtd_t * qtd)
1417 {
1418         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1419                     "ACK Received--\n", hc->hc_num);
1420
1421         if (hc->do_split) {
1422                 /*
1423                  * Handle ACK on SSPLIT.
1424                  * ACK should not occur in CSPLIT.
1425                  */
1426                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1427                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1428                 }
1429                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1430                         /* Don't need complete for isochronous out transfers. */
1431                         qtd->complete_split = 1;
1432                 }
1433
1434                 /* ISOC OUT */
1435                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1436                         switch (hc->xact_pos) {
1437                         case DWC_HCSPLIT_XACTPOS_ALL:
1438                                 break;
1439                         case DWC_HCSPLIT_XACTPOS_END:
1440                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1441                                 qtd->isoc_split_offset = 0;
1442                                 break;
1443                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1444                         case DWC_HCSPLIT_XACTPOS_MID:
1445                                 /*
1446                                  * For BEGIN or MID, calculate the length for
1447                                  * the next microframe to determine the correct
1448                                  * SSPLIT token, either MID or END.
1449                                  */
1450                                 {
1451                                         struct dwc_otg_hcd_iso_packet_desc
1452                                         *frame_desc;
1453
1454                                         frame_desc =
1455                                             &qtd->urb->
1456                                             iso_descs[qtd->isoc_frame_index];
1457                                         qtd->isoc_split_offset += 188;
1458
1459                                         if ((frame_desc->length -
1460                                              qtd->isoc_split_offset) <= 188) {
1461                                                 qtd->isoc_split_pos =
1462                                                     DWC_HCSPLIT_XACTPOS_END;
1463                                         } else {
1464                                                 qtd->isoc_split_pos =
1465                                                     DWC_HCSPLIT_XACTPOS_MID;
1466                                         }
1467
1468                                 }
1469                                 break;
1470                         }
1471                 } else {
1472                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1473                 }
1474         } else {
1475                 qtd->error_count = 0;
1476
1477                 if (hc->qh->ping_state) {
1478                         hc->qh->ping_state = 0;
1479                         /*
1480                          * Halt the channel so the transfer can be re-started
1481                          * from the appropriate point. This only happens in
1482                          * Slave mode. In DMA mode, the ping_state is cleared
1483                          * when the transfer is started because the core
1484                          * automatically executes the PING, then the transfer.
1485                          */
1486                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1487                 }
1488         }
1489
1490         /*
1491          * If the ACK occurred when _not_ in the PING state, let the channel
1492          * continue transferring data after clearing the error count.
1493          */
1494
1495         disable_hc_int(hc_regs, ack);
1496
1497         return 1;
1498 }
1499
1500 /**
1501  * Handles a host channel NYET interrupt. This interrupt should only occur on
1502  * Bulk and Control OUT endpoints and for complete split transactions. If a
1503  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1504  * handled in the xfercomp interrupt handler, not here. This handler may be
1505  * called in either DMA mode or Slave mode.
1506  */
1507 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
1508                                    dwc_hc_t * hc,
1509                                    dwc_otg_hc_regs_t * hc_regs,
1510                                    dwc_otg_qtd_t * qtd)
1511 {
1512         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1513                     "NYET Received--\n", hc->hc_num);
1514
1515         /*
1516          * NYET on CSPLIT
1517          * re-do the CSPLIT immediately on non-periodic
1518          */
1519         if (hc->do_split && hc->complete_split) {
1520                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1521                     && hcd->core_if->dma_enable) {
1522                         qtd->complete_split = 0;
1523                         qtd->isoc_split_offset = 0;
1524                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1525                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1526                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1527                         }
1528                         else
1529                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1530                         goto handle_nyet_done;
1531                 }
1532
1533                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1534                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1535                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1536
1537                         if (dwc_full_frame_num(frnum) !=
1538                             dwc_full_frame_num(hc->qh->sched_frame)) {
1539                                 /*
1540                                  * No longer in the same full speed frame.
1541                                  * Treat this as a transaction error.
1542                                  */
1543 #if 0
1544                                 /** @todo Fix system performance so this can
1545                                  * be treated as an error. Right now complete
1546                                  * splits cannot be scheduled precisely enough
1547                                  * due to other system activity, so this error
1548                                  * occurs regularly in Slave mode.
1549                                  */
1550                                 qtd->error_count++;
1551 #endif
1552                                 qtd->complete_split = 0;
1553                                 halt_channel(hcd, hc, qtd,
1554                                              DWC_OTG_HC_XFER_XACT_ERR);
1555                                 /** @todo add support for isoc release */
1556                                 goto handle_nyet_done;
1557                         }
1558                 }
1559
1560                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1561                 goto handle_nyet_done;
1562         }
1563
1564         hc->qh->ping_state = 1;
1565         qtd->error_count = 0;
1566
1567         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1568                                    DWC_OTG_HC_XFER_NYET);
1569         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1570
1571         /*
1572          * Halt the channel and re-start the transfer so the PING
1573          * protocol will start.
1574          */
1575         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1576
1577 handle_nyet_done:
1578         disable_hc_int(hc_regs, nyet);
1579         return 1;
1580 }
1581
1582 /**
1583  * Handles a host channel babble interrupt. This handler may be called in
1584  * either DMA mode or Slave mode.
1585  */
1586 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
1587                                      dwc_hc_t * hc,
1588                                      dwc_otg_hc_regs_t * hc_regs,
1589                                      dwc_otg_qtd_t * qtd)
1590 {
1591         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1592                     "Babble Error--\n", hc->hc_num);
1593
1594         if (hcd->core_if->dma_desc_enable) {
1595                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1596                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1597                 goto handle_babble_done;
1598         }
1599
1600         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1601                 hcd->fops->complete(hcd, qtd->urb->priv,
1602                                     qtd->urb, -DWC_E_OVERFLOW);
1603                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1604         } else {
1605                 dwc_otg_halt_status_e halt_status;
1606                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1607                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1608                 halt_channel(hcd, hc, qtd, halt_status);
1609         }
1610
1611 handle_babble_done:
1612         disable_hc_int(hc_regs, bblerr);
1613         return 1;
1614 }
1615
1616 /**
1617  * Handles a host channel AHB error interrupt. This handler is only called in
1618  * DMA mode.
1619  */
1620 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
1621                                      dwc_hc_t * hc,
1622                                      dwc_otg_hc_regs_t * hc_regs,
1623                                      dwc_otg_qtd_t * qtd)
1624 {
1625         hcchar_data_t hcchar;
1626         hcsplt_data_t hcsplt;
1627         hctsiz_data_t hctsiz;
1628         uint32_t hcdma;
1629         char *pipetype, *speed;
1630
1631         dwc_otg_hcd_urb_t *urb = qtd->urb;
1632
1633         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1634                     "AHB Error--\n", hc->hc_num);
1635
1636         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1637         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1638         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1639         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1640
1641         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1642         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1643         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1644         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1645         DWC_ERROR("  Device address: %d\n",
1646                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1647         DWC_ERROR("  Endpoint: %d, %s\n",
1648                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1649                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1650
1651         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1652         case UE_CONTROL:
1653                 pipetype = "CONTROL";
1654                 break;
1655         case UE_BULK:
1656                 pipetype = "BULK";
1657                 break;
1658         case UE_INTERRUPT:
1659                 pipetype = "INTERRUPT";
1660                 break;
1661         case UE_ISOCHRONOUS:
1662                 pipetype = "ISOCHRONOUS";
1663                 break;
1664         default:
1665                 pipetype = "UNKNOWN";
1666                 break;
1667         }
1668
1669         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1670
1671         switch (hc->speed) {
1672         case DWC_OTG_EP_SPEED_HIGH:
1673                 speed = "HIGH";
1674                 break;
1675         case DWC_OTG_EP_SPEED_FULL:
1676                 speed = "FULL";
1677                 break;
1678         case DWC_OTG_EP_SPEED_LOW:
1679                 speed = "LOW";
1680                 break;
1681         default:
1682                 speed = "UNKNOWN";
1683                 break;
1684         };
1685
1686         DWC_ERROR("  Speed: %s\n", speed);
1687
1688         DWC_ERROR("  Max packet size: %d\n",
1689                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1690         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1691         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1692                   urb->buf, (void *)urb->dma);
1693         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1694                   urb->setup_packet, (void *)urb->setup_dma);
1695         DWC_ERROR("  Interval: %d\n", urb->interval);
1696
1697         /* Core haltes the channel for Descriptor DMA mode */
1698         if (hcd->core_if->dma_desc_enable) {
1699                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1700                                                DWC_OTG_HC_XFER_AHB_ERR);
1701                 goto handle_ahberr_done;
1702         }
1703
1704         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1705
1706         /*
1707          * Force a channel halt. Don't call halt_channel because that won't
1708          * write to the HCCHARn register in DMA mode to force the halt.
1709          */
1710         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1711 handle_ahberr_done:
1712         disable_hc_int(hc_regs, ahberr);
1713         return 1;
1714 }
1715
1716 /**
1717  * Handles a host channel transaction error interrupt. This handler may be
1718  * called in either DMA mode or Slave mode.
1719  */
1720 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
1721                                       dwc_hc_t * hc,
1722                                       dwc_otg_hc_regs_t * hc_regs,
1723                                       dwc_otg_qtd_t * qtd)
1724 {
1725         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1726                     "Transaction Error--\n", hc->hc_num);
1727
1728         if (hcd->core_if->dma_desc_enable) {
1729                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1730                                                DWC_OTG_HC_XFER_XACT_ERR);
1731                 goto handle_xacterr_done;
1732         }
1733
1734         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1735         case UE_CONTROL:
1736         case UE_BULK:
1737                 qtd->error_count++;
1738                 if (!hc->qh->ping_state) {
1739
1740                         update_urb_state_xfer_intr(hc, hc_regs,
1741                                                    qtd->urb, qtd,
1742                                                    DWC_OTG_HC_XFER_XACT_ERR);
1743                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1744                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1745                                 hc->qh->ping_state = 1;
1746                         }
1747                 }
1748
1749                 /*
1750                  * Halt the channel so the transfer can be re-started from
1751                  * the appropriate point or the PING protocol will start.
1752                  */
1753                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1754                 break;
1755         case UE_INTERRUPT:
1756                 qtd->error_count++;
1757                 if (hc->do_split && hc->complete_split) {
1758                         qtd->complete_split = 0;
1759                 }
1760                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1761                 break;
1762         case UE_ISOCHRONOUS:
1763                 {
1764                         dwc_otg_halt_status_e halt_status;
1765                         halt_status =
1766                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1767                                                   DWC_OTG_HC_XFER_XACT_ERR);
1768
1769                         halt_channel(hcd, hc, qtd, halt_status);
1770                 }
1771                 break;
1772         }
1773 handle_xacterr_done:
1774         disable_hc_int(hc_regs, xacterr);
1775
1776         return 1;
1777 }
1778
1779 /**
1780  * Handles a host channel frame overrun interrupt. This handler may be called
1781  * in either DMA mode or Slave mode.
1782  */
1783 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
1784                                        dwc_hc_t * hc,
1785                                        dwc_otg_hc_regs_t * hc_regs,
1786                                        dwc_otg_qtd_t * qtd)
1787 {
1788         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1789                     "Frame Overrun--\n", hc->hc_num);
1790
1791         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1792         case UE_CONTROL:
1793         case UE_BULK:
1794                 break;
1795         case UE_INTERRUPT:
1796                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1797                 break;
1798         case UE_ISOCHRONOUS:
1799                 {
1800                         dwc_otg_halt_status_e halt_status;
1801                         halt_status =
1802                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1803                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1804
1805                         halt_channel(hcd, hc, qtd, halt_status);
1806                 }
1807                 break;
1808         }
1809
1810         disable_hc_int(hc_regs, frmovrun);
1811
1812         return 1;
1813 }
1814
1815 /**
1816  * Handles a host channel data toggle error interrupt. This handler may be
1817  * called in either DMA mode or Slave mode.
1818  */
1819 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
1820                                          dwc_hc_t * hc,
1821                                          dwc_otg_hc_regs_t * hc_regs,
1822                                          dwc_otg_qtd_t * qtd)
1823 {
1824         DWC_ERROR("--Host Channel %d Interrupt: "
1825                   "Data Toggle Error--\n", hc->hc_num);
1826         if (!hcd->flags.b.port_connect_status) {
1827                 /* No longer connected. */
1828                 DWC_ERROR("Not connected\n");
1829                 return 1;
1830         }
1831         if (hc->ep_is_in) {
1832                 qtd->error_count += 3;//Complete the error URB immediately
1833         } else {
1834                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1835                           "channel %d\n", hc->hc_num);
1836         }
1837         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1838         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1839         clear_hc_int(hc_regs,chhltd);
1840
1841         return 1;
1842 }
1843
1844 #ifdef DEBUG
1845 /**
1846  * This function is for debug only. It checks that a valid halt status is set
1847  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1848  * taken and a warning is issued.
1849  * @return 1 if halt status is ok, 0 otherwise.
1850  */
1851 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
1852                                  dwc_hc_t * hc,
1853                                  dwc_otg_hc_regs_t * hc_regs,
1854                                  dwc_otg_qtd_t * qtd)
1855 {
1856         hcchar_data_t hcchar;
1857         hctsiz_data_t hctsiz;
1858         hcint_data_t hcint;
1859         hcintmsk_data_t hcintmsk;
1860         hcsplt_data_t hcsplt;
1861
1862         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1863                 /*
1864                  * This code is here only as a check. This condition should
1865                  * never happen. Ignore the halt if it does occur.
1866                  */
1867                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1868                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1869                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1870                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1871                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1872                 DWC_WARN
1873                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1874                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1875                      "hcint 0x%08x, hcintmsk 0x%08x, "
1876                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1877                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1878                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1879
1880                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1881                          __func__, hc->hc_num);
1882                 DWC_WARN("\n");
1883                 clear_hc_int(hc_regs, chhltd);
1884                 return 0;
1885         }
1886
1887         /*
1888          * This code is here only as a check. hcchar.chdis should
1889          * never be set when the halt interrupt occurs. Halt the
1890          * channel again if it does occur.
1891          */
1892         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1893         if (hcchar.b.chdis) {
1894                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1895                          "hcchar 0x%08x, trying to halt again\n",
1896                          __func__, hcchar.d32);
1897                 clear_hc_int(hc_regs, chhltd);
1898                 hc->halt_pending = 0;
1899                 halt_channel(hcd, hc, qtd, hc->halt_status);
1900                 return 0;
1901         }
1902
1903         return 1;
1904 }
1905 #endif
1906
1907 /**
1908  * Handles a host Channel Halted interrupt in DMA mode. This handler
1909  * determines the reason the channel halted and proceeds accordingly.
1910  */
1911 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
1912                                       dwc_hc_t * hc,
1913                                       dwc_otg_hc_regs_t * hc_regs,
1914                                       dwc_otg_qtd_t * qtd)
1915 {
1916         hcint_data_t hcint;
1917         hcintmsk_data_t hcintmsk;
1918         int out_nak_enh = 0;
1919
1920         /* For core with OUT NAK enhancement, the flow for high-
1921          * speed CONTROL/BULK OUT is handled a little differently.
1922          */
1923         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1924                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1925                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1926                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1927                         out_nak_enh = 1;
1928                 }
1929         }
1930
1931         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1932             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1933              && !hcd->core_if->dma_desc_enable)) {
1934                 /*
1935                  * Just release the channel. A dequeue can happen on a
1936                  * transfer timeout. In the case of an AHB Error, the channel
1937                  * was forced to halt because there's no way to gracefully
1938                  * recover.
1939                  */
1940                 if (hcd->core_if->dma_desc_enable)
1941                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1942                                                        hc->halt_status);
1943                 else
1944                         release_channel(hcd, hc, qtd, hc->halt_status);
1945                 return;
1946         }
1947
1948         /* Read the HCINTn register to determine the cause for the halt. */
1949         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1950         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1951
1952         if (hcint.b.xfercomp) {
1953                 /** @todo This is here because of a possible hardware bug.  Spec
1954                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1955                  * interrupt w/ACK bit set should occur, but I only see the
1956                  * XFERCOMP bit, even with it masked out.  This is a workaround
1957                  * for that behavior.  Should fix this when hardware is fixed.
1958                  */
1959                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1960                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1961                 }
1962                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1963         } else if (hcint.b.stall) {
1964                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1965         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1966                 if (out_nak_enh) {
1967                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1968                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1969                                 qtd->error_count = 0;
1970                         } else {
1971                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1972                         }
1973                 }
1974
1975                 /*
1976                  * Must handle xacterr before nak or ack. Could get a xacterr
1977                  * at the same time as either of these on a BULK/CONTROL OUT
1978                  * that started with a PING. The xacterr takes precedence.
1979                  */
1980                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1981         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1982                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1983         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1984                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1985         } else if (hcint.b.bblerr) {
1986                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1987         } else if (hcint.b.frmovrun) {
1988                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1989         } else if(hcint.b.datatglerr){
1990         handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
1991         }
1992         else if (!out_nak_enh) {
1993                 if (hcint.b.nyet) {
1994                         /*
1995                          * Must handle nyet before nak or ack. Could get a nyet at the
1996                          * same time as either of those on a BULK/CONTROL OUT that
1997                          * started with a PING. The nyet takes precedence.
1998                          */
1999                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
2000                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
2001                         /*
2002                          * If nak is not masked, it's because a non-split IN transfer
2003                          * is in an error state. In that case, the nak is handled by
2004                          * the nak interrupt handler, not here. Handle nak here for
2005                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2006                          * rewinding the buffer pointer.
2007                          */
2008                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2009                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2010                         /*
2011                          * If ack is not masked, it's because a non-split IN transfer
2012                          * is in an error state. In that case, the ack is handled by
2013                          * the ack interrupt handler, not here. Handle ack here for
2014                          * split transfers. Start splits halt on ACK.
2015                          */
2016                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2017                 } else {
2018                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2019                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2020                                 /*
2021                                  * A periodic transfer halted with no other channel
2022                                  * interrupts set. Assume it was halted by the core
2023                                  * because it could not be completed in its scheduled
2024                                  * (micro)frame.
2025                                  */
2026 #ifdef DEBUG
2027                                 DWC_PRINTF
2028                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2029                                      __func__, hc->hc_num);
2030 #endif
2031                                 halt_channel(hcd, hc, qtd,
2032                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2033                         } else {
2034                                 DWC_ERROR
2035                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2036                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2037                                      __func__, hc->hc_num, hcint.d32,
2038                                      DWC_READ_REG32(&hcd->
2039                                                     core_if->core_global_regs->
2040                                                     gintsts));
2041                                          clear_hc_int(hc_regs,chhltd);
2042                         }
2043
2044                 }
2045         } else {
2046                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2047                            hcint.d32);
2048                 if(!hcint.b.nyet && !hcint.b.nak  && !hcint.b.ack)
2049                         clear_hc_int(hc_regs,chhltd);
2050         }
2051 }
2052
2053 /**
2054  * Handles a host channel Channel Halted interrupt.
2055  *
2056  * In slave mode, this handler is called only when the driver specifically
2057  * requests a halt. This occurs during handling other host channel interrupts
2058  * (e.g. nak, xacterr, stall, nyet, etc.).
2059  *
2060  * In DMA mode, this is the interrupt that occurs when the core has finished
2061  * processing a transfer on a channel. Other host channel interrupts (except
2062  * ahberr) are disabled in DMA mode.
2063  */
2064 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
2065                                      dwc_hc_t * hc,
2066                                      dwc_otg_hc_regs_t * hc_regs,
2067                                      dwc_otg_qtd_t * qtd)
2068 {
2069         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2070                     "Channel Halted--\n", hc->hc_num);
2071
2072         if (hcd->core_if->dma_enable) {
2073                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2074         } else {
2075 #ifdef DEBUG
2076                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2077                         return 1;
2078                 }
2079 #endif
2080                 release_channel(hcd, hc, qtd, hc->halt_status);
2081         }
2082
2083         return 1;
2084 }
2085
2086 /** Handles interrupt for a specific Host Channel */
2087 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
2088 {
2089         int retval = 0;
2090         hcint_data_t hcint;
2091         hcintmsk_data_t hcintmsk;
2092         dwc_hc_t *hc;
2093         dwc_otg_hc_regs_t *hc_regs;
2094         dwc_otg_qtd_t *qtd;
2095
2096         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2097
2098         hc = dwc_otg_hcd->hc_ptr_array[num];
2099         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2100         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2101
2102         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2103         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2104         DWC_DEBUGPL(DBG_HCDV,
2105                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2106                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2107         hcint.d32 = hcint.d32 & hcintmsk.d32;
2108
2109         if (!dwc_otg_hcd->core_if->dma_enable) {
2110                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2111                         hcint.b.chhltd = 0;
2112                 }
2113         }
2114
2115         if (hcint.b.chhltd) {
2116                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2117         }
2118         if (hcint.b.xfercomp) {
2119                 retval |=
2120                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2121                 /*
2122                  * If NYET occurred at same time as Xfer Complete, the NYET is
2123                  * handled by the Xfer Complete interrupt handler. Don't want
2124                  * to call the NYET interrupt handler in this case.
2125                  */
2126                 hcint.b.nyet = 0;
2127         }
2128         if (hcint.b.ahberr) {
2129                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2130         }
2131         if (hcint.b.stall) {
2132                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2133         }
2134         if (hcint.b.nak) {
2135                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2136         }
2137         if (hcint.b.ack) {
2138                 if(!hcint.b.chhltd)
2139                         retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2140         }
2141         if (hcint.b.nyet) {
2142                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2143         }
2144         if (hcint.b.xacterr) {
2145                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2146         }
2147         if (hcint.b.bblerr) {
2148                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2149         }
2150         if (hcint.b.frmovrun) {
2151                 retval |=
2152                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2153         }
2154         if (hcint.b.datatglerr) {
2155                 retval |=
2156                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2157         }
2158
2159         return retval;
2160 }
2161
2162 #endif /* DWC_DEVICE_ONLY */