1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
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19 * below, then you are not authorized to use the Software.
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22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t *hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list))
179 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
180 if (qtd->urb != NULL) {
181 hcd->fops->complete(hcd, qtd->urb->priv,
182 qtd->urb, -DWC_E_SHUTDOWN);
183 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
193 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
194 * and periodic schedules. The QTD associated with each URB is removed from
195 * the schedule and freed. This function may be called when a disconnect is
196 * detected or when the HCD is being stopped.
198 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
200 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
201 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
202 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
203 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
204 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
205 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
209 * Start the connection timer. An OTG host is required to display a
210 * message if the device does not connect within 10 seconds. The
211 * timer is deleted if a port connect interrupt occurs before the
214 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
216 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
220 * HCD Callback function for disconnect of the HCD.
222 * @param p void pointer to the <code>struct usb_hcd</code>
224 static int32_t dwc_otg_hcd_session_start_cb(void *p)
226 dwc_otg_hcd_t *dwc_otg_hcd;
227 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
229 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
234 * HCD Callback function for starting the HCD when A-Cable is
237 * @param p void pointer to the <code>struct usb_hcd</code>
239 static int32_t dwc_otg_hcd_start_cb(void *p)
241 dwc_otg_hcd_t *dwc_otg_hcd = p;
242 dwc_otg_core_if_t *core_if;
244 uint32_t timeout = 50;
246 core_if = dwc_otg_hcd->core_if;
248 if (core_if->op_state == B_HOST) {
250 * Reset the port. During a HNP mode switch the reset
251 * needs to occur within 1ms and have a duration of at
254 hprt0.d32 = dwc_otg_read_hprt0(core_if);
256 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
257 if (core_if->otg_ver) {
259 hprt0.d32 = dwc_otg_read_hprt0(core_if);
261 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
264 /**@todo vahrama: Check the timeout value for OTG 2.0 */
265 if (core_if->otg_ver)
267 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
268 hcd_start_func, dwc_otg_hcd, timeout,
275 * HCD Callback function for disconnect of the HCD.
277 * @param p void pointer to the <code>struct usb_hcd</code>
279 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
282 dwc_otg_hcd_t *dwc_otg_hcd = p;
285 dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
286 dwc_otg_hcd->non_periodic_channels = 0;
287 dwc_otg_hcd->periodic_channels = 0;
288 dwc_otg_hcd->frame_number =0;
290 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
291 /* In some case, we don't disconnect a usb device, but
292 * disconnect intr was triggered, so check hprt0 here. */
293 if (((!hprt0.b.prtenchng)
294 && (!hprt0.b.prtconndet)
295 && hprt0.b.prtconnsts)
296 || !hprt0.b.prtenchng) {
297 DWC_PRINTF("%s: Invalid disconnect interrupt "
298 "hprt0 = 0x%08x\n", __func__, hprt0.d32);
302 * Set status flags for the hub driver.
304 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
305 dwc_otg_hcd->flags.b.port_connect_status = 0;
308 * Shutdown any transfers in process by clearing the Tx FIFO Empty
309 * interrupt mask and status bits and disabling subsequent host
310 * channel interrupts.
313 intr.b.nptxfempty = 1;
314 intr.b.ptxfempty = 1;
316 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
318 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
322 * Turn off the vbus power only if the core has transitioned to device
323 * mode. If still in host mode, need to keep power on to detect a
326 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
327 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
328 hprt0_data_t hprt0 = {.d32 = 0 };
329 DWC_PRINTF("Disconnect: PortPower off\n");
331 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
334 /** Delete timers if become device */
335 del_timers(dwc_otg_hcd);
336 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
340 /* Respond with an error status to all URBs in the schedule. */
341 kill_all_urbs(dwc_otg_hcd);
343 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
344 /* Clean up any host channels that were in use. */
348 dwc_otg_hc_regs_t *hc_regs;
349 hcchar_data_t hcchar;
351 DWC_PRINTF("Disconnect cb-Host\n");
352 if (dwc_otg_hcd->core_if->otg_ver == 1)
353 del_xfer_timers(dwc_otg_hcd);
355 del_timers(dwc_otg_hcd);
357 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
359 if (!dwc_otg_hcd->core_if->dma_enable) {
360 /* Flush out any channel requests in slave mode. */
361 for (i = 0; i < num_channels; i++) {
362 channel = dwc_otg_hcd->hc_ptr_array[i];
363 if (DWC_CIRCLEQ_EMPTY_ENTRY
364 (channel, hc_list_entry)) {
366 dwc_otg_hcd->core_if->host_if->
369 DWC_READ_REG32(&hc_regs->hcchar);
382 for (i = 0; i < num_channels; i++) {
383 channel = dwc_otg_hcd->hc_ptr_array[i];
384 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
386 dwc_otg_hcd->core_if->host_if->hc_regs[i];
387 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
389 /* Halt the channel. */
391 DWC_WRITE_REG32(&hc_regs->hcchar,
395 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
397 DWC_CIRCLEQ_INSERT_TAIL
398 (&dwc_otg_hcd->free_hc_list, channel,
401 * Added for Descriptor DMA to prevent channel double cleanup
402 * in release_channel_ddma(). Which called from ep_disable
403 * when device disconnect.
411 if (dwc_otg_hcd->fops->disconnect) {
412 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
419 * HCD Callback function for stopping the HCD.
421 * @param p void pointer to the <code>struct usb_hcd</code>
423 static int32_t dwc_otg_hcd_stop_cb(void *p)
425 dwc_otg_hcd_t *dwc_otg_hcd = p;
427 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
428 dwc_otg_hcd_stop(dwc_otg_hcd);
432 #ifdef CONFIG_USB_DWC_OTG_LPM
434 * HCD Callback function for sleep of HCD.
436 * @param p void pointer to the <code>struct usb_hcd</code>
438 static int dwc_otg_hcd_sleep_cb(void *p)
440 dwc_otg_hcd_t *hcd = p;
442 dwc_otg_hcd_free_hc_from_lpm(hcd);
449 * HCD Callback function for Remote Wakeup.
451 * @param p void pointer to the <code>struct usb_hcd</code>
453 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
455 dwc_otg_hcd_t *dwc_otg_hcd = p;
456 struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
458 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
459 dwc_otg_hcd->flags.b.port_suspend_change = 1;
460 usb_hcd_resume_root_hub(hcd);
462 #ifdef CONFIG_USB_DWC_OTG_LPM
464 dwc_otg_hcd->flags.b.port_l1_change = 1;
471 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
474 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
476 hprt0_data_t hprt0 = {.d32 = 0 };
477 struct dwc_otg_platform_data *pldata;
478 dwc_irqflags_t flags;
480 pldata = hcd->core_if->otg_dev->pldata;
481 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
484 * Set status flags for the hub driver.
486 hcd->flags.b.port_connect_status_change = 1;
487 hcd->flags.b.port_connect_status = 0;
490 * The root hub should be disconnected before this function is called.
491 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
492 * and the QH lists (via ..._hcd_endpoint_disable).
494 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
495 /* Turn off all host-specific interrupts. */
496 dwc_otg_disable_host_interrupts(hcd->core_if);
499 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
501 /* Turn off the vbus power */
502 DWC_PRINTF("PortPower off\n");
504 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
506 if (pldata->power_enable)
507 pldata->power_enable(0);
512 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
513 dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
516 dwc_irqflags_t flags;
519 gintmsk_data_t intr_mask = {.d32 = 0 };
521 if (!hcd->flags.b.port_connect_status) {
522 /* No longer connected. */
523 DWC_DEBUG("Not connected\n");
524 return -DWC_E_NO_DEVICE;
527 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
529 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
530 return -DWC_E_NO_MEMORY;
532 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
534 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
537 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
538 "Error status %d\n", retval);
539 dwc_otg_hcd_qtd_free(qtd);
542 DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
543 if (!intr_mask.b.sofintr && retval == 0) {
544 dwc_otg_transaction_type_e tr_type;
545 if ((qtd->qh->ep_type == UE_BULK)
546 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
547 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
551 tr_type = dwc_otg_hcd_select_transactions(hcd);
552 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
553 dwc_otg_hcd_queue_transactions(hcd, tr_type);
557 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
561 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
562 dwc_otg_hcd_urb_t *dwc_otg_urb)
565 dwc_otg_qtd_t *urb_qtd;
567 urb_qtd = dwc_otg_urb->qtd;
569 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
570 __func__, urb_qtd, dwc_otg_urb);
575 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
576 if (urb_qtd->in_process) {
577 dump_channel_info(hcd, qh);
581 if (urb_qtd->in_process && qh->channel) {
582 /* The QTD is in process (it has been assigned to a channel). */
583 if (hcd->flags.b.port_connect_status) {
585 * If still connected (i.e. in host mode), halt the
586 * channel so it can be used for other transfers. If
587 * no longer connected, the host registers can't be
588 * written to halt the channel since the core is in
591 dwc_otg_hc_halt(hcd->core_if, qh->channel,
592 DWC_OTG_HC_XFER_URB_DEQUEUE);
597 * Free the QTD and clean up the associated QH. Leave the QH in the
598 * schedule if it has any remaining QTDs.
601 if (!hcd->core_if->dma_desc_enable) {
602 uint8_t b = urb_qtd->in_process;
603 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
605 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
607 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
608 dwc_otg_hcd_qh_remove(hcd, qh);
611 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
616 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
619 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
621 dwc_irqflags_t flags;
624 retval = -DWC_E_INVALID;
629 retval = -DWC_E_INVALID;
633 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
635 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
636 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
639 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
642 dwc_otg_hcd_qh_remove(hcd, qh);
644 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
646 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
647 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
648 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
649 * and dwc_otg_hcd_frame_list_alloc().
651 dwc_otg_hcd_qh_free(hcd, qh);
657 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
658 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
661 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
663 return -DWC_E_INVALID;
665 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
671 * HCD Callback structure for handling mode switching.
673 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
674 .start = dwc_otg_hcd_start_cb,
675 .stop = dwc_otg_hcd_stop_cb,
676 .disconnect = dwc_otg_hcd_disconnect_cb,
677 .session_start = dwc_otg_hcd_session_start_cb,
678 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
679 #ifdef CONFIG_USB_DWC_OTG_LPM
680 .sleep = dwc_otg_hcd_sleep_cb,
686 * Reset tasklet function
688 static void reset_tasklet_func(void *data)
690 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
691 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
694 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
696 hprt0.d32 = dwc_otg_read_hprt0(core_if);
698 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
702 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
703 dwc_otg_hcd->flags.b.port_reset_change = 1;
706 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
708 dwc_list_link_t *item;
710 dwc_irqflags_t flags;
712 if (!qh_list->next) {
713 /* The list hasn't been initialized yet. */
717 * Hold spinlock here. Not needed in that case if bellow
718 * function is being called from ISR
720 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
721 /* Ensure there are no QTDs or URBs left. */
722 kill_urbs_in_qh_list(hcd, qh_list);
723 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
725 DWC_LIST_FOREACH(item, qh_list) {
726 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
727 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
732 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
733 * Device during SRP time by host power up.
735 void dwc_otg_hcd_power_up(void *ptr)
737 gpwrdn_data_t gpwrdn = {.d32 = 0 };
738 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
740 DWC_PRINTF("%s called\n", __FUNCTION__);
742 if (!core_if->hibernation_suspend) {
743 DWC_PRINTF("Already exited from Hibernation\n");
747 /* Switch on the voltage to the core */
748 gpwrdn.b.pwrdnswtch = 1;
749 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
754 gpwrdn.b.pwrdnrstn = 1;
755 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
758 /* Disable power clamps */
760 gpwrdn.b.pwrdnclmp = 1;
761 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
763 /* Remove reset the core signal */
765 gpwrdn.b.pwrdnrstn = 1;
766 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
769 /* Disable PMU interrupt */
771 gpwrdn.b.pmuintsel = 1;
772 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
774 core_if->hibernation_suspend = 0;
778 gpwrdn.b.pmuactv = 1;
779 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
784 gpwrdn.b.dis_vbus = 1;
785 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
787 core_if->op_state = A_HOST;
788 dwc_otg_core_init(core_if);
789 dwc_otg_enable_global_interrupts(core_if);
790 cil_hcd_start(core_if);
794 * Frees secondary storage associated with the dwc_otg_hcd structure contained
795 * in the struct usb_hcd field.
797 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
801 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
803 del_timers(dwc_otg_hcd);
805 /* Free memory for QH/QTD lists */
806 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
807 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
808 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
809 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
810 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
811 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
813 /* Free memory for the host channels. */
814 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
815 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
818 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
819 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
823 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
829 if (dwc_otg_hcd->core_if->dma_enable) {
830 if (dwc_otg_hcd->status_buf_dma) {
831 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
832 dwc_otg_hcd->status_buf,
833 dwc_otg_hcd->status_buf_dma);
835 } else if (dwc_otg_hcd->status_buf != NULL) {
836 DWC_FREE(dwc_otg_hcd->status_buf);
838 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
839 /* Set core_if's lock pointer to NULL */
840 dwc_otg_hcd->core_if->lock = NULL;
842 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
843 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
845 #ifdef DWC_DEV_SRPCAP
846 if (dwc_otg_hcd->core_if->power_down == 2 &&
847 dwc_otg_hcd->core_if->pwron_timer) {
848 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
851 DWC_FREE(dwc_otg_hcd);
854 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
861 hcd->lock = DWC_SPINLOCK_ALLOC();
863 DWC_ERROR("Could not allocate lock for pcd");
865 retval = -DWC_E_NO_MEMORY;
868 hcd->core_if = core_if;
870 /* Register the HCD CIL Callbacks */
871 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
872 &hcd_cil_callbacks, hcd);
874 /* Initialize the non-periodic schedule. */
875 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
876 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
878 /* Initialize the periodic schedule. */
879 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
880 DWC_LIST_INIT(&hcd->periodic_sched_ready);
881 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
882 DWC_LIST_INIT(&hcd->periodic_sched_queued);
885 * Create a host channel descriptor for each host channel implemented
886 * in the controller. Initialize the channel descriptor array.
888 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
889 num_channels = hcd->core_if->core_params->host_channels;
890 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
891 for (i = 0; i < num_channels; i++) {
892 channel = DWC_ALLOC(sizeof(dwc_hc_t));
893 if (channel == NULL) {
894 retval = -DWC_E_NO_MEMORY;
895 DWC_ERROR("%s: host channel allocation failed\n",
897 dwc_otg_hcd_free(hcd);
901 hcd->hc_ptr_array[i] = channel;
903 hcd->core_if->hc_xfer_timer[i] =
904 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
905 &hcd->core_if->hc_xfer_info[i]);
907 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
911 /* Initialize the Connection timeout timer. */
912 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
913 dwc_otg_hcd_connect_timeout, hcd);
915 /* Initialize reset tasklet. */
917 DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
918 #ifdef DWC_DEV_SRPCAP
919 if (hcd->core_if->power_down == 2) {
920 /* Initialize Power on timer for Host power up in case hibernation */
921 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
922 dwc_otg_hcd_power_up,
928 * Allocate space for storing data on status transactions. Normally no
929 * data is sent, but this space acts as a bit bucket. This must be
930 * done after usb_add_hcd since that function allocates the DMA buffer
933 if (hcd->core_if->dma_enable) {
935 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
936 &hcd->status_buf_dma);
938 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
940 if (!hcd->status_buf) {
941 retval = -DWC_E_NO_MEMORY;
942 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
943 dwc_otg_hcd_free(hcd);
948 hcd->frame_list = NULL;
949 hcd->frame_list_dma = 0;
950 hcd->periodic_qh_count = 0;
955 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
957 /* Turn off all host-specific interrupts. */
958 dwc_otg_disable_host_interrupts(hcd->core_if);
960 dwc_otg_hcd_free(hcd);
964 * Initializes dynamic portions of the DWC_otg HCD state.
966 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
971 dwc_hc_t *channel_tmp;
972 dwc_irqflags_t flags;
973 dwc_spinlock_t *temp_lock;
976 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
977 hcd->non_periodic_channels = 0;
978 hcd->periodic_channels = 0;
980 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
982 * Put all channels in the free channel list and clean up channel
985 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
986 &hcd->free_hc_list, hc_list_entry) {
987 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
990 num_channels = hcd->core_if->core_params->host_channels;
991 for (i = 0; i < num_channels; i++) {
992 channel = hcd->hc_ptr_array[i];
993 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
995 dwc_otg_hc_cleanup(hcd->core_if, channel);
997 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
998 /* Initialize the DWC core for host mode operation. */
999 dwc_otg_core_host_init(hcd->core_if);
1001 /* Set core_if's lock pointer to the hcd->lock */
1002 /* Should get this lock before modify it */
1003 if (hcd->core_if->lock) {
1004 DWC_SPINLOCK_IRQSAVE(hcd->core_if->lock, &flags);
1005 temp_lock = hcd->core_if->lock;
1006 hcd->core_if->lock = hcd->lock;
1007 DWC_SPINUNLOCK_IRQRESTORE(temp_lock, flags);
1009 hcd->core_if->lock = hcd->lock;
1014 * Assigns transactions from a QTD to a free host channel and initializes the
1015 * host channel to perform the transactions. The host channel is removed from
1018 * @param hcd The HCD state structure.
1019 * @param qh Transactions from the first QTD for this QH are selected and
1020 * assigned to a free host channel.
1022 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1026 dwc_otg_hcd_urb_t *urb;
1030 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1032 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1034 /* Remove the host channel from the free list. */
1035 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1037 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1041 printk("%s : urb is NULL\n", __func__);
1048 qtd->in_process = 1;
1051 * Use usb_pipedevice to determine device address. This address is
1052 * 0 before the SET_ADDRESS command and the correct address afterward.
1054 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1055 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1056 hc->speed = qh->dev_speed;
1057 hc->max_packet = dwc_max_packet(qh->maxp);
1059 hc->xfer_started = 0;
1060 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1061 hc->error_state = (qtd->error_count > 0);
1062 hc->halt_on_queue = 0;
1063 hc->halt_pending = 0;
1067 * The following values may be modified in the transfer type section
1068 * below. The xfer_len value may be reduced when the transfer is
1069 * started to accommodate the max widths of the XferSize and PktCnt
1070 * fields in the HCTSIZn register.
1073 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1077 hc->do_ping = qh->ping_state;
1079 hc->data_pid_start = qh->data_toggle;
1080 hc->multi_count = 1;
1082 if (hcd->core_if->dma_enable) {
1083 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1085 /* For non-dword aligned case */
1086 if (((unsigned long)hc->xfer_buff & 0x3)
1087 && !hcd->core_if->dma_desc_enable) {
1088 ptr = (uint8_t *) urb->buf + urb->actual_length;
1091 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1093 hc->xfer_len = urb->length - urb->actual_length;
1097 * Set the split attributes
1102 uint32_t hub_addr, port_addr;
1104 hc->xact_pos = qtd->isoc_split_pos;
1105 hc->complete_split = qtd->complete_split;
1106 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1107 hc->hub_addr = (uint8_t) hub_addr;
1108 hc->port_addr = (uint8_t) port_addr;
1111 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1113 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1114 switch (qtd->control_phase) {
1115 case DWC_OTG_CONTROL_SETUP:
1116 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1119 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1120 if (hcd->core_if->dma_enable)
1121 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1123 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1128 case DWC_OTG_CONTROL_DATA:
1129 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1130 hc->data_pid_start = qtd->data_toggle;
1132 case DWC_OTG_CONTROL_STATUS:
1134 * Direction is opposite of data direction or IN if no
1137 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1138 if (urb->length == 0) {
1142 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1147 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1150 if (hcd->core_if->dma_enable)
1151 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1153 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1160 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1163 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1165 case UE_ISOCHRONOUS:
1167 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1169 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1171 if (hcd->core_if->dma_desc_enable)
1174 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1176 frame_desc->status = 0;
1178 if (hcd->core_if->dma_enable) {
1179 hc->xfer_buff = (uint8_t *) urb->dma;
1181 hc->xfer_buff = (uint8_t *) urb->buf;
1184 frame_desc->offset + qtd->isoc_split_offset;
1186 frame_desc->length - qtd->isoc_split_offset;
1188 /* For non-dword aligned buffers */
1189 if (((unsigned long)hc->xfer_buff & 0x3)
1190 && hcd->core_if->dma_enable) {
1192 (uint8_t *) urb->buf + frame_desc->offset +
1193 qtd->isoc_split_offset;
1197 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1198 if (hc->xfer_len <= 188) {
1199 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1202 DWC_HCSPLIT_XACTPOS_BEGIN;
1208 /* non DWORD-aligned buffer case */
1211 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1212 buf_size = hcd->core_if->core_params->max_transfer_size;
1216 if (!qh->dw_align_buf) {
1217 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1220 if (!qh->dw_align_buf) {
1222 ("%s: Failed to allocate memory to handle "
1223 "non-dword aligned buffer case\n",
1228 if (!hc->ep_is_in) {
1229 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1231 hc->align_buff = qh->dw_align_buf_dma;
1236 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1237 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1239 * This value may be modified when the transfer is started to
1240 * reflect the actual transfer length.
1242 hc->multi_count = dwc_hb_mult(qh->maxp);
1245 if (hcd->core_if->dma_desc_enable)
1246 hc->desc_list_addr = qh->desc_list_dma;
1248 dwc_otg_hc_init(hcd->core_if, hc);
1254 * This function selects transactions from the HCD transfer schedule and
1255 * assigns them to available host channels. It is called from HCD interrupt
1256 * handler functions.
1258 * @param hcd The HCD state structure.
1260 * @return The types of new transactions that were assigned to host channels.
1262 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1264 dwc_list_link_t *qh_ptr;
1267 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1271 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1274 /* Process entries in the periodic ready list. */
1275 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1277 while (qh_ptr != &hcd->periodic_sched_ready &&
1278 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1280 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1281 assign_and_init_hc(hcd, qh);
1284 * Move the QH from the periodic ready schedule to the
1285 * periodic assigned schedule.
1287 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1288 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1289 &qh->qh_list_entry);
1291 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1295 * Process entries in the inactive portion of the non-periodic
1296 * schedule. Some free host channels may not be used if they are
1297 * reserved for periodic transfers.
1299 qh_ptr = hcd->non_periodic_sched_inactive.next;
1300 num_channels = hcd->core_if->core_params->host_channels;
1301 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1302 (hcd->non_periodic_channels <
1303 num_channels - hcd->periodic_channels) &&
1304 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1306 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1308 err = assign_and_init_hc(hcd, qh);
1311 * Move the QH from the non-periodic inactive schedule to the
1312 * non-periodic active schedule.
1314 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1317 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1318 &qh->qh_list_entry);
1320 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1321 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1323 ret_val = DWC_OTG_TRANSACTION_ALL;
1326 hcd->non_periodic_channels++;
1333 * Attempts to queue a single transaction request for a host channel
1334 * associated with either a periodic or non-periodic transfer. This function
1335 * assumes that there is space available in the appropriate request queue. For
1336 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1337 * is available in the appropriate Tx FIFO.
1339 * @param hcd The HCD state structure.
1340 * @param hc Host channel descriptor associated with either a periodic or
1341 * non-periodic transfer.
1342 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1343 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1346 * @return 1 if a request is queued and more requests may be needed to
1347 * complete the transfer, 0 if no more requests are required for this
1348 * transfer, -1 if there is insufficient space in the Tx FIFO.
1350 static int queue_transaction(dwc_otg_hcd_t *hcd,
1351 dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1354 if (!hc || !(hc->qh))
1356 if (hcd->core_if->dma_enable) {
1357 if (hcd->core_if->dma_desc_enable) {
1358 if (!hc->xfer_started
1359 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1360 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1361 hc->qh->ping_state = 0;
1363 } else if (!hc->xfer_started) {
1364 if (!hc || !(hc->qh))
1366 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1367 hc->qh->ping_state = 0;
1370 } else if (hc->halt_pending) {
1371 /* Don't queue a request if the channel has been halted. */
1373 } else if (hc->halt_on_queue) {
1374 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1376 } else if (hc->do_ping) {
1377 if (!hc->xfer_started) {
1378 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1381 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1382 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1383 if (!hc->xfer_started) {
1384 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1388 dwc_otg_hc_continue_transfer(hcd->core_if,
1395 if (!hc->xfer_started) {
1396 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1399 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1407 * Processes periodic channels for the next frame and queues transactions for
1408 * these channels to the DWC_otg controller. After queueing transactions, the
1409 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1410 * to queue as Periodic Tx FIFO or request queue space becomes available.
1411 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1413 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1415 hptxsts_data_t tx_status;
1416 dwc_list_link_t *qh_ptr;
1419 int no_queue_space = 0;
1420 int no_fifo_space = 0;
1422 dwc_otg_host_global_regs_t *host_regs;
1423 host_regs = hcd->core_if->host_if->host_global_regs;
1425 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1427 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1428 DWC_DEBUGPL(DBG_HCDV,
1429 " P Tx Req Queue Space Avail (before queue): %d\n",
1430 tx_status.b.ptxqspcavail);
1431 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1432 tx_status.b.ptxfspcavail);
1435 qh_ptr = hcd->periodic_sched_assigned.next;
1436 while (qh_ptr != &hcd->periodic_sched_assigned) {
1437 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1438 if (tx_status.b.ptxqspcavail == 0) {
1443 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1446 * Set a flag if we're queuing high-bandwidth in slave mode.
1447 * The flag prevents any halts to get into the request queue in
1448 * the middle of multiple high-bandwidth packets getting queued.
1450 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1451 hcd->core_if->queuing_high_bandwidth = 1;
1454 queue_transaction(hcd, qh->channel,
1455 tx_status.b.ptxfspcavail);
1462 * In Slave mode, stay on the current transfer until there is
1463 * nothing more to do or the high-bandwidth request count is
1464 * reached. In DMA mode, only need to queue one request. The
1465 * controller automatically handles multiple packets for
1466 * high-bandwidth transfers.
1468 if (hcd->core_if->dma_enable || status == 0 ||
1469 qh->channel->requests == qh->channel->multi_count) {
1470 qh_ptr = qh_ptr->next;
1472 * Move the QH from the periodic assigned schedule to
1473 * the periodic queued schedule.
1475 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1476 &qh->qh_list_entry);
1478 /* done queuing high bandwidth */
1479 hcd->core_if->queuing_high_bandwidth = 0;
1483 if (!hcd->core_if->dma_enable) {
1484 dwc_otg_core_global_regs_t *global_regs;
1485 gintmsk_data_t intr_mask = {.d32 = 0 };
1487 global_regs = hcd->core_if->core_global_regs;
1488 intr_mask.b.ptxfempty = 1;
1490 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1491 DWC_DEBUGPL(DBG_HCDV,
1492 " P Tx Req Queue Space Avail (after queue): %d\n",
1493 tx_status.b.ptxqspcavail);
1494 DWC_DEBUGPL(DBG_HCDV,
1495 " P Tx FIFO Space Avail (after queue): %d\n",
1496 tx_status.b.ptxfspcavail);
1498 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1499 no_queue_space || no_fifo_space) {
1501 * May need to queue more transactions as the request
1502 * queue or Tx FIFO empties. Enable the periodic Tx
1503 * FIFO empty interrupt. (Always use the half-empty
1504 * level to ensure that new requests are loaded as
1505 * soon as possible.)
1507 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1511 * Disable the Tx FIFO empty interrupt since there are
1512 * no more transactions that need to be queued right
1513 * now. This function is called from interrupt
1514 * handlers to queue more transactions as transfer
1517 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1524 * Processes active non-periodic channels and queues transactions for these
1525 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1526 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1527 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1528 * FIFO Empty interrupt is disabled.
1530 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1532 gnptxsts_data_t tx_status;
1533 dwc_list_link_t *orig_qh_ptr;
1536 int no_queue_space = 0;
1537 int no_fifo_space = 0;
1540 dwc_otg_core_global_regs_t *global_regs =
1541 hcd->core_if->core_global_regs;
1543 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1545 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1546 DWC_DEBUGPL(DBG_HCDV,
1547 " NP Tx Req Queue Space Avail (before queue): %d\n",
1548 tx_status.b.nptxqspcavail);
1549 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1550 tx_status.b.nptxfspcavail);
1553 * Keep track of the starting point. Skip over the start-of-list
1556 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1557 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1559 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1562 * Process once through the active list or until no more space is
1563 * available in the request queue or the Tx FIFO.
1566 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1567 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1572 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1575 queue_transaction(hcd, qh->channel,
1576 tx_status.b.nptxfspcavail);
1580 } else if (status < 0) {
1585 /* Advance to next QH, skipping start-of-list entry. */
1586 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1587 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1588 hcd->non_periodic_qh_ptr =
1589 hcd->non_periodic_qh_ptr->next;
1592 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1594 if (!hcd->core_if->dma_enable) {
1595 gintmsk_data_t intr_mask = {.d32 = 0 };
1596 intr_mask.b.nptxfempty = 1;
1599 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1600 DWC_DEBUGPL(DBG_HCDV,
1601 " NP Tx Req Queue Space Avail (after queue): %d\n",
1602 tx_status.b.nptxqspcavail);
1603 DWC_DEBUGPL(DBG_HCDV,
1604 " NP Tx FIFO Space Avail (after queue): %d\n",
1605 tx_status.b.nptxfspcavail);
1607 if (more_to_do || no_queue_space || no_fifo_space) {
1609 * May need to queue more transactions as the request
1610 * queue or Tx FIFO empties. Enable the non-periodic
1611 * Tx FIFO empty interrupt. (Always use the half-empty
1612 * level to ensure that new requests are loaded as
1613 * soon as possible.)
1615 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1619 * Disable the Tx FIFO empty interrupt since there are
1620 * no more transactions that need to be queued right
1621 * now. This function is called from interrupt
1622 * handlers to queue more transactions as transfer
1625 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1632 * This function processes the currently active host channels and queues
1633 * transactions for these channels to the DWC_otg controller. It is called
1634 * from HCD interrupt handler functions.
1636 * @param hcd The HCD state structure.
1637 * @param tr_type The type(s) of transactions to queue (non-periodic,
1638 * periodic, or both).
1640 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1641 dwc_otg_transaction_type_e tr_type)
1644 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1646 /* Process host channels associated with periodic transfers. */
1647 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1648 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1649 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1651 process_periodic_channels(hcd);
1654 /* Process host channels associated with non-periodic transfers. */
1655 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1656 tr_type == DWC_OTG_TRANSACTION_ALL) {
1657 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1658 process_non_periodic_channels(hcd);
1661 * Ensure NP Tx FIFO empty interrupt is disabled when
1662 * there are no non-periodic transfers to process.
1664 gintmsk_data_t gintmsk = {.d32 = 0 };
1665 gintmsk.b.nptxfempty = 1;
1666 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1667 gintmsk, gintmsk.d32, 0);
1672 #ifdef DWC_HS_ELECT_TST
1674 * Quick and dirty hack to implement the HS Electrical Test
1675 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1677 * This code was copied from our userspace app "hset". It sends a
1678 * Get Device Descriptor control sequence in two parts, first the
1679 * Setup packet by itself, followed some time later by the In and
1680 * Ack packets. Rather than trying to figure out how to add this
1681 * functionality to the normal driver code, we just hijack the
1682 * hardware, using these two function to drive the hardware
1686 static dwc_otg_core_global_regs_t *global_regs;
1687 static dwc_otg_host_global_regs_t *hc_global_regs;
1688 static dwc_otg_hc_regs_t *hc_regs;
1689 static uint32_t *data_fifo;
1691 static void do_setup(void)
1693 gintsts_data_t gintsts;
1694 hctsiz_data_t hctsiz;
1695 hcchar_data_t hcchar;
1700 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1703 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1706 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1709 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1712 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1715 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1718 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1721 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1724 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1727 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1730 * Send Setup packet (Get Device Descriptor)
1733 /* Make sure channel is disabled */
1734 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1735 if (hcchar.b.chen) {
1737 /* hcchar.b.chen = 1; */
1738 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1743 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1746 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1749 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1752 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1755 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1758 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1761 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1763 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1768 hctsiz.b.xfersize = 8;
1769 hctsiz.b.pktcnt = 1;
1770 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1771 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1774 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1775 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1780 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1782 /* Fill FIFO with Setup data for Get Device Descriptor */
1783 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1784 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1785 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1787 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1789 /* Wait for host channel interrupt */
1791 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1792 } while (gintsts.b.hcintr == 0);
1794 /* Disable HCINTs */
1795 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1797 /* Disable HAINTs */
1798 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1801 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1804 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1807 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1810 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1813 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1816 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1819 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1822 static void do_in_ack(void)
1824 gintsts_data_t gintsts;
1825 hctsiz_data_t hctsiz;
1826 hcchar_data_t hcchar;
1829 host_grxsts_data_t grxsts;
1832 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1835 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1838 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1841 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1844 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1847 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1850 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1853 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1856 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1859 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1862 * Receive Control In packet
1865 /* Make sure channel is disabled */
1866 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1867 if (hcchar.b.chen) {
1870 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1875 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1878 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1881 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1884 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1887 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1890 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1893 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1895 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1900 hctsiz.b.xfersize = 8;
1901 hctsiz.b.pktcnt = 1;
1902 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1903 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1906 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1907 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1912 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1914 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1916 /* Wait for receive status queue interrupt */
1918 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1919 } while (gintsts.b.rxstsqlvl == 0);
1922 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1924 /* Clear RXSTSQLVL in GINTSTS */
1926 gintsts.b.rxstsqlvl = 1;
1927 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1929 switch (grxsts.b.pktsts) {
1930 case DWC_GRXSTS_PKTSTS_IN:
1931 /* Read the data into the host buffer */
1932 if (grxsts.b.bcnt > 0) {
1934 int word_count = (grxsts.b.bcnt + 3) / 4;
1936 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1938 for (i = 0; i < word_count; i++) {
1939 (void)DWC_READ_REG32(data_fifo++);
1948 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1950 /* Wait for receive status queue interrupt */
1952 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1953 } while (gintsts.b.rxstsqlvl == 0);
1956 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1958 /* Clear RXSTSQLVL in GINTSTS */
1960 gintsts.b.rxstsqlvl = 1;
1961 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1963 switch (grxsts.b.pktsts) {
1964 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1971 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1973 /* Wait for host channel interrupt */
1975 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1976 } while (gintsts.b.hcintr == 0);
1979 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1982 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1985 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1988 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1991 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1994 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1997 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1999 /* usleep(100000); */
2004 * Send handshake packet
2008 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2011 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2014 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2017 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2020 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2023 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2026 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2028 /* Make sure channel is disabled */
2029 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2030 if (hcchar.b.chen) {
2033 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2038 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2041 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2044 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2047 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2050 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2053 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2056 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2058 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2063 hctsiz.b.xfersize = 0;
2064 hctsiz.b.pktcnt = 1;
2065 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2066 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2069 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2070 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2075 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2077 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2079 /* Wait for host channel interrupt */
2081 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2082 } while (gintsts.b.hcintr == 0);
2084 /* Disable HCINTs */
2085 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2087 /* Disable HAINTs */
2088 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2091 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2094 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2097 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2100 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2103 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2106 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2109 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2113 /** Handles hub class-specific requests. */
2114 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2117 uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2121 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2122 usb_hub_descriptor_t *hub_desc;
2123 hprt0_data_t hprt0 = {.d32 = 0 };
2125 uint32_t port_status;
2128 case UCR_CLEAR_HUB_FEATURE:
2129 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2130 "ClearHubFeature 0x%x\n", wValue);
2132 case UHF_C_HUB_LOCAL_POWER:
2133 case UHF_C_HUB_OVER_CURRENT:
2134 /* Nothing required here */
2137 retval = -DWC_E_INVALID;
2138 DWC_ERROR("DWC OTG HCD - "
2139 "ClearHubFeature request %xh unknown\n",
2143 case UCR_CLEAR_PORT_FEATURE:
2144 #ifdef CONFIG_USB_DWC_OTG_LPM
2145 if (wValue != UHF_PORT_L1)
2147 if (!wIndex || wIndex > 1)
2151 case UHF_PORT_ENABLE:
2152 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2153 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2154 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2156 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2158 case UHF_PORT_SUSPEND:
2159 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2160 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2162 if (core_if->power_down == 2) {
2163 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2165 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2168 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2170 DWC_WRITE_REG32(core_if->host_if->hprt0,
2172 hprt0.b.prtsusp = 0;
2173 /* Clear Resume bit */
2176 DWC_WRITE_REG32(core_if->host_if->hprt0,
2180 #ifdef CONFIG_USB_DWC_OTG_LPM
2183 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2184 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2187 DWC_READ_REG32(&core_if->core_global_regs->
2189 lpmcfg.b.en_utmi_sleep = 0;
2190 lpmcfg.b.hird_thres &= (~(1 << 4));
2191 lpmcfg.b.prt_sleep_sts = 1;
2192 DWC_WRITE_REG32(&core_if->core_global_regs->
2193 glpmcfg, lpmcfg.d32);
2195 /* Clear Enbl_L1Gating bit. */
2196 pcgcctl.b.enbl_sleep_gating = 1;
2197 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2202 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2204 DWC_WRITE_REG32(core_if->host_if->hprt0,
2206 /* This bit will be cleared in wakeup interrupt handle */
2210 case UHF_PORT_POWER:
2211 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2212 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2213 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2215 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2217 case UHF_PORT_INDICATOR:
2218 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2219 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2220 /* Port inidicator not supported */
2222 case UHF_C_PORT_CONNECTION:
2223 /* Clears drivers internal connect status change
2225 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2226 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2227 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2229 case UHF_C_PORT_RESET:
2230 /* Clears the driver's internal Port Reset Change
2232 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2233 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2234 dwc_otg_hcd->flags.b.port_reset_change = 0;
2236 case UHF_C_PORT_ENABLE:
2237 /* Clears the driver's internal Port
2238 * Enable/Disable Change flag */
2239 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2240 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2241 dwc_otg_hcd->flags.b.port_enable_change = 0;
2243 case UHF_C_PORT_SUSPEND:
2244 /* Clears the driver's internal Port Suspend
2245 * Change flag, which is set when resume signaling on
2246 * the host port is complete */
2247 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2248 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2249 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2251 #ifdef CONFIG_USB_DWC_OTG_LPM
2253 dwc_otg_hcd->flags.b.port_l1_change = 0;
2256 case UHF_C_PORT_OVER_CURRENT:
2257 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2258 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2259 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2262 retval = -DWC_E_INVALID;
2263 DWC_ERROR("DWC OTG HCD - "
2264 "ClearPortFeature request %xh "
2265 "unknown or unsupported\n", wValue);
2268 case UCR_GET_HUB_DESCRIPTOR:
2269 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2270 "GetHubDescriptor\n");
2271 hub_desc = (usb_hub_descriptor_t *) buf;
2272 hub_desc->bDescLength = 9;
2273 hub_desc->bDescriptorType = 0x29;
2274 hub_desc->bNbrPorts = 1;
2275 USETW(hub_desc->wHubCharacteristics, 0x08);
2276 hub_desc->bPwrOn2PwrGood = 1;
2277 hub_desc->bHubContrCurrent = 0;
2278 hub_desc->DeviceRemovable[0] = 0;
2279 hub_desc->DeviceRemovable[1] = 0xff;
2281 case UCR_GET_HUB_STATUS:
2282 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2284 DWC_MEMSET(buf, 0, 4);
2286 case UCR_GET_PORT_STATUS:
2287 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2288 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2289 wIndex, dwc_otg_hcd->flags.d32);
2290 if (!wIndex || wIndex > 1)
2295 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2296 port_status |= (1 << UHF_C_PORT_CONNECTION);
2298 if (dwc_otg_hcd->flags.b.port_enable_change)
2299 port_status |= (1 << UHF_C_PORT_ENABLE);
2301 if (dwc_otg_hcd->flags.b.port_suspend_change)
2302 port_status |= (1 << UHF_C_PORT_SUSPEND);
2304 if (dwc_otg_hcd->flags.b.port_l1_change)
2305 port_status |= (1 << UHF_C_PORT_L1);
2307 if (dwc_otg_hcd->flags.b.port_reset_change) {
2308 port_status |= (1 << UHF_C_PORT_RESET);
2311 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2312 DWC_WARN("Overcurrent change detected\n");
2313 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2316 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2318 * The port is disconnected, which means the core is
2319 * either in device mode or it soon will be. Just
2320 * return 0's for the remainder of the port status
2321 * since the port register can't be read if the core
2322 * is in device mode.
2324 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2328 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2329 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2331 if (hprt0.b.prtconnsts)
2332 port_status |= (1 << UHF_PORT_CONNECTION);
2335 port_status |= (1 << UHF_PORT_ENABLE);
2337 if (hprt0.b.prtsusp)
2338 port_status |= (1 << UHF_PORT_SUSPEND);
2340 if (hprt0.b.prtovrcurract)
2341 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2344 port_status |= (1 << UHF_PORT_RESET);
2347 port_status |= (1 << UHF_PORT_POWER);
2349 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2350 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2351 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2352 port_status |= (1 << UHF_PORT_LOW_SPEED);
2354 if (hprt0.b.prttstctl)
2355 port_status |= (1 << UHF_PORT_TEST);
2356 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2357 port_status |= (1 << UHF_PORT_L1);
2360 For Synopsys HW emulation of Power down wkup_control asserts the
2361 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2362 We intentionally tell the software that port is in L2Suspend state.
2365 if ((core_if->power_down == 2)
2366 && (core_if->hibernation_suspend == 1)) {
2367 port_status |= (1 << UHF_PORT_SUSPEND);
2369 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2371 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2374 case UCR_SET_HUB_FEATURE:
2375 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2377 /* No HUB features supported */
2379 case UCR_SET_PORT_FEATURE:
2380 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2383 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2385 * The port is disconnected, which means the core is
2386 * either in device mode or it soon will be. Just
2387 * return without doing anything since the port
2388 * register can't be written if the core is in device
2395 case UHF_PORT_SUSPEND:
2396 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2397 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2398 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2401 if (core_if->power_down == 2) {
2403 dwc_irqflags_t flags;
2404 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2405 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2406 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2407 #ifdef DWC_DEV_SRPCAP
2408 int32_t otg_cap_param =
2409 core_if->core_params->otg_cap;
2412 ("Preparing for complete power-off\n");
2414 /* Save registers before hibernation */
2415 dwc_otg_save_global_regs(core_if);
2416 dwc_otg_save_host_regs(core_if);
2418 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2419 hprt0.b.prtsusp = 1;
2421 DWC_WRITE_REG32(core_if->host_if->hprt0,
2423 /* Spin hprt0.b.prtsusp to became 1 */
2425 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2426 if (hprt0.b.prtsusp) {
2430 } while (--timeout);
2432 DWC_WARN("Suspend wasn't genereted\n");
2437 * We need to disable interrupts to prevent servicing of any IRQ
2438 * during going to hibernation
2440 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2441 core_if->lx_state = DWC_OTG_L2;
2442 #ifdef DWC_DEV_SRPCAP
2443 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2446 DWC_WRITE_REG32(core_if->host_if->hprt0,
2450 DWC_READ_REG32(&core_if->
2451 core_global_regs->gusbcfg);
2452 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2453 /* ULPI interface */
2454 /* Suspend the Phy Clock */
2456 pcgcctl.b.stoppclk = 1;
2457 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2460 gpwrdn.b.pmuactv = 1;
2462 (&core_if->core_global_regs->gpwrdn,
2465 /* UTMI+ Interface */
2466 gpwrdn.b.pmuactv = 1;
2468 (&core_if->core_global_regs->gpwrdn,
2471 pcgcctl.b.stoppclk = 1;
2472 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2476 #ifdef DWC_DEV_SRPCAP
2478 gpwrdn.b.dis_vbus = 1;
2479 DWC_MODIFY_REG32(&core_if->
2480 core_global_regs->gpwrdn, 0,
2484 gpwrdn.b.pmuintsel = 1;
2485 DWC_MODIFY_REG32(&core_if->
2486 core_global_regs->gpwrdn, 0,
2491 #ifdef DWC_DEV_SRPCAP
2492 gpwrdn.b.srp_det_msk = 1;
2494 gpwrdn.b.disconn_det_msk = 1;
2495 gpwrdn.b.lnstchng_msk = 1;
2496 gpwrdn.b.sts_chngint_msk = 1;
2497 DWC_MODIFY_REG32(&core_if->
2498 core_global_regs->gpwrdn, 0,
2502 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2504 gpwrdn.b.pwrdnclmp = 1;
2505 DWC_MODIFY_REG32(&core_if->
2506 core_global_regs->gpwrdn, 0,
2510 /* Switch off VDD */
2512 gpwrdn.b.pwrdnswtch = 1;
2513 DWC_MODIFY_REG32(&core_if->
2514 core_global_regs->gpwrdn, 0,
2517 #ifdef DWC_DEV_SRPCAP
2518 if (otg_cap_param ==
2519 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2520 core_if->pwron_timer_started = 1;
2521 DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2525 /* Save gpwrdn register for further usage if stschng interrupt */
2526 core_if->gr_backup->gpwrdn_local =
2527 DWC_READ_REG32(&core_if->core_global_regs->
2530 /* Set flag to indicate that we are in hibernation */
2531 core_if->hibernation_suspend = 1;
2532 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2535 DWC_PRINTF("Host hibernation completed\n");
2536 /* Exit from case statement */
2540 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2541 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2542 gotgctl_data_t gotgctl = {.d32 = 0 };
2543 gotgctl.b.hstsethnpen = 1;
2544 DWC_MODIFY_REG32(&core_if->
2545 core_global_regs->gotgctl, 0,
2547 core_if->op_state = A_SUSPEND;
2549 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2550 hprt0.b.prtsusp = 1;
2551 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2553 dwc_irqflags_t flags;
2554 /* Update lx_state */
2555 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2556 core_if->lx_state = DWC_OTG_L2;
2557 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2560 /* Suspend the Phy Clock */
2561 if (core_if->otg_ver == 0) {
2562 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2563 pcgcctl.b.stoppclk = 1;
2564 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2569 /* For HNP the bus must be suspended for at least 200ms. */
2570 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2571 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2572 pcgcctl.b.stoppclk = 1;
2573 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2578 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2580 if (core_if->adp_enable) {
2581 gotgctl_data_t gotgctl = {.d32 = 0 };
2582 gpwrdn_data_t gpwrdn;
2584 while (gotgctl.b.asesvld == 1) {
2587 (&core_if->core_global_regs->gotgctl);
2591 /* Enable Power Down Logic */
2593 gpwrdn.b.pmuactv = 1;
2594 DWC_MODIFY_REG32(&core_if->
2595 core_global_regs->gpwrdn, 0,
2598 /* Unmask SRP detected interrupt from Power Down Logic */
2600 gpwrdn.b.srp_det_msk = 1;
2601 DWC_MODIFY_REG32(&core_if->
2602 core_global_regs->gpwrdn, 0,
2605 dwc_otg_adp_probe_start(core_if);
2609 case UHF_PORT_POWER:
2610 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2611 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2612 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2614 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2616 case UHF_PORT_RESET:
2617 if ((core_if->power_down == 2)
2618 && (core_if->hibernation_suspend == 1)) {
2619 /* If we are going to exit from Hibernated
2620 * state via USB RESET.
2622 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2624 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2626 DWC_DEBUGPL(DBG_HCD,
2627 "DWC OTG HCD HUB CONTROL - "
2628 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2630 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2631 pcgcctl.b.enbl_sleep_gating = 1;
2632 pcgcctl.b.stoppclk = 1;
2633 DWC_MODIFY_REG32(core_if->pcgcctl,
2635 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2637 #ifdef CONFIG_USB_DWC_OTG_LPM
2639 glpmcfg_data_t lpmcfg;
2641 DWC_READ_REG32(&core_if->
2644 if (lpmcfg.b.prt_sleep_sts) {
2645 lpmcfg.b.en_utmi_sleep = 0;
2646 lpmcfg.b.hird_thres &=
2648 DWC_WRITE_REG32(&core_if->
2656 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2657 /* Clear suspend bit if resetting from suspended state. */
2658 hprt0.b.prtsusp = 0;
2659 /* When B-Host the Port reset bit is set in
2660 * the Start HCD Callback function, so that
2661 * the reset is started within 1ms of the HNP
2662 * success interrupt. */
2663 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2667 ("Indeed it is in host mode hprt0 = %08x\n",
2669 DWC_WRITE_REG32(core_if->host_if->hprt0,
2672 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2675 DWC_WRITE_REG32(core_if->host_if->hprt0,
2677 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2680 #ifdef DWC_HS_ELECT_TST
2684 gintmsk_data_t gintmsk;
2686 t = (wIndex >> 8); /* MSB wIndex USB */
2687 DWC_DEBUGPL(DBG_HCD,
2688 "DWC OTG HCD HUB CONTROL - "
2689 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2691 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2693 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2694 hprt0.b.prttstctl = t;
2695 DWC_WRITE_REG32(core_if->host_if->hprt0,
2698 /* Setup global vars with reg addresses (quick and
2699 * dirty hack, should be cleaned up)
2701 global_regs = core_if->core_global_regs;
2703 core_if->host_if->host_global_regs;
2705 (dwc_otg_hc_regs_t *) ((char *)
2709 (uint32_t *) ((char *)global_regs +
2712 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2713 /* Save current interrupt mask */
2716 (&global_regs->gintmsk);
2718 /* Disable all interrupts while we muck with
2719 * the hardware directly
2721 DWC_WRITE_REG32(&global_regs->
2724 /* 15 second delay per the test spec */
2727 /* Drive suspend on the root port */
2729 dwc_otg_read_hprt0(core_if);
2730 hprt0.b.prtsusp = 1;
2732 DWC_WRITE_REG32(core_if->
2736 /* 15 second delay per the test spec */
2739 /* Drive resume on the root port */
2741 dwc_otg_read_hprt0(core_if);
2742 hprt0.b.prtsusp = 0;
2744 DWC_WRITE_REG32(core_if->
2749 /* Clear the resume bit */
2751 DWC_WRITE_REG32(core_if->
2755 /* Restore interrupts */
2756 DWC_WRITE_REG32(&global_regs->
2759 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2760 /* Save current interrupt mask */
2763 (&global_regs->gintmsk);
2765 /* Disable all interrupts while we muck with
2766 * the hardware directly
2768 DWC_WRITE_REG32(&global_regs->
2771 /* 15 second delay per the test spec */
2774 /* Send the Setup packet */
2777 /* 15 second delay so nothing else happens for awhile */
2780 /* Restore interrupts */
2781 DWC_WRITE_REG32(&global_regs->
2784 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2785 /* Save current interrupt mask */
2788 (&global_regs->gintmsk);
2790 /* Disable all interrupts while we muck with
2791 * the hardware directly
2793 DWC_WRITE_REG32(&global_regs->
2796 /* Send the Setup packet */
2799 /* 15 second delay so nothing else happens for awhile */
2802 /* Send the In and Ack packets */
2805 /* 15 second delay so nothing else happens for awhile */
2808 /* Restore interrupts */
2809 DWC_WRITE_REG32(&global_regs->
2816 #endif /* DWC_HS_ELECT_TST */
2818 case UHF_PORT_INDICATOR:
2819 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2820 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2824 retval = -DWC_E_INVALID;
2825 DWC_ERROR("DWC OTG HCD - "
2826 "SetPortFeature request %xh "
2827 "unknown or unsupported\n", wValue);
2831 #ifdef CONFIG_USB_DWC_OTG_LPM
2832 case UCR_SET_AND_TEST_PORT_FEATURE:
2833 if (wValue != UHF_PORT_L1) {
2837 int portnum, hird, devaddr, remwake;
2838 glpmcfg_data_t lpmcfg;
2839 uint32_t time_usecs;
2840 gintsts_data_t gintsts;
2841 gintmsk_data_t gintmsk;
2843 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2846 if (wValue != UHF_PORT_L1 || wLength != 1) {
2849 /* Check if the port currently is in SLEEP state */
2851 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2852 if (lpmcfg.b.prt_sleep_sts) {
2853 DWC_INFO("Port is already in sleep mode\n");
2854 buf[0] = 0; /* Return success */
2858 portnum = wIndex & 0xf;
2859 hird = (wIndex >> 4) & 0xf;
2860 devaddr = (wIndex >> 8) & 0x7f;
2861 remwake = (wIndex >> 15);
2864 retval = -DWC_E_INVALID;
2866 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2872 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2873 portnum, hird, devaddr, remwake);
2874 /* Disable LPM interrupt */
2876 gintmsk.b.lpmtranrcvd = 1;
2877 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2880 if (dwc_otg_hcd_send_lpm
2881 (dwc_otg_hcd, devaddr, hird, remwake)) {
2882 retval = -DWC_E_INVALID;
2886 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2887 /* We will consider timeout if time_usecs microseconds pass,
2888 * and we don't receive LPM transaction status.
2889 * After receiving non-error responce(ACK/NYET/STALL) from device,
2890 * core will set lpmtranrcvd bit.
2894 DWC_READ_REG32(&core_if->core_global_regs->
2896 if (gintsts.b.lpmtranrcvd) {
2900 } while (--time_usecs);
2901 /* lpm_int bit will be cleared in LPM interrupt handler */
2908 if (!gintsts.b.lpmtranrcvd) {
2909 buf[0] = 0x3; /* Completion code is Timeout */
2910 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2913 DWC_READ_REG32(&core_if->core_global_regs->
2915 if (lpmcfg.b.lpm_resp == 0x3) {
2916 /* ACK responce from the device */
2917 buf[0] = 0x00; /* Success */
2918 } else if (lpmcfg.b.lpm_resp == 0x2) {
2919 /* NYET responce from the device */
2922 /* Otherwise responce with Timeout */
2926 DWC_PRINTF("Device responce to LPM trans is %x\n",
2928 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2933 #endif /* CONFIG_USB_DWC_OTG_LPM */
2936 retval = -DWC_E_INVALID;
2937 DWC_WARN("DWC OTG HCD - "
2938 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2939 typeReq, wIndex, wValue);
2946 #ifdef CONFIG_USB_DWC_OTG_LPM
2947 /** Returns index of host channel to perform LPM transaction. */
2948 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2950 dwc_otg_core_if_t *core_if = hcd->core_if;
2952 hcchar_data_t hcchar;
2953 gintmsk_data_t gintmsk = {.d32 = 0 };
2955 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2956 DWC_PRINTF("No free channel to select for LPM transaction\n");
2960 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2962 /* Mask host channel interrupts. */
2963 gintmsk.b.hcintr = 1;
2964 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2966 /* Fill fields that core needs for LPM transaction */
2967 hcchar.b.devaddr = devaddr;
2969 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2971 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2972 hcchar.b.epdir = 0; /* OUT */
2973 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2976 /* Remove the host channel from the free list. */
2977 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2979 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2984 /** Release hc after performing LPM transaction */
2985 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2988 glpmcfg_data_t lpmcfg;
2991 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2992 hc_num = lpmcfg.b.lpm_chan_index;
2994 hc = hcd->hc_ptr_array[hc_num];
2996 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2997 /* Return host channel to free list */
2998 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
3001 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
3002 uint8_t bRemoteWake)
3004 glpmcfg_data_t lpmcfg;
3005 pcgcctl_data_t pcgcctl = {.d32 = 0 };
3008 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
3013 pcgcctl.b.enbl_sleep_gating = 1;
3014 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
3016 /* Read LPM config register */
3017 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
3019 /* Program LPM transaction fields */
3020 lpmcfg.b.rem_wkup_en = bRemoteWake;
3021 lpmcfg.b.hird = hird;
3023 if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
3024 lpmcfg.b.hird_thres = 0x16;
3025 lpmcfg.b.en_besl = 1;
3027 lpmcfg.b.hird_thres = 0x1c;
3030 lpmcfg.b.lpm_chan_index = channel;
3031 lpmcfg.b.en_utmi_sleep = 1;
3032 /* Program LPM config register */
3033 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3035 /* Send LPM transaction */
3036 lpmcfg.b.send_lpm = 1;
3037 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3042 #endif /* CONFIG_USB_DWC_OTG_LPM */
3044 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3049 return -DWC_E_INVALID;
3052 retval = (hcd->flags.b.port_connect_status_change ||
3053 hcd->flags.b.port_reset_change ||
3054 hcd->flags.b.port_enable_change ||
3055 hcd->flags.b.port_suspend_change ||
3056 hcd->flags.b.port_over_current_change);
3059 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3060 " Root port status changed\n");
3061 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
3062 hcd->flags.b.port_connect_status_change);
3063 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
3064 hcd->flags.b.port_reset_change);
3065 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
3066 hcd->flags.b.port_enable_change);
3067 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
3068 hcd->flags.b.port_suspend_change);
3069 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
3070 hcd->flags.b.port_over_current_change);
3076 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3080 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3081 host_global_regs->hfnum);
3084 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3087 return hfnum.b.frnum;
3090 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3091 struct dwc_otg_hcd_function_ops *fops)
3096 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3097 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3098 dwc_otg_hcd_reinit(hcd);
3100 retval = -DWC_E_NO_DEVICE;
3106 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3111 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3113 hcd->priv = priv_data;
3116 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3118 return hcd->otg_port;
3121 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3124 if (hcd->core_if->op_state == B_HOST) {
3133 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3134 int iso_desc_count, int atomic_alloc)
3136 dwc_otg_hcd_urb_t *dwc_otg_urb;
3140 sizeof(*dwc_otg_urb) +
3141 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3143 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3145 dwc_otg_urb = DWC_ALLOC(size);
3147 dwc_otg_urb->packet_count = iso_desc_count;
3152 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3153 uint8_t dev_addr, uint8_t ep_num,
3154 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3156 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3157 ep_type, ep_dir, mps);
3160 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3161 dev_addr, ep_num, ep_dir, ep_type, mps);
3165 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3166 void *urb_handle, void *buf, dwc_dma_t dma,
3167 uint32_t buflen, void *setup_packet,
3168 dwc_dma_t setup_dma, uint32_t flags,
3171 dwc_otg_urb->priv = urb_handle;
3172 dwc_otg_urb->buf = buf;
3173 dwc_otg_urb->dma = dma;
3174 dwc_otg_urb->length = buflen;
3175 dwc_otg_urb->setup_packet = setup_packet;
3176 dwc_otg_urb->setup_dma = setup_dma;
3177 dwc_otg_urb->flags = flags;
3178 dwc_otg_urb->interval = interval;
3179 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3182 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3184 return dwc_otg_urb->status;
3187 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3189 return dwc_otg_urb->actual_length;
3192 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3194 return dwc_otg_urb->error_count;
3197 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3198 int desc_num, uint32_t offset,
3201 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3202 dwc_otg_urb->iso_descs[desc_num].length = length;
3205 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3208 return dwc_otg_urb->iso_descs[desc_num].status;
3211 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3212 dwc_otg_urb, int desc_num)
3214 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3217 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3220 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3223 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3230 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3232 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3234 DWC_ASSERT(qh, "qh is not allocated\n");
3236 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3243 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3245 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3246 DWC_ASSERT(qh, "qh is not allocated\n");
3250 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3255 gnptxsts_data_t np_tx_status;
3256 hptxsts_data_t p_tx_status;
3258 num_channels = hcd->core_if->core_params->host_channels;
3261 ("************************************************************\n");
3262 DWC_PRINTF("HCD State:\n");
3263 DWC_PRINTF(" Num channels: %d\n", num_channels);
3264 for (i = 0; i < num_channels; i++) {
3265 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3266 DWC_PRINTF(" Channel %d:\n", i);
3267 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3268 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3269 DWC_PRINTF(" speed: %d\n", hc->speed);
3270 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3271 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3272 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3273 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3274 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3275 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3276 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3277 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3278 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3279 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3280 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3281 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3282 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3283 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3284 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3285 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3286 DWC_PRINTF(" requests: %d\n", hc->requests);
3287 DWC_PRINTF(" qh: %p\n", hc->qh);
3288 if (hc->xfer_started) {
3290 hcchar_data_t hcchar;
3291 hctsiz_data_t hctsiz;
3293 hcintmsk_data_t hcintmsk;
3295 DWC_READ_REG32(&hcd->core_if->host_if->
3296 host_global_regs->hfnum);
3298 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3301 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3304 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3307 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3309 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3310 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3311 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3312 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3313 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3315 if (hc->xfer_started && hc->qh) {
3317 dwc_otg_hcd_urb_t *urb;
3319 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3321 if (!qtd->in_process)
3325 DWC_PRINTF(" URB Info:\n");
3326 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd,
3329 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3330 dwc_otg_hcd_get_dev_addr
3332 dwc_otg_hcd_get_ep_num
3334 dwc_otg_hcd_is_pipe_in
3335 (&urb->pipe_info) ? "IN" :
3338 (" Max packet size: %d\n",
3342 (" transfer_buffer: %p\n",
3344 DWC_PRINTF(" transfer_dma: %p\n",
3347 (" transfer_buffer_length: %d\n",
3349 DWC_PRINTF(" actual_length: %d\n",
3350 urb->actual_length);
3355 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3356 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3357 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3359 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3360 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3361 np_tx_status.b.nptxqspcavail);
3362 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3363 np_tx_status.b.nptxfspcavail);
3365 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3366 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3367 p_tx_status.b.ptxqspcavail);
3368 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3369 dwc_otg_hcd_dump_frrem(hcd);
3370 dwc_otg_dump_global_registers(hcd->core_if);
3371 dwc_otg_dump_host_registers(hcd->core_if);
3373 ("************************************************************\n");
3379 void dwc_print_setup_data(uint8_t *setup)
3382 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3383 DWC_PRINTF("Setup Data = MSB ");
3384 for (i = 7; i >= 0; i--)
3385 DWC_PRINTF("%02x ", setup[i]);
3387 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3388 (setup[0] & 0x80) ? "Device-to-Host" :
3390 DWC_PRINTF(" bmRequestType Type = ");
3391 switch ((setup[0] & 0x60) >> 5) {
3393 DWC_PRINTF("Standard\n");
3396 DWC_PRINTF("Class\n");
3399 DWC_PRINTF("Vendor\n");
3402 DWC_PRINTF("Reserved\n");
3405 DWC_PRINTF(" bmRequestType Recipient = ");
3406 switch (setup[0] & 0x1f) {
3408 DWC_PRINTF("Device\n");
3411 DWC_PRINTF("Interface\n");
3414 DWC_PRINTF("Endpoint\n");
3417 DWC_PRINTF("Other\n");
3420 DWC_PRINTF("Reserved\n");
3423 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3424 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3425 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3426 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3431 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3434 DWC_PRINTF("Frame remaining at SOF:\n");
3435 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3436 hcd->frrem_samples, hcd->frrem_accum,
3437 (hcd->frrem_samples > 0) ?
3438 hcd->frrem_accum / hcd->frrem_samples : 0);
3441 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3442 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3443 hcd->core_if->hfnum_7_samples,
3444 hcd->core_if->hfnum_7_frrem_accum,
3445 (hcd->core_if->hfnum_7_samples >
3446 0) ? hcd->core_if->hfnum_7_frrem_accum /
3447 hcd->core_if->hfnum_7_samples : 0);
3448 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3449 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3450 hcd->core_if->hfnum_0_samples,
3451 hcd->core_if->hfnum_0_frrem_accum,
3452 (hcd->core_if->hfnum_0_samples >
3453 0) ? hcd->core_if->hfnum_0_frrem_accum /
3454 hcd->core_if->hfnum_0_samples : 0);
3455 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3456 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3457 hcd->core_if->hfnum_other_samples,
3458 hcd->core_if->hfnum_other_frrem_accum,
3459 (hcd->core_if->hfnum_other_samples >
3460 0) ? hcd->core_if->hfnum_other_frrem_accum /
3461 hcd->core_if->hfnum_other_samples : 0);
3464 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3465 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3466 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3467 (hcd->hfnum_7_samples_a > 0) ?
3468 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3469 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3470 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3471 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3472 (hcd->hfnum_0_samples_a > 0) ?
3473 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3474 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3475 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3476 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3477 (hcd->hfnum_other_samples_a > 0) ?
3478 hcd->hfnum_other_frrem_accum_a /
3479 hcd->hfnum_other_samples_a : 0);
3482 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3483 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3484 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3485 (hcd->hfnum_7_samples_b > 0) ?
3486 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3487 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3488 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3489 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3490 (hcd->hfnum_0_samples_b > 0) ?
3491 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3492 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3493 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3494 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3495 (hcd->hfnum_other_samples_b > 0) ?
3496 hcd->hfnum_other_frrem_accum_b /
3497 hcd->hfnum_other_samples_b : 0);
3501 #endif /* DWC_DEVICE_ONLY */