drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t *hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_SHUTDOWN);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         }
 183
 184                 }
 185         }
 186 }
 187
 188 /**
 189  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 190  * and periodic schedules. The QTD associated with each URB is removed from
 191  * the schedule and freed. This function may be called when a disconnect is
 192  * detected or when the HCD is being stopped.
 193  */
 194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
 195 {
 196         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 197         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 198         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 202 }
 203
 204 /**
 205  * Start the connection timer.  An OTG host is required to display a
 206  * message if the device does not connect within 10 seconds.  The
 207  * timer is deleted if a port connect interrupt occurs before the
 208  * timer expires.
 209  */
 210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
 211 {
 212         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
 213 }
 214
 215 /**
 216  * HCD Callback function for disconnect of the HCD.
 217  *
 218  * @param p void pointer to the <code>struct usb_hcd</code>
 219  */
 220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 221 {
 222         dwc_otg_hcd_t *dwc_otg_hcd;
 223         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 224         dwc_otg_hcd = p;
 225         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 226         return 1;
 227 }
 228
 229 /**
 230  * HCD Callback function for starting the HCD when A-Cable is
 231  * connected.
 232  *
 233  * @param p void pointer to the <code>struct usb_hcd</code>
 234  */
 235 static int32_t dwc_otg_hcd_start_cb(void *p)
 236 {
 237         dwc_otg_hcd_t *dwc_otg_hcd = p;
 238         dwc_otg_core_if_t *core_if;
 239         hprt0_data_t hprt0;
 240         uint32_t timeout = 50;
 241
 242         core_if = dwc_otg_hcd->core_if;
 243
 244         if (core_if->op_state == B_HOST) {
 245                 /*
 246                  * Reset the port.  During a HNP mode switch the reset
 247                  * needs to occur within 1ms and have a duration of at
 248                  * least 50ms.
 249                  */
 250                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 251                 hprt0.b.prtrst = 1;
 252                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 253                 if (core_if->otg_ver) {
 254                         dwc_mdelay(60);
 255                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 256                         hprt0.b.prtrst = 0;
 257                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 258                 }
 259         }
 260         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 261         if (core_if->otg_ver)
 262                 timeout = 25;
 263         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 264                                    hcd_start_func, dwc_otg_hcd, timeout,
 265                                    "start hcd");
 266
 267         return 1;
 268 }
 269
 270 /**
 271  * HCD Callback function for disconnect of the HCD.
 272  *
 273  * @param p void pointer to the <code>struct usb_hcd</code>
 274  */
 275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 276 {
 277         gintsts_data_t intr;
 278         dwc_otg_hcd_t *dwc_otg_hcd = p;
 279         hprt0_data_t hprt0;
 280
 281         dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
 282         dwc_otg_hcd->non_periodic_channels = 0;
 283         dwc_otg_hcd->periodic_channels = 0;
 284
 285         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 286         /* In some case, we don't disconnect a usb device, but
 287          * disconnect intr was triggered, so check hprt0 here. */
 288         if ((!hprt0.b.prtenchng)
 289             && (hprt0.d32 != 0x1000)
 290             && (hprt0.d32 != 0x1100)) {
 291                 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
 292                 return 1;
 293         }
 294         /*
 295          * Set status flags for the hub driver.
 296          */
 297         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 298         dwc_otg_hcd->flags.b.port_connect_status = 0;
 299
 300         /*
 301          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 302          * interrupt mask and status bits and disabling subsequent host
 303          * channel interrupts.
 304          */
 305         intr.d32 = 0;
 306         intr.b.nptxfempty = 1;
 307         intr.b.ptxfempty = 1;
 308         intr.b.hcintr = 1;
 309         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 310                          intr.d32, 0);
 311         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 312                          intr.d32, 0);
 313
 314         /*
 315          * Turn off the vbus power only if the core has transitioned to device
 316          * mode. If still in host mode, need to keep power on to detect a
 317          * reconnection.
 318          */
 319         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 320                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 321                         hprt0_data_t hprt0 = {.d32 = 0 };
 322                         DWC_PRINTF("Disconnect: PortPower off\n");
 323                         hprt0.b.prtpwr = 0;
 324                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 325                                         hprt0.d32);
 326                 }
 327                 /** Delete timers if become device */
 328                 del_timers(dwc_otg_hcd);
 329                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 330                 goto out;
 331         }
 332
 333         /* Respond with an error status to all URBs in the schedule. */
 334         kill_all_urbs(dwc_otg_hcd);
 335
 336         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 337                 /* Clean up any host channels that were in use. */
 338                 int num_channels;
 339                 int i;
 340                 dwc_hc_t *channel;
 341                 dwc_otg_hc_regs_t *hc_regs;
 342                 hcchar_data_t hcchar;
 343
 344                 DWC_PRINTF("Disconnect cb-Host\n");
 345                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 346                         del_xfer_timers(dwc_otg_hcd);
 347                 else
 348                         del_timers(dwc_otg_hcd);
 349
 350                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 351
 352                 if (!dwc_otg_hcd->core_if->dma_enable) {
 353                         /* Flush out any channel requests in slave mode. */
 354                         for (i = 0; i < num_channels; i++) {
 355                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 356                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 357                                     (channel, hc_list_entry)) {
 358                                         hc_regs =
 359                                             dwc_otg_hcd->core_if->host_if->
 360                                             hc_regs[i];
 361                                         hcchar.d32 =
 362                                             DWC_READ_REG32(&hc_regs->hcchar);
 363                                         if (hcchar.b.chen) {
 364                                                 hcchar.b.chen = 0;
 365                                                 hcchar.b.chdis = 1;
 366                                                 hcchar.b.epdir = 0;
 367                                                 DWC_WRITE_REG32
 368                                                     (&hc_regs->hcchar,
 369                                                      hcchar.d32);
 370                                         }
 371                                 }
 372                         }
 373                 }
 374
 375                 for (i = 0; i < num_channels; i++) {
 376                         channel = dwc_otg_hcd->hc_ptr_array[i];
 377                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 378                                 hc_regs =
 379                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 380                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 381                                 if (hcchar.b.chen) {
 382                                         /* Halt the channel. */
 383                                         hcchar.b.chdis = 1;
 384                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 385                                                         hcchar.d32);
 386                                 }
 387
 388                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 389                                                    channel);
 390                                 DWC_CIRCLEQ_INSERT_TAIL
 391                                     (&dwc_otg_hcd->free_hc_list, channel,
 392                                      hc_list_entry);
 393                                 /*
 394                                  * Added for Descriptor DMA to prevent channel double cleanup
 395                                  * in release_channel_ddma(). Which called from ep_disable
 396                                  * when device disconnect.
 397                                  */
 398                                 channel->qh = NULL;
 399                         }
 400                 }
 401         }
 402
 403 out:
 404         if (dwc_otg_hcd->fops->disconnect) {
 405                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 406         }
 407
 408         return 1;
 409 }
 410
 411 /**
 412  * HCD Callback function for stopping the HCD.
 413  *
 414  * @param p void pointer to the <code>struct usb_hcd</code>
 415  */
 416 static int32_t dwc_otg_hcd_stop_cb(void *p)
 417 {
 418         dwc_otg_hcd_t *dwc_otg_hcd = p;
 419
 420         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 421         dwc_otg_hcd_stop(dwc_otg_hcd);
 422         return 1;
 423 }
 424
 425 #ifdef CONFIG_USB_DWC_OTG_LPM
 426 /**
 427  * HCD Callback function for sleep of HCD.
 428  *
 429  * @param p void pointer to the <code>struct usb_hcd</code>
 430  */
 431 static int dwc_otg_hcd_sleep_cb(void *p)
 432 {
 433         dwc_otg_hcd_t *hcd = p;
 434
 435         dwc_otg_hcd_free_hc_from_lpm(hcd);
 436
 437         return 0;
 438 }
 439 #endif
 440
 441 /**
 442  * HCD Callback function for Remote Wakeup.
 443  *
 444  * @param p void pointer to the <code>struct usb_hcd</code>
 445  */
 446 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd);
 447 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 448 {
 449         dwc_otg_hcd_t *dwc_otg_hcd = p;
 450         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 451
 452         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 453                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 454                 usb_hcd_resume_root_hub(hcd);
 455         }
 456 #ifdef CONFIG_USB_DWC_OTG_LPM
 457         else {
 458                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 459         }
 460 #endif
 461         return 0;
 462 }
 463
 464 /**
 465  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 466  * stopped.
 467  */
 468 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
 469 {
 470         hprt0_data_t hprt0 = {.d32 = 0 };
 471         struct dwc_otg_platform_data *pldata;
 472         pldata = hcd->core_if->otg_dev->pldata;
 473
 474         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 475
 476         /*
 477          * The root hub should be disconnected before this function is called.
 478          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 479          * and the QH lists (via ..._hcd_endpoint_disable).
 480          */
 481
 482         /* Turn off all host-specific interrupts. */
 483         dwc_otg_disable_host_interrupts(hcd->core_if);
 484
 485         /* Turn off the vbus power */
 486         DWC_PRINTF("PortPower off\n");
 487         hprt0.b.prtpwr = 0;
 488         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 489
 490         if (pldata->power_enable)
 491                 pldata->power_enable(0);
 492
 493         dwc_mdelay(1);
 494 }
 495
 496 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
 497                             dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
 498                             int atomic_alloc)
 499 {
 500         dwc_irqflags_t flags;
 501         int retval = 0;
 502         dwc_otg_qtd_t *qtd;
 503         gintmsk_data_t intr_mask = {.d32 = 0 };
 504
 505         if (!hcd->flags.b.port_connect_status) {
 506                 /* No longer connected. */
 507                 DWC_DEBUG("Not connected\n");
 508                 return -DWC_E_NO_DEVICE;
 509         }
 510
 511         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 512         if (qtd == NULL) {
 513                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 514                 return -DWC_E_NO_MEMORY;
 515         }
 516
 517         retval =
 518             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle,
 519                                 atomic_alloc);
 520
 521         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 522         if (retval < 0) {
 523                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 524                           "Error status %d\n", retval);
 525                 dwc_otg_hcd_qtd_free(qtd);
 526         }
 527         intr_mask.d32 =
 528             DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 529         if (!intr_mask.b.sofintr && retval == 0) {
 530                 dwc_otg_transaction_type_e tr_type;
 531                 if ((qtd->qh->ep_type == UE_BULK)
 532                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 533                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 534                         retval = 0;
 535                         goto out;
 536                 }
 537                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 538                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 539                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 540                 }
 541         }
 542 out:
 543         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 544         return retval;
 545 }
 546
 547 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
 548                             dwc_otg_hcd_urb_t *dwc_otg_urb)
 549 {
 550         dwc_otg_qh_t *qh;
 551         dwc_otg_qtd_t *urb_qtd;
 552
 553         urb_qtd = dwc_otg_urb->qtd;
 554         if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
 555                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 556                            __func__, urb_qtd, dwc_otg_urb);
 557                 return 0;
 558         }
 559         qh = urb_qtd->qh;
 560 #ifdef DEBUG
 561         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 562                 if (urb_qtd->in_process) {
 563                         dump_channel_info(hcd, qh);
 564                 }
 565         }
 566 #endif
 567         if (urb_qtd->in_process && qh->channel) {
 568                 /* The QTD is in process (it has been assigned to a channel). */
 569                 if (hcd->flags.b.port_connect_status) {
 570                         /*
 571                          * If still connected (i.e. in host mode), halt the
 572                          * channel so it can be used for other transfers. If
 573                          * no longer connected, the host registers can't be
 574                          * written to halt the channel since the core is in
 575                          * device mode.
 576                          */
 577                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 578                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 579                 }
 580         }
 581
 582         /*
 583          * Free the QTD and clean up the associated QH. Leave the QH in the
 584          * schedule if it has any remaining QTDs.
 585          */
 586
 587         if (!hcd->core_if->dma_desc_enable) {
 588                 uint8_t b = urb_qtd->in_process;
 589                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 590                 if (b) {
 591                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 592                         qh->channel = NULL;
 593                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 594                         dwc_otg_hcd_qh_remove(hcd, qh);
 595                 }
 596         } else {
 597                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 598         }
 599         return 0;
 600 }
 601
 602 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
 603                                  int retry)
 604 {
 605         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 606         int retval = 0;
 607         dwc_irqflags_t flags;
 608
 609         if (retry < 0) {
 610                 retval = -DWC_E_INVALID;
 611                 goto done;
 612         }
 613
 614         if (!qh) {
 615                 retval = -DWC_E_INVALID;
 616                 goto done;
 617         }
 618
 619         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 620
 621         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 622                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 623                 retry--;
 624                 dwc_msleep(5);
 625                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 626         }
 627
 628         dwc_otg_hcd_qh_remove(hcd, qh);
 629
 630         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 631         /*
 632          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 633          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 634          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 635          * and dwc_otg_hcd_frame_list_alloc().
 636          */
 637         dwc_otg_hcd_qh_free(hcd, qh);
 638
 639 done:
 640         return retval;
 641 }
 642
 643 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
 644 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
 645 {
 646         int retval = 0;
 647         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 648         if (!qh)
 649                 return -DWC_E_INVALID;
 650
 651         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 652         return retval;
 653 }
 654 #endif
 655
 656 /**
 657  * HCD Callback structure for handling mode switching.
 658  */
 659 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 660         .start = dwc_otg_hcd_start_cb,
 661         .stop = dwc_otg_hcd_stop_cb,
 662         .disconnect = dwc_otg_hcd_disconnect_cb,
 663         .session_start = dwc_otg_hcd_session_start_cb,
 664         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 665 #ifdef CONFIG_USB_DWC_OTG_LPM
 666         .sleep = dwc_otg_hcd_sleep_cb,
 667 #endif
 668         .p = 0,
 669 };
 670
 671 /**
 672  * Reset tasklet function
 673  */
 674 static void reset_tasklet_func(void *data)
 675 {
 676         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 677         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 678         hprt0_data_t hprt0;
 679
 680         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 681
 682         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 683         hprt0.b.prtrst = 1;
 684         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 685         dwc_mdelay(60);
 686
 687         hprt0.b.prtrst = 0;
 688         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 689         dwc_otg_hcd->flags.b.port_reset_change = 1;
 690 }
 691
 692 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 693 {
 694         dwc_list_link_t *item;
 695         dwc_otg_qh_t *qh;
 696         dwc_irqflags_t flags;
 697
 698         if (!qh_list->next) {
 699                 /* The list hasn't been initialized yet. */
 700                 return;
 701         }
 702         /*
 703          * Hold spinlock here. Not needed in that case if bellow
 704          * function is being called from ISR
 705          */
 706         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 707         /* Ensure there are no QTDs or URBs left. */
 708         kill_urbs_in_qh_list(hcd, qh_list);
 709         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 710
 711         DWC_LIST_FOREACH(item, qh_list) {
 712                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 713                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 714         }
 715 }
 716
 717 /**
 718  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 719  * Device during SRP time by host power up.
 720  */
 721 void dwc_otg_hcd_power_up(void *ptr)
 722 {
 723         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 724         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 725
 726         DWC_PRINTF("%s called\n", __FUNCTION__);
 727
 728         if (!core_if->hibernation_suspend) {
 729                 DWC_PRINTF("Already exited from Hibernation\n");
 730                 return;
 731         }
 732
 733         /* Switch on the voltage to the core */
 734         gpwrdn.b.pwrdnswtch = 1;
 735         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 736         dwc_udelay(10);
 737
 738         /* Reset the core */
 739         gpwrdn.d32 = 0;
 740         gpwrdn.b.pwrdnrstn = 1;
 741         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 742         dwc_udelay(10);
 743
 744         /* Disable power clamps */
 745         gpwrdn.d32 = 0;
 746         gpwrdn.b.pwrdnclmp = 1;
 747         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 748
 749         /* Remove reset the core signal */
 750         gpwrdn.d32 = 0;
 751         gpwrdn.b.pwrdnrstn = 1;
 752         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 753         dwc_udelay(10);
 754
 755         /* Disable PMU interrupt */
 756         gpwrdn.d32 = 0;
 757         gpwrdn.b.pmuintsel = 1;
 758         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 759
 760         core_if->hibernation_suspend = 0;
 761
 762         /* Disable PMU */
 763         gpwrdn.d32 = 0;
 764         gpwrdn.b.pmuactv = 1;
 765         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 766         dwc_udelay(10);
 767
 768         /* Enable VBUS */
 769         gpwrdn.d32 = 0;
 770         gpwrdn.b.dis_vbus = 1;
 771         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 772
 773         core_if->op_state = A_HOST;
 774         dwc_otg_core_init(core_if);
 775         dwc_otg_enable_global_interrupts(core_if);
 776         cil_hcd_start(core_if);
 777 }
 778
 779 /**
 780  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 781  * in the struct usb_hcd field.
 782  */
 783 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
 784 {
 785         int i;
 786
 787         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 788
 789         del_timers(dwc_otg_hcd);
 790
 791         /* Free memory for QH/QTD lists */
 792         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 793         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 794         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 795         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 796         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 797         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 798
 799         /* Free memory for the host channels. */
 800         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 801                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 802
 803 #ifdef DEBUG
 804                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 805                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 806                 }
 807 #endif
 808                 if (hc != NULL) {
 809                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 810                                     i, hc);
 811                         DWC_FREE(hc);
 812                 }
 813         }
 814
 815         if (dwc_otg_hcd->core_if->dma_enable) {
 816                 if (dwc_otg_hcd->status_buf_dma) {
 817                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 818                                      dwc_otg_hcd->status_buf,
 819                                      dwc_otg_hcd->status_buf_dma);
 820                 }
 821         } else if (dwc_otg_hcd->status_buf != NULL) {
 822                 DWC_FREE(dwc_otg_hcd->status_buf);
 823         }
 824         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 825         /* Set core_if's lock pointer to NULL */
 826         dwc_otg_hcd->core_if->lock = NULL;
 827
 828         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 829         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 830
 831 #ifdef DWC_DEV_SRPCAP
 832         if (dwc_otg_hcd->core_if->power_down == 2 &&
 833             dwc_otg_hcd->core_if->pwron_timer) {
 834                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 835         }
 836 #endif
 837         DWC_FREE(dwc_otg_hcd);
 838 }
 839
 840 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 841 {
 842         int retval = 0;
 843         int num_channels;
 844         int i;
 845         dwc_hc_t *channel;
 846
 847         hcd->lock = DWC_SPINLOCK_ALLOC();
 848         if (!hcd->lock) {
 849                 DWC_ERROR("Could not allocate lock for pcd");
 850                 DWC_FREE(hcd);
 851                 retval = -DWC_E_NO_MEMORY;
 852                 goto out;
 853         }
 854         hcd->core_if = core_if;
 855
 856         /* Register the HCD CIL Callbacks */
 857         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 858                                            &hcd_cil_callbacks, hcd);
 859
 860         /* Initialize the non-periodic schedule. */
 861         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 862         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 863
 864         /* Initialize the periodic schedule. */
 865         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 866         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 867         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 868         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 869
 870         /*
 871          * Create a host channel descriptor for each host channel implemented
 872          * in the controller. Initialize the channel descriptor array.
 873          */
 874         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 875         num_channels = hcd->core_if->core_params->host_channels;
 876         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 877         for (i = 0; i < num_channels; i++) {
 878                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 879                 if (channel == NULL) {
 880                         retval = -DWC_E_NO_MEMORY;
 881                         DWC_ERROR("%s: host channel allocation failed\n",
 882                                   __func__);
 883                         dwc_otg_hcd_free(hcd);
 884                         goto out;
 885                 }
 886                 channel->hc_num = i;
 887                 hcd->hc_ptr_array[i] = channel;
 888 #ifdef DEBUG
 889                 hcd->core_if->hc_xfer_timer[i] =
 890                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 891                                     &hcd->core_if->hc_xfer_info[i]);
 892 #endif
 893                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 894                             channel);
 895         }
 896
 897         /* Initialize the Connection timeout timer. */
 898         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 899                                           dwc_otg_hcd_connect_timeout, hcd);
 900
 901         /* Initialize reset tasklet. */
 902         hcd->reset_tasklet =
 903             DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 904 #ifdef DWC_DEV_SRPCAP
 905         if (hcd->core_if->power_down == 2) {
 906                 /* Initialize Power on timer for Host power up in case hibernation */
 907                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 908                                                             dwc_otg_hcd_power_up,
 909                                                             core_if);
 910         }
 911 #endif
 912
 913         /*
 914          * Allocate space for storing data on status transactions. Normally no
 915          * data is sent, but this space acts as a bit bucket. This must be
 916          * done after usb_add_hcd since that function allocates the DMA buffer
 917          * pool.
 918          */
 919         if (hcd->core_if->dma_enable) {
 920                 hcd->status_buf =
 921                     DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 922                                          &hcd->status_buf_dma);
 923         } else {
 924                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 925         }
 926         if (!hcd->status_buf) {
 927                 retval = -DWC_E_NO_MEMORY;
 928                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 929                 dwc_otg_hcd_free(hcd);
 930                 goto out;
 931         }
 932
 933         hcd->otg_port = 1;
 934         hcd->frame_list = NULL;
 935         hcd->frame_list_dma = 0;
 936         hcd->periodic_qh_count = 0;
 937 out:
 938         return retval;
 939 }
 940
 941 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
 942 {
 943         /* Turn off all host-specific interrupts. */
 944         dwc_otg_disable_host_interrupts(hcd->core_if);
 945
 946         dwc_otg_hcd_free(hcd);
 947 }
 948
 949 /**
 950  * Initializes dynamic portions of the DWC_otg HCD state.
 951  */
 952 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
 953 {
 954         int num_channels;
 955         int i;
 956         dwc_hc_t *channel;
 957         dwc_hc_t *channel_tmp;
 958
 959         hcd->flags.d32 = 0;
 960
 961         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 962         hcd->non_periodic_channels = 0;
 963         hcd->periodic_channels = 0;
 964
 965         /*
 966          * Put all channels in the free channel list and clean up channel
 967          * states.
 968          */
 969         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 970                                  &hcd->free_hc_list, hc_list_entry) {
 971                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 972         }
 973
 974         num_channels = hcd->core_if->core_params->host_channels;
 975         for (i = 0; i < num_channels; i++) {
 976                 channel = hcd->hc_ptr_array[i];
 977                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 978                                         hc_list_entry);
 979                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 980         }
 981
 982         /* Initialize the DWC core for host mode operation. */
 983         dwc_otg_core_host_init(hcd->core_if);
 984
 985         /* Set core_if's lock pointer to the hcd->lock */
 986         hcd->core_if->lock = hcd->lock;
 987 }
 988
 989 /**
 990  * Assigns transactions from a QTD to a free host channel and initializes the
 991  * host channel to perform the transactions. The host channel is removed from
 992  * the free list.
 993  *
 994  * @param hcd The HCD state structure.
 995  * @param qh Transactions from the first QTD for this QH are selected and
 996  * assigned to a free host channel.
 997  */
 998 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 999 {
1000         dwc_hc_t *hc;
1001         dwc_otg_qtd_t *qtd;
1002         dwc_otg_hcd_urb_t *urb;
1003         void *ptr = NULL;
1004         int retval = 0;
1005
1006         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1007
1008         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1009
1010         /* Remove the host channel from the free list. */
1011         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1012
1013         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1014
1015         urb = qtd->urb;
1016         if (urb == NULL) {
1017                 printk("%s : urb is NULL\n", __func__);
1018                 retval = -EINVAL;
1019                 return retval;
1020         }
1021
1022         qh->channel = hc;
1023
1024         qtd->in_process = 1;
1025
1026         /*
1027          * Use usb_pipedevice to determine device address. This address is
1028          * 0 before the SET_ADDRESS command and the correct address afterward.
1029          */
1030         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1031         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1032         hc->speed = qh->dev_speed;
1033         hc->max_packet = dwc_max_packet(qh->maxp);
1034
1035         hc->xfer_started = 0;
1036         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1037         hc->error_state = (qtd->error_count > 0);
1038         hc->halt_on_queue = 0;
1039         hc->halt_pending = 0;
1040         hc->requests = 0;
1041
1042         /*
1043          * The following values may be modified in the transfer type section
1044          * below. The xfer_len value may be reduced when the transfer is
1045          * started to accommodate the max widths of the XferSize and PktCnt
1046          * fields in the HCTSIZn register.
1047          */
1048
1049         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1050         if (hc->ep_is_in)
1051                 hc->do_ping = 0;
1052         else
1053                 hc->do_ping = qh->ping_state;
1054
1055         hc->data_pid_start = qh->data_toggle;
1056         hc->multi_count = 1;
1057
1058         if (hcd->core_if->dma_enable) {
1059                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1060
1061                 /* For non-dword aligned case */
1062                 if (((unsigned long)hc->xfer_buff & 0x3)
1063                     && !hcd->core_if->dma_desc_enable) {
1064                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1065                 }
1066         } else {
1067                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1068         }
1069         hc->xfer_len = urb->length - urb->actual_length;
1070         hc->xfer_count = 0;
1071
1072         /*
1073          * Set the split attributes
1074          */
1075         hc->do_split = 0;
1076         if (qh->do_split) {
1077                 uint32_t hub_addr, port_addr;
1078                 hc->do_split = 1;
1079                 hc->xact_pos = qtd->isoc_split_pos;
1080                 hc->complete_split = qtd->complete_split;
1081                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1082                 hc->hub_addr = (uint8_t) hub_addr;
1083                 hc->port_addr = (uint8_t) port_addr;
1084         }
1085
1086         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1087         case UE_CONTROL:
1088                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1089                 switch (qtd->control_phase) {
1090                 case DWC_OTG_CONTROL_SETUP:
1091                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1092                         hc->do_ping = 0;
1093                         hc->ep_is_in = 0;
1094                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1095                         if (hcd->core_if->dma_enable)
1096                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1097                         else
1098                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1099
1100                         hc->xfer_len = 8;
1101                         ptr = NULL;
1102                         break;
1103                 case DWC_OTG_CONTROL_DATA:
1104                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1105                         hc->data_pid_start = qtd->data_toggle;
1106                         break;
1107                 case DWC_OTG_CONTROL_STATUS:
1108                         /*
1109                          * Direction is opposite of data direction or IN if no
1110                          * data.
1111                          */
1112                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1113                         if (urb->length == 0) {
1114                                 hc->ep_is_in = 1;
1115                         } else {
1116                                 hc->ep_is_in =
1117                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1118                         }
1119                         if (hc->ep_is_in)
1120                                 hc->do_ping = 0;
1121
1122                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1123
1124                         hc->xfer_len = 0;
1125                         if (hcd->core_if->dma_enable)
1126                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1127                         else
1128                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1129
1130                         ptr = NULL;
1131                         break;
1132                 }
1133                 break;
1134         case UE_BULK:
1135                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1136                 break;
1137         case UE_INTERRUPT:
1138                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1139                 break;
1140         case UE_ISOCHRONOUS:
1141                 {
1142                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1143
1144                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1145
1146                         if (hcd->core_if->dma_desc_enable)
1147                                 break;
1148
1149                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1150
1151                         frame_desc->status = 0;
1152
1153                         if (hcd->core_if->dma_enable) {
1154                                 hc->xfer_buff = (uint8_t *) urb->dma;
1155                         } else {
1156                                 hc->xfer_buff = (uint8_t *) urb->buf;
1157                         }
1158                         hc->xfer_buff +=
1159                             frame_desc->offset + qtd->isoc_split_offset;
1160                         hc->xfer_len =
1161                             frame_desc->length - qtd->isoc_split_offset;
1162
1163                         /* For non-dword aligned buffers */
1164                         if (((unsigned long)hc->xfer_buff & 0x3)
1165                             && hcd->core_if->dma_enable) {
1166                                 ptr =
1167                                     (uint8_t *) urb->buf + frame_desc->offset +
1168                                     qtd->isoc_split_offset;
1169                         } else
1170                                 ptr = NULL;
1171
1172                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1173                                 if (hc->xfer_len <= 188) {
1174                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1175                                 } else {
1176                                         hc->xact_pos =
1177                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1178                                 }
1179                         }
1180                 }
1181                 break;
1182         }
1183         /* non DWORD-aligned buffer case */
1184         if (ptr) {
1185                 uint32_t buf_size;
1186                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1187                         buf_size = hcd->core_if->core_params->max_transfer_size;
1188                 } else {
1189                         buf_size = 4096;
1190                 }
1191                 if (!qh->dw_align_buf) {
1192                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1193                                                                 &qh->
1194                                                                 dw_align_buf_dma);
1195                         if (!qh->dw_align_buf) {
1196                                 DWC_ERROR
1197                                     ("%s: Failed to allocate memory to handle "
1198                                      "non-dword aligned buffer case\n",
1199                                      __func__);
1200                                 return retval;
1201                         }
1202                 }
1203                 if (!hc->ep_is_in) {
1204                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1205                 }
1206                 hc->align_buff = qh->dw_align_buf_dma;
1207         } else {
1208                 hc->align_buff = 0;
1209         }
1210
1211         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1212             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1213                 /*
1214                  * This value may be modified when the transfer is started to
1215                  * reflect the actual transfer length.
1216                  */
1217                 hc->multi_count = dwc_hb_mult(qh->maxp);
1218         }
1219
1220         if (hcd->core_if->dma_desc_enable)
1221                 hc->desc_list_addr = qh->desc_list_dma;
1222
1223         dwc_otg_hc_init(hcd->core_if, hc);
1224         hc->qh = qh;
1225         return retval;
1226 }
1227
1228 /**
1229  * This function selects transactions from the HCD transfer schedule and
1230  * assigns them to available host channels. It is called from HCD interrupt
1231  * handler functions.
1232  *
1233  * @param hcd The HCD state structure.
1234  *
1235  * @return The types of new transactions that were assigned to host channels.
1236  */
1237 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1238 {
1239         dwc_list_link_t *qh_ptr;
1240         dwc_otg_qh_t *qh;
1241         int num_channels;
1242         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1243         int err;
1244
1245 #ifdef DEBUG_SOF
1246         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1247 #endif
1248
1249         /* Process entries in the periodic ready list. */
1250         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1251
1252         while (qh_ptr != &hcd->periodic_sched_ready &&
1253                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1254
1255                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1256                 assign_and_init_hc(hcd, qh);
1257
1258                 /*
1259                  * Move the QH from the periodic ready schedule to the
1260                  * periodic assigned schedule.
1261                  */
1262                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1263                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1264                                    &qh->qh_list_entry);
1265
1266                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1267         }
1268
1269         /*
1270          * Process entries in the inactive portion of the non-periodic
1271          * schedule. Some free host channels may not be used if they are
1272          * reserved for periodic transfers.
1273          */
1274         qh_ptr = hcd->non_periodic_sched_inactive.next;
1275         num_channels = hcd->core_if->core_params->host_channels;
1276         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1277                (hcd->non_periodic_channels <
1278                 num_channels - hcd->periodic_channels) &&
1279                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1280
1281                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1282
1283                 err = assign_and_init_hc(hcd, qh);
1284
1285                 /*
1286                  * Move the QH from the non-periodic inactive schedule to the
1287                  * non-periodic active schedule.
1288                  */
1289                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1290                 if (err != 0)
1291                         continue;
1292                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1293                                    &qh->qh_list_entry);
1294
1295                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1296                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1297                 } else {
1298                         ret_val = DWC_OTG_TRANSACTION_ALL;
1299                 }
1300
1301                 hcd->non_periodic_channels++;
1302         }
1303
1304         return ret_val;
1305 }
1306
1307 /**
1308  * Attempts to queue a single transaction request for a host channel
1309  * associated with either a periodic or non-periodic transfer. This function
1310  * assumes that there is space available in the appropriate request queue. For
1311  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1312  * is available in the appropriate Tx FIFO.
1313  *
1314  * @param hcd The HCD state structure.
1315  * @param hc Host channel descriptor associated with either a periodic or
1316  * non-periodic transfer.
1317  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1318  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1319  * transfers.
1320  *
1321  * @return 1 if a request is queued and more requests may be needed to
1322  * complete the transfer, 0 if no more requests are required for this
1323  * transfer, -1 if there is insufficient space in the Tx FIFO.
1324  */
1325 static int queue_transaction(dwc_otg_hcd_t *hcd,
1326                              dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1327 {
1328         int retval;
1329
1330         if (hcd->core_if->dma_enable) {
1331                 if (hcd->core_if->dma_desc_enable) {
1332                         if (!hc->xfer_started
1333                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1334                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1335                                 hc->qh->ping_state = 0;
1336                         }
1337                 } else if (!hc->xfer_started) {
1338                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1339                         hc->qh->ping_state = 0;
1340                 }
1341                 retval = 0;
1342         } else if (hc->halt_pending) {
1343                 /* Don't queue a request if the channel has been halted. */
1344                 retval = 0;
1345         } else if (hc->halt_on_queue) {
1346                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1347                 retval = 0;
1348         } else if (hc->do_ping) {
1349                 if (!hc->xfer_started) {
1350                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1351                 }
1352                 retval = 0;
1353         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1354                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1355                         if (!hc->xfer_started) {
1356                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1357                                 retval = 1;
1358                         } else {
1359                                 retval =
1360                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1361                                                                  hc);
1362                         }
1363                 } else {
1364                         retval = -1;
1365                 }
1366         } else {
1367                 if (!hc->xfer_started) {
1368                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1369                         retval = 1;
1370                 } else {
1371                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1372                 }
1373         }
1374
1375         return retval;
1376 }
1377
1378 /**
1379  * Processes periodic channels for the next frame and queues transactions for
1380  * these channels to the DWC_otg controller. After queueing transactions, the
1381  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1382  * to queue as Periodic Tx FIFO or request queue space becomes available.
1383  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1384  */
1385 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1386 {
1387         hptxsts_data_t tx_status;
1388         dwc_list_link_t *qh_ptr;
1389         dwc_otg_qh_t *qh;
1390         int status;
1391         int no_queue_space = 0;
1392         int no_fifo_space = 0;
1393
1394         dwc_otg_host_global_regs_t *host_regs;
1395         host_regs = hcd->core_if->host_if->host_global_regs;
1396
1397         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1398 #ifdef DEBUG
1399         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1400         DWC_DEBUGPL(DBG_HCDV,
1401                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1402                     tx_status.b.ptxqspcavail);
1403         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1404                     tx_status.b.ptxfspcavail);
1405 #endif
1406
1407         qh_ptr = hcd->periodic_sched_assigned.next;
1408         while (qh_ptr != &hcd->periodic_sched_assigned) {
1409                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1410                 if (tx_status.b.ptxqspcavail == 0) {
1411                         no_queue_space = 1;
1412                         break;
1413                 }
1414
1415                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1416
1417                 /*
1418                  * Set a flag if we're queuing high-bandwidth in slave mode.
1419                  * The flag prevents any halts to get into the request queue in
1420                  * the middle of multiple high-bandwidth packets getting queued.
1421                  */
1422                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1423                         hcd->core_if->queuing_high_bandwidth = 1;
1424                 }
1425                 status =
1426                     queue_transaction(hcd, qh->channel,
1427                                       tx_status.b.ptxfspcavail);
1428                 if (status < 0) {
1429                         no_fifo_space = 1;
1430                         break;
1431                 }
1432
1433                 /*
1434                  * In Slave mode, stay on the current transfer until there is
1435                  * nothing more to do or the high-bandwidth request count is
1436                  * reached. In DMA mode, only need to queue one request. The
1437                  * controller automatically handles multiple packets for
1438                  * high-bandwidth transfers.
1439                  */
1440                 if (hcd->core_if->dma_enable || status == 0 ||
1441                     qh->channel->requests == qh->channel->multi_count) {
1442                         qh_ptr = qh_ptr->next;
1443                         /*
1444                          * Move the QH from the periodic assigned schedule to
1445                          * the periodic queued schedule.
1446                          */
1447                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1448                                            &qh->qh_list_entry);
1449
1450                         /* done queuing high bandwidth */
1451                         hcd->core_if->queuing_high_bandwidth = 0;
1452                 }
1453         }
1454
1455         if (!hcd->core_if->dma_enable) {
1456                 dwc_otg_core_global_regs_t *global_regs;
1457                 gintmsk_data_t intr_mask = {.d32 = 0 };
1458
1459                 global_regs = hcd->core_if->core_global_regs;
1460                 intr_mask.b.ptxfempty = 1;
1461 #ifdef DEBUG
1462                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1463                 DWC_DEBUGPL(DBG_HCDV,
1464                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1465                             tx_status.b.ptxqspcavail);
1466                 DWC_DEBUGPL(DBG_HCDV,
1467                             "  P Tx FIFO Space Avail (after queue): %d\n",
1468                             tx_status.b.ptxfspcavail);
1469 #endif
1470                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1471                     no_queue_space || no_fifo_space) {
1472                         /*
1473                          * May need to queue more transactions as the request
1474                          * queue or Tx FIFO empties. Enable the periodic Tx
1475                          * FIFO empty interrupt. (Always use the half-empty
1476                          * level to ensure that new requests are loaded as
1477                          * soon as possible.)
1478                          */
1479                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1480                                          intr_mask.d32);
1481                 } else {
1482                         /*
1483                          * Disable the Tx FIFO empty interrupt since there are
1484                          * no more transactions that need to be queued right
1485                          * now. This function is called from interrupt
1486                          * handlers to queue more transactions as transfer
1487                          * states change.
1488                          */
1489                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1490                                          0);
1491                 }
1492         }
1493 }
1494
1495 /**
1496  * Processes active non-periodic channels and queues transactions for these
1497  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1498  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1499  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1500  * FIFO Empty interrupt is disabled.
1501  */
1502 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1503 {
1504         gnptxsts_data_t tx_status;
1505         dwc_list_link_t *orig_qh_ptr;
1506         dwc_otg_qh_t *qh;
1507         int status;
1508         int no_queue_space = 0;
1509         int no_fifo_space = 0;
1510         int more_to_do = 0;
1511
1512         dwc_otg_core_global_regs_t *global_regs =
1513             hcd->core_if->core_global_regs;
1514
1515         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1516 #ifdef DEBUG
1517         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1518         DWC_DEBUGPL(DBG_HCDV,
1519                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1520                     tx_status.b.nptxqspcavail);
1521         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1522                     tx_status.b.nptxfspcavail);
1523 #endif
1524         /*
1525          * Keep track of the starting point. Skip over the start-of-list
1526          * entry.
1527          */
1528         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1529                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1530         }
1531         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1532
1533         /*
1534          * Process once through the active list or until no more space is
1535          * available in the request queue or the Tx FIFO.
1536          */
1537         do {
1538                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1539                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1540                         no_queue_space = 1;
1541                         break;
1542                 }
1543
1544                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1545                                     qh_list_entry);
1546                 status =
1547                     queue_transaction(hcd, qh->channel,
1548                                       tx_status.b.nptxfspcavail);
1549
1550                 if (status > 0) {
1551                         more_to_do = 1;
1552                 } else if (status < 0) {
1553                         no_fifo_space = 1;
1554                         break;
1555                 }
1556
1557                 /* Advance to next QH, skipping start-of-list entry. */
1558                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1559                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1560                         hcd->non_periodic_qh_ptr =
1561                             hcd->non_periodic_qh_ptr->next;
1562                 }
1563
1564         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1565
1566         if (!hcd->core_if->dma_enable) {
1567                 gintmsk_data_t intr_mask = {.d32 = 0 };
1568                 intr_mask.b.nptxfempty = 1;
1569
1570 #ifdef DEBUG
1571                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1572                 DWC_DEBUGPL(DBG_HCDV,
1573                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1574                             tx_status.b.nptxqspcavail);
1575                 DWC_DEBUGPL(DBG_HCDV,
1576                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1577                             tx_status.b.nptxfspcavail);
1578 #endif
1579                 if (more_to_do || no_queue_space || no_fifo_space) {
1580                         /*
1581                          * May need to queue more transactions as the request
1582                          * queue or Tx FIFO empties. Enable the non-periodic
1583                          * Tx FIFO empty interrupt. (Always use the half-empty
1584                          * level to ensure that new requests are loaded as
1585                          * soon as possible.)
1586                          */
1587                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1588                                          intr_mask.d32);
1589                 } else {
1590                         /*
1591                          * Disable the Tx FIFO empty interrupt since there are
1592                          * no more transactions that need to be queued right
1593                          * now. This function is called from interrupt
1594                          * handlers to queue more transactions as transfer
1595                          * states change.
1596                          */
1597                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1598                                          0);
1599                 }
1600         }
1601 }
1602
1603 /**
1604  * This function processes the currently active host channels and queues
1605  * transactions for these channels to the DWC_otg controller. It is called
1606  * from HCD interrupt handler functions.
1607  *
1608  * @param hcd The HCD state structure.
1609  * @param tr_type The type(s) of transactions to queue (non-periodic,
1610  * periodic, or both).
1611  */
1612 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1613                                     dwc_otg_transaction_type_e tr_type)
1614 {
1615 #ifdef DEBUG_SOF
1616         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1617 #endif
1618         /* Process host channels associated with periodic transfers. */
1619         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1620              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1621             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1622
1623                 process_periodic_channels(hcd);
1624         }
1625
1626         /* Process host channels associated with non-periodic transfers. */
1627         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1628             tr_type == DWC_OTG_TRANSACTION_ALL) {
1629                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1630                         process_non_periodic_channels(hcd);
1631                 } else {
1632                         /*
1633                          * Ensure NP Tx FIFO empty interrupt is disabled when
1634                          * there are no non-periodic transfers to process.
1635                          */
1636                         gintmsk_data_t gintmsk = {.d32 = 0 };
1637                         gintmsk.b.nptxfempty = 1;
1638                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1639                                          gintmsk, gintmsk.d32, 0);
1640                 }
1641         }
1642 }
1643
1644 #ifdef DWC_HS_ELECT_TST
1645 /*
1646  * Quick and dirty hack to implement the HS Electrical Test
1647  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1648  *
1649  * This code was copied from our userspace app "hset". It sends a
1650  * Get Device Descriptor control sequence in two parts, first the
1651  * Setup packet by itself, followed some time later by the In and
1652  * Ack packets. Rather than trying to figure out how to add this
1653  * functionality to the normal driver code, we just hijack the
1654  * hardware, using these two function to drive the hardware
1655  * directly.
1656  */
1657
1658 static dwc_otg_core_global_regs_t *global_regs;
1659 static dwc_otg_host_global_regs_t *hc_global_regs;
1660 static dwc_otg_hc_regs_t *hc_regs;
1661 static uint32_t *data_fifo;
1662
1663 static void do_setup(void)
1664 {
1665         gintsts_data_t gintsts;
1666         hctsiz_data_t hctsiz;
1667         hcchar_data_t hcchar;
1668         haint_data_t haint;
1669         hcint_data_t hcint;
1670
1671         /* Enable HAINTs */
1672         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1673
1674         /* Enable HCINTs */
1675         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1676
1677         /* Read GINTSTS */
1678         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1679
1680         /* Read HAINT */
1681         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1682
1683         /* Read HCINT */
1684         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1685
1686         /* Read HCCHAR */
1687         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1688
1689         /* Clear HCINT */
1690         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1691
1692         /* Clear HAINT */
1693         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1694
1695         /* Clear GINTSTS */
1696         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1697
1698         /* Read GINTSTS */
1699         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1700
1701         /*
1702          * Send Setup packet (Get Device Descriptor)
1703          */
1704
1705         /* Make sure channel is disabled */
1706         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1707         if (hcchar.b.chen) {
1708                 hcchar.b.chdis = 1;
1709                 /* hcchar.b.chen = 1; */
1710                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1711                 /* sleep(1); */
1712                 dwc_mdelay(1000);
1713
1714                 /* Read GINTSTS */
1715                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1716
1717                 /* Read HAINT */
1718                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1719
1720                 /* Read HCINT */
1721                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1722
1723                 /* Read HCCHAR */
1724                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1725
1726                 /* Clear HCINT */
1727                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1728
1729                 /* Clear HAINT */
1730                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1731
1732                 /* Clear GINTSTS */
1733                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1734
1735                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1736         }
1737
1738         /* Set HCTSIZ */
1739         hctsiz.d32 = 0;
1740         hctsiz.b.xfersize = 8;
1741         hctsiz.b.pktcnt = 1;
1742         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1743         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1744
1745         /* Set HCCHAR */
1746         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1747         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1748         hcchar.b.epdir = 0;
1749         hcchar.b.epnum = 0;
1750         hcchar.b.mps = 8;
1751         hcchar.b.chen = 1;
1752         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1753
1754         /* Fill FIFO with Setup data for Get Device Descriptor */
1755         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1756         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1757         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1758
1759         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1760
1761         /* Wait for host channel interrupt */
1762         do {
1763                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1764         } while (gintsts.b.hcintr == 0);
1765
1766         /* Disable HCINTs */
1767         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1768
1769         /* Disable HAINTs */
1770         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1771
1772         /* Read HAINT */
1773         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1774
1775         /* Read HCINT */
1776         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1777
1778         /* Read HCCHAR */
1779         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1780
1781         /* Clear HCINT */
1782         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1783
1784         /* Clear HAINT */
1785         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1786
1787         /* Clear GINTSTS */
1788         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1789
1790         /* Read GINTSTS */
1791         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1792 }
1793
1794 static void do_in_ack(void)
1795 {
1796         gintsts_data_t gintsts;
1797         hctsiz_data_t hctsiz;
1798         hcchar_data_t hcchar;
1799         haint_data_t haint;
1800         hcint_data_t hcint;
1801         host_grxsts_data_t grxsts;
1802
1803         /* Enable HAINTs */
1804         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1805
1806         /* Enable HCINTs */
1807         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1808
1809         /* Read GINTSTS */
1810         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1811
1812         /* Read HAINT */
1813         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1814
1815         /* Read HCINT */
1816         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1817
1818         /* Read HCCHAR */
1819         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1820
1821         /* Clear HCINT */
1822         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1823
1824         /* Clear HAINT */
1825         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1826
1827         /* Clear GINTSTS */
1828         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1829
1830         /* Read GINTSTS */
1831         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1832
1833         /*
1834          * Receive Control In packet
1835          */
1836
1837         /* Make sure channel is disabled */
1838         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1839         if (hcchar.b.chen) {
1840                 hcchar.b.chdis = 1;
1841                 hcchar.b.chen = 1;
1842                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1843                 /* sleep(1); */
1844                 dwc_mdelay(1000);
1845
1846                 /* Read GINTSTS */
1847                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1848
1849                 /* Read HAINT */
1850                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1851
1852                 /* Read HCINT */
1853                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1854
1855                 /* Read HCCHAR */
1856                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1857
1858                 /* Clear HCINT */
1859                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1860
1861                 /* Clear HAINT */
1862                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1863
1864                 /* Clear GINTSTS */
1865                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1866
1867                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1868         }
1869
1870         /* Set HCTSIZ */
1871         hctsiz.d32 = 0;
1872         hctsiz.b.xfersize = 8;
1873         hctsiz.b.pktcnt = 1;
1874         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1875         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1876
1877         /* Set HCCHAR */
1878         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1879         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1880         hcchar.b.epdir = 1;
1881         hcchar.b.epnum = 0;
1882         hcchar.b.mps = 8;
1883         hcchar.b.chen = 1;
1884         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1885
1886         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1887
1888         /* Wait for receive status queue interrupt */
1889         do {
1890                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1891         } while (gintsts.b.rxstsqlvl == 0);
1892
1893         /* Read RXSTS */
1894         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1895
1896         /* Clear RXSTSQLVL in GINTSTS */
1897         gintsts.d32 = 0;
1898         gintsts.b.rxstsqlvl = 1;
1899         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1900
1901         switch (grxsts.b.pktsts) {
1902         case DWC_GRXSTS_PKTSTS_IN:
1903                 /* Read the data into the host buffer */
1904                 if (grxsts.b.bcnt > 0) {
1905                         int i;
1906                         int word_count = (grxsts.b.bcnt + 3) / 4;
1907
1908                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1909
1910                         for (i = 0; i < word_count; i++) {
1911                                 (void)DWC_READ_REG32(data_fifo++);
1912                         }
1913                 }
1914                 break;
1915
1916         default:
1917                 break;
1918         }
1919
1920         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1921
1922         /* Wait for receive status queue interrupt */
1923         do {
1924                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1925         } while (gintsts.b.rxstsqlvl == 0);
1926
1927         /* Read RXSTS */
1928         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1929
1930         /* Clear RXSTSQLVL in GINTSTS */
1931         gintsts.d32 = 0;
1932         gintsts.b.rxstsqlvl = 1;
1933         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1934
1935         switch (grxsts.b.pktsts) {
1936         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1937                 break;
1938
1939         default:
1940                 break;
1941         }
1942
1943         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1944
1945         /* Wait for host channel interrupt */
1946         do {
1947                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1948         } while (gintsts.b.hcintr == 0);
1949
1950         /* Read HAINT */
1951         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1952
1953         /* Read HCINT */
1954         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1955
1956         /* Read HCCHAR */
1957         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1958
1959         /* Clear HCINT */
1960         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1961
1962         /* Clear HAINT */
1963         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1964
1965         /* Clear GINTSTS */
1966         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1967
1968         /* Read GINTSTS */
1969         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1970
1971         /* usleep(100000); */
1972         /* mdelay(100); */
1973         dwc_mdelay(1);
1974
1975         /*
1976          * Send handshake packet
1977          */
1978
1979         /* Read HAINT */
1980         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1981
1982         /* Read HCINT */
1983         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1984
1985         /* Read HCCHAR */
1986         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1987
1988         /* Clear HCINT */
1989         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1990
1991         /* Clear HAINT */
1992         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1993
1994         /* Clear GINTSTS */
1995         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1996
1997         /* Read GINTSTS */
1998         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1999
2000         /* Make sure channel is disabled */
2001         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2002         if (hcchar.b.chen) {
2003                 hcchar.b.chdis = 1;
2004                 hcchar.b.chen = 1;
2005                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2006                 /* sleep(1); */
2007                 dwc_mdelay(1000);
2008
2009                 /* Read GINTSTS */
2010                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2011
2012                 /* Read HAINT */
2013                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2014
2015                 /* Read HCINT */
2016                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2017
2018                 /* Read HCCHAR */
2019                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2020
2021                 /* Clear HCINT */
2022                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2023
2024                 /* Clear HAINT */
2025                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2026
2027                 /* Clear GINTSTS */
2028                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2029
2030                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2031         }
2032
2033         /* Set HCTSIZ */
2034         hctsiz.d32 = 0;
2035         hctsiz.b.xfersize = 0;
2036         hctsiz.b.pktcnt = 1;
2037         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2038         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2039
2040         /* Set HCCHAR */
2041         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2042         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2043         hcchar.b.epdir = 0;
2044         hcchar.b.epnum = 0;
2045         hcchar.b.mps = 8;
2046         hcchar.b.chen = 1;
2047         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2048
2049         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2050
2051         /* Wait for host channel interrupt */
2052         do {
2053                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2054         } while (gintsts.b.hcintr == 0);
2055
2056         /* Disable HCINTs */
2057         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2058
2059         /* Disable HAINTs */
2060         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2061
2062         /* Read HAINT */
2063         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2064
2065         /* Read HCINT */
2066         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2067
2068         /* Read HCCHAR */
2069         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2070
2071         /* Clear HCINT */
2072         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2073
2074         /* Clear HAINT */
2075         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2076
2077         /* Clear GINTSTS */
2078         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2079
2080         /* Read GINTSTS */
2081         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2082 }
2083 #endif
2084
2085 /** Handles hub class-specific requests. */
2086 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2087                             uint16_t typeReq,
2088                             uint16_t wValue,
2089                             uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2090 {
2091         int retval = 0;
2092
2093         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2094         usb_hub_descriptor_t *hub_desc;
2095         hprt0_data_t hprt0 = {.d32 = 0 };
2096
2097         uint32_t port_status;
2098
2099         switch (typeReq) {
2100         case UCR_CLEAR_HUB_FEATURE:
2101                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2102                             "ClearHubFeature 0x%x\n", wValue);
2103                 switch (wValue) {
2104                 case UHF_C_HUB_LOCAL_POWER:
2105                 case UHF_C_HUB_OVER_CURRENT:
2106                         /* Nothing required here */
2107                         break;
2108                 default:
2109                         retval = -DWC_E_INVALID;
2110                         DWC_ERROR("DWC OTG HCD - "
2111                                   "ClearHubFeature request %xh unknown\n",
2112                                   wValue);
2113                 }
2114                 break;
2115         case UCR_CLEAR_PORT_FEATURE:
2116 #ifdef CONFIG_USB_DWC_OTG_LPM
2117                 if (wValue != UHF_PORT_L1)
2118 #endif
2119                         if (!wIndex || wIndex > 1)
2120                                 goto error;
2121
2122                 switch (wValue) {
2123                 case UHF_PORT_ENABLE:
2124                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2125                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2126                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2127                         hprt0.b.prtena = 1;
2128                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2129                         break;
2130                 case UHF_PORT_SUSPEND:
2131                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2132                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2133
2134                         if (core_if->power_down == 2) {
2135                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2136                         } else {
2137                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2138                                 dwc_mdelay(5);
2139
2140                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2141                                 hprt0.b.prtres = 1;
2142                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2143                                                 hprt0.d32);
2144                                 hprt0.b.prtsusp = 0;
2145                                 /* Clear Resume bit */
2146                                 dwc_mdelay(100);
2147                                 hprt0.b.prtres = 0;
2148                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2149                                                 hprt0.d32);
2150                         }
2151                         break;
2152 #ifdef CONFIG_USB_DWC_OTG_LPM
2153                 case UHF_PORT_L1:
2154                         {
2155                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2156                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2157
2158                                 lpmcfg.d32 =
2159                                     DWC_READ_REG32(&core_if->core_global_regs->
2160                                                    glpmcfg);
2161                                 lpmcfg.b.en_utmi_sleep = 0;
2162                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2163                                 lpmcfg.b.prt_sleep_sts = 1;
2164                                 DWC_WRITE_REG32(&core_if->core_global_regs->
2165                                                 glpmcfg, lpmcfg.d32);
2166
2167                                 /* Clear Enbl_L1Gating bit. */
2168                                 pcgcctl.b.enbl_sleep_gating = 1;
2169                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2170                                                  0);
2171
2172                                 dwc_mdelay(5);
2173
2174                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2175                                 hprt0.b.prtres = 1;
2176                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2177                                                 hprt0.d32);
2178                                 /* This bit will be cleared in wakeup interrupt handle */
2179                                 break;
2180                         }
2181 #endif
2182                 case UHF_PORT_POWER:
2183                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2184                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2185                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2186                         hprt0.b.prtpwr = 0;
2187                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2188                         break;
2189                 case UHF_PORT_INDICATOR:
2190                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2191                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2192                         /* Port inidicator not supported */
2193                         break;
2194                 case UHF_C_PORT_CONNECTION:
2195                         /* Clears drivers internal connect status change
2196                          * flag */
2197                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2198                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2199                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2200                         break;
2201                 case UHF_C_PORT_RESET:
2202                         /* Clears the driver's internal Port Reset Change
2203                          * flag */
2204                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2205                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2206                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2207                         break;
2208                 case UHF_C_PORT_ENABLE:
2209                         /* Clears the driver's internal Port
2210                          * Enable/Disable Change flag */
2211                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2212                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2213                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2214                         break;
2215                 case UHF_C_PORT_SUSPEND:
2216                         /* Clears the driver's internal Port Suspend
2217                          * Change flag, which is set when resume signaling on
2218                          * the host port is complete */
2219                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2220                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2221                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2222                         break;
2223 #ifdef CONFIG_USB_DWC_OTG_LPM
2224                 case UHF_C_PORT_L1:
2225                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2226                         break;
2227 #endif
2228                 case UHF_C_PORT_OVER_CURRENT:
2229                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2230                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2231                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2232                         break;
2233                 default:
2234                         retval = -DWC_E_INVALID;
2235                         DWC_ERROR("DWC OTG HCD - "
2236                                   "ClearPortFeature request %xh "
2237                                   "unknown or unsupported\n", wValue);
2238                 }
2239                 break;
2240         case UCR_GET_HUB_DESCRIPTOR:
2241                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2242                             "GetHubDescriptor\n");
2243                 hub_desc = (usb_hub_descriptor_t *) buf;
2244                 hub_desc->bDescLength = 9;
2245                 hub_desc->bDescriptorType = 0x29;
2246                 hub_desc->bNbrPorts = 1;
2247                 USETW(hub_desc->wHubCharacteristics, 0x08);
2248                 hub_desc->bPwrOn2PwrGood = 1;
2249                 hub_desc->bHubContrCurrent = 0;
2250                 hub_desc->DeviceRemovable[0] = 0;
2251                 hub_desc->DeviceRemovable[1] = 0xff;
2252                 break;
2253         case UCR_GET_HUB_STATUS:
2254                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2255                             "GetHubStatus\n");
2256                 DWC_MEMSET(buf, 0, 4);
2257                 break;
2258         case UCR_GET_PORT_STATUS:
2259                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2260                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2261                             wIndex, dwc_otg_hcd->flags.d32);
2262                 if (!wIndex || wIndex > 1)
2263                         goto error;
2264
2265                 port_status = 0;
2266
2267                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2268                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2269
2270                 if (dwc_otg_hcd->flags.b.port_enable_change)
2271                         port_status |= (1 << UHF_C_PORT_ENABLE);
2272
2273                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2274                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2275
2276                 if (dwc_otg_hcd->flags.b.port_l1_change)
2277                         port_status |= (1 << UHF_C_PORT_L1);
2278
2279                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2280                         port_status |= (1 << UHF_C_PORT_RESET);
2281                 }
2282
2283                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2284                         DWC_WARN("Overcurrent change detected\n");
2285                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2286                 }
2287
2288                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2289                         /*
2290                          * The port is disconnected, which means the core is
2291                          * either in device mode or it soon will be. Just
2292                          * return 0's for the remainder of the port status
2293                          * since the port register can't be read if the core
2294                          * is in device mode.
2295                          */
2296                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2297                         break;
2298                 }
2299
2300                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2301                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2302
2303                 if (hprt0.b.prtconnsts)
2304                         port_status |= (1 << UHF_PORT_CONNECTION);
2305
2306                 if (hprt0.b.prtena)
2307                         port_status |= (1 << UHF_PORT_ENABLE);
2308
2309                 if (hprt0.b.prtsusp)
2310                         port_status |= (1 << UHF_PORT_SUSPEND);
2311
2312                 if (hprt0.b.prtovrcurract)
2313                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2314
2315                 if (hprt0.b.prtrst)
2316                         port_status |= (1 << UHF_PORT_RESET);
2317
2318                 if (hprt0.b.prtpwr)
2319                         port_status |= (1 << UHF_PORT_POWER);
2320
2321                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2322                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2323                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2324                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2325
2326                 if (hprt0.b.prttstctl)
2327                         port_status |= (1 << UHF_PORT_TEST);
2328                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2329                         port_status |= (1 << UHF_PORT_L1);
2330                 }
2331                 /*
2332                    For Synopsys HW emulation of Power down wkup_control asserts the
2333                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2334                    We intentionally tell the software that port is in L2Suspend state.
2335                    Only for STE.
2336                  */
2337                 if ((core_if->power_down == 2)
2338                     && (core_if->hibernation_suspend == 1)) {
2339                         port_status |= (1 << UHF_PORT_SUSPEND);
2340                 }
2341                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2342
2343                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2344
2345                 break;
2346         case UCR_SET_HUB_FEATURE:
2347                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2348                             "SetHubFeature\n");
2349                 /* No HUB features supported */
2350                 break;
2351         case UCR_SET_PORT_FEATURE:
2352                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2353                         goto error;
2354
2355                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2356                         /*
2357                          * The port is disconnected, which means the core is
2358                          * either in device mode or it soon will be. Just
2359                          * return without doing anything since the port
2360                          * register can't be written if the core is in device
2361                          * mode.
2362                          */
2363                         break;
2364                 }
2365
2366                 switch (wValue) {
2367                 case UHF_PORT_SUSPEND:
2368                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2369                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2370                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2371                                 goto error;
2372                         }
2373                         if (core_if->power_down == 2) {
2374                                 int timeout = 300;
2375                                 dwc_irqflags_t flags;
2376                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2377                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2378                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2379 #ifdef DWC_DEV_SRPCAP
2380                                 int32_t otg_cap_param =
2381                                     core_if->core_params->otg_cap;
2382 #endif
2383                                 DWC_PRINTF
2384                                     ("Preparing for complete power-off\n");
2385
2386                                 /* Save registers before hibernation */
2387                                 dwc_otg_save_global_regs(core_if);
2388                                 dwc_otg_save_host_regs(core_if);
2389
2390                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2391                                 hprt0.b.prtsusp = 1;
2392                                 hprt0.b.prtena = 0;
2393                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2394                                                 hprt0.d32);
2395                                 /* Spin hprt0.b.prtsusp to became 1 */
2396                                 do {
2397                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2398                                         if (hprt0.b.prtsusp) {
2399                                                 break;
2400                                         }
2401                                         dwc_mdelay(1);
2402                                 } while (--timeout);
2403                                 if (!timeout) {
2404                                         DWC_WARN("Suspend wasn't genereted\n");
2405                                 }
2406                                 dwc_udelay(10);
2407
2408                                 /*
2409                                  * We need to disable interrupts to prevent servicing of any IRQ
2410                                  * during going to hibernation
2411                                  */
2412                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2413                                 core_if->lx_state = DWC_OTG_L2;
2414 #ifdef DWC_DEV_SRPCAP
2415                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2416                                 hprt0.b.prtpwr = 0;
2417                                 hprt0.b.prtena = 0;
2418                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2419                                                 hprt0.d32);
2420 #endif
2421                                 gusbcfg.d32 =
2422                                     DWC_READ_REG32(&core_if->
2423                                                    core_global_regs->gusbcfg);
2424                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2425                                         /* ULPI interface */
2426                                         /* Suspend the Phy Clock */
2427                                         pcgcctl.d32 = 0;
2428                                         pcgcctl.b.stoppclk = 1;
2429                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2430                                                          pcgcctl.d32);
2431                                         dwc_udelay(10);
2432                                         gpwrdn.b.pmuactv = 1;
2433                                         DWC_MODIFY_REG32
2434                                             (&core_if->core_global_regs->gpwrdn,
2435                                              0, gpwrdn.d32);
2436                                 } else {
2437                                         /* UTMI+ Interface */
2438                                         gpwrdn.b.pmuactv = 1;
2439                                         DWC_MODIFY_REG32
2440                                             (&core_if->core_global_regs->gpwrdn,
2441                                              0, gpwrdn.d32);
2442                                         dwc_udelay(10);
2443                                         pcgcctl.b.stoppclk = 1;
2444                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2445                                                          pcgcctl.d32);
2446                                         dwc_udelay(10);
2447                                 }
2448 #ifdef DWC_DEV_SRPCAP
2449                                 gpwrdn.d32 = 0;
2450                                 gpwrdn.b.dis_vbus = 1;
2451                                 DWC_MODIFY_REG32(&core_if->
2452                                                  core_global_regs->gpwrdn, 0,
2453                                                  gpwrdn.d32);
2454 #endif
2455                                 gpwrdn.d32 = 0;
2456                                 gpwrdn.b.pmuintsel = 1;
2457                                 DWC_MODIFY_REG32(&core_if->
2458                                                  core_global_regs->gpwrdn, 0,
2459                                                  gpwrdn.d32);
2460                                 dwc_udelay(10);
2461
2462                                 gpwrdn.d32 = 0;
2463 #ifdef DWC_DEV_SRPCAP
2464                                 gpwrdn.b.srp_det_msk = 1;
2465 #endif
2466                                 gpwrdn.b.disconn_det_msk = 1;
2467                                 gpwrdn.b.lnstchng_msk = 1;
2468                                 gpwrdn.b.sts_chngint_msk = 1;
2469                                 DWC_MODIFY_REG32(&core_if->
2470                                                  core_global_regs->gpwrdn, 0,
2471                                                  gpwrdn.d32);
2472                                 dwc_udelay(10);
2473
2474                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2475                                 gpwrdn.d32 = 0;
2476                                 gpwrdn.b.pwrdnclmp = 1;
2477                                 DWC_MODIFY_REG32(&core_if->
2478                                                  core_global_regs->gpwrdn, 0,
2479                                                  gpwrdn.d32);
2480                                 dwc_udelay(10);
2481
2482                                 /* Switch off VDD */
2483                                 gpwrdn.d32 = 0;
2484                                 gpwrdn.b.pwrdnswtch = 1;
2485                                 DWC_MODIFY_REG32(&core_if->
2486                                                  core_global_regs->gpwrdn, 0,
2487                                                  gpwrdn.d32);
2488
2489 #ifdef DWC_DEV_SRPCAP
2490                                 if (otg_cap_param ==
2491                                     DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2492                                         core_if->pwron_timer_started = 1;
2493                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2494                                                            6000 /* 6 secs */);
2495                                 }
2496 #endif
2497                                 /* Save gpwrdn register for further usage if stschng interrupt */
2498                                 core_if->gr_backup->gpwrdn_local =
2499                                     DWC_READ_REG32(&core_if->core_global_regs->
2500                                                    gpwrdn);
2501
2502                                 /* Set flag to indicate that we are in hibernation */
2503                                 core_if->hibernation_suspend = 1;
2504                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2505                                                           flags);
2506
2507                                 DWC_PRINTF("Host hibernation completed\n");
2508                                 /* Exit from case statement */
2509                                 break;
2510
2511                         }
2512                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2513                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2514                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2515                                 gotgctl.b.hstsethnpen = 1;
2516                                 DWC_MODIFY_REG32(&core_if->
2517                                                  core_global_regs->gotgctl, 0,
2518                                                  gotgctl.d32);
2519                                 core_if->op_state = A_SUSPEND;
2520                         }
2521                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2522                         hprt0.b.prtsusp = 1;
2523                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2524                         {
2525                                 dwc_irqflags_t flags;
2526                                 /* Update lx_state */
2527                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2528                                 core_if->lx_state = DWC_OTG_L2;
2529                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2530                                                           flags);
2531                         }
2532                         /* Suspend the Phy Clock */
2533                         if (core_if->otg_ver == 0) {
2534                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2535                                 pcgcctl.b.stoppclk = 1;
2536                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2537                                                  pcgcctl.d32);
2538                                 dwc_udelay(10);
2539                         }
2540
2541                         /* For HNP the bus must be suspended for at least 200ms. */
2542                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2543                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2544                                 pcgcctl.b.stoppclk = 1;
2545                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2546                                                  0);
2547                                 dwc_mdelay(200);
2548                         }
2549
2550                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2551 #if 0
2552                         if (core_if->adp_enable) {
2553                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2554                                 gpwrdn_data_t gpwrdn;
2555
2556                                 while (gotgctl.b.asesvld == 1) {
2557                                         gotgctl.d32 =
2558                                             DWC_READ_REG32
2559                                             (&core_if->core_global_regs->gotgctl);
2560                                         dwc_mdelay(100);
2561                                 }
2562
2563                                 /* Enable Power Down Logic */
2564                                 gpwrdn.d32 = 0;
2565                                 gpwrdn.b.pmuactv = 1;
2566                                 DWC_MODIFY_REG32(&core_if->
2567                                                  core_global_regs->gpwrdn, 0,
2568                                                  gpwrdn.d32);
2569
2570                                 /* Unmask SRP detected interrupt from Power Down Logic */
2571                                 gpwrdn.d32 = 0;
2572                                 gpwrdn.b.srp_det_msk = 1;
2573                                 DWC_MODIFY_REG32(&core_if->
2574                                                  core_global_regs->gpwrdn, 0,
2575                                                  gpwrdn.d32);
2576
2577                                 dwc_otg_adp_probe_start(core_if);
2578                         }
2579 #endif
2580                         break;
2581                 case UHF_PORT_POWER:
2582                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2583                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2584                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2585                         hprt0.b.prtpwr = 1;
2586                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2587                         break;
2588                 case UHF_PORT_RESET:
2589                         if ((core_if->power_down == 2)
2590                             && (core_if->hibernation_suspend == 1)) {
2591                                 /* If we are going to exit from Hibernated
2592                                  * state via USB RESET.
2593                                  */
2594                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2595                         } else {
2596                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2597
2598                                 DWC_DEBUGPL(DBG_HCD,
2599                                             "DWC OTG HCD HUB CONTROL - "
2600                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2601                                 {
2602                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2603                                         pcgcctl.b.enbl_sleep_gating = 1;
2604                                         pcgcctl.b.stoppclk = 1;
2605                                         DWC_MODIFY_REG32(core_if->pcgcctl,
2606                                                          pcgcctl.d32, 0);
2607                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2608                                 }
2609 #ifdef CONFIG_USB_DWC_OTG_LPM
2610                                 {
2611                                         glpmcfg_data_t lpmcfg;
2612                                         lpmcfg.d32 =
2613                                             DWC_READ_REG32(&core_if->
2614                                                            core_global_regs->
2615                                                            glpmcfg);
2616                                         if (lpmcfg.b.prt_sleep_sts) {
2617                                                 lpmcfg.b.en_utmi_sleep = 0;
2618                                                 lpmcfg.b.hird_thres &=
2619                                                     (~(1 << 4));
2620                                                 DWC_WRITE_REG32(&core_if->
2621                                                                 core_global_regs->
2622                                                                 glpmcfg,
2623                                                                 lpmcfg.d32);
2624                                                 dwc_mdelay(1);
2625                                         }
2626                                 }
2627 #endif
2628                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2629                                 /* Clear suspend bit if resetting from suspended state. */
2630                                 hprt0.b.prtsusp = 0;
2631                                 /* When B-Host the Port reset bit is set in
2632                                  * the Start HCD Callback function, so that
2633                                  * the reset is started within 1ms of the HNP
2634                                  * success interrupt. */
2635                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2636                                         hprt0.b.prtpwr = 1;
2637                                         hprt0.b.prtrst = 1;
2638                                         DWC_PRINTF
2639                                             ("Indeed it is in host mode hprt0 = %08x\n",
2640                                              hprt0.d32);
2641                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2642                                                         hprt0.d32);
2643                                 }
2644                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2645                                 dwc_mdelay(60);
2646                                 hprt0.b.prtrst = 0;
2647                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2648                                                 hprt0.d32);
2649                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2650                         }
2651                         break;
2652 #ifdef DWC_HS_ELECT_TST
2653                 case UHF_PORT_TEST:
2654                         {
2655                                 uint32_t t;
2656                                 gintmsk_data_t gintmsk;
2657
2658                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2659                                 DWC_DEBUGPL(DBG_HCD,
2660                                             "DWC OTG HCD HUB CONTROL - "
2661                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2662                                             t);
2663                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2664                                 if (t < 6) {
2665                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2666                                         hprt0.b.prttstctl = t;
2667                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2668                                                         hprt0.d32);
2669                                 } else {
2670                                         /* Setup global vars with reg addresses (quick and
2671                                          * dirty hack, should be cleaned up)
2672                                          */
2673                                         global_regs = core_if->core_global_regs;
2674                                         hc_global_regs =
2675                                             core_if->host_if->host_global_regs;
2676                                         hc_regs =
2677                                             (dwc_otg_hc_regs_t *) ((char *)
2678                                                                    global_regs +
2679                                                                    0x500);
2680                                         data_fifo =
2681                                             (uint32_t *) ((char *)global_regs +
2682                                                           0x1000);
2683
2684                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2685                                                 /* Save current interrupt mask */
2686                                                 gintmsk.d32 =
2687                                                     DWC_READ_REG32
2688                                                     (&global_regs->gintmsk);
2689
2690                                                 /* Disable all interrupts while we muck with
2691                                                  * the hardware directly
2692                                                  */
2693                                                 DWC_WRITE_REG32(&global_regs->
2694                                                                 gintmsk, 0);
2695
2696                                                 /* 15 second delay per the test spec */
2697                                                 dwc_mdelay(15000);
2698
2699                                                 /* Drive suspend on the root port */
2700                                                 hprt0.d32 =
2701                                                     dwc_otg_read_hprt0(core_if);
2702                                                 hprt0.b.prtsusp = 1;
2703                                                 hprt0.b.prtres = 0;
2704                                                 DWC_WRITE_REG32(core_if->
2705                                                                 host_if->hprt0,
2706                                                                 hprt0.d32);
2707
2708                                                 /* 15 second delay per the test spec */
2709                                                 dwc_mdelay(15000);
2710
2711                                                 /* Drive resume on the root port */
2712                                                 hprt0.d32 =
2713                                                     dwc_otg_read_hprt0(core_if);
2714                                                 hprt0.b.prtsusp = 0;
2715                                                 hprt0.b.prtres = 1;
2716                                                 DWC_WRITE_REG32(core_if->
2717                                                                 host_if->hprt0,
2718                                                                 hprt0.d32);
2719                                                 dwc_mdelay(100);
2720
2721                                                 /* Clear the resume bit */
2722                                                 hprt0.b.prtres = 0;
2723                                                 DWC_WRITE_REG32(core_if->
2724                                                                 host_if->hprt0,
2725                                                                 hprt0.d32);
2726
2727                                                 /* Restore interrupts */
2728                                                 DWC_WRITE_REG32(&global_regs->
2729                                                                 gintmsk,
2730                                                                 gintmsk.d32);
2731                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2732                                                 /* Save current interrupt mask */
2733                                                 gintmsk.d32 =
2734                                                     DWC_READ_REG32
2735                                                     (&global_regs->gintmsk);
2736
2737                                                 /* Disable all interrupts while we muck with
2738                                                  * the hardware directly
2739                                                  */
2740                                                 DWC_WRITE_REG32(&global_regs->
2741                                                                 gintmsk, 0);
2742
2743                                                 /* 15 second delay per the test spec */
2744                                                 dwc_mdelay(15000);
2745
2746                                                 /* Send the Setup packet */
2747                                                 do_setup();
2748
2749                                                 /* 15 second delay so nothing else happens for awhile */
2750                                                 dwc_mdelay(15000);
2751
2752                                                 /* Restore interrupts */
2753                                                 DWC_WRITE_REG32(&global_regs->
2754                                                                 gintmsk,
2755                                                                 gintmsk.d32);
2756                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2757                                                 /* Save current interrupt mask */
2758                                                 gintmsk.d32 =
2759                                                     DWC_READ_REG32
2760                                                     (&global_regs->gintmsk);
2761
2762                                                 /* Disable all interrupts while we muck with
2763                                                  * the hardware directly
2764                                                  */
2765                                                 DWC_WRITE_REG32(&global_regs->
2766                                                                 gintmsk, 0);
2767
2768                                                 /* Send the Setup packet */
2769                                                 do_setup();
2770
2771                                                 /* 15 second delay so nothing else happens for awhile */
2772                                                 dwc_mdelay(15000);
2773
2774                                                 /* Send the In and Ack packets */
2775                                                 do_in_ack();
2776
2777                                                 /* 15 second delay so nothing else happens for awhile */
2778                                                 dwc_mdelay(15000);
2779
2780                                                 /* Restore interrupts */
2781                                                 DWC_WRITE_REG32(&global_regs->
2782                                                                 gintmsk,
2783                                                                 gintmsk.d32);
2784                                         }
2785                                 }
2786                                 break;
2787                         }
2788 #endif /* DWC_HS_ELECT_TST */
2789
2790                 case UHF_PORT_INDICATOR:
2791                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2792                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2793                         /* Not supported */
2794                         break;
2795                 default:
2796                         retval = -DWC_E_INVALID;
2797                         DWC_ERROR("DWC OTG HCD - "
2798                                   "SetPortFeature request %xh "
2799                                   "unknown or unsupported\n", wValue);
2800                         break;
2801                 }
2802                 break;
2803 #ifdef CONFIG_USB_DWC_OTG_LPM
2804         case UCR_SET_AND_TEST_PORT_FEATURE:
2805                 if (wValue != UHF_PORT_L1) {
2806                         goto error;
2807                 }
2808                 {
2809                         int portnum, hird, devaddr, remwake;
2810                         glpmcfg_data_t lpmcfg;
2811                         uint32_t time_usecs;
2812                         gintsts_data_t gintsts;
2813                         gintmsk_data_t gintmsk;
2814
2815                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2816                                 goto error;
2817                         }
2818                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2819                                 goto error;
2820                         }
2821                         /* Check if the port currently is in SLEEP state */
2822                         lpmcfg.d32 =
2823                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2824                         if (lpmcfg.b.prt_sleep_sts) {
2825                                 DWC_INFO("Port is already in sleep mode\n");
2826                                 buf[0] = 0;     /* Return success */
2827                                 break;
2828                         }
2829
2830                         portnum = wIndex & 0xf;
2831                         hird = (wIndex >> 4) & 0xf;
2832                         devaddr = (wIndex >> 8) & 0x7f;
2833                         remwake = (wIndex >> 15);
2834
2835                         if (portnum != 1) {
2836                                 retval = -DWC_E_INVALID;
2837                                 DWC_WARN
2838                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2839                                      portnum);
2840                                 break;
2841                         }
2842
2843                         DWC_PRINTF
2844                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2845                              portnum, hird, devaddr, remwake);
2846                         /* Disable LPM interrupt */
2847                         gintmsk.d32 = 0;
2848                         gintmsk.b.lpmtranrcvd = 1;
2849                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2850                                          gintmsk.d32, 0);
2851
2852                         if (dwc_otg_hcd_send_lpm
2853                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2854                                 retval = -DWC_E_INVALID;
2855                                 break;
2856                         }
2857
2858                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2859                         /* We will consider timeout if time_usecs microseconds pass,
2860                          * and we don't receive LPM transaction status.
2861                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2862                          *  core will set lpmtranrcvd bit.
2863                          */
2864                         do {
2865                                 gintsts.d32 =
2866                                     DWC_READ_REG32(&core_if->core_global_regs->
2867                                                    gintsts);
2868                                 if (gintsts.b.lpmtranrcvd) {
2869                                         break;
2870                                 }
2871                                 dwc_udelay(1);
2872                         } while (--time_usecs);
2873                         /* lpm_int bit will be cleared in LPM interrupt handler */
2874
2875                         /* Now fill status
2876                          * 0x00 - Success
2877                          * 0x10 - NYET
2878                          * 0x11 - Timeout
2879                          */
2880                         if (!gintsts.b.lpmtranrcvd) {
2881                                 buf[0] = 0x3;   /* Completion code is Timeout */
2882                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2883                         } else {
2884                                 lpmcfg.d32 =
2885                                     DWC_READ_REG32(&core_if->core_global_regs->
2886                                                    glpmcfg);
2887                                 if (lpmcfg.b.lpm_resp == 0x3) {
2888                                         /* ACK responce from the device */
2889                                         buf[0] = 0x00;  /* Success */
2890                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2891                                         /* NYET responce from the device */
2892                                         buf[0] = 0x2;
2893                                 } else {
2894                                         /* Otherwise responce with Timeout */
2895                                         buf[0] = 0x3;
2896                                 }
2897                         }
2898                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2899                                    lpmcfg.b.lpm_resp);
2900                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2901                                          gintmsk.d32);
2902
2903                         break;
2904                 }
2905 #endif /* CONFIG_USB_DWC_OTG_LPM */
2906         default:
2907 error:
2908                 retval = -DWC_E_INVALID;
2909                 DWC_WARN("DWC OTG HCD - "
2910                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2911                          typeReq, wIndex, wValue);
2912                 break;
2913         }
2914
2915         return retval;
2916 }
2917
2918 #ifdef CONFIG_USB_DWC_OTG_LPM
2919 /** Returns index of host channel to perform LPM transaction. */
2920 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2921 {
2922         dwc_otg_core_if_t *core_if = hcd->core_if;
2923         dwc_hc_t *hc;
2924         hcchar_data_t hcchar;
2925         gintmsk_data_t gintmsk = {.d32 = 0 };
2926
2927         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2928                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2929                 return -1;
2930         }
2931
2932         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2933
2934         /* Mask host channel interrupts. */
2935         gintmsk.b.hcintr = 1;
2936         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2937
2938         /* Fill fields that core needs for LPM transaction */
2939         hcchar.b.devaddr = devaddr;
2940         hcchar.b.epnum = 0;
2941         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2942         hcchar.b.mps = 64;
2943         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2944         hcchar.b.epdir = 0;     /* OUT */
2945         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2946                         hcchar.d32);
2947
2948         /* Remove the host channel from the free list. */
2949         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2950
2951         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2952
2953         return hc->hc_num;
2954 }
2955
2956 /** Release hc after performing LPM transaction */
2957 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2958 {
2959         dwc_hc_t *hc;
2960         glpmcfg_data_t lpmcfg;
2961         uint8_t hc_num;
2962
2963         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2964         hc_num = lpmcfg.b.lpm_chan_index;
2965
2966         hc = hcd->hc_ptr_array[hc_num];
2967
2968         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2969         /* Return host channel to free list */
2970         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2971 }
2972
2973 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2974                          uint8_t bRemoteWake)
2975 {
2976         glpmcfg_data_t lpmcfg;
2977         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2978         int channel;
2979
2980         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2981         if (channel < 0) {
2982                 return channel;
2983         }
2984
2985         pcgcctl.b.enbl_sleep_gating = 1;
2986         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2987
2988         /* Read LPM config register */
2989         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2990
2991         /* Program LPM transaction fields */
2992         lpmcfg.b.rem_wkup_en = bRemoteWake;
2993         lpmcfg.b.hird = hird;
2994
2995         if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2996                 lpmcfg.b.hird_thres = 0x16;
2997                 lpmcfg.b.en_besl = 1;
2998         } else {
2999                 lpmcfg.b.hird_thres = 0x1c;
3000         }
3001
3002         lpmcfg.b.lpm_chan_index = channel;
3003         lpmcfg.b.en_utmi_sleep = 1;
3004         /* Program LPM config register */
3005         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3006
3007         /* Send LPM transaction */
3008         lpmcfg.b.send_lpm = 1;
3009         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3010
3011         return 0;
3012 }
3013
3014 #endif /* CONFIG_USB_DWC_OTG_LPM */
3015
3016 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3017 {
3018         int retval;
3019
3020         if (port != 1) {
3021                 return -DWC_E_INVALID;
3022         }
3023
3024         retval = (hcd->flags.b.port_connect_status_change ||
3025                   hcd->flags.b.port_reset_change ||
3026                   hcd->flags.b.port_enable_change ||
3027                   hcd->flags.b.port_suspend_change ||
3028                   hcd->flags.b.port_over_current_change);
3029 #ifdef DEBUG
3030         if (retval) {
3031                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3032                             " Root port status changed\n");
3033                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
3034                             hcd->flags.b.port_connect_status_change);
3035                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
3036                             hcd->flags.b.port_reset_change);
3037                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
3038                             hcd->flags.b.port_enable_change);
3039                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
3040                             hcd->flags.b.port_suspend_change);
3041                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
3042                             hcd->flags.b.port_over_current_change);
3043         }
3044 #endif
3045         return retval;
3046 }
3047
3048 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3049 {
3050         hfnum_data_t hfnum;
3051         hfnum.d32 =
3052             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3053                            host_global_regs->hfnum);
3054
3055 #ifdef DEBUG_SOF
3056         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3057                     hfnum.b.frnum);
3058 #endif
3059         return hfnum.b.frnum;
3060 }
3061
3062 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3063                       struct dwc_otg_hcd_function_ops *fops)
3064 {
3065         int retval = 0;
3066
3067         hcd->fops = fops;
3068         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3069             (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3070                 dwc_otg_hcd_reinit(hcd);
3071         } else {
3072                 retval = -DWC_E_NO_DEVICE;
3073         }
3074
3075         return retval;
3076 }
3077
3078 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3079 {
3080         return hcd->priv;
3081 }
3082
3083 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3084 {
3085         hcd->priv = priv_data;
3086 }
3087
3088 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3089 {
3090         return hcd->otg_port;
3091 }
3092
3093 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3094 {
3095         uint32_t is_b_host;
3096         if (hcd->core_if->op_state == B_HOST) {
3097                 is_b_host = 1;
3098         } else {
3099                 is_b_host = 0;
3100         }
3101
3102         return is_b_host;
3103 }
3104
3105 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3106                                          int iso_desc_count, int atomic_alloc)
3107 {
3108         dwc_otg_hcd_urb_t *dwc_otg_urb;
3109         uint32_t size;
3110
3111         size =
3112             sizeof(*dwc_otg_urb) +
3113             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3114         if (atomic_alloc)
3115                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3116         else
3117                 dwc_otg_urb = DWC_ALLOC(size);
3118
3119         dwc_otg_urb->packet_count = iso_desc_count;
3120
3121         return dwc_otg_urb;
3122 }
3123
3124 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3125                                   uint8_t dev_addr, uint8_t ep_num,
3126                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3127 {
3128         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3129                               ep_type, ep_dir, mps);
3130 #if 0
3131         DWC_PRINTF
3132             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3133              dev_addr, ep_num, ep_dir, ep_type, mps);
3134 #endif
3135 }
3136
3137 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3138                                 void *urb_handle, void *buf, dwc_dma_t dma,
3139                                 uint32_t buflen, void *setup_packet,
3140                                 dwc_dma_t setup_dma, uint32_t flags,
3141                                 uint16_t interval)
3142 {
3143         dwc_otg_urb->priv = urb_handle;
3144         dwc_otg_urb->buf = buf;
3145         dwc_otg_urb->dma = dma;
3146         dwc_otg_urb->length = buflen;
3147         dwc_otg_urb->setup_packet = setup_packet;
3148         dwc_otg_urb->setup_dma = setup_dma;
3149         dwc_otg_urb->flags = flags;
3150         dwc_otg_urb->interval = interval;
3151         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3152 }
3153
3154 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3155 {
3156         return dwc_otg_urb->status;
3157 }
3158
3159 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3160 {
3161         return dwc_otg_urb->actual_length;
3162 }
3163
3164 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3165 {
3166         return dwc_otg_urb->error_count;
3167 }
3168
3169 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3170                                          int desc_num, uint32_t offset,
3171                                          uint32_t length)
3172 {
3173         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3174         dwc_otg_urb->iso_descs[desc_num].length = length;
3175 }
3176
3177 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3178                                              int desc_num)
3179 {
3180         return dwc_otg_urb->iso_descs[desc_num].status;
3181 }
3182
3183 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3184                                                     dwc_otg_urb, int desc_num)
3185 {
3186         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3187 }
3188
3189 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3190 {
3191         int allocated = 0;
3192         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3193
3194         if (qh) {
3195                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3196                         allocated = 1;
3197                 }
3198         }
3199         return allocated;
3200 }
3201
3202 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3203 {
3204         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3205         int freed = 0;
3206         DWC_ASSERT(qh, "qh is not allocated\n");
3207
3208         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3209                 freed = 1;
3210         }
3211
3212         return freed;
3213 }
3214
3215 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3216 {
3217         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3218         DWC_ASSERT(qh, "qh is not allocated\n");
3219         return qh->usecs;
3220 }
3221
3222 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3223 {
3224 #ifdef DEBUG
3225         int num_channels;
3226         int i;
3227         gnptxsts_data_t np_tx_status;
3228         hptxsts_data_t p_tx_status;
3229
3230         num_channels = hcd->core_if->core_params->host_channels;
3231         DWC_PRINTF("\n");
3232         DWC_PRINTF
3233             ("************************************************************\n");
3234         DWC_PRINTF("HCD State:\n");
3235         DWC_PRINTF("  Num channels: %d\n", num_channels);
3236         for (i = 0; i < num_channels; i++) {
3237                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3238                 DWC_PRINTF("  Channel %d:\n", i);
3239                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3240                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3241                 DWC_PRINTF("    speed: %d\n", hc->speed);
3242                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3243                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3244                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3245                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3246                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3247                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3248                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3249                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3250                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3251                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3252                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3253                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3254                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3255                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3256                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3257                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3258                 DWC_PRINTF("    requests: %d\n", hc->requests);
3259                 DWC_PRINTF("    qh: %p\n", hc->qh);
3260                 if (hc->xfer_started) {
3261                         hfnum_data_t hfnum;
3262                         hcchar_data_t hcchar;
3263                         hctsiz_data_t hctsiz;
3264                         hcint_data_t hcint;
3265                         hcintmsk_data_t hcintmsk;
3266                         hfnum.d32 =
3267                             DWC_READ_REG32(&hcd->core_if->host_if->
3268                                            host_global_regs->hfnum);
3269                         hcchar.d32 =
3270                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3271                                            hcchar);
3272                         hctsiz.d32 =
3273                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3274                                            hctsiz);
3275                         hcint.d32 =
3276                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3277                                            hcint);
3278                         hcintmsk.d32 =
3279                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3280                                            hcintmsk);
3281                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3282                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3283                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3284                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3285                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3286                 }
3287                 if (hc->xfer_started && hc->qh) {
3288                         dwc_otg_qtd_t *qtd;
3289                         dwc_otg_hcd_urb_t *urb;
3290
3291                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3292                                             qtd_list_entry) {
3293                                 if (!qtd->in_process)
3294                                         break;
3295
3296                                 urb = qtd->urb;
3297                                 DWC_PRINTF("    URB Info:\n");
3298                                 DWC_PRINTF("      qtd: %p, urb: %p\n", qtd,
3299                                            urb);
3300                                 if (urb) {
3301                                         DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3302                                                    dwc_otg_hcd_get_dev_addr
3303                                                    (&urb->pipe_info),
3304                                                    dwc_otg_hcd_get_ep_num
3305                                                    (&urb->pipe_info),
3306                                                    dwc_otg_hcd_is_pipe_in
3307                                                    (&urb->pipe_info) ? "IN" :
3308                                                    "OUT");
3309                                         DWC_PRINTF
3310                                             ("      Max packet size: %d\n",
3311                                              dwc_otg_hcd_get_mps
3312                                              (&urb->pipe_info));
3313                                         DWC_PRINTF
3314                                             ("      transfer_buffer: %p\n",
3315                                              urb->buf);
3316                                         DWC_PRINTF("      transfer_dma: %p\n",
3317                                                    (void *)urb->dma);
3318                                         DWC_PRINTF
3319                                             ("      transfer_buffer_length: %d\n",
3320                                              urb->length);
3321                                         DWC_PRINTF("      actual_length: %d\n",
3322                                                    urb->actual_length);
3323                                 }
3324                         }
3325                 }
3326         }
3327         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3328         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3329         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3330         np_tx_status.d32 =
3331             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3332         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3333                    np_tx_status.b.nptxqspcavail);
3334         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3335                    np_tx_status.b.nptxfspcavail);
3336         p_tx_status.d32 =
3337             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3338         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3339                    p_tx_status.b.ptxqspcavail);
3340         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3341         dwc_otg_hcd_dump_frrem(hcd);
3342         dwc_otg_dump_global_registers(hcd->core_if);
3343         dwc_otg_dump_host_registers(hcd->core_if);
3344         DWC_PRINTF
3345             ("************************************************************\n");
3346         DWC_PRINTF("\n");
3347 #endif
3348 }
3349
3350 #ifdef DEBUG
3351 void dwc_print_setup_data(uint8_t *setup)
3352 {
3353         int i;
3354         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3355                 DWC_PRINTF("Setup Data = MSB ");
3356                 for (i = 7; i >= 0; i--)
3357                         DWC_PRINTF("%02x ", setup[i]);
3358                 DWC_PRINTF("\n");
3359                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3360                            (setup[0] & 0x80) ? "Device-to-Host" :
3361                            "Host-to-Device");
3362                 DWC_PRINTF("  bmRequestType Type = ");
3363                 switch ((setup[0] & 0x60) >> 5) {
3364                 case 0:
3365                         DWC_PRINTF("Standard\n");
3366                         break;
3367                 case 1:
3368                         DWC_PRINTF("Class\n");
3369                         break;
3370                 case 2:
3371                         DWC_PRINTF("Vendor\n");
3372                         break;
3373                 case 3:
3374                         DWC_PRINTF("Reserved\n");
3375                         break;
3376                 }
3377                 DWC_PRINTF("  bmRequestType Recipient = ");
3378                 switch (setup[0] & 0x1f) {
3379                 case 0:
3380                         DWC_PRINTF("Device\n");
3381                         break;
3382                 case 1:
3383                         DWC_PRINTF("Interface\n");
3384                         break;
3385                 case 2:
3386                         DWC_PRINTF("Endpoint\n");
3387                         break;
3388                 case 3:
3389                         DWC_PRINTF("Other\n");
3390                         break;
3391                 default:
3392                         DWC_PRINTF("Reserved\n");
3393                         break;
3394                 }
3395                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3396                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3397                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3398                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3399         }
3400 }
3401 #endif
3402
3403 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3404 {
3405 #if 0
3406         DWC_PRINTF("Frame remaining at SOF:\n");
3407         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3408                    hcd->frrem_samples, hcd->frrem_accum,
3409                    (hcd->frrem_samples > 0) ?
3410                    hcd->frrem_accum / hcd->frrem_samples : 0);
3411
3412         DWC_PRINTF("\n");
3413         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3414         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3415                    hcd->core_if->hfnum_7_samples,
3416                    hcd->core_if->hfnum_7_frrem_accum,
3417                    (hcd->core_if->hfnum_7_samples >
3418                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3419                    hcd->core_if->hfnum_7_samples : 0);
3420         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3421         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3422                    hcd->core_if->hfnum_0_samples,
3423                    hcd->core_if->hfnum_0_frrem_accum,
3424                    (hcd->core_if->hfnum_0_samples >
3425                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3426                    hcd->core_if->hfnum_0_samples : 0);
3427         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3428         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3429                    hcd->core_if->hfnum_other_samples,
3430                    hcd->core_if->hfnum_other_frrem_accum,
3431                    (hcd->core_if->hfnum_other_samples >
3432                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3433                    hcd->core_if->hfnum_other_samples : 0);
3434
3435         DWC_PRINTF("\n");
3436         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3437         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3438                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3439                    (hcd->hfnum_7_samples_a > 0) ?
3440                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3441         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3442         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3443                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3444                    (hcd->hfnum_0_samples_a > 0) ?
3445                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3446         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3447         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3448                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3449                    (hcd->hfnum_other_samples_a > 0) ?
3450                    hcd->hfnum_other_frrem_accum_a /
3451                    hcd->hfnum_other_samples_a : 0);
3452
3453         DWC_PRINTF("\n");
3454         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3455         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3456                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3457                    (hcd->hfnum_7_samples_b > 0) ?
3458                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3459         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3460         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3461                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3462                    (hcd->hfnum_0_samples_b > 0) ?
3463                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3464         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3465         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3466                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3467                    (hcd->hfnum_other_samples_b > 0) ?
3468                    hcd->hfnum_other_frrem_accum_b /
3469                    hcd->hfnum_other_samples_b : 0);
3470 #endif
3471 }
3472
3473 #endif /* DWC_DEVICE_ONLY */