drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t *hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_SHUTDOWN);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         } else {
 183                                 return;
 184                         }
 185
 186                 }
 187         }
 188 }
 189
 190 /**
 191  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 192  * and periodic schedules. The QTD associated with each URB is removed from
 193  * the schedule and freed. This function may be called when a disconnect is
 194  * detected or when the HCD is being stopped.
 195  */
 196 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
 197 {
 198         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 202         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 203         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 204 }
 205
 206 /**
 207  * Start the connection timer.  An OTG host is required to display a
 208  * message if the device does not connect within 10 seconds.  The
 209  * timer is deleted if a port connect interrupt occurs before the
 210  * timer expires.
 211  */
 212 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
 213 {
 214         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
 215 }
 216
 217 /**
 218  * HCD Callback function for disconnect of the HCD.
 219  *
 220  * @param p void pointer to the <code>struct usb_hcd</code>
 221  */
 222 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 223 {
 224         dwc_otg_hcd_t *dwc_otg_hcd;
 225         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 226         dwc_otg_hcd = p;
 227         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 228         return 1;
 229 }
 230
 231 /**
 232  * HCD Callback function for starting the HCD when A-Cable is
 233  * connected.
 234  *
 235  * @param p void pointer to the <code>struct usb_hcd</code>
 236  */
 237 static int32_t dwc_otg_hcd_start_cb(void *p)
 238 {
 239         dwc_otg_hcd_t *dwc_otg_hcd = p;
 240         dwc_otg_core_if_t *core_if;
 241         hprt0_data_t hprt0;
 242         uint32_t timeout = 50;
 243
 244         core_if = dwc_otg_hcd->core_if;
 245
 246         if (core_if->op_state == B_HOST) {
 247                 /*
 248                  * Reset the port.  During a HNP mode switch the reset
 249                  * needs to occur within 1ms and have a duration of at
 250                  * least 50ms.
 251                  */
 252                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 253                 hprt0.b.prtrst = 1;
 254                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 255                 if (core_if->otg_ver) {
 256                         dwc_mdelay(60);
 257                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 258                         hprt0.b.prtrst = 0;
 259                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 260                 }
 261         }
 262         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 263         if (core_if->otg_ver)
 264                 timeout = 25;
 265         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 266                                    hcd_start_func, dwc_otg_hcd, timeout,
 267                                    "start hcd");
 268
 269         return 1;
 270 }
 271
 272 /**
 273  * HCD Callback function for disconnect of the HCD.
 274  *
 275  * @param p void pointer to the <code>struct usb_hcd</code>
 276  */
 277 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 278 {
 279         gintsts_data_t intr;
 280         dwc_otg_hcd_t *dwc_otg_hcd = p;
 281         hprt0_data_t hprt0;
 282
 283         dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
 284         dwc_otg_hcd->non_periodic_channels = 0;
 285         dwc_otg_hcd->periodic_channels = 0;
 286         dwc_otg_hcd->frame_number =0;
 287
 288         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 289         /* In some case, we don't disconnect a usb device, but
 290          * disconnect intr was triggered, so check hprt0 here. */
 291         if (((!hprt0.b.prtenchng)
 292             && (!hprt0.b.prtconndet)
 293             && hprt0.b.prtconnsts)
 294             || !hprt0.b.prtenchng) {
 295                 DWC_PRINTF("%s: Invalid disconnect interrupt "
 296                            "hprt0 = 0x%08x\n", __func__, hprt0.d32);
 297                 return 1;
 298         }
 299         /*
 300          * Set status flags for the hub driver.
 301          */
 302         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 303         dwc_otg_hcd->flags.b.port_connect_status = 0;
 304
 305         /*
 306          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 307          * interrupt mask and status bits and disabling subsequent host
 308          * channel interrupts.
 309          */
 310         intr.d32 = 0;
 311         intr.b.nptxfempty = 1;
 312         intr.b.ptxfempty = 1;
 313         intr.b.hcintr = 1;
 314         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 315                          intr.d32, 0);
 316         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 317                          intr.d32, 0);
 318
 319         /*
 320          * Turn off the vbus power only if the core has transitioned to device
 321          * mode. If still in host mode, need to keep power on to detect a
 322          * reconnection.
 323          */
 324         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 325                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 326                         hprt0_data_t hprt0 = {.d32 = 0 };
 327                         DWC_PRINTF("Disconnect: PortPower off\n");
 328                         hprt0.b.prtpwr = 0;
 329                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 330                                         hprt0.d32);
 331                 }
 332                 /** Delete timers if become device */
 333                 del_timers(dwc_otg_hcd);
 334                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 335                 goto out;
 336         }
 337
 338         /* Respond with an error status to all URBs in the schedule. */
 339         kill_all_urbs(dwc_otg_hcd);
 340
 341         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 342                 /* Clean up any host channels that were in use. */
 343                 int num_channels;
 344                 int i;
 345                 dwc_hc_t *channel;
 346                 dwc_otg_hc_regs_t *hc_regs;
 347                 hcchar_data_t hcchar;
 348
 349                 DWC_PRINTF("Disconnect cb-Host\n");
 350                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 351                         del_xfer_timers(dwc_otg_hcd);
 352                 else
 353                         del_timers(dwc_otg_hcd);
 354
 355                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 356
 357                 if (!dwc_otg_hcd->core_if->dma_enable) {
 358                         /* Flush out any channel requests in slave mode. */
 359                         for (i = 0; i < num_channels; i++) {
 360                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 361                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 362                                     (channel, hc_list_entry)) {
 363                                         hc_regs =
 364                                             dwc_otg_hcd->core_if->host_if->
 365                                             hc_regs[i];
 366                                         hcchar.d32 =
 367                                             DWC_READ_REG32(&hc_regs->hcchar);
 368                                         if (hcchar.b.chen) {
 369                                                 hcchar.b.chen = 0;
 370                                                 hcchar.b.chdis = 1;
 371                                                 hcchar.b.epdir = 0;
 372                                                 DWC_WRITE_REG32
 373                                                     (&hc_regs->hcchar,
 374                                                      hcchar.d32);
 375                                         }
 376                                 }
 377                         }
 378                 }
 379
 380                 for (i = 0; i < num_channels; i++) {
 381                         channel = dwc_otg_hcd->hc_ptr_array[i];
 382                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 383                                 hc_regs =
 384                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 385                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 386                                 if (hcchar.b.chen) {
 387                                         /* Halt the channel. */
 388                                         hcchar.b.chdis = 1;
 389                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 390                                                         hcchar.d32);
 391                                 }
 392
 393                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 394                                                    channel);
 395                                 DWC_CIRCLEQ_INSERT_TAIL
 396                                     (&dwc_otg_hcd->free_hc_list, channel,
 397                                      hc_list_entry);
 398                                 /*
 399                                  * Added for Descriptor DMA to prevent channel double cleanup
 400                                  * in release_channel_ddma(). Which called from ep_disable
 401                                  * when device disconnect.
 402                                  */
 403                                 channel->qh = NULL;
 404                         }
 405                 }
 406         }
 407
 408 out:
 409         if (dwc_otg_hcd->fops->disconnect) {
 410                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 411         }
 412
 413         return 1;
 414 }
 415
 416 /**
 417  * HCD Callback function for stopping the HCD.
 418  *
 419  * @param p void pointer to the <code>struct usb_hcd</code>
 420  */
 421 static int32_t dwc_otg_hcd_stop_cb(void *p)
 422 {
 423         dwc_otg_hcd_t *dwc_otg_hcd = p;
 424
 425         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 426         dwc_otg_hcd_stop(dwc_otg_hcd);
 427         return 1;
 428 }
 429
 430 #ifdef CONFIG_USB_DWC_OTG_LPM
 431 /**
 432  * HCD Callback function for sleep of HCD.
 433  *
 434  * @param p void pointer to the <code>struct usb_hcd</code>
 435  */
 436 static int dwc_otg_hcd_sleep_cb(void *p)
 437 {
 438         dwc_otg_hcd_t *hcd = p;
 439
 440         dwc_otg_hcd_free_hc_from_lpm(hcd);
 441
 442         return 0;
 443 }
 444 #endif
 445
 446 /**
 447  * HCD Callback function for Remote Wakeup.
 448  *
 449  * @param p void pointer to the <code>struct usb_hcd</code>
 450  */
 451 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 452 {
 453         dwc_otg_hcd_t *dwc_otg_hcd = p;
 454         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 455
 456         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 457                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 458                 usb_hcd_resume_root_hub(hcd);
 459         }
 460 #ifdef CONFIG_USB_DWC_OTG_LPM
 461         else {
 462                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 463         }
 464 #endif
 465         return 0;
 466 }
 467
 468 /**
 469  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 470  * stopped.
 471  */
 472 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
 473 {
 474         hprt0_data_t hprt0 = {.d32 = 0 };
 475         struct dwc_otg_platform_data *pldata;
 476         dwc_irqflags_t flags;
 477
 478         pldata = hcd->core_if->otg_dev->pldata;
 479         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 480
 481         /*
 482          * The root hub should be disconnected before this function is called.
 483          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 484          * and the QH lists (via ..._hcd_endpoint_disable).
 485          */
 486         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 487         kill_all_urbs(hcd);
 488         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 489
 490         /*
 491          * Set status flags for the hub driver.
 492          */
 493         hcd->flags.b.port_connect_status_change = 1;
 494         hcd->flags.b.port_connect_status = 0;
 495
 496         /* Turn off all host-specific interrupts. */
 497         dwc_otg_disable_host_interrupts(hcd->core_if);
 498
 499         /* Turn off the vbus power */
 500         DWC_PRINTF("PortPower off\n");
 501         hprt0.b.prtpwr = 0;
 502         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 503
 504         if (pldata->power_enable)
 505                 pldata->power_enable(0);
 506
 507         dwc_mdelay(1);
 508 }
 509
 510 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
 511                             dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
 512                             int atomic_alloc)
 513 {
 514         dwc_irqflags_t flags;
 515         int retval = 0;
 516         dwc_otg_qtd_t *qtd;
 517         gintmsk_data_t intr_mask = {.d32 = 0 };
 518
 519         if (!hcd->flags.b.port_connect_status) {
 520                 /* No longer connected. */
 521                 DWC_DEBUG("Not connected\n");
 522                 return -DWC_E_NO_DEVICE;
 523         }
 524
 525         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 526         if (qtd == NULL) {
 527                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 528                 return -DWC_E_NO_MEMORY;
 529         }
 530         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 531         retval =
 532             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
 533
 534         if (retval < 0) {
 535                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 536                           "Error status %d\n", retval);
 537                 dwc_otg_hcd_qtd_free(qtd);
 538         }
 539         intr_mask.d32 =
 540             DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 541         if (!intr_mask.b.sofintr && retval == 0) {
 542                 dwc_otg_transaction_type_e tr_type;
 543                 if ((qtd->qh->ep_type == UE_BULK)
 544                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 545                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 546                         retval = 0;
 547                         goto out;
 548                 }
 549                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 550                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 551                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 552                 }
 553         }
 554 out:
 555         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 556         return retval;
 557 }
 558
 559 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
 560                             dwc_otg_hcd_urb_t *dwc_otg_urb)
 561 {
 562         dwc_otg_qh_t *qh;
 563         dwc_otg_qtd_t *urb_qtd;
 564
 565         urb_qtd = dwc_otg_urb->qtd;
 566         if (!urb_qtd) {
 567                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 568                            __func__, urb_qtd, dwc_otg_urb);
 569                 return 0;
 570         }
 571         qh = urb_qtd->qh;
 572 #ifdef DEBUG
 573         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 574                 if (urb_qtd->in_process) {
 575                         dump_channel_info(hcd, qh);
 576                 }
 577         }
 578 #endif
 579         if (urb_qtd->in_process && qh->channel) {
 580                 /* The QTD is in process (it has been assigned to a channel). */
 581                 if (hcd->flags.b.port_connect_status) {
 582                         /*
 583                          * If still connected (i.e. in host mode), halt the
 584                          * channel so it can be used for other transfers. If
 585                          * no longer connected, the host registers can't be
 586                          * written to halt the channel since the core is in
 587                          * device mode.
 588                          */
 589                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 590                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 591                 }
 592         }
 593
 594         /*
 595          * Free the QTD and clean up the associated QH. Leave the QH in the
 596          * schedule if it has any remaining QTDs.
 597          */
 598
 599         if (!hcd->core_if->dma_desc_enable) {
 600                 uint8_t b = urb_qtd->in_process;
 601                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 602                 if (b) {
 603                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 604                         qh->channel = NULL;
 605                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 606                         dwc_otg_hcd_qh_remove(hcd, qh);
 607                 }
 608         } else {
 609                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 610         }
 611         return 0;
 612 }
 613
 614 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
 615                                  int retry)
 616 {
 617         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 618         int retval = 0;
 619         dwc_irqflags_t flags;
 620
 621         if (retry < 0) {
 622                 retval = -DWC_E_INVALID;
 623                 goto done;
 624         }
 625
 626         if (!qh) {
 627                 retval = -DWC_E_INVALID;
 628                 goto done;
 629         }
 630
 631         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 632
 633         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 634                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 635                 retry--;
 636                 dwc_msleep(5);
 637                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 638         }
 639
 640         dwc_otg_hcd_qh_remove(hcd, qh);
 641
 642         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 643         /*
 644          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 645          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 646          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 647          * and dwc_otg_hcd_frame_list_alloc().
 648          */
 649         dwc_otg_hcd_qh_free(hcd, qh);
 650
 651 done:
 652         return retval;
 653 }
 654
 655 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
 656 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
 657 {
 658         int retval = 0;
 659         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 660         if (!qh)
 661                 return -DWC_E_INVALID;
 662
 663         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 664         return retval;
 665 }
 666 #endif
 667
 668 /**
 669  * HCD Callback structure for handling mode switching.
 670  */
 671 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 672         .start = dwc_otg_hcd_start_cb,
 673         .stop = dwc_otg_hcd_stop_cb,
 674         .disconnect = dwc_otg_hcd_disconnect_cb,
 675         .session_start = dwc_otg_hcd_session_start_cb,
 676         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 677 #ifdef CONFIG_USB_DWC_OTG_LPM
 678         .sleep = dwc_otg_hcd_sleep_cb,
 679 #endif
 680         .p = 0,
 681 };
 682
 683 /**
 684  * Reset tasklet function
 685  */
 686 static void reset_tasklet_func(void *data)
 687 {
 688         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 689         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 690         hprt0_data_t hprt0;
 691
 692         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 693
 694         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 695         hprt0.b.prtrst = 1;
 696         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 697         dwc_mdelay(60);
 698
 699         hprt0.b.prtrst = 0;
 700         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 701         dwc_otg_hcd->flags.b.port_reset_change = 1;
 702 }
 703
 704 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 705 {
 706         dwc_list_link_t *item;
 707         dwc_otg_qh_t *qh;
 708         dwc_irqflags_t flags;
 709
 710         if (!qh_list->next) {
 711                 /* The list hasn't been initialized yet. */
 712                 return;
 713         }
 714         /*
 715          * Hold spinlock here. Not needed in that case if bellow
 716          * function is being called from ISR
 717          */
 718         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 719         /* Ensure there are no QTDs or URBs left. */
 720         kill_urbs_in_qh_list(hcd, qh_list);
 721         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 722
 723         DWC_LIST_FOREACH(item, qh_list) {
 724                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 725                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 726         }
 727 }
 728
 729 /**
 730  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 731  * Device during SRP time by host power up.
 732  */
 733 void dwc_otg_hcd_power_up(void *ptr)
 734 {
 735         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 736         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 737
 738         DWC_PRINTF("%s called\n", __FUNCTION__);
 739
 740         if (!core_if->hibernation_suspend) {
 741                 DWC_PRINTF("Already exited from Hibernation\n");
 742                 return;
 743         }
 744
 745         /* Switch on the voltage to the core */
 746         gpwrdn.b.pwrdnswtch = 1;
 747         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 748         dwc_udelay(10);
 749
 750         /* Reset the core */
 751         gpwrdn.d32 = 0;
 752         gpwrdn.b.pwrdnrstn = 1;
 753         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 754         dwc_udelay(10);
 755
 756         /* Disable power clamps */
 757         gpwrdn.d32 = 0;
 758         gpwrdn.b.pwrdnclmp = 1;
 759         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 760
 761         /* Remove reset the core signal */
 762         gpwrdn.d32 = 0;
 763         gpwrdn.b.pwrdnrstn = 1;
 764         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 765         dwc_udelay(10);
 766
 767         /* Disable PMU interrupt */
 768         gpwrdn.d32 = 0;
 769         gpwrdn.b.pmuintsel = 1;
 770         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 771
 772         core_if->hibernation_suspend = 0;
 773
 774         /* Disable PMU */
 775         gpwrdn.d32 = 0;
 776         gpwrdn.b.pmuactv = 1;
 777         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 778         dwc_udelay(10);
 779
 780         /* Enable VBUS */
 781         gpwrdn.d32 = 0;
 782         gpwrdn.b.dis_vbus = 1;
 783         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 784
 785         core_if->op_state = A_HOST;
 786         dwc_otg_core_init(core_if);
 787         dwc_otg_enable_global_interrupts(core_if);
 788         cil_hcd_start(core_if);
 789 }
 790
 791 /**
 792  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 793  * in the struct usb_hcd field.
 794  */
 795 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
 796 {
 797         int i;
 798
 799         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 800
 801         del_timers(dwc_otg_hcd);
 802
 803         /* Free memory for QH/QTD lists */
 804         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 805         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 806         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 807         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 808         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 809         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 810
 811         /* Free memory for the host channels. */
 812         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 813                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 814
 815 #ifdef DEBUG
 816                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 817                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 818                 }
 819 #endif
 820                 if (hc != NULL) {
 821                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 822                                     i, hc);
 823                         DWC_FREE(hc);
 824                 }
 825         }
 826
 827         if (dwc_otg_hcd->core_if->dma_enable) {
 828                 if (dwc_otg_hcd->status_buf_dma) {
 829                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 830                                      dwc_otg_hcd->status_buf,
 831                                      dwc_otg_hcd->status_buf_dma);
 832                 }
 833         } else if (dwc_otg_hcd->status_buf != NULL) {
 834                 DWC_FREE(dwc_otg_hcd->status_buf);
 835         }
 836         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 837         /* Set core_if's lock pointer to NULL */
 838         dwc_otg_hcd->core_if->lock = NULL;
 839
 840         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 841         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 842
 843 #ifdef DWC_DEV_SRPCAP
 844         if (dwc_otg_hcd->core_if->power_down == 2 &&
 845             dwc_otg_hcd->core_if->pwron_timer) {
 846                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 847         }
 848 #endif
 849         DWC_FREE(dwc_otg_hcd);
 850 }
 851
 852 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 853 {
 854         int retval = 0;
 855         int num_channels;
 856         int i;
 857         dwc_hc_t *channel;
 858
 859         hcd->lock = DWC_SPINLOCK_ALLOC();
 860         if (!hcd->lock) {
 861                 DWC_ERROR("Could not allocate lock for pcd");
 862                 DWC_FREE(hcd);
 863                 retval = -DWC_E_NO_MEMORY;
 864                 goto out;
 865         }
 866         hcd->core_if = core_if;
 867
 868         /* Register the HCD CIL Callbacks */
 869         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 870                                            &hcd_cil_callbacks, hcd);
 871
 872         /* Initialize the non-periodic schedule. */
 873         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 874         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 875
 876         /* Initialize the periodic schedule. */
 877         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 878         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 879         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 880         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 881
 882         /*
 883          * Create a host channel descriptor for each host channel implemented
 884          * in the controller. Initialize the channel descriptor array.
 885          */
 886         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 887         num_channels = hcd->core_if->core_params->host_channels;
 888         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 889         for (i = 0; i < num_channels; i++) {
 890                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 891                 if (channel == NULL) {
 892                         retval = -DWC_E_NO_MEMORY;
 893                         DWC_ERROR("%s: host channel allocation failed\n",
 894                                   __func__);
 895                         dwc_otg_hcd_free(hcd);
 896                         goto out;
 897                 }
 898                 channel->hc_num = i;
 899                 hcd->hc_ptr_array[i] = channel;
 900 #ifdef DEBUG
 901                 hcd->core_if->hc_xfer_timer[i] =
 902                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 903                                     &hcd->core_if->hc_xfer_info[i]);
 904 #endif
 905                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 906                             channel);
 907         }
 908
 909         /* Initialize the Connection timeout timer. */
 910         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 911                                           dwc_otg_hcd_connect_timeout, hcd);
 912
 913         /* Initialize reset tasklet. */
 914         hcd->reset_tasklet =
 915             DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 916 #ifdef DWC_DEV_SRPCAP
 917         if (hcd->core_if->power_down == 2) {
 918                 /* Initialize Power on timer for Host power up in case hibernation */
 919                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 920                                                             dwc_otg_hcd_power_up,
 921                                                             core_if);
 922         }
 923 #endif
 924
 925         /*
 926          * Allocate space for storing data on status transactions. Normally no
 927          * data is sent, but this space acts as a bit bucket. This must be
 928          * done after usb_add_hcd since that function allocates the DMA buffer
 929          * pool.
 930          */
 931         if (hcd->core_if->dma_enable) {
 932                 hcd->status_buf =
 933                     DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 934                                          &hcd->status_buf_dma);
 935         } else {
 936                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 937         }
 938         if (!hcd->status_buf) {
 939                 retval = -DWC_E_NO_MEMORY;
 940                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 941                 dwc_otg_hcd_free(hcd);
 942                 goto out;
 943         }
 944
 945         hcd->otg_port = 1;
 946         hcd->frame_list = NULL;
 947         hcd->frame_list_dma = 0;
 948         hcd->periodic_qh_count = 0;
 949 out:
 950         return retval;
 951 }
 952
 953 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
 954 {
 955         /* Turn off all host-specific interrupts. */
 956         dwc_otg_disable_host_interrupts(hcd->core_if);
 957
 958         dwc_otg_hcd_free(hcd);
 959 }
 960
 961 /**
 962  * Initializes dynamic portions of the DWC_otg HCD state.
 963  */
 964 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
 965 {
 966         int num_channels;
 967         int i;
 968         dwc_hc_t *channel;
 969         dwc_hc_t *channel_tmp;
 970         dwc_irqflags_t flags;
 971         dwc_spinlock_t *temp_lock;
 972
 973         hcd->flags.d32 = 0;
 974         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 975         hcd->non_periodic_channels = 0;
 976         hcd->periodic_channels = 0;
 977
 978         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 979         /*
 980          * Put all channels in the free channel list and clean up channel
 981          * states.
 982          */
 983         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 984                                  &hcd->free_hc_list, hc_list_entry) {
 985                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 986         }
 987
 988         num_channels = hcd->core_if->core_params->host_channels;
 989         for (i = 0; i < num_channels; i++) {
 990                 channel = hcd->hc_ptr_array[i];
 991                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 992                                         hc_list_entry);
 993                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 994         }
 995         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 996         /* Initialize the DWC core for host mode operation. */
 997         dwc_otg_core_host_init(hcd->core_if);
 998
 999         /* Set core_if's lock pointer to the hcd->lock */
1000         /* Should get this lock before modify it */
1001         if (hcd->core_if->lock) {
1002                 DWC_SPINLOCK_IRQSAVE(hcd->core_if->lock, &flags);
1003                 temp_lock = hcd->core_if->lock;
1004                 hcd->core_if->lock = hcd->lock;
1005                 DWC_SPINUNLOCK_IRQRESTORE(temp_lock, flags);
1006         } else {
1007                 hcd->core_if->lock = hcd->lock;
1008         }
1009 }
1010
1011 /**
1012  * Assigns transactions from a QTD to a free host channel and initializes the
1013  * host channel to perform the transactions. The host channel is removed from
1014  * the free list.
1015  *
1016  * @param hcd The HCD state structure.
1017  * @param qh Transactions from the first QTD for this QH are selected and
1018  * assigned to a free host channel.
1019  */
1020 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1021 {
1022         dwc_hc_t *hc;
1023         dwc_otg_qtd_t *qtd;
1024         dwc_otg_hcd_urb_t *urb;
1025         void *ptr = NULL;
1026         int retval = 0;
1027
1028         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1029
1030         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1031
1032         /* Remove the host channel from the free list. */
1033         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1034
1035         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1036
1037         urb = qtd->urb;
1038         if (urb == NULL) {
1039                 printk("%s : urb is NULL\n", __func__);
1040                 retval = -EINVAL;
1041                 return retval;
1042         }
1043
1044         qh->channel = hc;
1045
1046         qtd->in_process = 1;
1047
1048         /*
1049          * Use usb_pipedevice to determine device address. This address is
1050          * 0 before the SET_ADDRESS command and the correct address afterward.
1051          */
1052         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1053         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1054         hc->speed = qh->dev_speed;
1055         hc->max_packet = dwc_max_packet(qh->maxp);
1056
1057         hc->xfer_started = 0;
1058         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1059         hc->error_state = (qtd->error_count > 0);
1060         hc->halt_on_queue = 0;
1061         hc->halt_pending = 0;
1062         hc->requests = 0;
1063
1064         /*
1065          * The following values may be modified in the transfer type section
1066          * below. The xfer_len value may be reduced when the transfer is
1067          * started to accommodate the max widths of the XferSize and PktCnt
1068          * fields in the HCTSIZn register.
1069          */
1070
1071         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1072         if (hc->ep_is_in)
1073                 hc->do_ping = 0;
1074         else
1075                 hc->do_ping = qh->ping_state;
1076
1077         hc->data_pid_start = qh->data_toggle;
1078         hc->multi_count = 1;
1079
1080         if (hcd->core_if->dma_enable) {
1081                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1082
1083                 /* For non-dword aligned case */
1084                 if (((unsigned long)hc->xfer_buff & 0x3)
1085                     && !hcd->core_if->dma_desc_enable) {
1086                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1087                 }
1088         } else {
1089                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1090         }
1091         hc->xfer_len = urb->length - urb->actual_length;
1092         hc->xfer_count = 0;
1093
1094         /*
1095          * Set the split attributes
1096          */
1097         hc->do_split = 0;
1098         hc->csplit_nak = 0;
1099         if (qh->do_split) {
1100                 uint32_t hub_addr, port_addr;
1101                 hc->do_split = 1;
1102                 hc->xact_pos = qtd->isoc_split_pos;
1103                 hc->complete_split = qtd->complete_split;
1104                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1105                 hc->hub_addr = (uint8_t) hub_addr;
1106                 hc->port_addr = (uint8_t) port_addr;
1107         }
1108
1109         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1110         case UE_CONTROL:
1111                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1112                 switch (qtd->control_phase) {
1113                 case DWC_OTG_CONTROL_SETUP:
1114                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1115                         hc->do_ping = 0;
1116                         hc->ep_is_in = 0;
1117                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1118                         if (hcd->core_if->dma_enable)
1119                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1120                         else
1121                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1122
1123                         hc->xfer_len = 8;
1124                         ptr = NULL;
1125                         break;
1126                 case DWC_OTG_CONTROL_DATA:
1127                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1128                         hc->data_pid_start = qtd->data_toggle;
1129                         break;
1130                 case DWC_OTG_CONTROL_STATUS:
1131                         /*
1132                          * Direction is opposite of data direction or IN if no
1133                          * data.
1134                          */
1135                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1136                         if (urb->length == 0) {
1137                                 hc->ep_is_in = 1;
1138                         } else {
1139                                 hc->ep_is_in =
1140                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1141                         }
1142                         if (hc->ep_is_in)
1143                                 hc->do_ping = 0;
1144
1145                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1146
1147                         hc->xfer_len = 0;
1148                         if (hcd->core_if->dma_enable)
1149                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1150                         else
1151                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1152
1153                         ptr = NULL;
1154                         break;
1155                 }
1156                 break;
1157         case UE_BULK:
1158                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1159                 break;
1160         case UE_INTERRUPT:
1161                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1162                 break;
1163         case UE_ISOCHRONOUS:
1164                 {
1165                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1166
1167                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1168
1169                         if (hcd->core_if->dma_desc_enable)
1170                                 break;
1171
1172                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1173
1174                         frame_desc->status = 0;
1175
1176                         if (hcd->core_if->dma_enable) {
1177                                 hc->xfer_buff = (uint8_t *) urb->dma;
1178                         } else {
1179                                 hc->xfer_buff = (uint8_t *) urb->buf;
1180                         }
1181                         hc->xfer_buff +=
1182                             frame_desc->offset + qtd->isoc_split_offset;
1183                         hc->xfer_len =
1184                             frame_desc->length - qtd->isoc_split_offset;
1185
1186                         /* For non-dword aligned buffers */
1187                         if (((unsigned long)hc->xfer_buff & 0x3)
1188                             && hcd->core_if->dma_enable) {
1189                                 ptr =
1190                                     (uint8_t *) urb->buf + frame_desc->offset +
1191                                     qtd->isoc_split_offset;
1192                         } else
1193                                 ptr = NULL;
1194
1195                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1196                                 if (hc->xfer_len <= 188) {
1197                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1198                                 } else {
1199                                         hc->xact_pos =
1200                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1201                                 }
1202                         }
1203                 }
1204                 break;
1205         }
1206         /* non DWORD-aligned buffer case */
1207         if (ptr) {
1208                 uint32_t buf_size;
1209                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1210                         buf_size = hcd->core_if->core_params->max_transfer_size;
1211                 } else {
1212                         buf_size = 4096;
1213                 }
1214                 if (!qh->dw_align_buf) {
1215                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1216                                                                 &qh->
1217                                                                 dw_align_buf_dma);
1218                         if (!qh->dw_align_buf) {
1219                                 DWC_ERROR
1220                                     ("%s: Failed to allocate memory to handle "
1221                                      "non-dword aligned buffer case\n",
1222                                      __func__);
1223                                 return retval;
1224                         }
1225                 }
1226                 if (!hc->ep_is_in) {
1227                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1228                 }
1229                 hc->align_buff = qh->dw_align_buf_dma;
1230         } else {
1231                 hc->align_buff = 0;
1232         }
1233
1234         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1235             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1236                 /*
1237                  * This value may be modified when the transfer is started to
1238                  * reflect the actual transfer length.
1239                  */
1240                 hc->multi_count = dwc_hb_mult(qh->maxp);
1241         }
1242
1243         if (hcd->core_if->dma_desc_enable)
1244                 hc->desc_list_addr = qh->desc_list_dma;
1245
1246         dwc_otg_hc_init(hcd->core_if, hc);
1247         hc->qh = qh;
1248         return retval;
1249 }
1250
1251 /**
1252  * This function selects transactions from the HCD transfer schedule and
1253  * assigns them to available host channels. It is called from HCD interrupt
1254  * handler functions.
1255  *
1256  * @param hcd The HCD state structure.
1257  *
1258  * @return The types of new transactions that were assigned to host channels.
1259  */
1260 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1261 {
1262         dwc_list_link_t *qh_ptr;
1263         dwc_otg_qh_t *qh;
1264         int num_channels;
1265         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1266         int err;
1267
1268 #ifdef DEBUG_SOF
1269         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1270 #endif
1271
1272         /* Process entries in the periodic ready list. */
1273         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1274
1275         while (qh_ptr != &hcd->periodic_sched_ready &&
1276                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1277
1278                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1279                 assign_and_init_hc(hcd, qh);
1280
1281                 /*
1282                  * Move the QH from the periodic ready schedule to the
1283                  * periodic assigned schedule.
1284                  */
1285                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1286                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1287                                    &qh->qh_list_entry);
1288
1289                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1290         }
1291
1292         /*
1293          * Process entries in the inactive portion of the non-periodic
1294          * schedule. Some free host channels may not be used if they are
1295          * reserved for periodic transfers.
1296          */
1297         qh_ptr = hcd->non_periodic_sched_inactive.next;
1298         num_channels = hcd->core_if->core_params->host_channels;
1299         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1300                (hcd->non_periodic_channels <
1301                 num_channels - hcd->periodic_channels) &&
1302                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1303
1304                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1305
1306                 err = assign_and_init_hc(hcd, qh);
1307
1308                 /*
1309                  * Move the QH from the non-periodic inactive schedule to the
1310                  * non-periodic active schedule.
1311                  */
1312                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1313                 if (err != 0)
1314                         continue;
1315                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1316                                    &qh->qh_list_entry);
1317
1318                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1319                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1320                 } else {
1321                         ret_val = DWC_OTG_TRANSACTION_ALL;
1322                 }
1323
1324                 hcd->non_periodic_channels++;
1325         }
1326
1327         return ret_val;
1328 }
1329
1330 /**
1331  * Attempts to queue a single transaction request for a host channel
1332  * associated with either a periodic or non-periodic transfer. This function
1333  * assumes that there is space available in the appropriate request queue. For
1334  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1335  * is available in the appropriate Tx FIFO.
1336  *
1337  * @param hcd The HCD state structure.
1338  * @param hc Host channel descriptor associated with either a periodic or
1339  * non-periodic transfer.
1340  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1341  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1342  * transfers.
1343  *
1344  * @return 1 if a request is queued and more requests may be needed to
1345  * complete the transfer, 0 if no more requests are required for this
1346  * transfer, -1 if there is insufficient space in the Tx FIFO.
1347  */
1348 static int queue_transaction(dwc_otg_hcd_t *hcd,
1349                              dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1350 {
1351         int retval;
1352
1353         if (hcd->core_if->dma_enable) {
1354                 if (hcd->core_if->dma_desc_enable) {
1355                         if (!hc->xfer_started
1356                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1357                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1358                                 hc->qh->ping_state = 0;
1359                         }
1360                 } else if (!hc->xfer_started) {
1361                         if (!hc || !(hc->qh))
1362                                 return -ENODEV;
1363                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1364                         hc->qh->ping_state = 0;
1365                 }
1366                 retval = 0;
1367         } else if (hc->halt_pending) {
1368                 /* Don't queue a request if the channel has been halted. */
1369                 retval = 0;
1370         } else if (hc->halt_on_queue) {
1371                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1372                 retval = 0;
1373         } else if (hc->do_ping) {
1374                 if (!hc->xfer_started) {
1375                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1376                 }
1377                 retval = 0;
1378         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1379                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1380                         if (!hc->xfer_started) {
1381                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1382                                 retval = 1;
1383                         } else {
1384                                 retval =
1385                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1386                                                                  hc);
1387                         }
1388                 } else {
1389                         retval = -1;
1390                 }
1391         } else {
1392                 if (!hc->xfer_started) {
1393                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1394                         retval = 1;
1395                 } else {
1396                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1397                 }
1398         }
1399
1400         return retval;
1401 }
1402
1403 /**
1404  * Processes periodic channels for the next frame and queues transactions for
1405  * these channels to the DWC_otg controller. After queueing transactions, the
1406  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1407  * to queue as Periodic Tx FIFO or request queue space becomes available.
1408  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1409  */
1410 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1411 {
1412         hptxsts_data_t tx_status;
1413         dwc_list_link_t *qh_ptr;
1414         dwc_otg_qh_t *qh;
1415         int status;
1416         int no_queue_space = 0;
1417         int no_fifo_space = 0;
1418
1419         dwc_otg_host_global_regs_t *host_regs;
1420         host_regs = hcd->core_if->host_if->host_global_regs;
1421
1422         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1423 #ifdef DEBUG
1424         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1425         DWC_DEBUGPL(DBG_HCDV,
1426                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1427                     tx_status.b.ptxqspcavail);
1428         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1429                     tx_status.b.ptxfspcavail);
1430 #endif
1431
1432         qh_ptr = hcd->periodic_sched_assigned.next;
1433         while (qh_ptr != &hcd->periodic_sched_assigned) {
1434                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1435                 if (tx_status.b.ptxqspcavail == 0) {
1436                         no_queue_space = 1;
1437                         break;
1438                 }
1439
1440                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1441
1442                 /*
1443                  * Set a flag if we're queuing high-bandwidth in slave mode.
1444                  * The flag prevents any halts to get into the request queue in
1445                  * the middle of multiple high-bandwidth packets getting queued.
1446                  */
1447                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1448                         hcd->core_if->queuing_high_bandwidth = 1;
1449                 }
1450                 status =
1451                     queue_transaction(hcd, qh->channel,
1452                                       tx_status.b.ptxfspcavail);
1453                 if (status < 0) {
1454                         no_fifo_space = 1;
1455                         break;
1456                 }
1457
1458                 /*
1459                  * In Slave mode, stay on the current transfer until there is
1460                  * nothing more to do or the high-bandwidth request count is
1461                  * reached. In DMA mode, only need to queue one request. The
1462                  * controller automatically handles multiple packets for
1463                  * high-bandwidth transfers.
1464                  */
1465                 if (hcd->core_if->dma_enable || status == 0 ||
1466                     qh->channel->requests == qh->channel->multi_count) {
1467                         qh_ptr = qh_ptr->next;
1468                         /*
1469                          * Move the QH from the periodic assigned schedule to
1470                          * the periodic queued schedule.
1471                          */
1472                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1473                                            &qh->qh_list_entry);
1474
1475                         /* done queuing high bandwidth */
1476                         hcd->core_if->queuing_high_bandwidth = 0;
1477                 }
1478         }
1479
1480         if (!hcd->core_if->dma_enable) {
1481                 dwc_otg_core_global_regs_t *global_regs;
1482                 gintmsk_data_t intr_mask = {.d32 = 0 };
1483
1484                 global_regs = hcd->core_if->core_global_regs;
1485                 intr_mask.b.ptxfempty = 1;
1486 #ifdef DEBUG
1487                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1488                 DWC_DEBUGPL(DBG_HCDV,
1489                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1490                             tx_status.b.ptxqspcavail);
1491                 DWC_DEBUGPL(DBG_HCDV,
1492                             "  P Tx FIFO Space Avail (after queue): %d\n",
1493                             tx_status.b.ptxfspcavail);
1494 #endif
1495                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1496                     no_queue_space || no_fifo_space) {
1497                         /*
1498                          * May need to queue more transactions as the request
1499                          * queue or Tx FIFO empties. Enable the periodic Tx
1500                          * FIFO empty interrupt. (Always use the half-empty
1501                          * level to ensure that new requests are loaded as
1502                          * soon as possible.)
1503                          */
1504                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1505                                          intr_mask.d32);
1506                 } else {
1507                         /*
1508                          * Disable the Tx FIFO empty interrupt since there are
1509                          * no more transactions that need to be queued right
1510                          * now. This function is called from interrupt
1511                          * handlers to queue more transactions as transfer
1512                          * states change.
1513                          */
1514                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1515                                          0);
1516                 }
1517         }
1518 }
1519
1520 /**
1521  * Processes active non-periodic channels and queues transactions for these
1522  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1523  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1524  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1525  * FIFO Empty interrupt is disabled.
1526  */
1527 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1528 {
1529         gnptxsts_data_t tx_status;
1530         dwc_list_link_t *orig_qh_ptr;
1531         dwc_otg_qh_t *qh;
1532         int status;
1533         int no_queue_space = 0;
1534         int no_fifo_space = 0;
1535         int more_to_do = 0;
1536
1537         dwc_otg_core_global_regs_t *global_regs =
1538             hcd->core_if->core_global_regs;
1539
1540         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1541 #ifdef DEBUG
1542         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1543         DWC_DEBUGPL(DBG_HCDV,
1544                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1545                     tx_status.b.nptxqspcavail);
1546         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1547                     tx_status.b.nptxfspcavail);
1548 #endif
1549         /*
1550          * Keep track of the starting point. Skip over the start-of-list
1551          * entry.
1552          */
1553         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1554                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1555         }
1556         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1557
1558         /*
1559          * Process once through the active list or until no more space is
1560          * available in the request queue or the Tx FIFO.
1561          */
1562         do {
1563                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1564                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1565                         no_queue_space = 1;
1566                         break;
1567                 }
1568
1569                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1570                                     qh_list_entry);
1571                 status =
1572                     queue_transaction(hcd, qh->channel,
1573                                       tx_status.b.nptxfspcavail);
1574
1575                 if (status > 0) {
1576                         more_to_do = 1;
1577                 } else if (status < 0) {
1578                         no_fifo_space = 1;
1579                         break;
1580                 }
1581
1582                 /* Advance to next QH, skipping start-of-list entry. */
1583                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1584                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1585                         hcd->non_periodic_qh_ptr =
1586                             hcd->non_periodic_qh_ptr->next;
1587                 }
1588
1589         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1590
1591         if (!hcd->core_if->dma_enable) {
1592                 gintmsk_data_t intr_mask = {.d32 = 0 };
1593                 intr_mask.b.nptxfempty = 1;
1594
1595 #ifdef DEBUG
1596                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1597                 DWC_DEBUGPL(DBG_HCDV,
1598                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1599                             tx_status.b.nptxqspcavail);
1600                 DWC_DEBUGPL(DBG_HCDV,
1601                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1602                             tx_status.b.nptxfspcavail);
1603 #endif
1604                 if (more_to_do || no_queue_space || no_fifo_space) {
1605                         /*
1606                          * May need to queue more transactions as the request
1607                          * queue or Tx FIFO empties. Enable the non-periodic
1608                          * Tx FIFO empty interrupt. (Always use the half-empty
1609                          * level to ensure that new requests are loaded as
1610                          * soon as possible.)
1611                          */
1612                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1613                                          intr_mask.d32);
1614                 } else {
1615                         /*
1616                          * Disable the Tx FIFO empty interrupt since there are
1617                          * no more transactions that need to be queued right
1618                          * now. This function is called from interrupt
1619                          * handlers to queue more transactions as transfer
1620                          * states change.
1621                          */
1622                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1623                                          0);
1624                 }
1625         }
1626 }
1627
1628 /**
1629  * This function processes the currently active host channels and queues
1630  * transactions for these channels to the DWC_otg controller. It is called
1631  * from HCD interrupt handler functions.
1632  *
1633  * @param hcd The HCD state structure.
1634  * @param tr_type The type(s) of transactions to queue (non-periodic,
1635  * periodic, or both).
1636  */
1637 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1638                                     dwc_otg_transaction_type_e tr_type)
1639 {
1640 #ifdef DEBUG_SOF
1641         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1642 #endif
1643         /* Process host channels associated with periodic transfers. */
1644         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1645              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1646             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1647
1648                 process_periodic_channels(hcd);
1649         }
1650
1651         /* Process host channels associated with non-periodic transfers. */
1652         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1653             tr_type == DWC_OTG_TRANSACTION_ALL) {
1654                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1655                         process_non_periodic_channels(hcd);
1656                 } else {
1657                         /*
1658                          * Ensure NP Tx FIFO empty interrupt is disabled when
1659                          * there are no non-periodic transfers to process.
1660                          */
1661                         gintmsk_data_t gintmsk = {.d32 = 0 };
1662                         gintmsk.b.nptxfempty = 1;
1663                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1664                                          gintmsk, gintmsk.d32, 0);
1665                 }
1666         }
1667 }
1668
1669 #ifdef DWC_HS_ELECT_TST
1670 /*
1671  * Quick and dirty hack to implement the HS Electrical Test
1672  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1673  *
1674  * This code was copied from our userspace app "hset". It sends a
1675  * Get Device Descriptor control sequence in two parts, first the
1676  * Setup packet by itself, followed some time later by the In and
1677  * Ack packets. Rather than trying to figure out how to add this
1678  * functionality to the normal driver code, we just hijack the
1679  * hardware, using these two function to drive the hardware
1680  * directly.
1681  */
1682
1683 static dwc_otg_core_global_regs_t *global_regs;
1684 static dwc_otg_host_global_regs_t *hc_global_regs;
1685 static dwc_otg_hc_regs_t *hc_regs;
1686 static uint32_t *data_fifo;
1687
1688 static void do_setup(void)
1689 {
1690         gintsts_data_t gintsts;
1691         hctsiz_data_t hctsiz;
1692         hcchar_data_t hcchar;
1693         haint_data_t haint;
1694         hcint_data_t hcint;
1695
1696         /* Enable HAINTs */
1697         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1698
1699         /* Enable HCINTs */
1700         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1701
1702         /* Read GINTSTS */
1703         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1704
1705         /* Read HAINT */
1706         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1707
1708         /* Read HCINT */
1709         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1710
1711         /* Read HCCHAR */
1712         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1713
1714         /* Clear HCINT */
1715         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1716
1717         /* Clear HAINT */
1718         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1719
1720         /* Clear GINTSTS */
1721         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1722
1723         /* Read GINTSTS */
1724         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1725
1726         /*
1727          * Send Setup packet (Get Device Descriptor)
1728          */
1729
1730         /* Make sure channel is disabled */
1731         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1732         if (hcchar.b.chen) {
1733                 hcchar.b.chdis = 1;
1734                 /* hcchar.b.chen = 1; */
1735                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1736                 /* sleep(1); */
1737                 dwc_mdelay(1000);
1738
1739                 /* Read GINTSTS */
1740                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1741
1742                 /* Read HAINT */
1743                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1744
1745                 /* Read HCINT */
1746                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1747
1748                 /* Read HCCHAR */
1749                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1750
1751                 /* Clear HCINT */
1752                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1753
1754                 /* Clear HAINT */
1755                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1756
1757                 /* Clear GINTSTS */
1758                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1759
1760                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1761         }
1762
1763         /* Set HCTSIZ */
1764         hctsiz.d32 = 0;
1765         hctsiz.b.xfersize = 8;
1766         hctsiz.b.pktcnt = 1;
1767         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1768         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1769
1770         /* Set HCCHAR */
1771         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1772         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1773         hcchar.b.epdir = 0;
1774         hcchar.b.epnum = 0;
1775         hcchar.b.mps = 8;
1776         hcchar.b.chen = 1;
1777         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1778
1779         /* Fill FIFO with Setup data for Get Device Descriptor */
1780         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1781         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1782         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1783
1784         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1785
1786         /* Wait for host channel interrupt */
1787         do {
1788                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1789         } while (gintsts.b.hcintr == 0);
1790
1791         /* Disable HCINTs */
1792         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1793
1794         /* Disable HAINTs */
1795         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1796
1797         /* Read HAINT */
1798         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1799
1800         /* Read HCINT */
1801         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1802
1803         /* Read HCCHAR */
1804         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1805
1806         /* Clear HCINT */
1807         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1808
1809         /* Clear HAINT */
1810         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1811
1812         /* Clear GINTSTS */
1813         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1814
1815         /* Read GINTSTS */
1816         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1817 }
1818
1819 static void do_in_ack(void)
1820 {
1821         gintsts_data_t gintsts;
1822         hctsiz_data_t hctsiz;
1823         hcchar_data_t hcchar;
1824         haint_data_t haint;
1825         hcint_data_t hcint;
1826         host_grxsts_data_t grxsts;
1827
1828         /* Enable HAINTs */
1829         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1830
1831         /* Enable HCINTs */
1832         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1833
1834         /* Read GINTSTS */
1835         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1836
1837         /* Read HAINT */
1838         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1839
1840         /* Read HCINT */
1841         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1842
1843         /* Read HCCHAR */
1844         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1845
1846         /* Clear HCINT */
1847         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1848
1849         /* Clear HAINT */
1850         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1851
1852         /* Clear GINTSTS */
1853         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1854
1855         /* Read GINTSTS */
1856         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1857
1858         /*
1859          * Receive Control In packet
1860          */
1861
1862         /* Make sure channel is disabled */
1863         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1864         if (hcchar.b.chen) {
1865                 hcchar.b.chdis = 1;
1866                 hcchar.b.chen = 1;
1867                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1868                 /* sleep(1); */
1869                 dwc_mdelay(1000);
1870
1871                 /* Read GINTSTS */
1872                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1873
1874                 /* Read HAINT */
1875                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1876
1877                 /* Read HCINT */
1878                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1879
1880                 /* Read HCCHAR */
1881                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1882
1883                 /* Clear HCINT */
1884                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1885
1886                 /* Clear HAINT */
1887                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1888
1889                 /* Clear GINTSTS */
1890                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1891
1892                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1893         }
1894
1895         /* Set HCTSIZ */
1896         hctsiz.d32 = 0;
1897         hctsiz.b.xfersize = 8;
1898         hctsiz.b.pktcnt = 1;
1899         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1900         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1901
1902         /* Set HCCHAR */
1903         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1904         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1905         hcchar.b.epdir = 1;
1906         hcchar.b.epnum = 0;
1907         hcchar.b.mps = 8;
1908         hcchar.b.chen = 1;
1909         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1910
1911         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1912
1913         /* Wait for receive status queue interrupt */
1914         do {
1915                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1916         } while (gintsts.b.rxstsqlvl == 0);
1917
1918         /* Read RXSTS */
1919         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1920
1921         /* Clear RXSTSQLVL in GINTSTS */
1922         gintsts.d32 = 0;
1923         gintsts.b.rxstsqlvl = 1;
1924         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1925
1926         switch (grxsts.b.pktsts) {
1927         case DWC_GRXSTS_PKTSTS_IN:
1928                 /* Read the data into the host buffer */
1929                 if (grxsts.b.bcnt > 0) {
1930                         int i;
1931                         int word_count = (grxsts.b.bcnt + 3) / 4;
1932
1933                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1934
1935                         for (i = 0; i < word_count; i++) {
1936                                 (void)DWC_READ_REG32(data_fifo++);
1937                         }
1938                 }
1939                 break;
1940
1941         default:
1942                 break;
1943         }
1944
1945         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1946
1947         /* Wait for receive status queue interrupt */
1948         do {
1949                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1950         } while (gintsts.b.rxstsqlvl == 0);
1951
1952         /* Read RXSTS */
1953         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1954
1955         /* Clear RXSTSQLVL in GINTSTS */
1956         gintsts.d32 = 0;
1957         gintsts.b.rxstsqlvl = 1;
1958         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1959
1960         switch (grxsts.b.pktsts) {
1961         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1962                 break;
1963
1964         default:
1965                 break;
1966         }
1967
1968         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1969
1970         /* Wait for host channel interrupt */
1971         do {
1972                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1973         } while (gintsts.b.hcintr == 0);
1974
1975         /* Read HAINT */
1976         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1977
1978         /* Read HCINT */
1979         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1980
1981         /* Read HCCHAR */
1982         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1983
1984         /* Clear HCINT */
1985         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1986
1987         /* Clear HAINT */
1988         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1989
1990         /* Clear GINTSTS */
1991         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1992
1993         /* Read GINTSTS */
1994         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1995
1996         /* usleep(100000); */
1997         /* mdelay(100); */
1998         dwc_mdelay(1);
1999
2000         /*
2001          * Send handshake packet
2002          */
2003
2004         /* Read HAINT */
2005         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2006
2007         /* Read HCINT */
2008         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2009
2010         /* Read HCCHAR */
2011         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2012
2013         /* Clear HCINT */
2014         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2015
2016         /* Clear HAINT */
2017         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2018
2019         /* Clear GINTSTS */
2020         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2021
2022         /* Read GINTSTS */
2023         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2024
2025         /* Make sure channel is disabled */
2026         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2027         if (hcchar.b.chen) {
2028                 hcchar.b.chdis = 1;
2029                 hcchar.b.chen = 1;
2030                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2031                 /* sleep(1); */
2032                 dwc_mdelay(1000);
2033
2034                 /* Read GINTSTS */
2035                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2036
2037                 /* Read HAINT */
2038                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2039
2040                 /* Read HCINT */
2041                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2042
2043                 /* Read HCCHAR */
2044                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2045
2046                 /* Clear HCINT */
2047                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2048
2049                 /* Clear HAINT */
2050                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2051
2052                 /* Clear GINTSTS */
2053                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2054
2055                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2056         }
2057
2058         /* Set HCTSIZ */
2059         hctsiz.d32 = 0;
2060         hctsiz.b.xfersize = 0;
2061         hctsiz.b.pktcnt = 1;
2062         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2063         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2064
2065         /* Set HCCHAR */
2066         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2067         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2068         hcchar.b.epdir = 0;
2069         hcchar.b.epnum = 0;
2070         hcchar.b.mps = 8;
2071         hcchar.b.chen = 1;
2072         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2073
2074         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2075
2076         /* Wait for host channel interrupt */
2077         do {
2078                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2079         } while (gintsts.b.hcintr == 0);
2080
2081         /* Disable HCINTs */
2082         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2083
2084         /* Disable HAINTs */
2085         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2086
2087         /* Read HAINT */
2088         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2089
2090         /* Read HCINT */
2091         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2092
2093         /* Read HCCHAR */
2094         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2095
2096         /* Clear HCINT */
2097         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2098
2099         /* Clear HAINT */
2100         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2101
2102         /* Clear GINTSTS */
2103         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2104
2105         /* Read GINTSTS */
2106         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2107 }
2108 #endif
2109
2110 /** Handles hub class-specific requests. */
2111 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2112                             uint16_t typeReq,
2113                             uint16_t wValue,
2114                             uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2115 {
2116         int retval = 0;
2117
2118         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2119         usb_hub_descriptor_t *hub_desc;
2120         hprt0_data_t hprt0 = {.d32 = 0 };
2121
2122         uint32_t port_status;
2123
2124         switch (typeReq) {
2125         case UCR_CLEAR_HUB_FEATURE:
2126                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2127                             "ClearHubFeature 0x%x\n", wValue);
2128                 switch (wValue) {
2129                 case UHF_C_HUB_LOCAL_POWER:
2130                 case UHF_C_HUB_OVER_CURRENT:
2131                         /* Nothing required here */
2132                         break;
2133                 default:
2134                         retval = -DWC_E_INVALID;
2135                         DWC_ERROR("DWC OTG HCD - "
2136                                   "ClearHubFeature request %xh unknown\n",
2137                                   wValue);
2138                 }
2139                 break;
2140         case UCR_CLEAR_PORT_FEATURE:
2141 #ifdef CONFIG_USB_DWC_OTG_LPM
2142                 if (wValue != UHF_PORT_L1)
2143 #endif
2144                         if (!wIndex || wIndex > 1)
2145                                 goto error;
2146
2147                 switch (wValue) {
2148                 case UHF_PORT_ENABLE:
2149                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2150                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2151                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2152                         hprt0.b.prtena = 1;
2153                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2154                         break;
2155                 case UHF_PORT_SUSPEND:
2156                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2157                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2158
2159                         if (core_if->power_down == 2) {
2160                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2161                         } else {
2162                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2163                                 dwc_mdelay(5);
2164
2165                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2166                                 hprt0.b.prtres = 1;
2167                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2168                                                 hprt0.d32);
2169                                 hprt0.b.prtsusp = 0;
2170                                 /* Clear Resume bit */
2171                                 dwc_mdelay(100);
2172                                 hprt0.b.prtres = 0;
2173                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2174                                                 hprt0.d32);
2175                         }
2176                         break;
2177 #ifdef CONFIG_USB_DWC_OTG_LPM
2178                 case UHF_PORT_L1:
2179                         {
2180                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2181                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2182
2183                                 lpmcfg.d32 =
2184                                     DWC_READ_REG32(&core_if->core_global_regs->
2185                                                    glpmcfg);
2186                                 lpmcfg.b.en_utmi_sleep = 0;
2187                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2188                                 lpmcfg.b.prt_sleep_sts = 1;
2189                                 DWC_WRITE_REG32(&core_if->core_global_regs->
2190                                                 glpmcfg, lpmcfg.d32);
2191
2192                                 /* Clear Enbl_L1Gating bit. */
2193                                 pcgcctl.b.enbl_sleep_gating = 1;
2194                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2195                                                  0);
2196
2197                                 dwc_mdelay(5);
2198
2199                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2200                                 hprt0.b.prtres = 1;
2201                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2202                                                 hprt0.d32);
2203                                 /* This bit will be cleared in wakeup interrupt handle */
2204                                 break;
2205                         }
2206 #endif
2207                 case UHF_PORT_POWER:
2208                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2209                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2210                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2211                         hprt0.b.prtpwr = 0;
2212                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2213                         break;
2214                 case UHF_PORT_INDICATOR:
2215                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2216                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2217                         /* Port inidicator not supported */
2218                         break;
2219                 case UHF_C_PORT_CONNECTION:
2220                         /* Clears drivers internal connect status change
2221                          * flag */
2222                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2223                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2224                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2225                         break;
2226                 case UHF_C_PORT_RESET:
2227                         /* Clears the driver's internal Port Reset Change
2228                          * flag */
2229                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2230                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2231                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2232                         break;
2233                 case UHF_C_PORT_ENABLE:
2234                         /* Clears the driver's internal Port
2235                          * Enable/Disable Change flag */
2236                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2237                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2238                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2239                         break;
2240                 case UHF_C_PORT_SUSPEND:
2241                         /* Clears the driver's internal Port Suspend
2242                          * Change flag, which is set when resume signaling on
2243                          * the host port is complete */
2244                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2245                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2246                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2247                         break;
2248 #ifdef CONFIG_USB_DWC_OTG_LPM
2249                 case UHF_C_PORT_L1:
2250                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2251                         break;
2252 #endif
2253                 case UHF_C_PORT_OVER_CURRENT:
2254                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2255                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2256                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2257                         break;
2258                 default:
2259                         retval = -DWC_E_INVALID;
2260                         DWC_ERROR("DWC OTG HCD - "
2261                                   "ClearPortFeature request %xh "
2262                                   "unknown or unsupported\n", wValue);
2263                 }
2264                 break;
2265         case UCR_GET_HUB_DESCRIPTOR:
2266                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2267                             "GetHubDescriptor\n");
2268                 hub_desc = (usb_hub_descriptor_t *) buf;
2269                 hub_desc->bDescLength = 9;
2270                 hub_desc->bDescriptorType = 0x29;
2271                 hub_desc->bNbrPorts = 1;
2272                 USETW(hub_desc->wHubCharacteristics, 0x08);
2273                 hub_desc->bPwrOn2PwrGood = 1;
2274                 hub_desc->bHubContrCurrent = 0;
2275                 hub_desc->DeviceRemovable[0] = 0;
2276                 hub_desc->DeviceRemovable[1] = 0xff;
2277                 break;
2278         case UCR_GET_HUB_STATUS:
2279                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2280                             "GetHubStatus\n");
2281                 DWC_MEMSET(buf, 0, 4);
2282                 break;
2283         case UCR_GET_PORT_STATUS:
2284                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2285                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2286                             wIndex, dwc_otg_hcd->flags.d32);
2287                 if (!wIndex || wIndex > 1)
2288                         goto error;
2289
2290                 port_status = 0;
2291
2292                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2293                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2294
2295                 if (dwc_otg_hcd->flags.b.port_enable_change)
2296                         port_status |= (1 << UHF_C_PORT_ENABLE);
2297
2298                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2299                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2300
2301                 if (dwc_otg_hcd->flags.b.port_l1_change)
2302                         port_status |= (1 << UHF_C_PORT_L1);
2303
2304                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2305                         port_status |= (1 << UHF_C_PORT_RESET);
2306                 }
2307
2308                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2309                         DWC_WARN("Overcurrent change detected\n");
2310                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2311                 }
2312
2313                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2314                         /*
2315                          * The port is disconnected, which means the core is
2316                          * either in device mode or it soon will be. Just
2317                          * return 0's for the remainder of the port status
2318                          * since the port register can't be read if the core
2319                          * is in device mode.
2320                          */
2321                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2322                         break;
2323                 }
2324
2325                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2326                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2327
2328                 if (hprt0.b.prtconnsts)
2329                         port_status |= (1 << UHF_PORT_CONNECTION);
2330
2331                 if (hprt0.b.prtena)
2332                         port_status |= (1 << UHF_PORT_ENABLE);
2333
2334                 if (hprt0.b.prtsusp)
2335                         port_status |= (1 << UHF_PORT_SUSPEND);
2336
2337                 if (hprt0.b.prtovrcurract)
2338                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2339
2340                 if (hprt0.b.prtrst)
2341                         port_status |= (1 << UHF_PORT_RESET);
2342
2343                 if (hprt0.b.prtpwr)
2344                         port_status |= (1 << UHF_PORT_POWER);
2345
2346                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2347                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2348                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2349                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2350
2351                 if (hprt0.b.prttstctl)
2352                         port_status |= (1 << UHF_PORT_TEST);
2353                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2354                         port_status |= (1 << UHF_PORT_L1);
2355                 }
2356                 /*
2357                    For Synopsys HW emulation of Power down wkup_control asserts the
2358                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2359                    We intentionally tell the software that port is in L2Suspend state.
2360                    Only for STE.
2361                  */
2362                 if ((core_if->power_down == 2)
2363                     && (core_if->hibernation_suspend == 1)) {
2364                         port_status |= (1 << UHF_PORT_SUSPEND);
2365                 }
2366                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2367
2368                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2369
2370                 break;
2371         case UCR_SET_HUB_FEATURE:
2372                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2373                             "SetHubFeature\n");
2374                 /* No HUB features supported */
2375                 break;
2376         case UCR_SET_PORT_FEATURE:
2377                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2378                         goto error;
2379
2380                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2381                         /*
2382                          * The port is disconnected, which means the core is
2383                          * either in device mode or it soon will be. Just
2384                          * return without doing anything since the port
2385                          * register can't be written if the core is in device
2386                          * mode.
2387                          */
2388                         break;
2389                 }
2390
2391                 switch (wValue) {
2392                 case UHF_PORT_SUSPEND:
2393                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2394                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2395                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2396                                 goto error;
2397                         }
2398                         if (core_if->power_down == 2) {
2399                                 int timeout = 300;
2400                                 dwc_irqflags_t flags;
2401                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2402                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2403                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2404 #ifdef DWC_DEV_SRPCAP
2405                                 int32_t otg_cap_param =
2406                                     core_if->core_params->otg_cap;
2407 #endif
2408                                 DWC_PRINTF
2409                                     ("Preparing for complete power-off\n");
2410
2411                                 /* Save registers before hibernation */
2412                                 dwc_otg_save_global_regs(core_if);
2413                                 dwc_otg_save_host_regs(core_if);
2414
2415                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2416                                 hprt0.b.prtsusp = 1;
2417                                 hprt0.b.prtena = 0;
2418                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2419                                                 hprt0.d32);
2420                                 /* Spin hprt0.b.prtsusp to became 1 */
2421                                 do {
2422                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2423                                         if (hprt0.b.prtsusp) {
2424                                                 break;
2425                                         }
2426                                         dwc_mdelay(1);
2427                                 } while (--timeout);
2428                                 if (!timeout) {
2429                                         DWC_WARN("Suspend wasn't genereted\n");
2430                                 }
2431                                 dwc_udelay(10);
2432
2433                                 /*
2434                                  * We need to disable interrupts to prevent servicing of any IRQ
2435                                  * during going to hibernation
2436                                  */
2437                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2438                                 core_if->lx_state = DWC_OTG_L2;
2439 #ifdef DWC_DEV_SRPCAP
2440                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2441                                 hprt0.b.prtpwr = 0;
2442                                 hprt0.b.prtena = 0;
2443                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2444                                                 hprt0.d32);
2445 #endif
2446                                 gusbcfg.d32 =
2447                                     DWC_READ_REG32(&core_if->
2448                                                    core_global_regs->gusbcfg);
2449                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2450                                         /* ULPI interface */
2451                                         /* Suspend the Phy Clock */
2452                                         pcgcctl.d32 = 0;
2453                                         pcgcctl.b.stoppclk = 1;
2454                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2455                                                          pcgcctl.d32);
2456                                         dwc_udelay(10);
2457                                         gpwrdn.b.pmuactv = 1;
2458                                         DWC_MODIFY_REG32
2459                                             (&core_if->core_global_regs->gpwrdn,
2460                                              0, gpwrdn.d32);
2461                                 } else {
2462                                         /* UTMI+ Interface */
2463                                         gpwrdn.b.pmuactv = 1;
2464                                         DWC_MODIFY_REG32
2465                                             (&core_if->core_global_regs->gpwrdn,
2466                                              0, gpwrdn.d32);
2467                                         dwc_udelay(10);
2468                                         pcgcctl.b.stoppclk = 1;
2469                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2470                                                          pcgcctl.d32);
2471                                         dwc_udelay(10);
2472                                 }
2473 #ifdef DWC_DEV_SRPCAP
2474                                 gpwrdn.d32 = 0;
2475                                 gpwrdn.b.dis_vbus = 1;
2476                                 DWC_MODIFY_REG32(&core_if->
2477                                                  core_global_regs->gpwrdn, 0,
2478                                                  gpwrdn.d32);
2479 #endif
2480                                 gpwrdn.d32 = 0;
2481                                 gpwrdn.b.pmuintsel = 1;
2482                                 DWC_MODIFY_REG32(&core_if->
2483                                                  core_global_regs->gpwrdn, 0,
2484                                                  gpwrdn.d32);
2485                                 dwc_udelay(10);
2486
2487                                 gpwrdn.d32 = 0;
2488 #ifdef DWC_DEV_SRPCAP
2489                                 gpwrdn.b.srp_det_msk = 1;
2490 #endif
2491                                 gpwrdn.b.disconn_det_msk = 1;
2492                                 gpwrdn.b.lnstchng_msk = 1;
2493                                 gpwrdn.b.sts_chngint_msk = 1;
2494                                 DWC_MODIFY_REG32(&core_if->
2495                                                  core_global_regs->gpwrdn, 0,
2496                                                  gpwrdn.d32);
2497                                 dwc_udelay(10);
2498
2499                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2500                                 gpwrdn.d32 = 0;
2501                                 gpwrdn.b.pwrdnclmp = 1;
2502                                 DWC_MODIFY_REG32(&core_if->
2503                                                  core_global_regs->gpwrdn, 0,
2504                                                  gpwrdn.d32);
2505                                 dwc_udelay(10);
2506
2507                                 /* Switch off VDD */
2508                                 gpwrdn.d32 = 0;
2509                                 gpwrdn.b.pwrdnswtch = 1;
2510                                 DWC_MODIFY_REG32(&core_if->
2511                                                  core_global_regs->gpwrdn, 0,
2512                                                  gpwrdn.d32);
2513
2514 #ifdef DWC_DEV_SRPCAP
2515                                 if (otg_cap_param ==
2516                                     DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2517                                         core_if->pwron_timer_started = 1;
2518                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2519                                                            6000 /* 6 secs */);
2520                                 }
2521 #endif
2522                                 /* Save gpwrdn register for further usage if stschng interrupt */
2523                                 core_if->gr_backup->gpwrdn_local =
2524                                     DWC_READ_REG32(&core_if->core_global_regs->
2525                                                    gpwrdn);
2526
2527                                 /* Set flag to indicate that we are in hibernation */
2528                                 core_if->hibernation_suspend = 1;
2529                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2530                                                           flags);
2531
2532                                 DWC_PRINTF("Host hibernation completed\n");
2533                                 /* Exit from case statement */
2534                                 break;
2535
2536                         }
2537                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2538                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2539                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2540                                 gotgctl.b.hstsethnpen = 1;
2541                                 DWC_MODIFY_REG32(&core_if->
2542                                                  core_global_regs->gotgctl, 0,
2543                                                  gotgctl.d32);
2544                                 core_if->op_state = A_SUSPEND;
2545                         }
2546                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2547                         hprt0.b.prtsusp = 1;
2548                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2549                         {
2550                                 dwc_irqflags_t flags;
2551                                 /* Update lx_state */
2552                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2553                                 core_if->lx_state = DWC_OTG_L2;
2554                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2555                                                           flags);
2556                         }
2557                         /* Suspend the Phy Clock */
2558                         if (core_if->otg_ver == 0) {
2559                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2560                                 pcgcctl.b.stoppclk = 1;
2561                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2562                                                  pcgcctl.d32);
2563                                 dwc_udelay(10);
2564                         }
2565
2566                         /* For HNP the bus must be suspended for at least 200ms. */
2567                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2568                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2569                                 pcgcctl.b.stoppclk = 1;
2570                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2571                                                  0);
2572                                 dwc_mdelay(200);
2573                         }
2574
2575                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2576 #if 0
2577                         if (core_if->adp_enable) {
2578                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2579                                 gpwrdn_data_t gpwrdn;
2580
2581                                 while (gotgctl.b.asesvld == 1) {
2582                                         gotgctl.d32 =
2583                                             DWC_READ_REG32
2584                                             (&core_if->core_global_regs->gotgctl);
2585                                         dwc_mdelay(100);
2586                                 }
2587
2588                                 /* Enable Power Down Logic */
2589                                 gpwrdn.d32 = 0;
2590                                 gpwrdn.b.pmuactv = 1;
2591                                 DWC_MODIFY_REG32(&core_if->
2592                                                  core_global_regs->gpwrdn, 0,
2593                                                  gpwrdn.d32);
2594
2595                                 /* Unmask SRP detected interrupt from Power Down Logic */
2596                                 gpwrdn.d32 = 0;
2597                                 gpwrdn.b.srp_det_msk = 1;
2598                                 DWC_MODIFY_REG32(&core_if->
2599                                                  core_global_regs->gpwrdn, 0,
2600                                                  gpwrdn.d32);
2601
2602                                 dwc_otg_adp_probe_start(core_if);
2603                         }
2604 #endif
2605                         break;
2606                 case UHF_PORT_POWER:
2607                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2608                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2609                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2610                         hprt0.b.prtpwr = 1;
2611                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2612                         break;
2613                 case UHF_PORT_RESET:
2614                         if ((core_if->power_down == 2)
2615                             && (core_if->hibernation_suspend == 1)) {
2616                                 /* If we are going to exit from Hibernated
2617                                  * state via USB RESET.
2618                                  */
2619                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2620                         } else {
2621                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2622
2623                                 DWC_DEBUGPL(DBG_HCD,
2624                                             "DWC OTG HCD HUB CONTROL - "
2625                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2626                                 {
2627                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2628                                         pcgcctl.b.enbl_sleep_gating = 1;
2629                                         pcgcctl.b.stoppclk = 1;
2630                                         DWC_MODIFY_REG32(core_if->pcgcctl,
2631                                                          pcgcctl.d32, 0);
2632                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2633                                 }
2634 #ifdef CONFIG_USB_DWC_OTG_LPM
2635                                 {
2636                                         glpmcfg_data_t lpmcfg;
2637                                         lpmcfg.d32 =
2638                                             DWC_READ_REG32(&core_if->
2639                                                            core_global_regs->
2640                                                            glpmcfg);
2641                                         if (lpmcfg.b.prt_sleep_sts) {
2642                                                 lpmcfg.b.en_utmi_sleep = 0;
2643                                                 lpmcfg.b.hird_thres &=
2644                                                     (~(1 << 4));
2645                                                 DWC_WRITE_REG32(&core_if->
2646                                                                 core_global_regs->
2647                                                                 glpmcfg,
2648                                                                 lpmcfg.d32);
2649                                                 dwc_mdelay(1);
2650                                         }
2651                                 }
2652 #endif
2653                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2654                                 /* Clear suspend bit if resetting from suspended state. */
2655                                 hprt0.b.prtsusp = 0;
2656                                 /* When B-Host the Port reset bit is set in
2657                                  * the Start HCD Callback function, so that
2658                                  * the reset is started within 1ms of the HNP
2659                                  * success interrupt. */
2660                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2661                                         hprt0.b.prtpwr = 1;
2662                                         hprt0.b.prtrst = 1;
2663                                         DWC_PRINTF
2664                                             ("Indeed it is in host mode hprt0 = %08x\n",
2665                                              hprt0.d32);
2666                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2667                                                         hprt0.d32);
2668                                 }
2669                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2670                                 dwc_mdelay(60);
2671                                 hprt0.b.prtrst = 0;
2672                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2673                                                 hprt0.d32);
2674                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2675                         }
2676                         break;
2677 #ifdef DWC_HS_ELECT_TST
2678                 case UHF_PORT_TEST:
2679                         {
2680                                 uint32_t t;
2681                                 gintmsk_data_t gintmsk;
2682
2683                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2684                                 DWC_DEBUGPL(DBG_HCD,
2685                                             "DWC OTG HCD HUB CONTROL - "
2686                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2687                                             t);
2688                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2689                                 if (t < 6) {
2690                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2691                                         hprt0.b.prttstctl = t;
2692                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2693                                                         hprt0.d32);
2694                                 } else {
2695                                         /* Setup global vars with reg addresses (quick and
2696                                          * dirty hack, should be cleaned up)
2697                                          */
2698                                         global_regs = core_if->core_global_regs;
2699                                         hc_global_regs =
2700                                             core_if->host_if->host_global_regs;
2701                                         hc_regs =
2702                                             (dwc_otg_hc_regs_t *) ((char *)
2703                                                                    global_regs +
2704                                                                    0x500);
2705                                         data_fifo =
2706                                             (uint32_t *) ((char *)global_regs +
2707                                                           0x1000);
2708
2709                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2710                                                 /* Save current interrupt mask */
2711                                                 gintmsk.d32 =
2712                                                     DWC_READ_REG32
2713                                                     (&global_regs->gintmsk);
2714
2715                                                 /* Disable all interrupts while we muck with
2716                                                  * the hardware directly
2717                                                  */
2718                                                 DWC_WRITE_REG32(&global_regs->
2719                                                                 gintmsk, 0);
2720
2721                                                 /* 15 second delay per the test spec */
2722                                                 dwc_mdelay(15000);
2723
2724                                                 /* Drive suspend on the root port */
2725                                                 hprt0.d32 =
2726                                                     dwc_otg_read_hprt0(core_if);
2727                                                 hprt0.b.prtsusp = 1;
2728                                                 hprt0.b.prtres = 0;
2729                                                 DWC_WRITE_REG32(core_if->
2730                                                                 host_if->hprt0,
2731                                                                 hprt0.d32);
2732
2733                                                 /* 15 second delay per the test spec */
2734                                                 dwc_mdelay(15000);
2735
2736                                                 /* Drive resume on the root port */
2737                                                 hprt0.d32 =
2738                                                     dwc_otg_read_hprt0(core_if);
2739                                                 hprt0.b.prtsusp = 0;
2740                                                 hprt0.b.prtres = 1;
2741                                                 DWC_WRITE_REG32(core_if->
2742                                                                 host_if->hprt0,
2743                                                                 hprt0.d32);
2744                                                 dwc_mdelay(100);
2745
2746                                                 /* Clear the resume bit */
2747                                                 hprt0.b.prtres = 0;
2748                                                 DWC_WRITE_REG32(core_if->
2749                                                                 host_if->hprt0,
2750                                                                 hprt0.d32);
2751
2752                                                 /* Restore interrupts */
2753                                                 DWC_WRITE_REG32(&global_regs->
2754                                                                 gintmsk,
2755                                                                 gintmsk.d32);
2756                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2757                                                 /* Save current interrupt mask */
2758                                                 gintmsk.d32 =
2759                                                     DWC_READ_REG32
2760                                                     (&global_regs->gintmsk);
2761
2762                                                 /* Disable all interrupts while we muck with
2763                                                  * the hardware directly
2764                                                  */
2765                                                 DWC_WRITE_REG32(&global_regs->
2766                                                                 gintmsk, 0);
2767
2768                                                 /* 15 second delay per the test spec */
2769                                                 dwc_mdelay(15000);
2770
2771                                                 /* Send the Setup packet */
2772                                                 do_setup();
2773
2774                                                 /* 15 second delay so nothing else happens for awhile */
2775                                                 dwc_mdelay(15000);
2776
2777                                                 /* Restore interrupts */
2778                                                 DWC_WRITE_REG32(&global_regs->
2779                                                                 gintmsk,
2780                                                                 gintmsk.d32);
2781                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2782                                                 /* Save current interrupt mask */
2783                                                 gintmsk.d32 =
2784                                                     DWC_READ_REG32
2785                                                     (&global_regs->gintmsk);
2786
2787                                                 /* Disable all interrupts while we muck with
2788                                                  * the hardware directly
2789                                                  */
2790                                                 DWC_WRITE_REG32(&global_regs->
2791                                                                 gintmsk, 0);
2792
2793                                                 /* Send the Setup packet */
2794                                                 do_setup();
2795
2796                                                 /* 15 second delay so nothing else happens for awhile */
2797                                                 dwc_mdelay(15000);
2798
2799                                                 /* Send the In and Ack packets */
2800                                                 do_in_ack();
2801
2802                                                 /* 15 second delay so nothing else happens for awhile */
2803                                                 dwc_mdelay(15000);
2804
2805                                                 /* Restore interrupts */
2806                                                 DWC_WRITE_REG32(&global_regs->
2807                                                                 gintmsk,
2808                                                                 gintmsk.d32);
2809                                         }
2810                                 }
2811                                 break;
2812                         }
2813 #endif /* DWC_HS_ELECT_TST */
2814
2815                 case UHF_PORT_INDICATOR:
2816                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2817                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2818                         /* Not supported */
2819                         break;
2820                 default:
2821                         retval = -DWC_E_INVALID;
2822                         DWC_ERROR("DWC OTG HCD - "
2823                                   "SetPortFeature request %xh "
2824                                   "unknown or unsupported\n", wValue);
2825                         break;
2826                 }
2827                 break;
2828 #ifdef CONFIG_USB_DWC_OTG_LPM
2829         case UCR_SET_AND_TEST_PORT_FEATURE:
2830                 if (wValue != UHF_PORT_L1) {
2831                         goto error;
2832                 }
2833                 {
2834                         int portnum, hird, devaddr, remwake;
2835                         glpmcfg_data_t lpmcfg;
2836                         uint32_t time_usecs;
2837                         gintsts_data_t gintsts;
2838                         gintmsk_data_t gintmsk;
2839
2840                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2841                                 goto error;
2842                         }
2843                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2844                                 goto error;
2845                         }
2846                         /* Check if the port currently is in SLEEP state */
2847                         lpmcfg.d32 =
2848                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2849                         if (lpmcfg.b.prt_sleep_sts) {
2850                                 DWC_INFO("Port is already in sleep mode\n");
2851                                 buf[0] = 0;     /* Return success */
2852                                 break;
2853                         }
2854
2855                         portnum = wIndex & 0xf;
2856                         hird = (wIndex >> 4) & 0xf;
2857                         devaddr = (wIndex >> 8) & 0x7f;
2858                         remwake = (wIndex >> 15);
2859
2860                         if (portnum != 1) {
2861                                 retval = -DWC_E_INVALID;
2862                                 DWC_WARN
2863                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2864                                      portnum);
2865                                 break;
2866                         }
2867
2868                         DWC_PRINTF
2869                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2870                              portnum, hird, devaddr, remwake);
2871                         /* Disable LPM interrupt */
2872                         gintmsk.d32 = 0;
2873                         gintmsk.b.lpmtranrcvd = 1;
2874                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2875                                          gintmsk.d32, 0);
2876
2877                         if (dwc_otg_hcd_send_lpm
2878                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2879                                 retval = -DWC_E_INVALID;
2880                                 break;
2881                         }
2882
2883                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2884                         /* We will consider timeout if time_usecs microseconds pass,
2885                          * and we don't receive LPM transaction status.
2886                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2887                          *  core will set lpmtranrcvd bit.
2888                          */
2889                         do {
2890                                 gintsts.d32 =
2891                                     DWC_READ_REG32(&core_if->core_global_regs->
2892                                                    gintsts);
2893                                 if (gintsts.b.lpmtranrcvd) {
2894                                         break;
2895                                 }
2896                                 dwc_udelay(1);
2897                         } while (--time_usecs);
2898                         /* lpm_int bit will be cleared in LPM interrupt handler */
2899
2900                         /* Now fill status
2901                          * 0x00 - Success
2902                          * 0x10 - NYET
2903                          * 0x11 - Timeout
2904                          */
2905                         if (!gintsts.b.lpmtranrcvd) {
2906                                 buf[0] = 0x3;   /* Completion code is Timeout */
2907                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2908                         } else {
2909                                 lpmcfg.d32 =
2910                                     DWC_READ_REG32(&core_if->core_global_regs->
2911                                                    glpmcfg);
2912                                 if (lpmcfg.b.lpm_resp == 0x3) {
2913                                         /* ACK responce from the device */
2914                                         buf[0] = 0x00;  /* Success */
2915                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2916                                         /* NYET responce from the device */
2917                                         buf[0] = 0x2;
2918                                 } else {
2919                                         /* Otherwise responce with Timeout */
2920                                         buf[0] = 0x3;
2921                                 }
2922                         }
2923                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2924                                    lpmcfg.b.lpm_resp);
2925                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2926                                          gintmsk.d32);
2927
2928                         break;
2929                 }
2930 #endif /* CONFIG_USB_DWC_OTG_LPM */
2931         default:
2932 error:
2933                 retval = -DWC_E_INVALID;
2934                 DWC_WARN("DWC OTG HCD - "
2935                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2936                          typeReq, wIndex, wValue);
2937                 break;
2938         }
2939
2940         return retval;
2941 }
2942
2943 #ifdef CONFIG_USB_DWC_OTG_LPM
2944 /** Returns index of host channel to perform LPM transaction. */
2945 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2946 {
2947         dwc_otg_core_if_t *core_if = hcd->core_if;
2948         dwc_hc_t *hc;
2949         hcchar_data_t hcchar;
2950         gintmsk_data_t gintmsk = {.d32 = 0 };
2951
2952         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2953                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2954                 return -1;
2955         }
2956
2957         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2958
2959         /* Mask host channel interrupts. */
2960         gintmsk.b.hcintr = 1;
2961         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2962
2963         /* Fill fields that core needs for LPM transaction */
2964         hcchar.b.devaddr = devaddr;
2965         hcchar.b.epnum = 0;
2966         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2967         hcchar.b.mps = 64;
2968         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2969         hcchar.b.epdir = 0;     /* OUT */
2970         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2971                         hcchar.d32);
2972
2973         /* Remove the host channel from the free list. */
2974         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2975
2976         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2977
2978         return hc->hc_num;
2979 }
2980
2981 /** Release hc after performing LPM transaction */
2982 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2983 {
2984         dwc_hc_t *hc;
2985         glpmcfg_data_t lpmcfg;
2986         uint8_t hc_num;
2987
2988         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2989         hc_num = lpmcfg.b.lpm_chan_index;
2990
2991         hc = hcd->hc_ptr_array[hc_num];
2992
2993         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2994         /* Return host channel to free list */
2995         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2996 }
2997
2998 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2999                          uint8_t bRemoteWake)
3000 {
3001         glpmcfg_data_t lpmcfg;
3002         pcgcctl_data_t pcgcctl = {.d32 = 0 };
3003         int channel;
3004
3005         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
3006         if (channel < 0) {
3007                 return channel;
3008         }
3009
3010         pcgcctl.b.enbl_sleep_gating = 1;
3011         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
3012
3013         /* Read LPM config register */
3014         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
3015
3016         /* Program LPM transaction fields */
3017         lpmcfg.b.rem_wkup_en = bRemoteWake;
3018         lpmcfg.b.hird = hird;
3019
3020         if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
3021                 lpmcfg.b.hird_thres = 0x16;
3022                 lpmcfg.b.en_besl = 1;
3023         } else {
3024                 lpmcfg.b.hird_thres = 0x1c;
3025         }
3026
3027         lpmcfg.b.lpm_chan_index = channel;
3028         lpmcfg.b.en_utmi_sleep = 1;
3029         /* Program LPM config register */
3030         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3031
3032         /* Send LPM transaction */
3033         lpmcfg.b.send_lpm = 1;
3034         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3035
3036         return 0;
3037 }
3038
3039 #endif /* CONFIG_USB_DWC_OTG_LPM */
3040
3041 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3042 {
3043         int retval;
3044
3045         if (port != 1) {
3046                 return -DWC_E_INVALID;
3047         }
3048
3049         retval = (hcd->flags.b.port_connect_status_change ||
3050                   hcd->flags.b.port_reset_change ||
3051                   hcd->flags.b.port_enable_change ||
3052                   hcd->flags.b.port_suspend_change ||
3053                   hcd->flags.b.port_over_current_change);
3054 #ifdef DEBUG
3055         if (retval) {
3056                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3057                             " Root port status changed\n");
3058                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
3059                             hcd->flags.b.port_connect_status_change);
3060                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
3061                             hcd->flags.b.port_reset_change);
3062                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
3063                             hcd->flags.b.port_enable_change);
3064                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
3065                             hcd->flags.b.port_suspend_change);
3066                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
3067                             hcd->flags.b.port_over_current_change);
3068         }
3069 #endif
3070         return retval;
3071 }
3072
3073 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3074 {
3075         hfnum_data_t hfnum;
3076         hfnum.d32 =
3077             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3078                            host_global_regs->hfnum);
3079
3080 #ifdef DEBUG_SOF
3081         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3082                     hfnum.b.frnum);
3083 #endif
3084         return hfnum.b.frnum;
3085 }
3086
3087 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3088                       struct dwc_otg_hcd_function_ops *fops)
3089 {
3090         int retval = 0;
3091
3092         hcd->fops = fops;
3093         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3094             (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3095                 dwc_otg_hcd_reinit(hcd);
3096         } else {
3097                 retval = -DWC_E_NO_DEVICE;
3098         }
3099
3100         return retval;
3101 }
3102
3103 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3104 {
3105         return hcd->priv;
3106 }
3107
3108 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3109 {
3110         hcd->priv = priv_data;
3111 }
3112
3113 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3114 {
3115         return hcd->otg_port;
3116 }
3117
3118 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3119 {
3120         uint32_t is_b_host;
3121         if (hcd->core_if->op_state == B_HOST) {
3122                 is_b_host = 1;
3123         } else {
3124                 is_b_host = 0;
3125         }
3126
3127         return is_b_host;
3128 }
3129
3130 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3131                                          int iso_desc_count, int atomic_alloc)
3132 {
3133         dwc_otg_hcd_urb_t *dwc_otg_urb;
3134         uint32_t size;
3135
3136         size =
3137             sizeof(*dwc_otg_urb) +
3138             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3139         if (atomic_alloc)
3140                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3141         else
3142                 dwc_otg_urb = DWC_ALLOC(size);
3143
3144         dwc_otg_urb->packet_count = iso_desc_count;
3145
3146         return dwc_otg_urb;
3147 }
3148
3149 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3150                                   uint8_t dev_addr, uint8_t ep_num,
3151                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3152 {
3153         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3154                               ep_type, ep_dir, mps);
3155 #if 0
3156         DWC_PRINTF
3157             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3158              dev_addr, ep_num, ep_dir, ep_type, mps);
3159 #endif
3160 }
3161
3162 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3163                                 void *urb_handle, void *buf, dwc_dma_t dma,
3164                                 uint32_t buflen, void *setup_packet,
3165                                 dwc_dma_t setup_dma, uint32_t flags,
3166                                 uint16_t interval)
3167 {
3168         dwc_otg_urb->priv = urb_handle;
3169         dwc_otg_urb->buf = buf;
3170         dwc_otg_urb->dma = dma;
3171         dwc_otg_urb->length = buflen;
3172         dwc_otg_urb->setup_packet = setup_packet;
3173         dwc_otg_urb->setup_dma = setup_dma;
3174         dwc_otg_urb->flags = flags;
3175         dwc_otg_urb->interval = interval;
3176         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3177 }
3178
3179 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3180 {
3181         return dwc_otg_urb->status;
3182 }
3183
3184 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3185 {
3186         return dwc_otg_urb->actual_length;
3187 }
3188
3189 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3190 {
3191         return dwc_otg_urb->error_count;
3192 }
3193
3194 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3195                                          int desc_num, uint32_t offset,
3196                                          uint32_t length)
3197 {
3198         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3199         dwc_otg_urb->iso_descs[desc_num].length = length;
3200 }
3201
3202 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3203                                              int desc_num)
3204 {
3205         return dwc_otg_urb->iso_descs[desc_num].status;
3206 }
3207
3208 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3209                                                     dwc_otg_urb, int desc_num)
3210 {
3211         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3212 }
3213
3214 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3215 {
3216         int allocated = 0;
3217         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3218
3219         if (qh) {
3220                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3221                         allocated = 1;
3222                 }
3223         }
3224         return allocated;
3225 }
3226
3227 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3228 {
3229         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3230         int freed = 0;
3231         DWC_ASSERT(qh, "qh is not allocated\n");
3232
3233         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3234                 freed = 1;
3235         }
3236
3237         return freed;
3238 }
3239
3240 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3241 {
3242         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3243         DWC_ASSERT(qh, "qh is not allocated\n");
3244         return qh->usecs;
3245 }
3246
3247 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3248 {
3249 #ifdef DEBUG
3250         int num_channels;
3251         int i;
3252         gnptxsts_data_t np_tx_status;
3253         hptxsts_data_t p_tx_status;
3254
3255         num_channels = hcd->core_if->core_params->host_channels;
3256         DWC_PRINTF("\n");
3257         DWC_PRINTF
3258             ("************************************************************\n");
3259         DWC_PRINTF("HCD State:\n");
3260         DWC_PRINTF("  Num channels: %d\n", num_channels);
3261         for (i = 0; i < num_channels; i++) {
3262                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3263                 DWC_PRINTF("  Channel %d:\n", i);
3264                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3265                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3266                 DWC_PRINTF("    speed: %d\n", hc->speed);
3267                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3268                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3269                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3270                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3271                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3272                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3273                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3274                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3275                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3276                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3277                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3278                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3279                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3280                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3281                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3282                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3283                 DWC_PRINTF("    requests: %d\n", hc->requests);
3284                 DWC_PRINTF("    qh: %p\n", hc->qh);
3285                 if (hc->xfer_started) {
3286                         hfnum_data_t hfnum;
3287                         hcchar_data_t hcchar;
3288                         hctsiz_data_t hctsiz;
3289                         hcint_data_t hcint;
3290                         hcintmsk_data_t hcintmsk;
3291                         hfnum.d32 =
3292                             DWC_READ_REG32(&hcd->core_if->host_if->
3293                                            host_global_regs->hfnum);
3294                         hcchar.d32 =
3295                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3296                                            hcchar);
3297                         hctsiz.d32 =
3298                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3299                                            hctsiz);
3300                         hcint.d32 =
3301                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3302                                            hcint);
3303                         hcintmsk.d32 =
3304                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3305                                            hcintmsk);
3306                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3307                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3308                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3309                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3310                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3311                 }
3312                 if (hc->xfer_started && hc->qh) {
3313                         dwc_otg_qtd_t *qtd;
3314                         dwc_otg_hcd_urb_t *urb;
3315
3316                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3317                                             qtd_list_entry) {
3318                                 if (!qtd->in_process)
3319                                         break;
3320
3321                                 urb = qtd->urb;
3322                                 DWC_PRINTF("    URB Info:\n");
3323                                 DWC_PRINTF("      qtd: %p, urb: %p\n", qtd,
3324                                            urb);
3325                                 if (urb) {
3326                                         DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3327                                                    dwc_otg_hcd_get_dev_addr
3328                                                    (&urb->pipe_info),
3329                                                    dwc_otg_hcd_get_ep_num
3330                                                    (&urb->pipe_info),
3331                                                    dwc_otg_hcd_is_pipe_in
3332                                                    (&urb->pipe_info) ? "IN" :
3333                                                    "OUT");
3334                                         DWC_PRINTF
3335                                             ("      Max packet size: %d\n",
3336                                              dwc_otg_hcd_get_mps
3337                                              (&urb->pipe_info));
3338                                         DWC_PRINTF
3339                                             ("      transfer_buffer: %p\n",
3340                                              urb->buf);
3341                                         DWC_PRINTF("      transfer_dma: %p\n",
3342                                                    (void *)urb->dma);
3343                                         DWC_PRINTF
3344                                             ("      transfer_buffer_length: %d\n",
3345                                              urb->length);
3346                                         DWC_PRINTF("      actual_length: %d\n",
3347                                                    urb->actual_length);
3348                                 }
3349                         }
3350                 }
3351         }
3352         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3353         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3354         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3355         np_tx_status.d32 =
3356             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3357         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3358                    np_tx_status.b.nptxqspcavail);
3359         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3360                    np_tx_status.b.nptxfspcavail);
3361         p_tx_status.d32 =
3362             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3363         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3364                    p_tx_status.b.ptxqspcavail);
3365         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3366         dwc_otg_hcd_dump_frrem(hcd);
3367         dwc_otg_dump_global_registers(hcd->core_if);
3368         dwc_otg_dump_host_registers(hcd->core_if);
3369         DWC_PRINTF
3370             ("************************************************************\n");
3371         DWC_PRINTF("\n");
3372 #endif
3373 }
3374
3375 #ifdef DEBUG
3376 void dwc_print_setup_data(uint8_t *setup)
3377 {
3378         int i;
3379         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3380                 DWC_PRINTF("Setup Data = MSB ");
3381                 for (i = 7; i >= 0; i--)
3382                         DWC_PRINTF("%02x ", setup[i]);
3383                 DWC_PRINTF("\n");
3384                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3385                            (setup[0] & 0x80) ? "Device-to-Host" :
3386                            "Host-to-Device");
3387                 DWC_PRINTF("  bmRequestType Type = ");
3388                 switch ((setup[0] & 0x60) >> 5) {
3389                 case 0:
3390                         DWC_PRINTF("Standard\n");
3391                         break;
3392                 case 1:
3393                         DWC_PRINTF("Class\n");
3394                         break;
3395                 case 2:
3396                         DWC_PRINTF("Vendor\n");
3397                         break;
3398                 case 3:
3399                         DWC_PRINTF("Reserved\n");
3400                         break;
3401                 }
3402                 DWC_PRINTF("  bmRequestType Recipient = ");
3403                 switch (setup[0] & 0x1f) {
3404                 case 0:
3405                         DWC_PRINTF("Device\n");
3406                         break;
3407                 case 1:
3408                         DWC_PRINTF("Interface\n");
3409                         break;
3410                 case 2:
3411                         DWC_PRINTF("Endpoint\n");
3412                         break;
3413                 case 3:
3414                         DWC_PRINTF("Other\n");
3415                         break;
3416                 default:
3417                         DWC_PRINTF("Reserved\n");
3418                         break;
3419                 }
3420                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3421                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3422                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3423                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3424         }
3425 }
3426 #endif
3427
3428 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3429 {
3430 #if 0
3431         DWC_PRINTF("Frame remaining at SOF:\n");
3432         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3433                    hcd->frrem_samples, hcd->frrem_accum,
3434                    (hcd->frrem_samples > 0) ?
3435                    hcd->frrem_accum / hcd->frrem_samples : 0);
3436
3437         DWC_PRINTF("\n");
3438         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3439         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3440                    hcd->core_if->hfnum_7_samples,
3441                    hcd->core_if->hfnum_7_frrem_accum,
3442                    (hcd->core_if->hfnum_7_samples >
3443                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3444                    hcd->core_if->hfnum_7_samples : 0);
3445         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3446         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3447                    hcd->core_if->hfnum_0_samples,
3448                    hcd->core_if->hfnum_0_frrem_accum,
3449                    (hcd->core_if->hfnum_0_samples >
3450                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3451                    hcd->core_if->hfnum_0_samples : 0);
3452         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3453         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3454                    hcd->core_if->hfnum_other_samples,
3455                    hcd->core_if->hfnum_other_frrem_accum,
3456                    (hcd->core_if->hfnum_other_samples >
3457                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3458                    hcd->core_if->hfnum_other_samples : 0);
3459
3460         DWC_PRINTF("\n");
3461         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3462         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3463                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3464                    (hcd->hfnum_7_samples_a > 0) ?
3465                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3466         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3467         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3468                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3469                    (hcd->hfnum_0_samples_a > 0) ?
3470                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3471         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3472         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3473                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3474                    (hcd->hfnum_other_samples_a > 0) ?
3475                    hcd->hfnum_other_frrem_accum_a /
3476                    hcd->hfnum_other_samples_a : 0);
3477
3478         DWC_PRINTF("\n");
3479         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3480         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3481                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3482                    (hcd->hfnum_7_samples_b > 0) ?
3483                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3484         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3485         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3486                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3487                    (hcd->hfnum_0_samples_b > 0) ?
3488                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3489         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3490         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3491                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3492                    (hcd->hfnum_other_samples_b > 0) ?
3493                    hcd->hfnum_other_frrem_accum_b /
3494                    hcd->hfnum_other_samples_b : 0);
3495 #endif
3496 }
3497
3498 #endif /* DWC_DEVICE_ONLY */