drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t *hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_SHUTDOWN);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         } else {
 183                                 return;
 184                         }
 185
 186                 }
 187         }
 188 }
 189
 190 /**
 191  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 192  * and periodic schedules. The QTD associated with each URB is removed from
 193  * the schedule and freed. This function may be called when a disconnect is
 194  * detected or when the HCD is being stopped.
 195  */
 196 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
 197 {
 198         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 202         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 203         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 204 }
 205
 206 /**
 207  * Start the connection timer.  An OTG host is required to display a
 208  * message if the device does not connect within 10 seconds.  The
 209  * timer is deleted if a port connect interrupt occurs before the
 210  * timer expires.
 211  */
 212 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
 213 {
 214         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
 215 }
 216
 217 /**
 218  * HCD Callback function for disconnect of the HCD.
 219  *
 220  * @param p void pointer to the <code>struct usb_hcd</code>
 221  */
 222 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 223 {
 224         dwc_otg_hcd_t *dwc_otg_hcd;
 225         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 226         dwc_otg_hcd = p;
 227         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 228         return 1;
 229 }
 230
 231 /**
 232  * HCD Callback function for starting the HCD when A-Cable is
 233  * connected.
 234  *
 235  * @param p void pointer to the <code>struct usb_hcd</code>
 236  */
 237 static int32_t dwc_otg_hcd_start_cb(void *p)
 238 {
 239         dwc_otg_hcd_t *dwc_otg_hcd = p;
 240         dwc_otg_core_if_t *core_if;
 241         hprt0_data_t hprt0;
 242         uint32_t timeout = 50;
 243
 244         core_if = dwc_otg_hcd->core_if;
 245
 246         if (core_if->op_state == B_HOST) {
 247                 /*
 248                  * Reset the port.  During a HNP mode switch the reset
 249                  * needs to occur within 1ms and have a duration of at
 250                  * least 50ms.
 251                  */
 252                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 253                 hprt0.b.prtrst = 1;
 254                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 255                 if (core_if->otg_ver) {
 256                         dwc_mdelay(60);
 257                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 258                         hprt0.b.prtrst = 0;
 259                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 260                 }
 261         }
 262         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 263         if (core_if->otg_ver)
 264                 timeout = 25;
 265         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 266                                    hcd_start_func, dwc_otg_hcd, timeout,
 267                                    "start hcd");
 268
 269         return 1;
 270 }
 271
 272 /**
 273  * HCD Callback function for disconnect of the HCD.
 274  *
 275  * @param p void pointer to the <code>struct usb_hcd</code>
 276  */
 277 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 278 {
 279         gintsts_data_t intr;
 280         dwc_otg_hcd_t *dwc_otg_hcd = p;
 281         hprt0_data_t hprt0;
 282
 283         dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
 284         dwc_otg_hcd->non_periodic_channels = 0;
 285         dwc_otg_hcd->periodic_channels = 0;
 286         dwc_otg_hcd->frame_number =0;
 287
 288         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 289         /* In some case, we don't disconnect a usb device, but
 290          * disconnect intr was triggered, so check hprt0 here. */
 291         if ((!hprt0.b.prtenchng)
 292             && (!hprt0.b.prtconndet)
 293             && hprt0.b.prtconnsts) {
 294                 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
 295                 return 1;
 296         }
 297         /*
 298          * Set status flags for the hub driver.
 299          */
 300         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 301         dwc_otg_hcd->flags.b.port_connect_status = 0;
 302
 303         /*
 304          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 305          * interrupt mask and status bits and disabling subsequent host
 306          * channel interrupts.
 307          */
 308         intr.d32 = 0;
 309         intr.b.nptxfempty = 1;
 310         intr.b.ptxfempty = 1;
 311         intr.b.hcintr = 1;
 312         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 313                          intr.d32, 0);
 314         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 315                          intr.d32, 0);
 316
 317         /*
 318          * Turn off the vbus power only if the core has transitioned to device
 319          * mode. If still in host mode, need to keep power on to detect a
 320          * reconnection.
 321          */
 322         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 323                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 324                         hprt0_data_t hprt0 = {.d32 = 0 };
 325                         DWC_PRINTF("Disconnect: PortPower off\n");
 326                         hprt0.b.prtpwr = 0;
 327                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 328                                         hprt0.d32);
 329                 }
 330                 /** Delete timers if become device */
 331                 del_timers(dwc_otg_hcd);
 332                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 333                 goto out;
 334         }
 335
 336         /* Respond with an error status to all URBs in the schedule. */
 337         kill_all_urbs(dwc_otg_hcd);
 338
 339         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 340                 /* Clean up any host channels that were in use. */
 341                 int num_channels;
 342                 int i;
 343                 dwc_hc_t *channel;
 344                 dwc_otg_hc_regs_t *hc_regs;
 345                 hcchar_data_t hcchar;
 346
 347                 DWC_PRINTF("Disconnect cb-Host\n");
 348                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 349                         del_xfer_timers(dwc_otg_hcd);
 350                 else
 351                         del_timers(dwc_otg_hcd);
 352
 353                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 354
 355                 if (!dwc_otg_hcd->core_if->dma_enable) {
 356                         /* Flush out any channel requests in slave mode. */
 357                         for (i = 0; i < num_channels; i++) {
 358                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 359                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 360                                     (channel, hc_list_entry)) {
 361                                         hc_regs =
 362                                             dwc_otg_hcd->core_if->host_if->
 363                                             hc_regs[i];
 364                                         hcchar.d32 =
 365                                             DWC_READ_REG32(&hc_regs->hcchar);
 366                                         if (hcchar.b.chen) {
 367                                                 hcchar.b.chen = 0;
 368                                                 hcchar.b.chdis = 1;
 369                                                 hcchar.b.epdir = 0;
 370                                                 DWC_WRITE_REG32
 371                                                     (&hc_regs->hcchar,
 372                                                      hcchar.d32);
 373                                         }
 374                                 }
 375                         }
 376                 }
 377
 378                 for (i = 0; i < num_channels; i++) {
 379                         channel = dwc_otg_hcd->hc_ptr_array[i];
 380                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 381                                 hc_regs =
 382                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 383                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 384                                 if (hcchar.b.chen) {
 385                                         /* Halt the channel. */
 386                                         hcchar.b.chdis = 1;
 387                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 388                                                         hcchar.d32);
 389                                 }
 390
 391                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 392                                                    channel);
 393                                 DWC_CIRCLEQ_INSERT_TAIL
 394                                     (&dwc_otg_hcd->free_hc_list, channel,
 395                                      hc_list_entry);
 396                                 /*
 397                                  * Added for Descriptor DMA to prevent channel double cleanup
 398                                  * in release_channel_ddma(). Which called from ep_disable
 399                                  * when device disconnect.
 400                                  */
 401                                 channel->qh = NULL;
 402                         }
 403                 }
 404         }
 405
 406 out:
 407         if (dwc_otg_hcd->fops->disconnect) {
 408                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 409         }
 410
 411         return 1;
 412 }
 413
 414 /**
 415  * HCD Callback function for stopping the HCD.
 416  *
 417  * @param p void pointer to the <code>struct usb_hcd</code>
 418  */
 419 static int32_t dwc_otg_hcd_stop_cb(void *p)
 420 {
 421         dwc_otg_hcd_t *dwc_otg_hcd = p;
 422
 423         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 424         dwc_otg_hcd_stop(dwc_otg_hcd);
 425         return 1;
 426 }
 427
 428 #ifdef CONFIG_USB_DWC_OTG_LPM
 429 /**
 430  * HCD Callback function for sleep of HCD.
 431  *
 432  * @param p void pointer to the <code>struct usb_hcd</code>
 433  */
 434 static int dwc_otg_hcd_sleep_cb(void *p)
 435 {
 436         dwc_otg_hcd_t *hcd = p;
 437
 438         dwc_otg_hcd_free_hc_from_lpm(hcd);
 439
 440         return 0;
 441 }
 442 #endif
 443
 444 /**
 445  * HCD Callback function for Remote Wakeup.
 446  *
 447  * @param p void pointer to the <code>struct usb_hcd</code>
 448  */
 449 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 450 {
 451         dwc_otg_hcd_t *dwc_otg_hcd = p;
 452         struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
 453
 454         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 455                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 456                 usb_hcd_resume_root_hub(hcd);
 457         }
 458 #ifdef CONFIG_USB_DWC_OTG_LPM
 459         else {
 460                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 461         }
 462 #endif
 463         return 0;
 464 }
 465
 466 /**
 467  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 468  * stopped.
 469  */
 470 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
 471 {
 472         hprt0_data_t hprt0 = {.d32 = 0 };
 473         struct dwc_otg_platform_data *pldata;
 474         dwc_irqflags_t flags;
 475
 476         pldata = hcd->core_if->otg_dev->pldata;
 477         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 478
 479         /*
 480          * The root hub should be disconnected before this function is called.
 481          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 482          * and the QH lists (via ..._hcd_endpoint_disable).
 483          */
 484         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 485         kill_all_urbs(hcd);
 486         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 487
 488         /*
 489          * Set status flags for the hub driver.
 490          */
 491         hcd->flags.b.port_connect_status_change = 1;
 492         hcd->flags.b.port_connect_status = 0;
 493
 494         /* Turn off all host-specific interrupts. */
 495         dwc_otg_disable_host_interrupts(hcd->core_if);
 496
 497         /* Turn off the vbus power */
 498         DWC_PRINTF("PortPower off\n");
 499         hprt0.b.prtpwr = 0;
 500         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 501
 502         if (pldata->power_enable)
 503                 pldata->power_enable(0);
 504
 505         dwc_mdelay(1);
 506 }
 507
 508 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
 509                             dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
 510                             int atomic_alloc)
 511 {
 512         dwc_irqflags_t flags;
 513         int retval = 0;
 514         dwc_otg_qtd_t *qtd;
 515         gintmsk_data_t intr_mask = {.d32 = 0 };
 516
 517         if (!hcd->flags.b.port_connect_status) {
 518                 /* No longer connected. */
 519                 DWC_DEBUG("Not connected\n");
 520                 return -DWC_E_NO_DEVICE;
 521         }
 522
 523         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 524         if (qtd == NULL) {
 525                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 526                 return -DWC_E_NO_MEMORY;
 527         }
 528         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 529         retval =
 530             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
 531
 532         if (retval < 0) {
 533                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 534                           "Error status %d\n", retval);
 535                 dwc_otg_hcd_qtd_free(qtd);
 536         }
 537         intr_mask.d32 =
 538             DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 539         if (!intr_mask.b.sofintr && retval == 0) {
 540                 dwc_otg_transaction_type_e tr_type;
 541                 if ((qtd->qh->ep_type == UE_BULK)
 542                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 543                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 544                         retval = 0;
 545                         goto out;
 546                 }
 547                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 548                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 549                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 550                 }
 551         }
 552 out:
 553         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 554         return retval;
 555 }
 556
 557 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
 558                             dwc_otg_hcd_urb_t *dwc_otg_urb)
 559 {
 560         dwc_otg_qh_t *qh;
 561         dwc_otg_qtd_t *urb_qtd;
 562
 563         urb_qtd = dwc_otg_urb->qtd;
 564         if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
 565                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 566                            __func__, urb_qtd, dwc_otg_urb);
 567                 return 0;
 568         }
 569         qh = urb_qtd->qh;
 570 #ifdef DEBUG
 571         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 572                 if (urb_qtd->in_process) {
 573                         dump_channel_info(hcd, qh);
 574                 }
 575         }
 576 #endif
 577         if (urb_qtd->in_process && qh->channel) {
 578                 /* The QTD is in process (it has been assigned to a channel). */
 579                 if (hcd->flags.b.port_connect_status) {
 580                         /*
 581                          * If still connected (i.e. in host mode), halt the
 582                          * channel so it can be used for other transfers. If
 583                          * no longer connected, the host registers can't be
 584                          * written to halt the channel since the core is in
 585                          * device mode.
 586                          */
 587                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 588                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 589                 }
 590         }
 591
 592         /*
 593          * Free the QTD and clean up the associated QH. Leave the QH in the
 594          * schedule if it has any remaining QTDs.
 595          */
 596
 597         if (!hcd->core_if->dma_desc_enable) {
 598                 uint8_t b = urb_qtd->in_process;
 599                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 600                 if (b) {
 601                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 602                         qh->channel = NULL;
 603                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 604                         dwc_otg_hcd_qh_remove(hcd, qh);
 605                 }
 606         } else {
 607                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 608         }
 609         return 0;
 610 }
 611
 612 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
 613                                  int retry)
 614 {
 615         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 616         int retval = 0;
 617         dwc_irqflags_t flags;
 618
 619         if (retry < 0) {
 620                 retval = -DWC_E_INVALID;
 621                 goto done;
 622         }
 623
 624         if (!qh) {
 625                 retval = -DWC_E_INVALID;
 626                 goto done;
 627         }
 628
 629         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 630
 631         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 632                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 633                 retry--;
 634                 dwc_msleep(5);
 635                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 636         }
 637
 638         dwc_otg_hcd_qh_remove(hcd, qh);
 639
 640         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 641         /*
 642          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 643          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 644          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 645          * and dwc_otg_hcd_frame_list_alloc().
 646          */
 647         dwc_otg_hcd_qh_free(hcd, qh);
 648
 649 done:
 650         return retval;
 651 }
 652
 653 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
 654 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
 655 {
 656         int retval = 0;
 657         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 658         if (!qh)
 659                 return -DWC_E_INVALID;
 660
 661         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 662         return retval;
 663 }
 664 #endif
 665
 666 /**
 667  * HCD Callback structure for handling mode switching.
 668  */
 669 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 670         .start = dwc_otg_hcd_start_cb,
 671         .stop = dwc_otg_hcd_stop_cb,
 672         .disconnect = dwc_otg_hcd_disconnect_cb,
 673         .session_start = dwc_otg_hcd_session_start_cb,
 674         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 675 #ifdef CONFIG_USB_DWC_OTG_LPM
 676         .sleep = dwc_otg_hcd_sleep_cb,
 677 #endif
 678         .p = 0,
 679 };
 680
 681 /**
 682  * Reset tasklet function
 683  */
 684 static void reset_tasklet_func(void *data)
 685 {
 686         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 687         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 688         hprt0_data_t hprt0;
 689
 690         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 691
 692         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 693         hprt0.b.prtrst = 1;
 694         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 695         dwc_mdelay(60);
 696
 697         hprt0.b.prtrst = 0;
 698         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 699         dwc_otg_hcd->flags.b.port_reset_change = 1;
 700 }
 701
 702 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 703 {
 704         dwc_list_link_t *item;
 705         dwc_otg_qh_t *qh;
 706         dwc_irqflags_t flags;
 707
 708         if (!qh_list->next) {
 709                 /* The list hasn't been initialized yet. */
 710                 return;
 711         }
 712         /*
 713          * Hold spinlock here. Not needed in that case if bellow
 714          * function is being called from ISR
 715          */
 716         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 717         /* Ensure there are no QTDs or URBs left. */
 718         kill_urbs_in_qh_list(hcd, qh_list);
 719         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 720
 721         DWC_LIST_FOREACH(item, qh_list) {
 722                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 723                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 724         }
 725 }
 726
 727 /**
 728  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 729  * Device during SRP time by host power up.
 730  */
 731 void dwc_otg_hcd_power_up(void *ptr)
 732 {
 733         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 734         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 735
 736         DWC_PRINTF("%s called\n", __FUNCTION__);
 737
 738         if (!core_if->hibernation_suspend) {
 739                 DWC_PRINTF("Already exited from Hibernation\n");
 740                 return;
 741         }
 742
 743         /* Switch on the voltage to the core */
 744         gpwrdn.b.pwrdnswtch = 1;
 745         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 746         dwc_udelay(10);
 747
 748         /* Reset the core */
 749         gpwrdn.d32 = 0;
 750         gpwrdn.b.pwrdnrstn = 1;
 751         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 752         dwc_udelay(10);
 753
 754         /* Disable power clamps */
 755         gpwrdn.d32 = 0;
 756         gpwrdn.b.pwrdnclmp = 1;
 757         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 758
 759         /* Remove reset the core signal */
 760         gpwrdn.d32 = 0;
 761         gpwrdn.b.pwrdnrstn = 1;
 762         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 763         dwc_udelay(10);
 764
 765         /* Disable PMU interrupt */
 766         gpwrdn.d32 = 0;
 767         gpwrdn.b.pmuintsel = 1;
 768         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 769
 770         core_if->hibernation_suspend = 0;
 771
 772         /* Disable PMU */
 773         gpwrdn.d32 = 0;
 774         gpwrdn.b.pmuactv = 1;
 775         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 776         dwc_udelay(10);
 777
 778         /* Enable VBUS */
 779         gpwrdn.d32 = 0;
 780         gpwrdn.b.dis_vbus = 1;
 781         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 782
 783         core_if->op_state = A_HOST;
 784         dwc_otg_core_init(core_if);
 785         dwc_otg_enable_global_interrupts(core_if);
 786         cil_hcd_start(core_if);
 787 }
 788
 789 /**
 790  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 791  * in the struct usb_hcd field.
 792  */
 793 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
 794 {
 795         int i;
 796
 797         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 798
 799         del_timers(dwc_otg_hcd);
 800
 801         /* Free memory for QH/QTD lists */
 802         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 803         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 804         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 805         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 806         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 807         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 808
 809         /* Free memory for the host channels. */
 810         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 811                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 812
 813 #ifdef DEBUG
 814                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 815                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 816                 }
 817 #endif
 818                 if (hc != NULL) {
 819                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 820                                     i, hc);
 821                         DWC_FREE(hc);
 822                 }
 823         }
 824
 825         if (dwc_otg_hcd->core_if->dma_enable) {
 826                 if (dwc_otg_hcd->status_buf_dma) {
 827                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 828                                      dwc_otg_hcd->status_buf,
 829                                      dwc_otg_hcd->status_buf_dma);
 830                 }
 831         } else if (dwc_otg_hcd->status_buf != NULL) {
 832                 DWC_FREE(dwc_otg_hcd->status_buf);
 833         }
 834         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 835         /* Set core_if's lock pointer to NULL */
 836         dwc_otg_hcd->core_if->lock = NULL;
 837
 838         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 839         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 840
 841 #ifdef DWC_DEV_SRPCAP
 842         if (dwc_otg_hcd->core_if->power_down == 2 &&
 843             dwc_otg_hcd->core_if->pwron_timer) {
 844                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 845         }
 846 #endif
 847         DWC_FREE(dwc_otg_hcd);
 848 }
 849
 850 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 851 {
 852         int retval = 0;
 853         int num_channels;
 854         int i;
 855         dwc_hc_t *channel;
 856
 857         hcd->lock = DWC_SPINLOCK_ALLOC();
 858         if (!hcd->lock) {
 859                 DWC_ERROR("Could not allocate lock for pcd");
 860                 DWC_FREE(hcd);
 861                 retval = -DWC_E_NO_MEMORY;
 862                 goto out;
 863         }
 864         hcd->core_if = core_if;
 865
 866         /* Register the HCD CIL Callbacks */
 867         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 868                                            &hcd_cil_callbacks, hcd);
 869
 870         /* Initialize the non-periodic schedule. */
 871         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 872         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 873
 874         /* Initialize the periodic schedule. */
 875         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 876         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 877         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 878         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 879
 880         /*
 881          * Create a host channel descriptor for each host channel implemented
 882          * in the controller. Initialize the channel descriptor array.
 883          */
 884         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 885         num_channels = hcd->core_if->core_params->host_channels;
 886         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 887         for (i = 0; i < num_channels; i++) {
 888                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 889                 if (channel == NULL) {
 890                         retval = -DWC_E_NO_MEMORY;
 891                         DWC_ERROR("%s: host channel allocation failed\n",
 892                                   __func__);
 893                         dwc_otg_hcd_free(hcd);
 894                         goto out;
 895                 }
 896                 channel->hc_num = i;
 897                 hcd->hc_ptr_array[i] = channel;
 898 #ifdef DEBUG
 899                 hcd->core_if->hc_xfer_timer[i] =
 900                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 901                                     &hcd->core_if->hc_xfer_info[i]);
 902 #endif
 903                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 904                             channel);
 905         }
 906
 907         /* Initialize the Connection timeout timer. */
 908         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 909                                           dwc_otg_hcd_connect_timeout, hcd);
 910
 911         /* Initialize reset tasklet. */
 912         hcd->reset_tasklet =
 913             DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 914 #ifdef DWC_DEV_SRPCAP
 915         if (hcd->core_if->power_down == 2) {
 916                 /* Initialize Power on timer for Host power up in case hibernation */
 917                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 918                                                             dwc_otg_hcd_power_up,
 919                                                             core_if);
 920         }
 921 #endif
 922
 923         /*
 924          * Allocate space for storing data on status transactions. Normally no
 925          * data is sent, but this space acts as a bit bucket. This must be
 926          * done after usb_add_hcd since that function allocates the DMA buffer
 927          * pool.
 928          */
 929         if (hcd->core_if->dma_enable) {
 930                 hcd->status_buf =
 931                     DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 932                                          &hcd->status_buf_dma);
 933         } else {
 934                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 935         }
 936         if (!hcd->status_buf) {
 937                 retval = -DWC_E_NO_MEMORY;
 938                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 939                 dwc_otg_hcd_free(hcd);
 940                 goto out;
 941         }
 942
 943         hcd->otg_port = 1;
 944         hcd->frame_list = NULL;
 945         hcd->frame_list_dma = 0;
 946         hcd->periodic_qh_count = 0;
 947 out:
 948         return retval;
 949 }
 950
 951 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
 952 {
 953         /* Turn off all host-specific interrupts. */
 954         dwc_otg_disable_host_interrupts(hcd->core_if);
 955
 956         dwc_otg_hcd_free(hcd);
 957 }
 958
 959 /**
 960  * Initializes dynamic portions of the DWC_otg HCD state.
 961  */
 962 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
 963 {
 964         int num_channels;
 965         int i;
 966         dwc_hc_t *channel;
 967         dwc_hc_t *channel_tmp;
 968         dwc_irqflags_t flags;
 969         dwc_spinlock_t *temp_lock;
 970
 971         hcd->flags.d32 = 0;
 972         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 973         hcd->non_periodic_channels = 0;
 974         hcd->periodic_channels = 0;
 975
 976         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 977         /*
 978          * Put all channels in the free channel list and clean up channel
 979          * states.
 980          */
 981         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 982                                  &hcd->free_hc_list, hc_list_entry) {
 983                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 984         }
 985
 986         num_channels = hcd->core_if->core_params->host_channels;
 987         for (i = 0; i < num_channels; i++) {
 988                 channel = hcd->hc_ptr_array[i];
 989                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 990                                         hc_list_entry);
 991                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 992         }
 993         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 994         /* Initialize the DWC core for host mode operation. */
 995         dwc_otg_core_host_init(hcd->core_if);
 996
 997         /* Set core_if's lock pointer to the hcd->lock */
 998         /* Should get this lock before modify it */
 999         if (hcd->core_if->lock) {
1000                 DWC_SPINLOCK_IRQSAVE(hcd->core_if->lock, &flags);
1001                 temp_lock = hcd->core_if->lock;
1002                 hcd->core_if->lock = hcd->lock;
1003                 DWC_SPINUNLOCK_IRQRESTORE(temp_lock, flags);
1004         } else {
1005                 hcd->core_if->lock = hcd->lock;
1006         }
1007 }
1008
1009 /**
1010  * Assigns transactions from a QTD to a free host channel and initializes the
1011  * host channel to perform the transactions. The host channel is removed from
1012  * the free list.
1013  *
1014  * @param hcd The HCD state structure.
1015  * @param qh Transactions from the first QTD for this QH are selected and
1016  * assigned to a free host channel.
1017  */
1018 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1019 {
1020         dwc_hc_t *hc;
1021         dwc_otg_qtd_t *qtd;
1022         dwc_otg_hcd_urb_t *urb;
1023         void *ptr = NULL;
1024         int retval = 0;
1025
1026         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1027
1028         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1029
1030         /* Remove the host channel from the free list. */
1031         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1032
1033         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1034
1035         urb = qtd->urb;
1036         if (urb == NULL) {
1037                 printk("%s : urb is NULL\n", __func__);
1038                 retval = -EINVAL;
1039                 return retval;
1040         }
1041
1042         qh->channel = hc;
1043
1044         qtd->in_process = 1;
1045
1046         /*
1047          * Use usb_pipedevice to determine device address. This address is
1048          * 0 before the SET_ADDRESS command and the correct address afterward.
1049          */
1050         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1051         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1052         hc->speed = qh->dev_speed;
1053         hc->max_packet = dwc_max_packet(qh->maxp);
1054
1055         hc->xfer_started = 0;
1056         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1057         hc->error_state = (qtd->error_count > 0);
1058         hc->halt_on_queue = 0;
1059         hc->halt_pending = 0;
1060         hc->requests = 0;
1061
1062         /*
1063          * The following values may be modified in the transfer type section
1064          * below. The xfer_len value may be reduced when the transfer is
1065          * started to accommodate the max widths of the XferSize and PktCnt
1066          * fields in the HCTSIZn register.
1067          */
1068
1069         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1070         if (hc->ep_is_in)
1071                 hc->do_ping = 0;
1072         else
1073                 hc->do_ping = qh->ping_state;
1074
1075         hc->data_pid_start = qh->data_toggle;
1076         hc->multi_count = 1;
1077
1078         if (hcd->core_if->dma_enable) {
1079                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1080
1081                 /* For non-dword aligned case */
1082                 if (((unsigned long)hc->xfer_buff & 0x3)
1083                     && !hcd->core_if->dma_desc_enable) {
1084                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1085                 }
1086         } else {
1087                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1088         }
1089         hc->xfer_len = urb->length - urb->actual_length;
1090         hc->xfer_count = 0;
1091
1092         /*
1093          * Set the split attributes
1094          */
1095         hc->do_split = 0;
1096         hc->csplit_nak = 0;
1097         if (qh->do_split) {
1098                 uint32_t hub_addr, port_addr;
1099                 hc->do_split = 1;
1100                 hc->xact_pos = qtd->isoc_split_pos;
1101                 hc->complete_split = qtd->complete_split;
1102                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1103                 hc->hub_addr = (uint8_t) hub_addr;
1104                 hc->port_addr = (uint8_t) port_addr;
1105         }
1106
1107         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1108         case UE_CONTROL:
1109                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1110                 switch (qtd->control_phase) {
1111                 case DWC_OTG_CONTROL_SETUP:
1112                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1113                         hc->do_ping = 0;
1114                         hc->ep_is_in = 0;
1115                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1116                         if (hcd->core_if->dma_enable)
1117                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1118                         else
1119                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1120
1121                         hc->xfer_len = 8;
1122                         ptr = NULL;
1123                         break;
1124                 case DWC_OTG_CONTROL_DATA:
1125                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1126                         hc->data_pid_start = qtd->data_toggle;
1127                         break;
1128                 case DWC_OTG_CONTROL_STATUS:
1129                         /*
1130                          * Direction is opposite of data direction or IN if no
1131                          * data.
1132                          */
1133                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1134                         if (urb->length == 0) {
1135                                 hc->ep_is_in = 1;
1136                         } else {
1137                                 hc->ep_is_in =
1138                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1139                         }
1140                         if (hc->ep_is_in)
1141                                 hc->do_ping = 0;
1142
1143                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1144
1145                         hc->xfer_len = 0;
1146                         if (hcd->core_if->dma_enable)
1147                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1148                         else
1149                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1150
1151                         ptr = NULL;
1152                         break;
1153                 }
1154                 break;
1155         case UE_BULK:
1156                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1157                 break;
1158         case UE_INTERRUPT:
1159                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1160                 break;
1161         case UE_ISOCHRONOUS:
1162                 {
1163                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1164
1165                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1166
1167                         if (hcd->core_if->dma_desc_enable)
1168                                 break;
1169
1170                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1171
1172                         frame_desc->status = 0;
1173
1174                         if (hcd->core_if->dma_enable) {
1175                                 hc->xfer_buff = (uint8_t *) urb->dma;
1176                         } else {
1177                                 hc->xfer_buff = (uint8_t *) urb->buf;
1178                         }
1179                         hc->xfer_buff +=
1180                             frame_desc->offset + qtd->isoc_split_offset;
1181                         hc->xfer_len =
1182                             frame_desc->length - qtd->isoc_split_offset;
1183
1184                         /* For non-dword aligned buffers */
1185                         if (((unsigned long)hc->xfer_buff & 0x3)
1186                             && hcd->core_if->dma_enable) {
1187                                 ptr =
1188                                     (uint8_t *) urb->buf + frame_desc->offset +
1189                                     qtd->isoc_split_offset;
1190                         } else
1191                                 ptr = NULL;
1192
1193                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1194                                 if (hc->xfer_len <= 188) {
1195                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1196                                 } else {
1197                                         hc->xact_pos =
1198                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1199                                 }
1200                         }
1201                 }
1202                 break;
1203         }
1204         /* non DWORD-aligned buffer case */
1205         if (ptr) {
1206                 uint32_t buf_size;
1207                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1208                         buf_size = hcd->core_if->core_params->max_transfer_size;
1209                 } else {
1210                         buf_size = 4096;
1211                 }
1212                 if (!qh->dw_align_buf) {
1213                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1214                                                                 &qh->
1215                                                                 dw_align_buf_dma);
1216                         if (!qh->dw_align_buf) {
1217                                 DWC_ERROR
1218                                     ("%s: Failed to allocate memory to handle "
1219                                      "non-dword aligned buffer case\n",
1220                                      __func__);
1221                                 return retval;
1222                         }
1223                 }
1224                 if (!hc->ep_is_in) {
1225                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1226                 }
1227                 hc->align_buff = qh->dw_align_buf_dma;
1228         } else {
1229                 hc->align_buff = 0;
1230         }
1231
1232         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1233             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1234                 /*
1235                  * This value may be modified when the transfer is started to
1236                  * reflect the actual transfer length.
1237                  */
1238                 hc->multi_count = dwc_hb_mult(qh->maxp);
1239         }
1240
1241         if (hcd->core_if->dma_desc_enable)
1242                 hc->desc_list_addr = qh->desc_list_dma;
1243
1244         dwc_otg_hc_init(hcd->core_if, hc);
1245         hc->qh = qh;
1246         return retval;
1247 }
1248
1249 /**
1250  * This function selects transactions from the HCD transfer schedule and
1251  * assigns them to available host channels. It is called from HCD interrupt
1252  * handler functions.
1253  *
1254  * @param hcd The HCD state structure.
1255  *
1256  * @return The types of new transactions that were assigned to host channels.
1257  */
1258 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1259 {
1260         dwc_list_link_t *qh_ptr;
1261         dwc_otg_qh_t *qh;
1262         int num_channels;
1263         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1264         int err;
1265
1266 #ifdef DEBUG_SOF
1267         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1268 #endif
1269
1270         /* Process entries in the periodic ready list. */
1271         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1272
1273         while (qh_ptr != &hcd->periodic_sched_ready &&
1274                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1275
1276                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1277                 assign_and_init_hc(hcd, qh);
1278
1279                 /*
1280                  * Move the QH from the periodic ready schedule to the
1281                  * periodic assigned schedule.
1282                  */
1283                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1284                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1285                                    &qh->qh_list_entry);
1286
1287                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1288         }
1289
1290         /*
1291          * Process entries in the inactive portion of the non-periodic
1292          * schedule. Some free host channels may not be used if they are
1293          * reserved for periodic transfers.
1294          */
1295         qh_ptr = hcd->non_periodic_sched_inactive.next;
1296         num_channels = hcd->core_if->core_params->host_channels;
1297         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1298                (hcd->non_periodic_channels <
1299                 num_channels - hcd->periodic_channels) &&
1300                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1301
1302                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1303
1304                 err = assign_and_init_hc(hcd, qh);
1305
1306                 /*
1307                  * Move the QH from the non-periodic inactive schedule to the
1308                  * non-periodic active schedule.
1309                  */
1310                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1311                 if (err != 0)
1312                         continue;
1313                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1314                                    &qh->qh_list_entry);
1315
1316                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1317                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1318                 } else {
1319                         ret_val = DWC_OTG_TRANSACTION_ALL;
1320                 }
1321
1322                 hcd->non_periodic_channels++;
1323         }
1324
1325         return ret_val;
1326 }
1327
1328 /**
1329  * Attempts to queue a single transaction request for a host channel
1330  * associated with either a periodic or non-periodic transfer. This function
1331  * assumes that there is space available in the appropriate request queue. For
1332  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1333  * is available in the appropriate Tx FIFO.
1334  *
1335  * @param hcd The HCD state structure.
1336  * @param hc Host channel descriptor associated with either a periodic or
1337  * non-periodic transfer.
1338  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1339  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1340  * transfers.
1341  *
1342  * @return 1 if a request is queued and more requests may be needed to
1343  * complete the transfer, 0 if no more requests are required for this
1344  * transfer, -1 if there is insufficient space in the Tx FIFO.
1345  */
1346 static int queue_transaction(dwc_otg_hcd_t *hcd,
1347                              dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1348 {
1349         int retval;
1350
1351         if (hcd->core_if->dma_enable) {
1352                 if (hcd->core_if->dma_desc_enable) {
1353                         if (!hc->xfer_started
1354                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1355                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1356                                 hc->qh->ping_state = 0;
1357                         }
1358                 } else if (!hc->xfer_started) {
1359                         if (!hc || !(hc->qh))
1360                                 return -ENODEV;
1361                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1362                         hc->qh->ping_state = 0;
1363                 }
1364                 retval = 0;
1365         } else if (hc->halt_pending) {
1366                 /* Don't queue a request if the channel has been halted. */
1367                 retval = 0;
1368         } else if (hc->halt_on_queue) {
1369                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1370                 retval = 0;
1371         } else if (hc->do_ping) {
1372                 if (!hc->xfer_started) {
1373                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1374                 }
1375                 retval = 0;
1376         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1377                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1378                         if (!hc->xfer_started) {
1379                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1380                                 retval = 1;
1381                         } else {
1382                                 retval =
1383                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1384                                                                  hc);
1385                         }
1386                 } else {
1387                         retval = -1;
1388                 }
1389         } else {
1390                 if (!hc->xfer_started) {
1391                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1392                         retval = 1;
1393                 } else {
1394                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1395                 }
1396         }
1397
1398         return retval;
1399 }
1400
1401 /**
1402  * Processes periodic channels for the next frame and queues transactions for
1403  * these channels to the DWC_otg controller. After queueing transactions, the
1404  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1405  * to queue as Periodic Tx FIFO or request queue space becomes available.
1406  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1407  */
1408 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1409 {
1410         hptxsts_data_t tx_status;
1411         dwc_list_link_t *qh_ptr;
1412         dwc_otg_qh_t *qh;
1413         int status;
1414         int no_queue_space = 0;
1415         int no_fifo_space = 0;
1416
1417         dwc_otg_host_global_regs_t *host_regs;
1418         host_regs = hcd->core_if->host_if->host_global_regs;
1419
1420         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1421 #ifdef DEBUG
1422         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1423         DWC_DEBUGPL(DBG_HCDV,
1424                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1425                     tx_status.b.ptxqspcavail);
1426         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1427                     tx_status.b.ptxfspcavail);
1428 #endif
1429
1430         qh_ptr = hcd->periodic_sched_assigned.next;
1431         while (qh_ptr != &hcd->periodic_sched_assigned) {
1432                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1433                 if (tx_status.b.ptxqspcavail == 0) {
1434                         no_queue_space = 1;
1435                         break;
1436                 }
1437
1438                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1439
1440                 /*
1441                  * Set a flag if we're queuing high-bandwidth in slave mode.
1442                  * The flag prevents any halts to get into the request queue in
1443                  * the middle of multiple high-bandwidth packets getting queued.
1444                  */
1445                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1446                         hcd->core_if->queuing_high_bandwidth = 1;
1447                 }
1448                 status =
1449                     queue_transaction(hcd, qh->channel,
1450                                       tx_status.b.ptxfspcavail);
1451                 if (status < 0) {
1452                         no_fifo_space = 1;
1453                         break;
1454                 }
1455
1456                 /*
1457                  * In Slave mode, stay on the current transfer until there is
1458                  * nothing more to do or the high-bandwidth request count is
1459                  * reached. In DMA mode, only need to queue one request. The
1460                  * controller automatically handles multiple packets for
1461                  * high-bandwidth transfers.
1462                  */
1463                 if (hcd->core_if->dma_enable || status == 0 ||
1464                     qh->channel->requests == qh->channel->multi_count) {
1465                         qh_ptr = qh_ptr->next;
1466                         /*
1467                          * Move the QH from the periodic assigned schedule to
1468                          * the periodic queued schedule.
1469                          */
1470                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1471                                            &qh->qh_list_entry);
1472
1473                         /* done queuing high bandwidth */
1474                         hcd->core_if->queuing_high_bandwidth = 0;
1475                 }
1476         }
1477
1478         if (!hcd->core_if->dma_enable) {
1479                 dwc_otg_core_global_regs_t *global_regs;
1480                 gintmsk_data_t intr_mask = {.d32 = 0 };
1481
1482                 global_regs = hcd->core_if->core_global_regs;
1483                 intr_mask.b.ptxfempty = 1;
1484 #ifdef DEBUG
1485                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1486                 DWC_DEBUGPL(DBG_HCDV,
1487                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1488                             tx_status.b.ptxqspcavail);
1489                 DWC_DEBUGPL(DBG_HCDV,
1490                             "  P Tx FIFO Space Avail (after queue): %d\n",
1491                             tx_status.b.ptxfspcavail);
1492 #endif
1493                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1494                     no_queue_space || no_fifo_space) {
1495                         /*
1496                          * May need to queue more transactions as the request
1497                          * queue or Tx FIFO empties. Enable the periodic Tx
1498                          * FIFO empty interrupt. (Always use the half-empty
1499                          * level to ensure that new requests are loaded as
1500                          * soon as possible.)
1501                          */
1502                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1503                                          intr_mask.d32);
1504                 } else {
1505                         /*
1506                          * Disable the Tx FIFO empty interrupt since there are
1507                          * no more transactions that need to be queued right
1508                          * now. This function is called from interrupt
1509                          * handlers to queue more transactions as transfer
1510                          * states change.
1511                          */
1512                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1513                                          0);
1514                 }
1515         }
1516 }
1517
1518 /**
1519  * Processes active non-periodic channels and queues transactions for these
1520  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1521  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1522  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1523  * FIFO Empty interrupt is disabled.
1524  */
1525 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1526 {
1527         gnptxsts_data_t tx_status;
1528         dwc_list_link_t *orig_qh_ptr;
1529         dwc_otg_qh_t *qh;
1530         int status;
1531         int no_queue_space = 0;
1532         int no_fifo_space = 0;
1533         int more_to_do = 0;
1534
1535         dwc_otg_core_global_regs_t *global_regs =
1536             hcd->core_if->core_global_regs;
1537
1538         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1539 #ifdef DEBUG
1540         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1541         DWC_DEBUGPL(DBG_HCDV,
1542                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1543                     tx_status.b.nptxqspcavail);
1544         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1545                     tx_status.b.nptxfspcavail);
1546 #endif
1547         /*
1548          * Keep track of the starting point. Skip over the start-of-list
1549          * entry.
1550          */
1551         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1552                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1553         }
1554         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1555
1556         /*
1557          * Process once through the active list or until no more space is
1558          * available in the request queue or the Tx FIFO.
1559          */
1560         do {
1561                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1562                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1563                         no_queue_space = 1;
1564                         break;
1565                 }
1566
1567                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1568                                     qh_list_entry);
1569                 status =
1570                     queue_transaction(hcd, qh->channel,
1571                                       tx_status.b.nptxfspcavail);
1572
1573                 if (status > 0) {
1574                         more_to_do = 1;
1575                 } else if (status < 0) {
1576                         no_fifo_space = 1;
1577                         break;
1578                 }
1579
1580                 /* Advance to next QH, skipping start-of-list entry. */
1581                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1582                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1583                         hcd->non_periodic_qh_ptr =
1584                             hcd->non_periodic_qh_ptr->next;
1585                 }
1586
1587         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1588
1589         if (!hcd->core_if->dma_enable) {
1590                 gintmsk_data_t intr_mask = {.d32 = 0 };
1591                 intr_mask.b.nptxfempty = 1;
1592
1593 #ifdef DEBUG
1594                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1595                 DWC_DEBUGPL(DBG_HCDV,
1596                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1597                             tx_status.b.nptxqspcavail);
1598                 DWC_DEBUGPL(DBG_HCDV,
1599                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1600                             tx_status.b.nptxfspcavail);
1601 #endif
1602                 if (more_to_do || no_queue_space || no_fifo_space) {
1603                         /*
1604                          * May need to queue more transactions as the request
1605                          * queue or Tx FIFO empties. Enable the non-periodic
1606                          * Tx FIFO empty interrupt. (Always use the half-empty
1607                          * level to ensure that new requests are loaded as
1608                          * soon as possible.)
1609                          */
1610                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1611                                          intr_mask.d32);
1612                 } else {
1613                         /*
1614                          * Disable the Tx FIFO empty interrupt since there are
1615                          * no more transactions that need to be queued right
1616                          * now. This function is called from interrupt
1617                          * handlers to queue more transactions as transfer
1618                          * states change.
1619                          */
1620                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1621                                          0);
1622                 }
1623         }
1624 }
1625
1626 /**
1627  * This function processes the currently active host channels and queues
1628  * transactions for these channels to the DWC_otg controller. It is called
1629  * from HCD interrupt handler functions.
1630  *
1631  * @param hcd The HCD state structure.
1632  * @param tr_type The type(s) of transactions to queue (non-periodic,
1633  * periodic, or both).
1634  */
1635 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1636                                     dwc_otg_transaction_type_e tr_type)
1637 {
1638 #ifdef DEBUG_SOF
1639         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1640 #endif
1641         /* Process host channels associated with periodic transfers. */
1642         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1643              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1644             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1645
1646                 process_periodic_channels(hcd);
1647         }
1648
1649         /* Process host channels associated with non-periodic transfers. */
1650         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1651             tr_type == DWC_OTG_TRANSACTION_ALL) {
1652                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1653                         process_non_periodic_channels(hcd);
1654                 } else {
1655                         /*
1656                          * Ensure NP Tx FIFO empty interrupt is disabled when
1657                          * there are no non-periodic transfers to process.
1658                          */
1659                         gintmsk_data_t gintmsk = {.d32 = 0 };
1660                         gintmsk.b.nptxfempty = 1;
1661                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1662                                          gintmsk, gintmsk.d32, 0);
1663                 }
1664         }
1665 }
1666
1667 #ifdef DWC_HS_ELECT_TST
1668 /*
1669  * Quick and dirty hack to implement the HS Electrical Test
1670  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1671  *
1672  * This code was copied from our userspace app "hset". It sends a
1673  * Get Device Descriptor control sequence in two parts, first the
1674  * Setup packet by itself, followed some time later by the In and
1675  * Ack packets. Rather than trying to figure out how to add this
1676  * functionality to the normal driver code, we just hijack the
1677  * hardware, using these two function to drive the hardware
1678  * directly.
1679  */
1680
1681 static dwc_otg_core_global_regs_t *global_regs;
1682 static dwc_otg_host_global_regs_t *hc_global_regs;
1683 static dwc_otg_hc_regs_t *hc_regs;
1684 static uint32_t *data_fifo;
1685
1686 static void do_setup(void)
1687 {
1688         gintsts_data_t gintsts;
1689         hctsiz_data_t hctsiz;
1690         hcchar_data_t hcchar;
1691         haint_data_t haint;
1692         hcint_data_t hcint;
1693
1694         /* Enable HAINTs */
1695         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1696
1697         /* Enable HCINTs */
1698         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1699
1700         /* Read GINTSTS */
1701         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1702
1703         /* Read HAINT */
1704         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1705
1706         /* Read HCINT */
1707         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1708
1709         /* Read HCCHAR */
1710         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1711
1712         /* Clear HCINT */
1713         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1714
1715         /* Clear HAINT */
1716         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1717
1718         /* Clear GINTSTS */
1719         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1720
1721         /* Read GINTSTS */
1722         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1723
1724         /*
1725          * Send Setup packet (Get Device Descriptor)
1726          */
1727
1728         /* Make sure channel is disabled */
1729         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1730         if (hcchar.b.chen) {
1731                 hcchar.b.chdis = 1;
1732                 /* hcchar.b.chen = 1; */
1733                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1734                 /* sleep(1); */
1735                 dwc_mdelay(1000);
1736
1737                 /* Read GINTSTS */
1738                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1739
1740                 /* Read HAINT */
1741                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1742
1743                 /* Read HCINT */
1744                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1745
1746                 /* Read HCCHAR */
1747                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1748
1749                 /* Clear HCINT */
1750                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1751
1752                 /* Clear HAINT */
1753                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1754
1755                 /* Clear GINTSTS */
1756                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1757
1758                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1759         }
1760
1761         /* Set HCTSIZ */
1762         hctsiz.d32 = 0;
1763         hctsiz.b.xfersize = 8;
1764         hctsiz.b.pktcnt = 1;
1765         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1766         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1767
1768         /* Set HCCHAR */
1769         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1770         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1771         hcchar.b.epdir = 0;
1772         hcchar.b.epnum = 0;
1773         hcchar.b.mps = 8;
1774         hcchar.b.chen = 1;
1775         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1776
1777         /* Fill FIFO with Setup data for Get Device Descriptor */
1778         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1779         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1780         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1781
1782         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1783
1784         /* Wait for host channel interrupt */
1785         do {
1786                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1787         } while (gintsts.b.hcintr == 0);
1788
1789         /* Disable HCINTs */
1790         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1791
1792         /* Disable HAINTs */
1793         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1794
1795         /* Read HAINT */
1796         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1797
1798         /* Read HCINT */
1799         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1800
1801         /* Read HCCHAR */
1802         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1803
1804         /* Clear HCINT */
1805         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1806
1807         /* Clear HAINT */
1808         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1809
1810         /* Clear GINTSTS */
1811         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1812
1813         /* Read GINTSTS */
1814         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1815 }
1816
1817 static void do_in_ack(void)
1818 {
1819         gintsts_data_t gintsts;
1820         hctsiz_data_t hctsiz;
1821         hcchar_data_t hcchar;
1822         haint_data_t haint;
1823         hcint_data_t hcint;
1824         host_grxsts_data_t grxsts;
1825
1826         /* Enable HAINTs */
1827         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1828
1829         /* Enable HCINTs */
1830         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1831
1832         /* Read GINTSTS */
1833         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1834
1835         /* Read HAINT */
1836         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1837
1838         /* Read HCINT */
1839         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1840
1841         /* Read HCCHAR */
1842         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1843
1844         /* Clear HCINT */
1845         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1846
1847         /* Clear HAINT */
1848         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1849
1850         /* Clear GINTSTS */
1851         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1852
1853         /* Read GINTSTS */
1854         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1855
1856         /*
1857          * Receive Control In packet
1858          */
1859
1860         /* Make sure channel is disabled */
1861         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1862         if (hcchar.b.chen) {
1863                 hcchar.b.chdis = 1;
1864                 hcchar.b.chen = 1;
1865                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1866                 /* sleep(1); */
1867                 dwc_mdelay(1000);
1868
1869                 /* Read GINTSTS */
1870                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1871
1872                 /* Read HAINT */
1873                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1874
1875                 /* Read HCINT */
1876                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1877
1878                 /* Read HCCHAR */
1879                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1880
1881                 /* Clear HCINT */
1882                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1883
1884                 /* Clear HAINT */
1885                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1886
1887                 /* Clear GINTSTS */
1888                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1889
1890                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1891         }
1892
1893         /* Set HCTSIZ */
1894         hctsiz.d32 = 0;
1895         hctsiz.b.xfersize = 8;
1896         hctsiz.b.pktcnt = 1;
1897         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1898         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1899
1900         /* Set HCCHAR */
1901         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1902         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1903         hcchar.b.epdir = 1;
1904         hcchar.b.epnum = 0;
1905         hcchar.b.mps = 8;
1906         hcchar.b.chen = 1;
1907         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1908
1909         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1910
1911         /* Wait for receive status queue interrupt */
1912         do {
1913                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1914         } while (gintsts.b.rxstsqlvl == 0);
1915
1916         /* Read RXSTS */
1917         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1918
1919         /* Clear RXSTSQLVL in GINTSTS */
1920         gintsts.d32 = 0;
1921         gintsts.b.rxstsqlvl = 1;
1922         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1923
1924         switch (grxsts.b.pktsts) {
1925         case DWC_GRXSTS_PKTSTS_IN:
1926                 /* Read the data into the host buffer */
1927                 if (grxsts.b.bcnt > 0) {
1928                         int i;
1929                         int word_count = (grxsts.b.bcnt + 3) / 4;
1930
1931                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1932
1933                         for (i = 0; i < word_count; i++) {
1934                                 (void)DWC_READ_REG32(data_fifo++);
1935                         }
1936                 }
1937                 break;
1938
1939         default:
1940                 break;
1941         }
1942
1943         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1944
1945         /* Wait for receive status queue interrupt */
1946         do {
1947                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1948         } while (gintsts.b.rxstsqlvl == 0);
1949
1950         /* Read RXSTS */
1951         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1952
1953         /* Clear RXSTSQLVL in GINTSTS */
1954         gintsts.d32 = 0;
1955         gintsts.b.rxstsqlvl = 1;
1956         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1957
1958         switch (grxsts.b.pktsts) {
1959         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1960                 break;
1961
1962         default:
1963                 break;
1964         }
1965
1966         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1967
1968         /* Wait for host channel interrupt */
1969         do {
1970                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1971         } while (gintsts.b.hcintr == 0);
1972
1973         /* Read HAINT */
1974         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1975
1976         /* Read HCINT */
1977         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1978
1979         /* Read HCCHAR */
1980         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1981
1982         /* Clear HCINT */
1983         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1984
1985         /* Clear HAINT */
1986         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1987
1988         /* Clear GINTSTS */
1989         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1990
1991         /* Read GINTSTS */
1992         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1993
1994         /* usleep(100000); */
1995         /* mdelay(100); */
1996         dwc_mdelay(1);
1997
1998         /*
1999          * Send handshake packet
2000          */
2001
2002         /* Read HAINT */
2003         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2004
2005         /* Read HCINT */
2006         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2007
2008         /* Read HCCHAR */
2009         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2010
2011         /* Clear HCINT */
2012         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2013
2014         /* Clear HAINT */
2015         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2016
2017         /* Clear GINTSTS */
2018         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2019
2020         /* Read GINTSTS */
2021         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2022
2023         /* Make sure channel is disabled */
2024         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2025         if (hcchar.b.chen) {
2026                 hcchar.b.chdis = 1;
2027                 hcchar.b.chen = 1;
2028                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2029                 /* sleep(1); */
2030                 dwc_mdelay(1000);
2031
2032                 /* Read GINTSTS */
2033                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2034
2035                 /* Read HAINT */
2036                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2037
2038                 /* Read HCINT */
2039                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2040
2041                 /* Read HCCHAR */
2042                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2043
2044                 /* Clear HCINT */
2045                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2046
2047                 /* Clear HAINT */
2048                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2049
2050                 /* Clear GINTSTS */
2051                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2052
2053                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2054         }
2055
2056         /* Set HCTSIZ */
2057         hctsiz.d32 = 0;
2058         hctsiz.b.xfersize = 0;
2059         hctsiz.b.pktcnt = 1;
2060         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2061         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2062
2063         /* Set HCCHAR */
2064         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2065         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2066         hcchar.b.epdir = 0;
2067         hcchar.b.epnum = 0;
2068         hcchar.b.mps = 8;
2069         hcchar.b.chen = 1;
2070         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2071
2072         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2073
2074         /* Wait for host channel interrupt */
2075         do {
2076                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2077         } while (gintsts.b.hcintr == 0);
2078
2079         /* Disable HCINTs */
2080         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2081
2082         /* Disable HAINTs */
2083         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2084
2085         /* Read HAINT */
2086         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2087
2088         /* Read HCINT */
2089         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2090
2091         /* Read HCCHAR */
2092         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2093
2094         /* Clear HCINT */
2095         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2096
2097         /* Clear HAINT */
2098         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2099
2100         /* Clear GINTSTS */
2101         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2102
2103         /* Read GINTSTS */
2104         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2105 }
2106 #endif
2107
2108 /** Handles hub class-specific requests. */
2109 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2110                             uint16_t typeReq,
2111                             uint16_t wValue,
2112                             uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2113 {
2114         int retval = 0;
2115
2116         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2117         usb_hub_descriptor_t *hub_desc;
2118         hprt0_data_t hprt0 = {.d32 = 0 };
2119
2120         uint32_t port_status;
2121
2122         switch (typeReq) {
2123         case UCR_CLEAR_HUB_FEATURE:
2124                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2125                             "ClearHubFeature 0x%x\n", wValue);
2126                 switch (wValue) {
2127                 case UHF_C_HUB_LOCAL_POWER:
2128                 case UHF_C_HUB_OVER_CURRENT:
2129                         /* Nothing required here */
2130                         break;
2131                 default:
2132                         retval = -DWC_E_INVALID;
2133                         DWC_ERROR("DWC OTG HCD - "
2134                                   "ClearHubFeature request %xh unknown\n",
2135                                   wValue);
2136                 }
2137                 break;
2138         case UCR_CLEAR_PORT_FEATURE:
2139 #ifdef CONFIG_USB_DWC_OTG_LPM
2140                 if (wValue != UHF_PORT_L1)
2141 #endif
2142                         if (!wIndex || wIndex > 1)
2143                                 goto error;
2144
2145                 switch (wValue) {
2146                 case UHF_PORT_ENABLE:
2147                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2148                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2149                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2150                         hprt0.b.prtena = 1;
2151                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2152                         break;
2153                 case UHF_PORT_SUSPEND:
2154                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2155                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2156
2157                         if (core_if->power_down == 2) {
2158                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2159                         } else {
2160                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2161                                 dwc_mdelay(5);
2162
2163                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2164                                 hprt0.b.prtres = 1;
2165                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2166                                                 hprt0.d32);
2167                                 hprt0.b.prtsusp = 0;
2168                                 /* Clear Resume bit */
2169                                 dwc_mdelay(100);
2170                                 hprt0.b.prtres = 0;
2171                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2172                                                 hprt0.d32);
2173                         }
2174                         break;
2175 #ifdef CONFIG_USB_DWC_OTG_LPM
2176                 case UHF_PORT_L1:
2177                         {
2178                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2179                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2180
2181                                 lpmcfg.d32 =
2182                                     DWC_READ_REG32(&core_if->core_global_regs->
2183                                                    glpmcfg);
2184                                 lpmcfg.b.en_utmi_sleep = 0;
2185                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2186                                 lpmcfg.b.prt_sleep_sts = 1;
2187                                 DWC_WRITE_REG32(&core_if->core_global_regs->
2188                                                 glpmcfg, lpmcfg.d32);
2189
2190                                 /* Clear Enbl_L1Gating bit. */
2191                                 pcgcctl.b.enbl_sleep_gating = 1;
2192                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2193                                                  0);
2194
2195                                 dwc_mdelay(5);
2196
2197                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2198                                 hprt0.b.prtres = 1;
2199                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2200                                                 hprt0.d32);
2201                                 /* This bit will be cleared in wakeup interrupt handle */
2202                                 break;
2203                         }
2204 #endif
2205                 case UHF_PORT_POWER:
2206                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2207                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2208                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2209                         hprt0.b.prtpwr = 0;
2210                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2211                         break;
2212                 case UHF_PORT_INDICATOR:
2213                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2214                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2215                         /* Port inidicator not supported */
2216                         break;
2217                 case UHF_C_PORT_CONNECTION:
2218                         /* Clears drivers internal connect status change
2219                          * flag */
2220                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2221                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2222                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2223                         break;
2224                 case UHF_C_PORT_RESET:
2225                         /* Clears the driver's internal Port Reset Change
2226                          * flag */
2227                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2228                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2229                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2230                         break;
2231                 case UHF_C_PORT_ENABLE:
2232                         /* Clears the driver's internal Port
2233                          * Enable/Disable Change flag */
2234                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2235                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2236                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2237                         break;
2238                 case UHF_C_PORT_SUSPEND:
2239                         /* Clears the driver's internal Port Suspend
2240                          * Change flag, which is set when resume signaling on
2241                          * the host port is complete */
2242                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2243                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2244                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2245                         break;
2246 #ifdef CONFIG_USB_DWC_OTG_LPM
2247                 case UHF_C_PORT_L1:
2248                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2249                         break;
2250 #endif
2251                 case UHF_C_PORT_OVER_CURRENT:
2252                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2253                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2254                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2255                         break;
2256                 default:
2257                         retval = -DWC_E_INVALID;
2258                         DWC_ERROR("DWC OTG HCD - "
2259                                   "ClearPortFeature request %xh "
2260                                   "unknown or unsupported\n", wValue);
2261                 }
2262                 break;
2263         case UCR_GET_HUB_DESCRIPTOR:
2264                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2265                             "GetHubDescriptor\n");
2266                 hub_desc = (usb_hub_descriptor_t *) buf;
2267                 hub_desc->bDescLength = 9;
2268                 hub_desc->bDescriptorType = 0x29;
2269                 hub_desc->bNbrPorts = 1;
2270                 USETW(hub_desc->wHubCharacteristics, 0x08);
2271                 hub_desc->bPwrOn2PwrGood = 1;
2272                 hub_desc->bHubContrCurrent = 0;
2273                 hub_desc->DeviceRemovable[0] = 0;
2274                 hub_desc->DeviceRemovable[1] = 0xff;
2275                 break;
2276         case UCR_GET_HUB_STATUS:
2277                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2278                             "GetHubStatus\n");
2279                 DWC_MEMSET(buf, 0, 4);
2280                 break;
2281         case UCR_GET_PORT_STATUS:
2282                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2283                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2284                             wIndex, dwc_otg_hcd->flags.d32);
2285                 if (!wIndex || wIndex > 1)
2286                         goto error;
2287
2288                 port_status = 0;
2289
2290                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2291                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2292
2293                 if (dwc_otg_hcd->flags.b.port_enable_change)
2294                         port_status |= (1 << UHF_C_PORT_ENABLE);
2295
2296                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2297                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2298
2299                 if (dwc_otg_hcd->flags.b.port_l1_change)
2300                         port_status |= (1 << UHF_C_PORT_L1);
2301
2302                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2303                         port_status |= (1 << UHF_C_PORT_RESET);
2304                 }
2305
2306                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2307                         DWC_WARN("Overcurrent change detected\n");
2308                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2309                 }
2310
2311                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2312                         /*
2313                          * The port is disconnected, which means the core is
2314                          * either in device mode or it soon will be. Just
2315                          * return 0's for the remainder of the port status
2316                          * since the port register can't be read if the core
2317                          * is in device mode.
2318                          */
2319                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2320                         break;
2321                 }
2322
2323                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2324                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2325
2326                 if (hprt0.b.prtconnsts)
2327                         port_status |= (1 << UHF_PORT_CONNECTION);
2328
2329                 if (hprt0.b.prtena)
2330                         port_status |= (1 << UHF_PORT_ENABLE);
2331
2332                 if (hprt0.b.prtsusp)
2333                         port_status |= (1 << UHF_PORT_SUSPEND);
2334
2335                 if (hprt0.b.prtovrcurract)
2336                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2337
2338                 if (hprt0.b.prtrst)
2339                         port_status |= (1 << UHF_PORT_RESET);
2340
2341                 if (hprt0.b.prtpwr)
2342                         port_status |= (1 << UHF_PORT_POWER);
2343
2344                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2345                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2346                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2347                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2348
2349                 if (hprt0.b.prttstctl)
2350                         port_status |= (1 << UHF_PORT_TEST);
2351                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2352                         port_status |= (1 << UHF_PORT_L1);
2353                 }
2354                 /*
2355                    For Synopsys HW emulation of Power down wkup_control asserts the
2356                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2357                    We intentionally tell the software that port is in L2Suspend state.
2358                    Only for STE.
2359                  */
2360                 if ((core_if->power_down == 2)
2361                     && (core_if->hibernation_suspend == 1)) {
2362                         port_status |= (1 << UHF_PORT_SUSPEND);
2363                 }
2364                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2365
2366                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2367
2368                 break;
2369         case UCR_SET_HUB_FEATURE:
2370                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2371                             "SetHubFeature\n");
2372                 /* No HUB features supported */
2373                 break;
2374         case UCR_SET_PORT_FEATURE:
2375                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2376                         goto error;
2377
2378                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2379                         /*
2380                          * The port is disconnected, which means the core is
2381                          * either in device mode or it soon will be. Just
2382                          * return without doing anything since the port
2383                          * register can't be written if the core is in device
2384                          * mode.
2385                          */
2386                         break;
2387                 }
2388
2389                 switch (wValue) {
2390                 case UHF_PORT_SUSPEND:
2391                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2392                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2393                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2394                                 goto error;
2395                         }
2396                         if (core_if->power_down == 2) {
2397                                 int timeout = 300;
2398                                 dwc_irqflags_t flags;
2399                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2400                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2401                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2402 #ifdef DWC_DEV_SRPCAP
2403                                 int32_t otg_cap_param =
2404                                     core_if->core_params->otg_cap;
2405 #endif
2406                                 DWC_PRINTF
2407                                     ("Preparing for complete power-off\n");
2408
2409                                 /* Save registers before hibernation */
2410                                 dwc_otg_save_global_regs(core_if);
2411                                 dwc_otg_save_host_regs(core_if);
2412
2413                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2414                                 hprt0.b.prtsusp = 1;
2415                                 hprt0.b.prtena = 0;
2416                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2417                                                 hprt0.d32);
2418                                 /* Spin hprt0.b.prtsusp to became 1 */
2419                                 do {
2420                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2421                                         if (hprt0.b.prtsusp) {
2422                                                 break;
2423                                         }
2424                                         dwc_mdelay(1);
2425                                 } while (--timeout);
2426                                 if (!timeout) {
2427                                         DWC_WARN("Suspend wasn't genereted\n");
2428                                 }
2429                                 dwc_udelay(10);
2430
2431                                 /*
2432                                  * We need to disable interrupts to prevent servicing of any IRQ
2433                                  * during going to hibernation
2434                                  */
2435                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2436                                 core_if->lx_state = DWC_OTG_L2;
2437 #ifdef DWC_DEV_SRPCAP
2438                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2439                                 hprt0.b.prtpwr = 0;
2440                                 hprt0.b.prtena = 0;
2441                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2442                                                 hprt0.d32);
2443 #endif
2444                                 gusbcfg.d32 =
2445                                     DWC_READ_REG32(&core_if->
2446                                                    core_global_regs->gusbcfg);
2447                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2448                                         /* ULPI interface */
2449                                         /* Suspend the Phy Clock */
2450                                         pcgcctl.d32 = 0;
2451                                         pcgcctl.b.stoppclk = 1;
2452                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2453                                                          pcgcctl.d32);
2454                                         dwc_udelay(10);
2455                                         gpwrdn.b.pmuactv = 1;
2456                                         DWC_MODIFY_REG32
2457                                             (&core_if->core_global_regs->gpwrdn,
2458                                              0, gpwrdn.d32);
2459                                 } else {
2460                                         /* UTMI+ Interface */
2461                                         gpwrdn.b.pmuactv = 1;
2462                                         DWC_MODIFY_REG32
2463                                             (&core_if->core_global_regs->gpwrdn,
2464                                              0, gpwrdn.d32);
2465                                         dwc_udelay(10);
2466                                         pcgcctl.b.stoppclk = 1;
2467                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2468                                                          pcgcctl.d32);
2469                                         dwc_udelay(10);
2470                                 }
2471 #ifdef DWC_DEV_SRPCAP
2472                                 gpwrdn.d32 = 0;
2473                                 gpwrdn.b.dis_vbus = 1;
2474                                 DWC_MODIFY_REG32(&core_if->
2475                                                  core_global_regs->gpwrdn, 0,
2476                                                  gpwrdn.d32);
2477 #endif
2478                                 gpwrdn.d32 = 0;
2479                                 gpwrdn.b.pmuintsel = 1;
2480                                 DWC_MODIFY_REG32(&core_if->
2481                                                  core_global_regs->gpwrdn, 0,
2482                                                  gpwrdn.d32);
2483                                 dwc_udelay(10);
2484
2485                                 gpwrdn.d32 = 0;
2486 #ifdef DWC_DEV_SRPCAP
2487                                 gpwrdn.b.srp_det_msk = 1;
2488 #endif
2489                                 gpwrdn.b.disconn_det_msk = 1;
2490                                 gpwrdn.b.lnstchng_msk = 1;
2491                                 gpwrdn.b.sts_chngint_msk = 1;
2492                                 DWC_MODIFY_REG32(&core_if->
2493                                                  core_global_regs->gpwrdn, 0,
2494                                                  gpwrdn.d32);
2495                                 dwc_udelay(10);
2496
2497                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2498                                 gpwrdn.d32 = 0;
2499                                 gpwrdn.b.pwrdnclmp = 1;
2500                                 DWC_MODIFY_REG32(&core_if->
2501                                                  core_global_regs->gpwrdn, 0,
2502                                                  gpwrdn.d32);
2503                                 dwc_udelay(10);
2504
2505                                 /* Switch off VDD */
2506                                 gpwrdn.d32 = 0;
2507                                 gpwrdn.b.pwrdnswtch = 1;
2508                                 DWC_MODIFY_REG32(&core_if->
2509                                                  core_global_regs->gpwrdn, 0,
2510                                                  gpwrdn.d32);
2511
2512 #ifdef DWC_DEV_SRPCAP
2513                                 if (otg_cap_param ==
2514                                     DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2515                                         core_if->pwron_timer_started = 1;
2516                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2517                                                            6000 /* 6 secs */);
2518                                 }
2519 #endif
2520                                 /* Save gpwrdn register for further usage if stschng interrupt */
2521                                 core_if->gr_backup->gpwrdn_local =
2522                                     DWC_READ_REG32(&core_if->core_global_regs->
2523                                                    gpwrdn);
2524
2525                                 /* Set flag to indicate that we are in hibernation */
2526                                 core_if->hibernation_suspend = 1;
2527                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2528                                                           flags);
2529
2530                                 DWC_PRINTF("Host hibernation completed\n");
2531                                 /* Exit from case statement */
2532                                 break;
2533
2534                         }
2535                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2536                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2537                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2538                                 gotgctl.b.hstsethnpen = 1;
2539                                 DWC_MODIFY_REG32(&core_if->
2540                                                  core_global_regs->gotgctl, 0,
2541                                                  gotgctl.d32);
2542                                 core_if->op_state = A_SUSPEND;
2543                         }
2544                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2545                         hprt0.b.prtsusp = 1;
2546                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2547                         {
2548                                 dwc_irqflags_t flags;
2549                                 /* Update lx_state */
2550                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2551                                 core_if->lx_state = DWC_OTG_L2;
2552                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2553                                                           flags);
2554                         }
2555                         /* Suspend the Phy Clock */
2556                         if (core_if->otg_ver == 0) {
2557                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2558                                 pcgcctl.b.stoppclk = 1;
2559                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2560                                                  pcgcctl.d32);
2561                                 dwc_udelay(10);
2562                         }
2563
2564                         /* For HNP the bus must be suspended for at least 200ms. */
2565                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2566                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2567                                 pcgcctl.b.stoppclk = 1;
2568                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2569                                                  0);
2570                                 dwc_mdelay(200);
2571                         }
2572
2573                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2574 #if 0
2575                         if (core_if->adp_enable) {
2576                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2577                                 gpwrdn_data_t gpwrdn;
2578
2579                                 while (gotgctl.b.asesvld == 1) {
2580                                         gotgctl.d32 =
2581                                             DWC_READ_REG32
2582                                             (&core_if->core_global_regs->gotgctl);
2583                                         dwc_mdelay(100);
2584                                 }
2585
2586                                 /* Enable Power Down Logic */
2587                                 gpwrdn.d32 = 0;
2588                                 gpwrdn.b.pmuactv = 1;
2589                                 DWC_MODIFY_REG32(&core_if->
2590                                                  core_global_regs->gpwrdn, 0,
2591                                                  gpwrdn.d32);
2592
2593                                 /* Unmask SRP detected interrupt from Power Down Logic */
2594                                 gpwrdn.d32 = 0;
2595                                 gpwrdn.b.srp_det_msk = 1;
2596                                 DWC_MODIFY_REG32(&core_if->
2597                                                  core_global_regs->gpwrdn, 0,
2598                                                  gpwrdn.d32);
2599
2600                                 dwc_otg_adp_probe_start(core_if);
2601                         }
2602 #endif
2603                         break;
2604                 case UHF_PORT_POWER:
2605                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2606                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2607                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2608                         hprt0.b.prtpwr = 1;
2609                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2610                         break;
2611                 case UHF_PORT_RESET:
2612                         if ((core_if->power_down == 2)
2613                             && (core_if->hibernation_suspend == 1)) {
2614                                 /* If we are going to exit from Hibernated
2615                                  * state via USB RESET.
2616                                  */
2617                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2618                         } else {
2619                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2620
2621                                 DWC_DEBUGPL(DBG_HCD,
2622                                             "DWC OTG HCD HUB CONTROL - "
2623                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2624                                 {
2625                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2626                                         pcgcctl.b.enbl_sleep_gating = 1;
2627                                         pcgcctl.b.stoppclk = 1;
2628                                         DWC_MODIFY_REG32(core_if->pcgcctl,
2629                                                          pcgcctl.d32, 0);
2630                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2631                                 }
2632 #ifdef CONFIG_USB_DWC_OTG_LPM
2633                                 {
2634                                         glpmcfg_data_t lpmcfg;
2635                                         lpmcfg.d32 =
2636                                             DWC_READ_REG32(&core_if->
2637                                                            core_global_regs->
2638                                                            glpmcfg);
2639                                         if (lpmcfg.b.prt_sleep_sts) {
2640                                                 lpmcfg.b.en_utmi_sleep = 0;
2641                                                 lpmcfg.b.hird_thres &=
2642                                                     (~(1 << 4));
2643                                                 DWC_WRITE_REG32(&core_if->
2644                                                                 core_global_regs->
2645                                                                 glpmcfg,
2646                                                                 lpmcfg.d32);
2647                                                 dwc_mdelay(1);
2648                                         }
2649                                 }
2650 #endif
2651                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2652                                 /* Clear suspend bit if resetting from suspended state. */
2653                                 hprt0.b.prtsusp = 0;
2654                                 /* When B-Host the Port reset bit is set in
2655                                  * the Start HCD Callback function, so that
2656                                  * the reset is started within 1ms of the HNP
2657                                  * success interrupt. */
2658                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2659                                         hprt0.b.prtpwr = 1;
2660                                         hprt0.b.prtrst = 1;
2661                                         DWC_PRINTF
2662                                             ("Indeed it is in host mode hprt0 = %08x\n",
2663                                              hprt0.d32);
2664                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2665                                                         hprt0.d32);
2666                                 }
2667                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2668                                 dwc_mdelay(60);
2669                                 hprt0.b.prtrst = 0;
2670                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2671                                                 hprt0.d32);
2672                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2673                         }
2674                         break;
2675 #ifdef DWC_HS_ELECT_TST
2676                 case UHF_PORT_TEST:
2677                         {
2678                                 uint32_t t;
2679                                 gintmsk_data_t gintmsk;
2680
2681                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2682                                 DWC_DEBUGPL(DBG_HCD,
2683                                             "DWC OTG HCD HUB CONTROL - "
2684                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2685                                             t);
2686                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2687                                 if (t < 6) {
2688                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2689                                         hprt0.b.prttstctl = t;
2690                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2691                                                         hprt0.d32);
2692                                 } else {
2693                                         /* Setup global vars with reg addresses (quick and
2694                                          * dirty hack, should be cleaned up)
2695                                          */
2696                                         global_regs = core_if->core_global_regs;
2697                                         hc_global_regs =
2698                                             core_if->host_if->host_global_regs;
2699                                         hc_regs =
2700                                             (dwc_otg_hc_regs_t *) ((char *)
2701                                                                    global_regs +
2702                                                                    0x500);
2703                                         data_fifo =
2704                                             (uint32_t *) ((char *)global_regs +
2705                                                           0x1000);
2706
2707                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2708                                                 /* Save current interrupt mask */
2709                                                 gintmsk.d32 =
2710                                                     DWC_READ_REG32
2711                                                     (&global_regs->gintmsk);
2712
2713                                                 /* Disable all interrupts while we muck with
2714                                                  * the hardware directly
2715                                                  */
2716                                                 DWC_WRITE_REG32(&global_regs->
2717                                                                 gintmsk, 0);
2718
2719                                                 /* 15 second delay per the test spec */
2720                                                 dwc_mdelay(15000);
2721
2722                                                 /* Drive suspend on the root port */
2723                                                 hprt0.d32 =
2724                                                     dwc_otg_read_hprt0(core_if);
2725                                                 hprt0.b.prtsusp = 1;
2726                                                 hprt0.b.prtres = 0;
2727                                                 DWC_WRITE_REG32(core_if->
2728                                                                 host_if->hprt0,
2729                                                                 hprt0.d32);
2730
2731                                                 /* 15 second delay per the test spec */
2732                                                 dwc_mdelay(15000);
2733
2734                                                 /* Drive resume on the root port */
2735                                                 hprt0.d32 =
2736                                                     dwc_otg_read_hprt0(core_if);
2737                                                 hprt0.b.prtsusp = 0;
2738                                                 hprt0.b.prtres = 1;
2739                                                 DWC_WRITE_REG32(core_if->
2740                                                                 host_if->hprt0,
2741                                                                 hprt0.d32);
2742                                                 dwc_mdelay(100);
2743
2744                                                 /* Clear the resume bit */
2745                                                 hprt0.b.prtres = 0;
2746                                                 DWC_WRITE_REG32(core_if->
2747                                                                 host_if->hprt0,
2748                                                                 hprt0.d32);
2749
2750                                                 /* Restore interrupts */
2751                                                 DWC_WRITE_REG32(&global_regs->
2752                                                                 gintmsk,
2753                                                                 gintmsk.d32);
2754                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2755                                                 /* Save current interrupt mask */
2756                                                 gintmsk.d32 =
2757                                                     DWC_READ_REG32
2758                                                     (&global_regs->gintmsk);
2759
2760                                                 /* Disable all interrupts while we muck with
2761                                                  * the hardware directly
2762                                                  */
2763                                                 DWC_WRITE_REG32(&global_regs->
2764                                                                 gintmsk, 0);
2765
2766                                                 /* 15 second delay per the test spec */
2767                                                 dwc_mdelay(15000);
2768
2769                                                 /* Send the Setup packet */
2770                                                 do_setup();
2771
2772                                                 /* 15 second delay so nothing else happens for awhile */
2773                                                 dwc_mdelay(15000);
2774
2775                                                 /* Restore interrupts */
2776                                                 DWC_WRITE_REG32(&global_regs->
2777                                                                 gintmsk,
2778                                                                 gintmsk.d32);
2779                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2780                                                 /* Save current interrupt mask */
2781                                                 gintmsk.d32 =
2782                                                     DWC_READ_REG32
2783                                                     (&global_regs->gintmsk);
2784
2785                                                 /* Disable all interrupts while we muck with
2786                                                  * the hardware directly
2787                                                  */
2788                                                 DWC_WRITE_REG32(&global_regs->
2789                                                                 gintmsk, 0);
2790
2791                                                 /* Send the Setup packet */
2792                                                 do_setup();
2793
2794                                                 /* 15 second delay so nothing else happens for awhile */
2795                                                 dwc_mdelay(15000);
2796
2797                                                 /* Send the In and Ack packets */
2798                                                 do_in_ack();
2799
2800                                                 /* 15 second delay so nothing else happens for awhile */
2801                                                 dwc_mdelay(15000);
2802
2803                                                 /* Restore interrupts */
2804                                                 DWC_WRITE_REG32(&global_regs->
2805                                                                 gintmsk,
2806                                                                 gintmsk.d32);
2807                                         }
2808                                 }
2809                                 break;
2810                         }
2811 #endif /* DWC_HS_ELECT_TST */
2812
2813                 case UHF_PORT_INDICATOR:
2814                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2815                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2816                         /* Not supported */
2817                         break;
2818                 default:
2819                         retval = -DWC_E_INVALID;
2820                         DWC_ERROR("DWC OTG HCD - "
2821                                   "SetPortFeature request %xh "
2822                                   "unknown or unsupported\n", wValue);
2823                         break;
2824                 }
2825                 break;
2826 #ifdef CONFIG_USB_DWC_OTG_LPM
2827         case UCR_SET_AND_TEST_PORT_FEATURE:
2828                 if (wValue != UHF_PORT_L1) {
2829                         goto error;
2830                 }
2831                 {
2832                         int portnum, hird, devaddr, remwake;
2833                         glpmcfg_data_t lpmcfg;
2834                         uint32_t time_usecs;
2835                         gintsts_data_t gintsts;
2836                         gintmsk_data_t gintmsk;
2837
2838                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2839                                 goto error;
2840                         }
2841                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2842                                 goto error;
2843                         }
2844                         /* Check if the port currently is in SLEEP state */
2845                         lpmcfg.d32 =
2846                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2847                         if (lpmcfg.b.prt_sleep_sts) {
2848                                 DWC_INFO("Port is already in sleep mode\n");
2849                                 buf[0] = 0;     /* Return success */
2850                                 break;
2851                         }
2852
2853                         portnum = wIndex & 0xf;
2854                         hird = (wIndex >> 4) & 0xf;
2855                         devaddr = (wIndex >> 8) & 0x7f;
2856                         remwake = (wIndex >> 15);
2857
2858                         if (portnum != 1) {
2859                                 retval = -DWC_E_INVALID;
2860                                 DWC_WARN
2861                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2862                                      portnum);
2863                                 break;
2864                         }
2865
2866                         DWC_PRINTF
2867                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2868                              portnum, hird, devaddr, remwake);
2869                         /* Disable LPM interrupt */
2870                         gintmsk.d32 = 0;
2871                         gintmsk.b.lpmtranrcvd = 1;
2872                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2873                                          gintmsk.d32, 0);
2874
2875                         if (dwc_otg_hcd_send_lpm
2876                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2877                                 retval = -DWC_E_INVALID;
2878                                 break;
2879                         }
2880
2881                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2882                         /* We will consider timeout if time_usecs microseconds pass,
2883                          * and we don't receive LPM transaction status.
2884                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2885                          *  core will set lpmtranrcvd bit.
2886                          */
2887                         do {
2888                                 gintsts.d32 =
2889                                     DWC_READ_REG32(&core_if->core_global_regs->
2890                                                    gintsts);
2891                                 if (gintsts.b.lpmtranrcvd) {
2892                                         break;
2893                                 }
2894                                 dwc_udelay(1);
2895                         } while (--time_usecs);
2896                         /* lpm_int bit will be cleared in LPM interrupt handler */
2897
2898                         /* Now fill status
2899                          * 0x00 - Success
2900                          * 0x10 - NYET
2901                          * 0x11 - Timeout
2902                          */
2903                         if (!gintsts.b.lpmtranrcvd) {
2904                                 buf[0] = 0x3;   /* Completion code is Timeout */
2905                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2906                         } else {
2907                                 lpmcfg.d32 =
2908                                     DWC_READ_REG32(&core_if->core_global_regs->
2909                                                    glpmcfg);
2910                                 if (lpmcfg.b.lpm_resp == 0x3) {
2911                                         /* ACK responce from the device */
2912                                         buf[0] = 0x00;  /* Success */
2913                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2914                                         /* NYET responce from the device */
2915                                         buf[0] = 0x2;
2916                                 } else {
2917                                         /* Otherwise responce with Timeout */
2918                                         buf[0] = 0x3;
2919                                 }
2920                         }
2921                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2922                                    lpmcfg.b.lpm_resp);
2923                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2924                                          gintmsk.d32);
2925
2926                         break;
2927                 }
2928 #endif /* CONFIG_USB_DWC_OTG_LPM */
2929         default:
2930 error:
2931                 retval = -DWC_E_INVALID;
2932                 DWC_WARN("DWC OTG HCD - "
2933                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2934                          typeReq, wIndex, wValue);
2935                 break;
2936         }
2937
2938         return retval;
2939 }
2940
2941 #ifdef CONFIG_USB_DWC_OTG_LPM
2942 /** Returns index of host channel to perform LPM transaction. */
2943 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2944 {
2945         dwc_otg_core_if_t *core_if = hcd->core_if;
2946         dwc_hc_t *hc;
2947         hcchar_data_t hcchar;
2948         gintmsk_data_t gintmsk = {.d32 = 0 };
2949
2950         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2951                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2952                 return -1;
2953         }
2954
2955         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2956
2957         /* Mask host channel interrupts. */
2958         gintmsk.b.hcintr = 1;
2959         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2960
2961         /* Fill fields that core needs for LPM transaction */
2962         hcchar.b.devaddr = devaddr;
2963         hcchar.b.epnum = 0;
2964         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2965         hcchar.b.mps = 64;
2966         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2967         hcchar.b.epdir = 0;     /* OUT */
2968         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2969                         hcchar.d32);
2970
2971         /* Remove the host channel from the free list. */
2972         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2973
2974         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2975
2976         return hc->hc_num;
2977 }
2978
2979 /** Release hc after performing LPM transaction */
2980 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2981 {
2982         dwc_hc_t *hc;
2983         glpmcfg_data_t lpmcfg;
2984         uint8_t hc_num;
2985
2986         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2987         hc_num = lpmcfg.b.lpm_chan_index;
2988
2989         hc = hcd->hc_ptr_array[hc_num];
2990
2991         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2992         /* Return host channel to free list */
2993         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2994 }
2995
2996 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2997                          uint8_t bRemoteWake)
2998 {
2999         glpmcfg_data_t lpmcfg;
3000         pcgcctl_data_t pcgcctl = {.d32 = 0 };
3001         int channel;
3002
3003         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
3004         if (channel < 0) {
3005                 return channel;
3006         }
3007
3008         pcgcctl.b.enbl_sleep_gating = 1;
3009         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
3010
3011         /* Read LPM config register */
3012         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
3013
3014         /* Program LPM transaction fields */
3015         lpmcfg.b.rem_wkup_en = bRemoteWake;
3016         lpmcfg.b.hird = hird;
3017
3018         if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
3019                 lpmcfg.b.hird_thres = 0x16;
3020                 lpmcfg.b.en_besl = 1;
3021         } else {
3022                 lpmcfg.b.hird_thres = 0x1c;
3023         }
3024
3025         lpmcfg.b.lpm_chan_index = channel;
3026         lpmcfg.b.en_utmi_sleep = 1;
3027         /* Program LPM config register */
3028         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3029
3030         /* Send LPM transaction */
3031         lpmcfg.b.send_lpm = 1;
3032         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3033
3034         return 0;
3035 }
3036
3037 #endif /* CONFIG_USB_DWC_OTG_LPM */
3038
3039 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3040 {
3041         int retval;
3042
3043         if (port != 1) {
3044                 return -DWC_E_INVALID;
3045         }
3046
3047         retval = (hcd->flags.b.port_connect_status_change ||
3048                   hcd->flags.b.port_reset_change ||
3049                   hcd->flags.b.port_enable_change ||
3050                   hcd->flags.b.port_suspend_change ||
3051                   hcd->flags.b.port_over_current_change);
3052 #ifdef DEBUG
3053         if (retval) {
3054                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3055                             " Root port status changed\n");
3056                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
3057                             hcd->flags.b.port_connect_status_change);
3058                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
3059                             hcd->flags.b.port_reset_change);
3060                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
3061                             hcd->flags.b.port_enable_change);
3062                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
3063                             hcd->flags.b.port_suspend_change);
3064                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
3065                             hcd->flags.b.port_over_current_change);
3066         }
3067 #endif
3068         return retval;
3069 }
3070
3071 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3072 {
3073         hfnum_data_t hfnum;
3074         hfnum.d32 =
3075             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3076                            host_global_regs->hfnum);
3077
3078 #ifdef DEBUG_SOF
3079         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3080                     hfnum.b.frnum);
3081 #endif
3082         return hfnum.b.frnum;
3083 }
3084
3085 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3086                       struct dwc_otg_hcd_function_ops *fops)
3087 {
3088         int retval = 0;
3089
3090         hcd->fops = fops;
3091         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3092             (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3093                 dwc_otg_hcd_reinit(hcd);
3094         } else {
3095                 retval = -DWC_E_NO_DEVICE;
3096         }
3097
3098         return retval;
3099 }
3100
3101 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3102 {
3103         return hcd->priv;
3104 }
3105
3106 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3107 {
3108         hcd->priv = priv_data;
3109 }
3110
3111 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3112 {
3113         return hcd->otg_port;
3114 }
3115
3116 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3117 {
3118         uint32_t is_b_host;
3119         if (hcd->core_if->op_state == B_HOST) {
3120                 is_b_host = 1;
3121         } else {
3122                 is_b_host = 0;
3123         }
3124
3125         return is_b_host;
3126 }
3127
3128 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3129                                          int iso_desc_count, int atomic_alloc)
3130 {
3131         dwc_otg_hcd_urb_t *dwc_otg_urb;
3132         uint32_t size;
3133
3134         size =
3135             sizeof(*dwc_otg_urb) +
3136             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3137         if (atomic_alloc)
3138                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3139         else
3140                 dwc_otg_urb = DWC_ALLOC(size);
3141
3142         dwc_otg_urb->packet_count = iso_desc_count;
3143
3144         return dwc_otg_urb;
3145 }
3146
3147 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3148                                   uint8_t dev_addr, uint8_t ep_num,
3149                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3150 {
3151         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3152                               ep_type, ep_dir, mps);
3153 #if 0
3154         DWC_PRINTF
3155             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3156              dev_addr, ep_num, ep_dir, ep_type, mps);
3157 #endif
3158 }
3159
3160 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3161                                 void *urb_handle, void *buf, dwc_dma_t dma,
3162                                 uint32_t buflen, void *setup_packet,
3163                                 dwc_dma_t setup_dma, uint32_t flags,
3164                                 uint16_t interval)
3165 {
3166         dwc_otg_urb->priv = urb_handle;
3167         dwc_otg_urb->buf = buf;
3168         dwc_otg_urb->dma = dma;
3169         dwc_otg_urb->length = buflen;
3170         dwc_otg_urb->setup_packet = setup_packet;
3171         dwc_otg_urb->setup_dma = setup_dma;
3172         dwc_otg_urb->flags = flags;
3173         dwc_otg_urb->interval = interval;
3174         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3175 }
3176
3177 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3178 {
3179         return dwc_otg_urb->status;
3180 }
3181
3182 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3183 {
3184         return dwc_otg_urb->actual_length;
3185 }
3186
3187 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3188 {
3189         return dwc_otg_urb->error_count;
3190 }
3191
3192 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3193                                          int desc_num, uint32_t offset,
3194                                          uint32_t length)
3195 {
3196         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3197         dwc_otg_urb->iso_descs[desc_num].length = length;
3198 }
3199
3200 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3201                                              int desc_num)
3202 {
3203         return dwc_otg_urb->iso_descs[desc_num].status;
3204 }
3205
3206 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3207                                                     dwc_otg_urb, int desc_num)
3208 {
3209         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3210 }
3211
3212 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3213 {
3214         int allocated = 0;
3215         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3216
3217         if (qh) {
3218                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3219                         allocated = 1;
3220                 }
3221         }
3222         return allocated;
3223 }
3224
3225 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3226 {
3227         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3228         int freed = 0;
3229         DWC_ASSERT(qh, "qh is not allocated\n");
3230
3231         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3232                 freed = 1;
3233         }
3234
3235         return freed;
3236 }
3237
3238 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3239 {
3240         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3241         DWC_ASSERT(qh, "qh is not allocated\n");
3242         return qh->usecs;
3243 }
3244
3245 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3246 {
3247 #ifdef DEBUG
3248         int num_channels;
3249         int i;
3250         gnptxsts_data_t np_tx_status;
3251         hptxsts_data_t p_tx_status;
3252
3253         num_channels = hcd->core_if->core_params->host_channels;
3254         DWC_PRINTF("\n");
3255         DWC_PRINTF
3256             ("************************************************************\n");
3257         DWC_PRINTF("HCD State:\n");
3258         DWC_PRINTF("  Num channels: %d\n", num_channels);
3259         for (i = 0; i < num_channels; i++) {
3260                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3261                 DWC_PRINTF("  Channel %d:\n", i);
3262                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3263                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3264                 DWC_PRINTF("    speed: %d\n", hc->speed);
3265                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3266                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3267                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3268                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3269                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3270                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3271                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3272                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3273                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3274                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3275                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3276                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3277                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3278                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3279                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3280                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3281                 DWC_PRINTF("    requests: %d\n", hc->requests);
3282                 DWC_PRINTF("    qh: %p\n", hc->qh);
3283                 if (hc->xfer_started) {
3284                         hfnum_data_t hfnum;
3285                         hcchar_data_t hcchar;
3286                         hctsiz_data_t hctsiz;
3287                         hcint_data_t hcint;
3288                         hcintmsk_data_t hcintmsk;
3289                         hfnum.d32 =
3290                             DWC_READ_REG32(&hcd->core_if->host_if->
3291                                            host_global_regs->hfnum);
3292                         hcchar.d32 =
3293                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3294                                            hcchar);
3295                         hctsiz.d32 =
3296                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3297                                            hctsiz);
3298                         hcint.d32 =
3299                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3300                                            hcint);
3301                         hcintmsk.d32 =
3302                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3303                                            hcintmsk);
3304                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3305                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3306                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3307                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3308                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3309                 }
3310                 if (hc->xfer_started && hc->qh) {
3311                         dwc_otg_qtd_t *qtd;
3312                         dwc_otg_hcd_urb_t *urb;
3313
3314                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3315                                             qtd_list_entry) {
3316                                 if (!qtd->in_process)
3317                                         break;
3318
3319                                 urb = qtd->urb;
3320                                 DWC_PRINTF("    URB Info:\n");
3321                                 DWC_PRINTF("      qtd: %p, urb: %p\n", qtd,
3322                                            urb);
3323                                 if (urb) {
3324                                         DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3325                                                    dwc_otg_hcd_get_dev_addr
3326                                                    (&urb->pipe_info),
3327                                                    dwc_otg_hcd_get_ep_num
3328                                                    (&urb->pipe_info),
3329                                                    dwc_otg_hcd_is_pipe_in
3330                                                    (&urb->pipe_info) ? "IN" :
3331                                                    "OUT");
3332                                         DWC_PRINTF
3333                                             ("      Max packet size: %d\n",
3334                                              dwc_otg_hcd_get_mps
3335                                              (&urb->pipe_info));
3336                                         DWC_PRINTF
3337                                             ("      transfer_buffer: %p\n",
3338                                              urb->buf);
3339                                         DWC_PRINTF("      transfer_dma: %p\n",
3340                                                    (void *)urb->dma);
3341                                         DWC_PRINTF
3342                                             ("      transfer_buffer_length: %d\n",
3343                                              urb->length);
3344                                         DWC_PRINTF("      actual_length: %d\n",
3345                                                    urb->actual_length);
3346                                 }
3347                         }
3348                 }
3349         }
3350         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3351         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3352         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3353         np_tx_status.d32 =
3354             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3355         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3356                    np_tx_status.b.nptxqspcavail);
3357         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3358                    np_tx_status.b.nptxfspcavail);
3359         p_tx_status.d32 =
3360             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3361         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3362                    p_tx_status.b.ptxqspcavail);
3363         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3364         dwc_otg_hcd_dump_frrem(hcd);
3365         dwc_otg_dump_global_registers(hcd->core_if);
3366         dwc_otg_dump_host_registers(hcd->core_if);
3367         DWC_PRINTF
3368             ("************************************************************\n");
3369         DWC_PRINTF("\n");
3370 #endif
3371 }
3372
3373 #ifdef DEBUG
3374 void dwc_print_setup_data(uint8_t *setup)
3375 {
3376         int i;
3377         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3378                 DWC_PRINTF("Setup Data = MSB ");
3379                 for (i = 7; i >= 0; i--)
3380                         DWC_PRINTF("%02x ", setup[i]);
3381                 DWC_PRINTF("\n");
3382                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3383                            (setup[0] & 0x80) ? "Device-to-Host" :
3384                            "Host-to-Device");
3385                 DWC_PRINTF("  bmRequestType Type = ");
3386                 switch ((setup[0] & 0x60) >> 5) {
3387                 case 0:
3388                         DWC_PRINTF("Standard\n");
3389                         break;
3390                 case 1:
3391                         DWC_PRINTF("Class\n");
3392                         break;
3393                 case 2:
3394                         DWC_PRINTF("Vendor\n");
3395                         break;
3396                 case 3:
3397                         DWC_PRINTF("Reserved\n");
3398                         break;
3399                 }
3400                 DWC_PRINTF("  bmRequestType Recipient = ");
3401                 switch (setup[0] & 0x1f) {
3402                 case 0:
3403                         DWC_PRINTF("Device\n");
3404                         break;
3405                 case 1:
3406                         DWC_PRINTF("Interface\n");
3407                         break;
3408                 case 2:
3409                         DWC_PRINTF("Endpoint\n");
3410                         break;
3411                 case 3:
3412                         DWC_PRINTF("Other\n");
3413                         break;
3414                 default:
3415                         DWC_PRINTF("Reserved\n");
3416                         break;
3417                 }
3418                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3419                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3420                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3421                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3422         }
3423 }
3424 #endif
3425
3426 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3427 {
3428 #if 0
3429         DWC_PRINTF("Frame remaining at SOF:\n");
3430         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3431                    hcd->frrem_samples, hcd->frrem_accum,
3432                    (hcd->frrem_samples > 0) ?
3433                    hcd->frrem_accum / hcd->frrem_samples : 0);
3434
3435         DWC_PRINTF("\n");
3436         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3437         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3438                    hcd->core_if->hfnum_7_samples,
3439                    hcd->core_if->hfnum_7_frrem_accum,
3440                    (hcd->core_if->hfnum_7_samples >
3441                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3442                    hcd->core_if->hfnum_7_samples : 0);
3443         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3444         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3445                    hcd->core_if->hfnum_0_samples,
3446                    hcd->core_if->hfnum_0_frrem_accum,
3447                    (hcd->core_if->hfnum_0_samples >
3448                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3449                    hcd->core_if->hfnum_0_samples : 0);
3450         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3451         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3452                    hcd->core_if->hfnum_other_samples,
3453                    hcd->core_if->hfnum_other_frrem_accum,
3454                    (hcd->core_if->hfnum_other_samples >
3455                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3456                    hcd->core_if->hfnum_other_samples : 0);
3457
3458         DWC_PRINTF("\n");
3459         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3460         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3461                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3462                    (hcd->hfnum_7_samples_a > 0) ?
3463                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3464         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3465         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3466                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3467                    (hcd->hfnum_0_samples_a > 0) ?
3468                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3469         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3470         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3471                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3472                    (hcd->hfnum_other_samples_a > 0) ?
3473                    hcd->hfnum_other_frrem_accum_a /
3474                    hcd->hfnum_other_samples_a : 0);
3475
3476         DWC_PRINTF("\n");
3477         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3478         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3479                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3480                    (hcd->hfnum_7_samples_b > 0) ?
3481                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3482         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3483         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3484                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3485                    (hcd->hfnum_0_samples_b > 0) ?
3486                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3487         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3488         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3489                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3490                    (hcd->hfnum_other_samples_b > 0) ?
3491                    hcd->hfnum_other_frrem_accum_b /
3492                    hcd->hfnum_other_samples_b : 0);
3493 #endif
3494 }
3495
3496 #endif /* DWC_DEVICE_ONLY */