drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t *hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_SHUTDOWN);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         }
 183
 184                 }
 185         }
 186 }
 187
 188 /**
 189  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 190  * and periodic schedules. The QTD associated with each URB is removed from
 191  * the schedule and freed. This function may be called when a disconnect is
 192  * detected or when the HCD is being stopped.
 193  */
 194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
 195 {
 196         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 197         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 198         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 202 }
 203
 204 /**
 205  * Start the connection timer.  An OTG host is required to display a
 206  * message if the device does not connect within 10 seconds.  The
 207  * timer is deleted if a port connect interrupt occurs before the
 208  * timer expires.
 209  */
 210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
 211 {
 212         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
 213 }
 214
 215 /**
 216  * HCD Callback function for disconnect of the HCD.
 217  *
 218  * @param p void pointer to the <code>struct usb_hcd</code>
 219  */
 220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 221 {
 222         dwc_otg_hcd_t *dwc_otg_hcd;
 223         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 224         dwc_otg_hcd = p;
 225         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 226         return 1;
 227 }
 228
 229 /**
 230  * HCD Callback function for starting the HCD when A-Cable is
 231  * connected.
 232  *
 233  * @param p void pointer to the <code>struct usb_hcd</code>
 234  */
 235 static int32_t dwc_otg_hcd_start_cb(void *p)
 236 {
 237         dwc_otg_hcd_t *dwc_otg_hcd = p;
 238         dwc_otg_core_if_t *core_if;
 239         hprt0_data_t hprt0;
 240         uint32_t timeout = 50;
 241
 242         core_if = dwc_otg_hcd->core_if;
 243
 244         if (core_if->op_state == B_HOST) {
 245                 /*
 246                  * Reset the port.  During a HNP mode switch the reset
 247                  * needs to occur within 1ms and have a duration of at
 248                  * least 50ms.
 249                  */
 250                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 251                 hprt0.b.prtrst = 1;
 252                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 253                 if (core_if->otg_ver) {
 254                         dwc_mdelay(60);
 255                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 256                         hprt0.b.prtrst = 0;
 257                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 258                 }
 259         }
 260         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 261         if (core_if->otg_ver)
 262                 timeout = 25;
 263         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 264                                    hcd_start_func, dwc_otg_hcd, timeout,
 265                                    "start hcd");
 266
 267         return 1;
 268 }
 269
 270 /**
 271  * HCD Callback function for disconnect of the HCD.
 272  *
 273  * @param p void pointer to the <code>struct usb_hcd</code>
 274  */
 275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 276 {
 277         gintsts_data_t intr;
 278         dwc_otg_hcd_t *dwc_otg_hcd = p;
 279
 280         /*
 281          * Set status flags for the hub driver.
 282          */
 283         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 284         dwc_otg_hcd->flags.b.port_connect_status = 0;
 285
 286         /*
 287          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 288          * interrupt mask and status bits and disabling subsequent host
 289          * channel interrupts.
 290          */
 291         intr.d32 = 0;
 292         intr.b.nptxfempty = 1;
 293         intr.b.ptxfempty = 1;
 294         intr.b.hcintr = 1;
 295         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 296                          intr.d32, 0);
 297         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 298                          intr.d32, 0);
 299
 300         /*
 301          * Turn off the vbus power only if the core has transitioned to device
 302          * mode. If still in host mode, need to keep power on to detect a
 303          * reconnection.
 304          */
 305         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 306                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 307                         hprt0_data_t hprt0 = {.d32 = 0 };
 308                         DWC_PRINTF("Disconnect: PortPower off\n");
 309                         hprt0.b.prtpwr = 0;
 310                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 311                                         hprt0.d32);
 312                 }
 313                 /** Delete timers if become device */
 314                 del_timers(dwc_otg_hcd);
 315                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 316         }
 317
 318         /* Respond with an error status to all URBs in the schedule. */
 319         kill_all_urbs(dwc_otg_hcd);
 320
 321         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 322                 /* Clean up any host channels that were in use. */
 323                 int num_channels;
 324                 int i;
 325                 dwc_hc_t *channel;
 326                 dwc_otg_hc_regs_t *hc_regs;
 327                 hcchar_data_t hcchar;
 328
 329                 DWC_PRINTF("Disconnect cb-Host\n");
 330                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 331                         del_xfer_timers(dwc_otg_hcd);
 332                 else
 333                         del_timers(dwc_otg_hcd);
 334
 335                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 336
 337                 if (!dwc_otg_hcd->core_if->dma_enable) {
 338                         /* Flush out any channel requests in slave mode. */
 339                         for (i = 0; i < num_channels; i++) {
 340                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 341                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 342                                     (channel, hc_list_entry)) {
 343                                         hc_regs =
 344                                             dwc_otg_hcd->core_if->host_if->
 345                                             hc_regs[i];
 346                                         hcchar.d32 =
 347                                             DWC_READ_REG32(&hc_regs->hcchar);
 348                                         if (hcchar.b.chen) {
 349                                                 hcchar.b.chen = 0;
 350                                                 hcchar.b.chdis = 1;
 351                                                 hcchar.b.epdir = 0;
 352                                                 DWC_WRITE_REG32
 353                                                     (&hc_regs->hcchar,
 354                                                      hcchar.d32);
 355                                         }
 356                                 }
 357                         }
 358                 }
 359
 360                 for (i = 0; i < num_channels; i++) {
 361                         channel = dwc_otg_hcd->hc_ptr_array[i];
 362                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 363                                 hc_regs =
 364                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 365                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 366                                 if (hcchar.b.chen) {
 367                                         /* Halt the channel. */
 368                                         hcchar.b.chdis = 1;
 369                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 370                                                         hcchar.d32);
 371                                 }
 372
 373                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 374                                                    channel);
 375                                 DWC_CIRCLEQ_INSERT_TAIL
 376                                     (&dwc_otg_hcd->free_hc_list, channel,
 377                                      hc_list_entry);
 378                                 /*
 379                                  * Added for Descriptor DMA to prevent channel double cleanup
 380                                  * in release_channel_ddma(). Which called from ep_disable
 381                                  * when device disconnect.
 382                                  */
 383                                 channel->qh = NULL;
 384                         }
 385                 }
 386         }
 387
 388         if (dwc_otg_hcd->fops->disconnect) {
 389                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 390         }
 391
 392         return 1;
 393 }
 394
 395 /**
 396  * HCD Callback function for stopping the HCD.
 397  *
 398  * @param p void pointer to the <code>struct usb_hcd</code>
 399  */
 400 static int32_t dwc_otg_hcd_stop_cb(void *p)
 401 {
 402         dwc_otg_hcd_t *dwc_otg_hcd = p;
 403
 404         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 405         dwc_otg_hcd_stop(dwc_otg_hcd);
 406         return 1;
 407 }
 408
 409 #ifdef CONFIG_USB_DWC_OTG_LPM
 410 /**
 411  * HCD Callback function for sleep of HCD.
 412  *
 413  * @param p void pointer to the <code>struct usb_hcd</code>
 414  */
 415 static int dwc_otg_hcd_sleep_cb(void *p)
 416 {
 417         dwc_otg_hcd_t *hcd = p;
 418
 419         dwc_otg_hcd_free_hc_from_lpm(hcd);
 420
 421         return 0;
 422 }
 423 #endif
 424
 425 /**
 426  * HCD Callback function for Remote Wakeup.
 427  *
 428  * @param p void pointer to the <code>struct usb_hcd</code>
 429  */
 430 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd);
 431 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 432 {
 433         dwc_otg_hcd_t *dwc_otg_hcd = p;
 434         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 435
 436         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 437                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 438                 usb_hcd_resume_root_hub(hcd);
 439         }
 440 #ifdef CONFIG_USB_DWC_OTG_LPM
 441         else {
 442                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 443         }
 444 #endif
 445         return 0;
 446 }
 447
 448 /**
 449  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 450  * stopped.
 451  */
 452 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
 453 {
 454         hprt0_data_t hprt0 = {.d32 = 0 };
 455         struct dwc_otg_platform_data *pldata;
 456         pldata = hcd->core_if->otg_dev->pldata;
 457
 458         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 459
 460         /*
 461          * The root hub should be disconnected before this function is called.
 462          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 463          * and the QH lists (via ..._hcd_endpoint_disable).
 464          */
 465
 466         /* Turn off all host-specific interrupts. */
 467         dwc_otg_disable_host_interrupts(hcd->core_if);
 468
 469         /* Turn off the vbus power */
 470         DWC_PRINTF("PortPower off\n");
 471         hprt0.b.prtpwr = 0;
 472         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 473
 474         if (pldata->power_enable)
 475                 pldata->power_enable(0);
 476
 477         dwc_mdelay(1);
 478 }
 479
 480 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
 481                             dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
 482                             int atomic_alloc)
 483 {
 484         dwc_irqflags_t flags;
 485         int retval = 0;
 486         dwc_otg_qtd_t *qtd;
 487         gintmsk_data_t intr_mask = {.d32 = 0 };
 488
 489         if (!hcd->flags.b.port_connect_status) {
 490                 /* No longer connected. */
 491                 DWC_DEBUG("Not connected\n");
 492                 return -DWC_E_NO_DEVICE;
 493         }
 494
 495         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 496         if (qtd == NULL) {
 497                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 498                 return -DWC_E_NO_MEMORY;
 499         }
 500
 501         retval =
 502             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle,
 503                                 atomic_alloc);
 504
 505         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 506         if (retval < 0) {
 507                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 508                           "Error status %d\n", retval);
 509                 dwc_otg_hcd_qtd_free(qtd);
 510         }
 511         intr_mask.d32 =
 512             DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 513         if (!intr_mask.b.sofintr && retval == 0) {
 514                 dwc_otg_transaction_type_e tr_type;
 515                 if ((qtd->qh->ep_type == UE_BULK)
 516                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 517                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 518                         retval = 0;
 519                         goto out;
 520                 }
 521                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 522                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 523                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 524                 }
 525         }
 526 out:
 527         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 528         return retval;
 529 }
 530
 531 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
 532                             dwc_otg_hcd_urb_t *dwc_otg_urb)
 533 {
 534         dwc_otg_qh_t *qh;
 535         dwc_otg_qtd_t *urb_qtd;
 536
 537         urb_qtd = dwc_otg_urb->qtd;
 538         if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
 539                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 540                            __func__, urb_qtd, dwc_otg_urb);
 541                 return 0;
 542         }
 543         qh = urb_qtd->qh;
 544 #ifdef DEBUG
 545         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 546                 if (urb_qtd->in_process) {
 547                         dump_channel_info(hcd, qh);
 548                 }
 549         }
 550 #endif
 551         if (urb_qtd->in_process && qh->channel) {
 552                 /* The QTD is in process (it has been assigned to a channel). */
 553                 if (hcd->flags.b.port_connect_status) {
 554                         /*
 555                          * If still connected (i.e. in host mode), halt the
 556                          * channel so it can be used for other transfers. If
 557                          * no longer connected, the host registers can't be
 558                          * written to halt the channel since the core is in
 559                          * device mode.
 560                          */
 561                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 562                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 563                 }
 564         }
 565
 566         /*
 567          * Free the QTD and clean up the associated QH. Leave the QH in the
 568          * schedule if it has any remaining QTDs.
 569          */
 570
 571         if (!hcd->core_if->dma_desc_enable) {
 572                 uint8_t b = urb_qtd->in_process;
 573                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 574                 if (b) {
 575                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 576                         qh->channel = NULL;
 577                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 578                         dwc_otg_hcd_qh_remove(hcd, qh);
 579                 }
 580         } else {
 581                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 582         }
 583         return 0;
 584 }
 585
 586 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
 587                                  int retry)
 588 {
 589         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 590         int retval = 0;
 591         dwc_irqflags_t flags;
 592
 593         if (retry < 0) {
 594                 retval = -DWC_E_INVALID;
 595                 goto done;
 596         }
 597
 598         if (!qh) {
 599                 retval = -DWC_E_INVALID;
 600                 goto done;
 601         }
 602
 603         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 604
 605         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 606                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 607                 retry--;
 608                 dwc_msleep(5);
 609                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 610         }
 611
 612         dwc_otg_hcd_qh_remove(hcd, qh);
 613
 614         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 615         /*
 616          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 617          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 618          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 619          * and dwc_otg_hcd_frame_list_alloc().
 620          */
 621         dwc_otg_hcd_qh_free(hcd, qh);
 622
 623 done:
 624         return retval;
 625 }
 626
 627 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
 628 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
 629 {
 630         int retval = 0;
 631         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 632         if (!qh)
 633                 return -DWC_E_INVALID;
 634
 635         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 636         return retval;
 637 }
 638 #endif
 639
 640 /**
 641  * HCD Callback structure for handling mode switching.
 642  */
 643 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 644         .start = dwc_otg_hcd_start_cb,
 645         .stop = dwc_otg_hcd_stop_cb,
 646         .disconnect = dwc_otg_hcd_disconnect_cb,
 647         .session_start = dwc_otg_hcd_session_start_cb,
 648         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 649 #ifdef CONFIG_USB_DWC_OTG_LPM
 650         .sleep = dwc_otg_hcd_sleep_cb,
 651 #endif
 652         .p = 0,
 653 };
 654
 655 /**
 656  * Reset tasklet function
 657  */
 658 static void reset_tasklet_func(void *data)
 659 {
 660         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 661         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 662         hprt0_data_t hprt0;
 663
 664         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 665
 666         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 667         hprt0.b.prtrst = 1;
 668         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 669         dwc_mdelay(60);
 670
 671         hprt0.b.prtrst = 0;
 672         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 673         dwc_otg_hcd->flags.b.port_reset_change = 1;
 674 }
 675
 676 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 677 {
 678         dwc_list_link_t *item;
 679         dwc_otg_qh_t *qh;
 680         dwc_irqflags_t flags;
 681
 682         if (!qh_list->next) {
 683                 /* The list hasn't been initialized yet. */
 684                 return;
 685         }
 686         /*
 687          * Hold spinlock here. Not needed in that case if bellow
 688          * function is being called from ISR
 689          */
 690         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 691         /* Ensure there are no QTDs or URBs left. */
 692         kill_urbs_in_qh_list(hcd, qh_list);
 693         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 694
 695         DWC_LIST_FOREACH(item, qh_list) {
 696                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 697                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 698         }
 699 }
 700
 701 /**
 702  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 703  * Device during SRP time by host power up.
 704  */
 705 void dwc_otg_hcd_power_up(void *ptr)
 706 {
 707         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 708         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 709
 710         DWC_PRINTF("%s called\n", __FUNCTION__);
 711
 712         if (!core_if->hibernation_suspend) {
 713                 DWC_PRINTF("Already exited from Hibernation\n");
 714                 return;
 715         }
 716
 717         /* Switch on the voltage to the core */
 718         gpwrdn.b.pwrdnswtch = 1;
 719         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 720         dwc_udelay(10);
 721
 722         /* Reset the core */
 723         gpwrdn.d32 = 0;
 724         gpwrdn.b.pwrdnrstn = 1;
 725         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 726         dwc_udelay(10);
 727
 728         /* Disable power clamps */
 729         gpwrdn.d32 = 0;
 730         gpwrdn.b.pwrdnclmp = 1;
 731         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 732
 733         /* Remove reset the core signal */
 734         gpwrdn.d32 = 0;
 735         gpwrdn.b.pwrdnrstn = 1;
 736         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 737         dwc_udelay(10);
 738
 739         /* Disable PMU interrupt */
 740         gpwrdn.d32 = 0;
 741         gpwrdn.b.pmuintsel = 1;
 742         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 743
 744         core_if->hibernation_suspend = 0;
 745
 746         /* Disable PMU */
 747         gpwrdn.d32 = 0;
 748         gpwrdn.b.pmuactv = 1;
 749         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 750         dwc_udelay(10);
 751
 752         /* Enable VBUS */
 753         gpwrdn.d32 = 0;
 754         gpwrdn.b.dis_vbus = 1;
 755         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 756
 757         core_if->op_state = A_HOST;
 758         dwc_otg_core_init(core_if);
 759         dwc_otg_enable_global_interrupts(core_if);
 760         cil_hcd_start(core_if);
 761 }
 762
 763 /**
 764  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 765  * in the struct usb_hcd field.
 766  */
 767 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
 768 {
 769         int i;
 770
 771         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 772
 773         del_timers(dwc_otg_hcd);
 774
 775         /* Free memory for QH/QTD lists */
 776         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 777         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 778         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 779         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 780         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 781         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 782
 783         /* Free memory for the host channels. */
 784         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 785                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 786
 787 #ifdef DEBUG
 788                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 789                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 790                 }
 791 #endif
 792                 if (hc != NULL) {
 793                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 794                                     i, hc);
 795                         DWC_FREE(hc);
 796                 }
 797         }
 798
 799         if (dwc_otg_hcd->core_if->dma_enable) {
 800                 if (dwc_otg_hcd->status_buf_dma) {
 801                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 802                                      dwc_otg_hcd->status_buf,
 803                                      dwc_otg_hcd->status_buf_dma);
 804                 }
 805         } else if (dwc_otg_hcd->status_buf != NULL) {
 806                 DWC_FREE(dwc_otg_hcd->status_buf);
 807         }
 808         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 809         /* Set core_if's lock pointer to NULL */
 810         dwc_otg_hcd->core_if->lock = NULL;
 811
 812         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 813         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 814
 815 #ifdef DWC_DEV_SRPCAP
 816         if (dwc_otg_hcd->core_if->power_down == 2 &&
 817             dwc_otg_hcd->core_if->pwron_timer) {
 818                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 819         }
 820 #endif
 821         DWC_FREE(dwc_otg_hcd);
 822 }
 823
 824 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 825 {
 826         int retval = 0;
 827         int num_channels;
 828         int i;
 829         dwc_hc_t *channel;
 830
 831         hcd->lock = DWC_SPINLOCK_ALLOC();
 832         if (!hcd->lock) {
 833                 DWC_ERROR("Could not allocate lock for pcd");
 834                 DWC_FREE(hcd);
 835                 retval = -DWC_E_NO_MEMORY;
 836                 goto out;
 837         }
 838         hcd->core_if = core_if;
 839
 840         /* Register the HCD CIL Callbacks */
 841         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 842                                            &hcd_cil_callbacks, hcd);
 843
 844         /* Initialize the non-periodic schedule. */
 845         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 846         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 847
 848         /* Initialize the periodic schedule. */
 849         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 850         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 851         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 852         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 853
 854         /*
 855          * Create a host channel descriptor for each host channel implemented
 856          * in the controller. Initialize the channel descriptor array.
 857          */
 858         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 859         num_channels = hcd->core_if->core_params->host_channels;
 860         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 861         for (i = 0; i < num_channels; i++) {
 862                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 863                 if (channel == NULL) {
 864                         retval = -DWC_E_NO_MEMORY;
 865                         DWC_ERROR("%s: host channel allocation failed\n",
 866                                   __func__);
 867                         dwc_otg_hcd_free(hcd);
 868                         goto out;
 869                 }
 870                 channel->hc_num = i;
 871                 hcd->hc_ptr_array[i] = channel;
 872 #ifdef DEBUG
 873                 hcd->core_if->hc_xfer_timer[i] =
 874                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 875                                     &hcd->core_if->hc_xfer_info[i]);
 876 #endif
 877                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 878                             channel);
 879         }
 880
 881         /* Initialize the Connection timeout timer. */
 882         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 883                                           dwc_otg_hcd_connect_timeout, hcd);
 884
 885         /* Initialize reset tasklet. */
 886         hcd->reset_tasklet =
 887             DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 888 #ifdef DWC_DEV_SRPCAP
 889         if (hcd->core_if->power_down == 2) {
 890                 /* Initialize Power on timer for Host power up in case hibernation */
 891                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 892                                                             dwc_otg_hcd_power_up,
 893                                                             core_if);
 894         }
 895 #endif
 896
 897         /*
 898          * Allocate space for storing data on status transactions. Normally no
 899          * data is sent, but this space acts as a bit bucket. This must be
 900          * done after usb_add_hcd since that function allocates the DMA buffer
 901          * pool.
 902          */
 903         if (hcd->core_if->dma_enable) {
 904                 hcd->status_buf =
 905                     DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 906                                          &hcd->status_buf_dma);
 907         } else {
 908                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 909         }
 910         if (!hcd->status_buf) {
 911                 retval = -DWC_E_NO_MEMORY;
 912                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 913                 dwc_otg_hcd_free(hcd);
 914                 goto out;
 915         }
 916
 917         hcd->otg_port = 1;
 918         hcd->frame_list = NULL;
 919         hcd->frame_list_dma = 0;
 920         hcd->periodic_qh_count = 0;
 921 out:
 922         return retval;
 923 }
 924
 925 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
 926 {
 927         /* Turn off all host-specific interrupts. */
 928         dwc_otg_disable_host_interrupts(hcd->core_if);
 929
 930         dwc_otg_hcd_free(hcd);
 931 }
 932
 933 /**
 934  * Initializes dynamic portions of the DWC_otg HCD state.
 935  */
 936 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
 937 {
 938         int num_channels;
 939         int i;
 940         dwc_hc_t *channel;
 941         dwc_hc_t *channel_tmp;
 942
 943         hcd->flags.d32 = 0;
 944
 945         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 946         hcd->non_periodic_channels = 0;
 947         hcd->periodic_channels = 0;
 948
 949         /*
 950          * Put all channels in the free channel list and clean up channel
 951          * states.
 952          */
 953         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 954                                  &hcd->free_hc_list, hc_list_entry) {
 955                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 956         }
 957
 958         num_channels = hcd->core_if->core_params->host_channels;
 959         for (i = 0; i < num_channels; i++) {
 960                 channel = hcd->hc_ptr_array[i];
 961                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 962                                         hc_list_entry);
 963                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 964         }
 965
 966         /* Initialize the DWC core for host mode operation. */
 967         dwc_otg_core_host_init(hcd->core_if);
 968
 969         /* Set core_if's lock pointer to the hcd->lock */
 970         hcd->core_if->lock = hcd->lock;
 971 }
 972
 973 /**
 974  * Assigns transactions from a QTD to a free host channel and initializes the
 975  * host channel to perform the transactions. The host channel is removed from
 976  * the free list.
 977  *
 978  * @param hcd The HCD state structure.
 979  * @param qh Transactions from the first QTD for this QH are selected and
 980  * assigned to a free host channel.
 981  */
 982 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 983 {
 984         dwc_hc_t *hc;
 985         dwc_otg_qtd_t *qtd;
 986         dwc_otg_hcd_urb_t *urb;
 987         void *ptr = NULL;
 988         int retval = 0;
 989
 990         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
 991
 992         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
 993
 994         /* Remove the host channel from the free list. */
 995         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
 996
 997         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 998
 999         urb = qtd->urb;
1000         if (urb == NULL) {
1001                 printk("%s : urb is NULL\n", __func__);
1002                 retval = -EINVAL;
1003                 return retval;
1004         }
1005
1006         qh->channel = hc;
1007
1008         qtd->in_process = 1;
1009
1010         /*
1011          * Use usb_pipedevice to determine device address. This address is
1012          * 0 before the SET_ADDRESS command and the correct address afterward.
1013          */
1014         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1015         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1016         hc->speed = qh->dev_speed;
1017         hc->max_packet = dwc_max_packet(qh->maxp);
1018
1019         hc->xfer_started = 0;
1020         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1021         hc->error_state = (qtd->error_count > 0);
1022         hc->halt_on_queue = 0;
1023         hc->halt_pending = 0;
1024         hc->requests = 0;
1025
1026         /*
1027          * The following values may be modified in the transfer type section
1028          * below. The xfer_len value may be reduced when the transfer is
1029          * started to accommodate the max widths of the XferSize and PktCnt
1030          * fields in the HCTSIZn register.
1031          */
1032
1033         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1034         if (hc->ep_is_in)
1035                 hc->do_ping = 0;
1036         else
1037                 hc->do_ping = qh->ping_state;
1038
1039         hc->data_pid_start = qh->data_toggle;
1040         hc->multi_count = 1;
1041
1042         if (hcd->core_if->dma_enable) {
1043                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1044
1045                 /* For non-dword aligned case */
1046                 if (((unsigned long)hc->xfer_buff & 0x3)
1047                     && !hcd->core_if->dma_desc_enable) {
1048                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1049                 }
1050         } else {
1051                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1052         }
1053         hc->xfer_len = urb->length - urb->actual_length;
1054         hc->xfer_count = 0;
1055
1056         /*
1057          * Set the split attributes
1058          */
1059         hc->do_split = 0;
1060         if (qh->do_split) {
1061                 uint32_t hub_addr, port_addr;
1062                 hc->do_split = 1;
1063                 hc->xact_pos = qtd->isoc_split_pos;
1064                 hc->complete_split = qtd->complete_split;
1065                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1066                 hc->hub_addr = (uint8_t) hub_addr;
1067                 hc->port_addr = (uint8_t) port_addr;
1068         }
1069
1070         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1071         case UE_CONTROL:
1072                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1073                 switch (qtd->control_phase) {
1074                 case DWC_OTG_CONTROL_SETUP:
1075                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1076                         hc->do_ping = 0;
1077                         hc->ep_is_in = 0;
1078                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1079                         if (hcd->core_if->dma_enable)
1080                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1081                         else
1082                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1083
1084                         hc->xfer_len = 8;
1085                         ptr = NULL;
1086                         break;
1087                 case DWC_OTG_CONTROL_DATA:
1088                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1089                         hc->data_pid_start = qtd->data_toggle;
1090                         break;
1091                 case DWC_OTG_CONTROL_STATUS:
1092                         /*
1093                          * Direction is opposite of data direction or IN if no
1094                          * data.
1095                          */
1096                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1097                         if (urb->length == 0) {
1098                                 hc->ep_is_in = 1;
1099                         } else {
1100                                 hc->ep_is_in =
1101                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1102                         }
1103                         if (hc->ep_is_in)
1104                                 hc->do_ping = 0;
1105
1106                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1107
1108                         hc->xfer_len = 0;
1109                         if (hcd->core_if->dma_enable)
1110                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1111                         else
1112                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1113
1114                         ptr = NULL;
1115                         break;
1116                 }
1117                 break;
1118         case UE_BULK:
1119                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1120                 break;
1121         case UE_INTERRUPT:
1122                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1123                 break;
1124         case UE_ISOCHRONOUS:
1125                 {
1126                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1127
1128                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1129
1130                         if (hcd->core_if->dma_desc_enable)
1131                                 break;
1132
1133                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1134
1135                         frame_desc->status = 0;
1136
1137                         if (hcd->core_if->dma_enable) {
1138                                 hc->xfer_buff = (uint8_t *) urb->dma;
1139                         } else {
1140                                 hc->xfer_buff = (uint8_t *) urb->buf;
1141                         }
1142                         hc->xfer_buff +=
1143                             frame_desc->offset + qtd->isoc_split_offset;
1144                         hc->xfer_len =
1145                             frame_desc->length - qtd->isoc_split_offset;
1146
1147                         /* For non-dword aligned buffers */
1148                         if (((unsigned long)hc->xfer_buff & 0x3)
1149                             && hcd->core_if->dma_enable) {
1150                                 ptr =
1151                                     (uint8_t *) urb->buf + frame_desc->offset +
1152                                     qtd->isoc_split_offset;
1153                         } else
1154                                 ptr = NULL;
1155
1156                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1157                                 if (hc->xfer_len <= 188) {
1158                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1159                                 } else {
1160                                         hc->xact_pos =
1161                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1162                                 }
1163                         }
1164                 }
1165                 break;
1166         }
1167         /* non DWORD-aligned buffer case */
1168         if (ptr) {
1169                 uint32_t buf_size;
1170                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1171                         buf_size = hcd->core_if->core_params->max_transfer_size;
1172                 } else {
1173                         buf_size = 4096;
1174                 }
1175                 if (!qh->dw_align_buf) {
1176                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1177                                                                 &qh->
1178                                                                 dw_align_buf_dma);
1179                         if (!qh->dw_align_buf) {
1180                                 DWC_ERROR
1181                                     ("%s: Failed to allocate memory to handle "
1182                                      "non-dword aligned buffer case\n",
1183                                      __func__);
1184                                 return retval;
1185                         }
1186                 }
1187                 if (!hc->ep_is_in) {
1188                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1189                 }
1190                 hc->align_buff = qh->dw_align_buf_dma;
1191         } else {
1192                 hc->align_buff = 0;
1193         }
1194
1195         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1196             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1197                 /*
1198                  * This value may be modified when the transfer is started to
1199                  * reflect the actual transfer length.
1200                  */
1201                 hc->multi_count = dwc_hb_mult(qh->maxp);
1202         }
1203
1204         if (hcd->core_if->dma_desc_enable)
1205                 hc->desc_list_addr = qh->desc_list_dma;
1206
1207         dwc_otg_hc_init(hcd->core_if, hc);
1208         hc->qh = qh;
1209         return retval;
1210 }
1211
1212 /**
1213  * This function selects transactions from the HCD transfer schedule and
1214  * assigns them to available host channels. It is called from HCD interrupt
1215  * handler functions.
1216  *
1217  * @param hcd The HCD state structure.
1218  *
1219  * @return The types of new transactions that were assigned to host channels.
1220  */
1221 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1222 {
1223         dwc_list_link_t *qh_ptr;
1224         dwc_otg_qh_t *qh;
1225         int num_channels;
1226         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1227         int err;
1228
1229 #ifdef DEBUG_SOF
1230         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1231 #endif
1232
1233         /* Process entries in the periodic ready list. */
1234         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1235
1236         while (qh_ptr != &hcd->periodic_sched_ready &&
1237                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1238
1239                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1240                 assign_and_init_hc(hcd, qh);
1241
1242                 /*
1243                  * Move the QH from the periodic ready schedule to the
1244                  * periodic assigned schedule.
1245                  */
1246                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1247                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1248                                    &qh->qh_list_entry);
1249
1250                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1251         }
1252
1253         /*
1254          * Process entries in the inactive portion of the non-periodic
1255          * schedule. Some free host channels may not be used if they are
1256          * reserved for periodic transfers.
1257          */
1258         qh_ptr = hcd->non_periodic_sched_inactive.next;
1259         num_channels = hcd->core_if->core_params->host_channels;
1260         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1261                (hcd->non_periodic_channels <
1262                 num_channels - hcd->periodic_channels) &&
1263                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1264
1265                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1266
1267                 err = assign_and_init_hc(hcd, qh);
1268
1269                 /*
1270                  * Move the QH from the non-periodic inactive schedule to the
1271                  * non-periodic active schedule.
1272                  */
1273                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1274                 if (err != 0)
1275                         continue;
1276                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1277                                    &qh->qh_list_entry);
1278
1279                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1280                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1281                 } else {
1282                         ret_val = DWC_OTG_TRANSACTION_ALL;
1283                 }
1284
1285                 hcd->non_periodic_channels++;
1286         }
1287
1288         return ret_val;
1289 }
1290
1291 /**
1292  * Attempts to queue a single transaction request for a host channel
1293  * associated with either a periodic or non-periodic transfer. This function
1294  * assumes that there is space available in the appropriate request queue. For
1295  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1296  * is available in the appropriate Tx FIFO.
1297  *
1298  * @param hcd The HCD state structure.
1299  * @param hc Host channel descriptor associated with either a periodic or
1300  * non-periodic transfer.
1301  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1302  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1303  * transfers.
1304  *
1305  * @return 1 if a request is queued and more requests may be needed to
1306  * complete the transfer, 0 if no more requests are required for this
1307  * transfer, -1 if there is insufficient space in the Tx FIFO.
1308  */
1309 static int queue_transaction(dwc_otg_hcd_t *hcd,
1310                              dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1311 {
1312         int retval;
1313
1314         if (hcd->core_if->dma_enable) {
1315                 if (hcd->core_if->dma_desc_enable) {
1316                         if (!hc->xfer_started
1317                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1318                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1319                                 hc->qh->ping_state = 0;
1320                         }
1321                 } else if (!hc->xfer_started) {
1322                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1323                         hc->qh->ping_state = 0;
1324                 }
1325                 retval = 0;
1326         } else if (hc->halt_pending) {
1327                 /* Don't queue a request if the channel has been halted. */
1328                 retval = 0;
1329         } else if (hc->halt_on_queue) {
1330                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1331                 retval = 0;
1332         } else if (hc->do_ping) {
1333                 if (!hc->xfer_started) {
1334                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1335                 }
1336                 retval = 0;
1337         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1338                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1339                         if (!hc->xfer_started) {
1340                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1341                                 retval = 1;
1342                         } else {
1343                                 retval =
1344                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1345                                                                  hc);
1346                         }
1347                 } else {
1348                         retval = -1;
1349                 }
1350         } else {
1351                 if (!hc->xfer_started) {
1352                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1353                         retval = 1;
1354                 } else {
1355                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1356                 }
1357         }
1358
1359         return retval;
1360 }
1361
1362 /**
1363  * Processes periodic channels for the next frame and queues transactions for
1364  * these channels to the DWC_otg controller. After queueing transactions, the
1365  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1366  * to queue as Periodic Tx FIFO or request queue space becomes available.
1367  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1368  */
1369 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1370 {
1371         hptxsts_data_t tx_status;
1372         dwc_list_link_t *qh_ptr;
1373         dwc_otg_qh_t *qh;
1374         int status;
1375         int no_queue_space = 0;
1376         int no_fifo_space = 0;
1377
1378         dwc_otg_host_global_regs_t *host_regs;
1379         host_regs = hcd->core_if->host_if->host_global_regs;
1380
1381         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1382 #ifdef DEBUG
1383         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1384         DWC_DEBUGPL(DBG_HCDV,
1385                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1386                     tx_status.b.ptxqspcavail);
1387         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1388                     tx_status.b.ptxfspcavail);
1389 #endif
1390
1391         qh_ptr = hcd->periodic_sched_assigned.next;
1392         while (qh_ptr != &hcd->periodic_sched_assigned) {
1393                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1394                 if (tx_status.b.ptxqspcavail == 0) {
1395                         no_queue_space = 1;
1396                         break;
1397                 }
1398
1399                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1400
1401                 /*
1402                  * Set a flag if we're queuing high-bandwidth in slave mode.
1403                  * The flag prevents any halts to get into the request queue in
1404                  * the middle of multiple high-bandwidth packets getting queued.
1405                  */
1406                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1407                         hcd->core_if->queuing_high_bandwidth = 1;
1408                 }
1409                 status =
1410                     queue_transaction(hcd, qh->channel,
1411                                       tx_status.b.ptxfspcavail);
1412                 if (status < 0) {
1413                         no_fifo_space = 1;
1414                         break;
1415                 }
1416
1417                 /*
1418                  * In Slave mode, stay on the current transfer until there is
1419                  * nothing more to do or the high-bandwidth request count is
1420                  * reached. In DMA mode, only need to queue one request. The
1421                  * controller automatically handles multiple packets for
1422                  * high-bandwidth transfers.
1423                  */
1424                 if (hcd->core_if->dma_enable || status == 0 ||
1425                     qh->channel->requests == qh->channel->multi_count) {
1426                         qh_ptr = qh_ptr->next;
1427                         /*
1428                          * Move the QH from the periodic assigned schedule to
1429                          * the periodic queued schedule.
1430                          */
1431                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1432                                            &qh->qh_list_entry);
1433
1434                         /* done queuing high bandwidth */
1435                         hcd->core_if->queuing_high_bandwidth = 0;
1436                 }
1437         }
1438
1439         if (!hcd->core_if->dma_enable) {
1440                 dwc_otg_core_global_regs_t *global_regs;
1441                 gintmsk_data_t intr_mask = {.d32 = 0 };
1442
1443                 global_regs = hcd->core_if->core_global_regs;
1444                 intr_mask.b.ptxfempty = 1;
1445 #ifdef DEBUG
1446                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1447                 DWC_DEBUGPL(DBG_HCDV,
1448                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1449                             tx_status.b.ptxqspcavail);
1450                 DWC_DEBUGPL(DBG_HCDV,
1451                             "  P Tx FIFO Space Avail (after queue): %d\n",
1452                             tx_status.b.ptxfspcavail);
1453 #endif
1454                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1455                     no_queue_space || no_fifo_space) {
1456                         /*
1457                          * May need to queue more transactions as the request
1458                          * queue or Tx FIFO empties. Enable the periodic Tx
1459                          * FIFO empty interrupt. (Always use the half-empty
1460                          * level to ensure that new requests are loaded as
1461                          * soon as possible.)
1462                          */
1463                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1464                                          intr_mask.d32);
1465                 } else {
1466                         /*
1467                          * Disable the Tx FIFO empty interrupt since there are
1468                          * no more transactions that need to be queued right
1469                          * now. This function is called from interrupt
1470                          * handlers to queue more transactions as transfer
1471                          * states change.
1472                          */
1473                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1474                                          0);
1475                 }
1476         }
1477 }
1478
1479 /**
1480  * Processes active non-periodic channels and queues transactions for these
1481  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1482  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1483  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1484  * FIFO Empty interrupt is disabled.
1485  */
1486 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1487 {
1488         gnptxsts_data_t tx_status;
1489         dwc_list_link_t *orig_qh_ptr;
1490         dwc_otg_qh_t *qh;
1491         int status;
1492         int no_queue_space = 0;
1493         int no_fifo_space = 0;
1494         int more_to_do = 0;
1495
1496         dwc_otg_core_global_regs_t *global_regs =
1497             hcd->core_if->core_global_regs;
1498
1499         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1500 #ifdef DEBUG
1501         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1502         DWC_DEBUGPL(DBG_HCDV,
1503                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1504                     tx_status.b.nptxqspcavail);
1505         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1506                     tx_status.b.nptxfspcavail);
1507 #endif
1508         /*
1509          * Keep track of the starting point. Skip over the start-of-list
1510          * entry.
1511          */
1512         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1513                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1514         }
1515         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1516
1517         /*
1518          * Process once through the active list or until no more space is
1519          * available in the request queue or the Tx FIFO.
1520          */
1521         do {
1522                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1523                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1524                         no_queue_space = 1;
1525                         break;
1526                 }
1527
1528                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1529                                     qh_list_entry);
1530                 status =
1531                     queue_transaction(hcd, qh->channel,
1532                                       tx_status.b.nptxfspcavail);
1533
1534                 if (status > 0) {
1535                         more_to_do = 1;
1536                 } else if (status < 0) {
1537                         no_fifo_space = 1;
1538                         break;
1539                 }
1540
1541                 /* Advance to next QH, skipping start-of-list entry. */
1542                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1543                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1544                         hcd->non_periodic_qh_ptr =
1545                             hcd->non_periodic_qh_ptr->next;
1546                 }
1547
1548         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1549
1550         if (!hcd->core_if->dma_enable) {
1551                 gintmsk_data_t intr_mask = {.d32 = 0 };
1552                 intr_mask.b.nptxfempty = 1;
1553
1554 #ifdef DEBUG
1555                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1556                 DWC_DEBUGPL(DBG_HCDV,
1557                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1558                             tx_status.b.nptxqspcavail);
1559                 DWC_DEBUGPL(DBG_HCDV,
1560                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1561                             tx_status.b.nptxfspcavail);
1562 #endif
1563                 if (more_to_do || no_queue_space || no_fifo_space) {
1564                         /*
1565                          * May need to queue more transactions as the request
1566                          * queue or Tx FIFO empties. Enable the non-periodic
1567                          * Tx FIFO empty interrupt. (Always use the half-empty
1568                          * level to ensure that new requests are loaded as
1569                          * soon as possible.)
1570                          */
1571                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1572                                          intr_mask.d32);
1573                 } else {
1574                         /*
1575                          * Disable the Tx FIFO empty interrupt since there are
1576                          * no more transactions that need to be queued right
1577                          * now. This function is called from interrupt
1578                          * handlers to queue more transactions as transfer
1579                          * states change.
1580                          */
1581                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1582                                          0);
1583                 }
1584         }
1585 }
1586
1587 /**
1588  * This function processes the currently active host channels and queues
1589  * transactions for these channels to the DWC_otg controller. It is called
1590  * from HCD interrupt handler functions.
1591  *
1592  * @param hcd The HCD state structure.
1593  * @param tr_type The type(s) of transactions to queue (non-periodic,
1594  * periodic, or both).
1595  */
1596 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1597                                     dwc_otg_transaction_type_e tr_type)
1598 {
1599 #ifdef DEBUG_SOF
1600         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1601 #endif
1602         /* Process host channels associated with periodic transfers. */
1603         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1604              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1605             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1606
1607                 process_periodic_channels(hcd);
1608         }
1609
1610         /* Process host channels associated with non-periodic transfers. */
1611         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1612             tr_type == DWC_OTG_TRANSACTION_ALL) {
1613                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1614                         process_non_periodic_channels(hcd);
1615                 } else {
1616                         /*
1617                          * Ensure NP Tx FIFO empty interrupt is disabled when
1618                          * there are no non-periodic transfers to process.
1619                          */
1620                         gintmsk_data_t gintmsk = {.d32 = 0 };
1621                         gintmsk.b.nptxfempty = 1;
1622                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1623                                          gintmsk, gintmsk.d32, 0);
1624                 }
1625         }
1626 }
1627
1628 #ifdef DWC_HS_ELECT_TST
1629 /*
1630  * Quick and dirty hack to implement the HS Electrical Test
1631  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1632  *
1633  * This code was copied from our userspace app "hset". It sends a
1634  * Get Device Descriptor control sequence in two parts, first the
1635  * Setup packet by itself, followed some time later by the In and
1636  * Ack packets. Rather than trying to figure out how to add this
1637  * functionality to the normal driver code, we just hijack the
1638  * hardware, using these two function to drive the hardware
1639  * directly.
1640  */
1641
1642 static dwc_otg_core_global_regs_t *global_regs;
1643 static dwc_otg_host_global_regs_t *hc_global_regs;
1644 static dwc_otg_hc_regs_t *hc_regs;
1645 static uint32_t *data_fifo;
1646
1647 static void do_setup(void)
1648 {
1649         gintsts_data_t gintsts;
1650         hctsiz_data_t hctsiz;
1651         hcchar_data_t hcchar;
1652         haint_data_t haint;
1653         hcint_data_t hcint;
1654
1655         /* Enable HAINTs */
1656         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1657
1658         /* Enable HCINTs */
1659         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1660
1661         /* Read GINTSTS */
1662         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1663
1664         /* Read HAINT */
1665         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1666
1667         /* Read HCINT */
1668         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1669
1670         /* Read HCCHAR */
1671         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1672
1673         /* Clear HCINT */
1674         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1675
1676         /* Clear HAINT */
1677         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1678
1679         /* Clear GINTSTS */
1680         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1681
1682         /* Read GINTSTS */
1683         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1684
1685         /*
1686          * Send Setup packet (Get Device Descriptor)
1687          */
1688
1689         /* Make sure channel is disabled */
1690         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1691         if (hcchar.b.chen) {
1692                 hcchar.b.chdis = 1;
1693                 /* hcchar.b.chen = 1; */
1694                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1695                 /* sleep(1); */
1696                 dwc_mdelay(1000);
1697
1698                 /* Read GINTSTS */
1699                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1700
1701                 /* Read HAINT */
1702                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1703
1704                 /* Read HCINT */
1705                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1706
1707                 /* Read HCCHAR */
1708                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1709
1710                 /* Clear HCINT */
1711                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1712
1713                 /* Clear HAINT */
1714                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1715
1716                 /* Clear GINTSTS */
1717                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1718
1719                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1720         }
1721
1722         /* Set HCTSIZ */
1723         hctsiz.d32 = 0;
1724         hctsiz.b.xfersize = 8;
1725         hctsiz.b.pktcnt = 1;
1726         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1727         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1728
1729         /* Set HCCHAR */
1730         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1731         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1732         hcchar.b.epdir = 0;
1733         hcchar.b.epnum = 0;
1734         hcchar.b.mps = 8;
1735         hcchar.b.chen = 1;
1736         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1737
1738         /* Fill FIFO with Setup data for Get Device Descriptor */
1739         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1740         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1741         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1742
1743         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1744
1745         /* Wait for host channel interrupt */
1746         do {
1747                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1748         } while (gintsts.b.hcintr == 0);
1749
1750         /* Disable HCINTs */
1751         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1752
1753         /* Disable HAINTs */
1754         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1755
1756         /* Read HAINT */
1757         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1758
1759         /* Read HCINT */
1760         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1761
1762         /* Read HCCHAR */
1763         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1764
1765         /* Clear HCINT */
1766         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1767
1768         /* Clear HAINT */
1769         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1770
1771         /* Clear GINTSTS */
1772         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1773
1774         /* Read GINTSTS */
1775         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1776 }
1777
1778 static void do_in_ack(void)
1779 {
1780         gintsts_data_t gintsts;
1781         hctsiz_data_t hctsiz;
1782         hcchar_data_t hcchar;
1783         haint_data_t haint;
1784         hcint_data_t hcint;
1785         host_grxsts_data_t grxsts;
1786
1787         /* Enable HAINTs */
1788         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1789
1790         /* Enable HCINTs */
1791         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1792
1793         /* Read GINTSTS */
1794         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1795
1796         /* Read HAINT */
1797         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1798
1799         /* Read HCINT */
1800         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1801
1802         /* Read HCCHAR */
1803         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1804
1805         /* Clear HCINT */
1806         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1807
1808         /* Clear HAINT */
1809         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1810
1811         /* Clear GINTSTS */
1812         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1813
1814         /* Read GINTSTS */
1815         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1816
1817         /*
1818          * Receive Control In packet
1819          */
1820
1821         /* Make sure channel is disabled */
1822         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1823         if (hcchar.b.chen) {
1824                 hcchar.b.chdis = 1;
1825                 hcchar.b.chen = 1;
1826                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1827                 /* sleep(1); */
1828                 dwc_mdelay(1000);
1829
1830                 /* Read GINTSTS */
1831                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1832
1833                 /* Read HAINT */
1834                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1835
1836                 /* Read HCINT */
1837                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1838
1839                 /* Read HCCHAR */
1840                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1841
1842                 /* Clear HCINT */
1843                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1844
1845                 /* Clear HAINT */
1846                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1847
1848                 /* Clear GINTSTS */
1849                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1850
1851                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1852         }
1853
1854         /* Set HCTSIZ */
1855         hctsiz.d32 = 0;
1856         hctsiz.b.xfersize = 8;
1857         hctsiz.b.pktcnt = 1;
1858         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1859         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1860
1861         /* Set HCCHAR */
1862         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1863         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1864         hcchar.b.epdir = 1;
1865         hcchar.b.epnum = 0;
1866         hcchar.b.mps = 8;
1867         hcchar.b.chen = 1;
1868         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1869
1870         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1871
1872         /* Wait for receive status queue interrupt */
1873         do {
1874                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1875         } while (gintsts.b.rxstsqlvl == 0);
1876
1877         /* Read RXSTS */
1878         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1879
1880         /* Clear RXSTSQLVL in GINTSTS */
1881         gintsts.d32 = 0;
1882         gintsts.b.rxstsqlvl = 1;
1883         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1884
1885         switch (grxsts.b.pktsts) {
1886         case DWC_GRXSTS_PKTSTS_IN:
1887                 /* Read the data into the host buffer */
1888                 if (grxsts.b.bcnt > 0) {
1889                         int i;
1890                         int word_count = (grxsts.b.bcnt + 3) / 4;
1891
1892                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1893
1894                         for (i = 0; i < word_count; i++) {
1895                                 (void)DWC_READ_REG32(data_fifo++);
1896                         }
1897                 }
1898                 break;
1899
1900         default:
1901                 break;
1902         }
1903
1904         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1905
1906         /* Wait for receive status queue interrupt */
1907         do {
1908                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1909         } while (gintsts.b.rxstsqlvl == 0);
1910
1911         /* Read RXSTS */
1912         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1913
1914         /* Clear RXSTSQLVL in GINTSTS */
1915         gintsts.d32 = 0;
1916         gintsts.b.rxstsqlvl = 1;
1917         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1918
1919         switch (grxsts.b.pktsts) {
1920         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1921                 break;
1922
1923         default:
1924                 break;
1925         }
1926
1927         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1928
1929         /* Wait for host channel interrupt */
1930         do {
1931                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1932         } while (gintsts.b.hcintr == 0);
1933
1934         /* Read HAINT */
1935         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1936
1937         /* Read HCINT */
1938         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1939
1940         /* Read HCCHAR */
1941         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1942
1943         /* Clear HCINT */
1944         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1945
1946         /* Clear HAINT */
1947         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1948
1949         /* Clear GINTSTS */
1950         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1951
1952         /* Read GINTSTS */
1953         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1954
1955         /* usleep(100000); */
1956         /* mdelay(100); */
1957         dwc_mdelay(1);
1958
1959         /*
1960          * Send handshake packet
1961          */
1962
1963         /* Read HAINT */
1964         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1965
1966         /* Read HCINT */
1967         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1968
1969         /* Read HCCHAR */
1970         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1971
1972         /* Clear HCINT */
1973         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1974
1975         /* Clear HAINT */
1976         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1977
1978         /* Clear GINTSTS */
1979         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1980
1981         /* Read GINTSTS */
1982         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1983
1984         /* Make sure channel is disabled */
1985         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1986         if (hcchar.b.chen) {
1987                 hcchar.b.chdis = 1;
1988                 hcchar.b.chen = 1;
1989                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1990                 /* sleep(1); */
1991                 dwc_mdelay(1000);
1992
1993                 /* Read GINTSTS */
1994                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1995
1996                 /* Read HAINT */
1997                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1998
1999                 /* Read HCINT */
2000                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2001
2002                 /* Read HCCHAR */
2003                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2004
2005                 /* Clear HCINT */
2006                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2007
2008                 /* Clear HAINT */
2009                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2010
2011                 /* Clear GINTSTS */
2012                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2013
2014                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2015         }
2016
2017         /* Set HCTSIZ */
2018         hctsiz.d32 = 0;
2019         hctsiz.b.xfersize = 0;
2020         hctsiz.b.pktcnt = 1;
2021         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2022         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2023
2024         /* Set HCCHAR */
2025         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2026         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2027         hcchar.b.epdir = 0;
2028         hcchar.b.epnum = 0;
2029         hcchar.b.mps = 8;
2030         hcchar.b.chen = 1;
2031         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2032
2033         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2034
2035         /* Wait for host channel interrupt */
2036         do {
2037                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2038         } while (gintsts.b.hcintr == 0);
2039
2040         /* Disable HCINTs */
2041         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2042
2043         /* Disable HAINTs */
2044         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2045
2046         /* Read HAINT */
2047         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2048
2049         /* Read HCINT */
2050         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2051
2052         /* Read HCCHAR */
2053         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2054
2055         /* Clear HCINT */
2056         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2057
2058         /* Clear HAINT */
2059         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2060
2061         /* Clear GINTSTS */
2062         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2063
2064         /* Read GINTSTS */
2065         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2066 }
2067 #endif
2068
2069 /** Handles hub class-specific requests. */
2070 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2071                             uint16_t typeReq,
2072                             uint16_t wValue,
2073                             uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2074 {
2075         int retval = 0;
2076
2077         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2078         usb_hub_descriptor_t *hub_desc;
2079         hprt0_data_t hprt0 = {.d32 = 0 };
2080
2081         uint32_t port_status;
2082
2083         switch (typeReq) {
2084         case UCR_CLEAR_HUB_FEATURE:
2085                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2086                             "ClearHubFeature 0x%x\n", wValue);
2087                 switch (wValue) {
2088                 case UHF_C_HUB_LOCAL_POWER:
2089                 case UHF_C_HUB_OVER_CURRENT:
2090                         /* Nothing required here */
2091                         break;
2092                 default:
2093                         retval = -DWC_E_INVALID;
2094                         DWC_ERROR("DWC OTG HCD - "
2095                                   "ClearHubFeature request %xh unknown\n",
2096                                   wValue);
2097                 }
2098                 break;
2099         case UCR_CLEAR_PORT_FEATURE:
2100 #ifdef CONFIG_USB_DWC_OTG_LPM
2101                 if (wValue != UHF_PORT_L1)
2102 #endif
2103                         if (!wIndex || wIndex > 1)
2104                                 goto error;
2105
2106                 switch (wValue) {
2107                 case UHF_PORT_ENABLE:
2108                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2109                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2110                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2111                         hprt0.b.prtena = 1;
2112                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2113                         break;
2114                 case UHF_PORT_SUSPEND:
2115                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2116                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2117
2118                         if (core_if->power_down == 2) {
2119                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2120                         } else {
2121                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2122                                 dwc_mdelay(5);
2123
2124                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2125                                 hprt0.b.prtres = 1;
2126                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2127                                                 hprt0.d32);
2128                                 hprt0.b.prtsusp = 0;
2129                                 /* Clear Resume bit */
2130                                 dwc_mdelay(100);
2131                                 hprt0.b.prtres = 0;
2132                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2133                                                 hprt0.d32);
2134                         }
2135                         break;
2136 #ifdef CONFIG_USB_DWC_OTG_LPM
2137                 case UHF_PORT_L1:
2138                         {
2139                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2140                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2141
2142                                 lpmcfg.d32 =
2143                                     DWC_READ_REG32(&core_if->core_global_regs->
2144                                                    glpmcfg);
2145                                 lpmcfg.b.en_utmi_sleep = 0;
2146                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2147                                 lpmcfg.b.prt_sleep_sts = 1;
2148                                 DWC_WRITE_REG32(&core_if->core_global_regs->
2149                                                 glpmcfg, lpmcfg.d32);
2150
2151                                 /* Clear Enbl_L1Gating bit. */
2152                                 pcgcctl.b.enbl_sleep_gating = 1;
2153                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2154                                                  0);
2155
2156                                 dwc_mdelay(5);
2157
2158                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2159                                 hprt0.b.prtres = 1;
2160                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2161                                                 hprt0.d32);
2162                                 /* This bit will be cleared in wakeup interrupt handle */
2163                                 break;
2164                         }
2165 #endif
2166                 case UHF_PORT_POWER:
2167                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2168                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2169                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2170                         hprt0.b.prtpwr = 0;
2171                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2172                         break;
2173                 case UHF_PORT_INDICATOR:
2174                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2175                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2176                         /* Port inidicator not supported */
2177                         break;
2178                 case UHF_C_PORT_CONNECTION:
2179                         /* Clears drivers internal connect status change
2180                          * flag */
2181                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2182                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2183                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2184                         break;
2185                 case UHF_C_PORT_RESET:
2186                         /* Clears the driver's internal Port Reset Change
2187                          * flag */
2188                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2189                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2190                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2191                         break;
2192                 case UHF_C_PORT_ENABLE:
2193                         /* Clears the driver's internal Port
2194                          * Enable/Disable Change flag */
2195                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2196                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2197                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2198                         break;
2199                 case UHF_C_PORT_SUSPEND:
2200                         /* Clears the driver's internal Port Suspend
2201                          * Change flag, which is set when resume signaling on
2202                          * the host port is complete */
2203                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2204                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2205                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2206                         break;
2207 #ifdef CONFIG_USB_DWC_OTG_LPM
2208                 case UHF_C_PORT_L1:
2209                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2210                         break;
2211 #endif
2212                 case UHF_C_PORT_OVER_CURRENT:
2213                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2214                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2215                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2216                         break;
2217                 default:
2218                         retval = -DWC_E_INVALID;
2219                         DWC_ERROR("DWC OTG HCD - "
2220                                   "ClearPortFeature request %xh "
2221                                   "unknown or unsupported\n", wValue);
2222                 }
2223                 break;
2224         case UCR_GET_HUB_DESCRIPTOR:
2225                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2226                             "GetHubDescriptor\n");
2227                 hub_desc = (usb_hub_descriptor_t *) buf;
2228                 hub_desc->bDescLength = 9;
2229                 hub_desc->bDescriptorType = 0x29;
2230                 hub_desc->bNbrPorts = 1;
2231                 USETW(hub_desc->wHubCharacteristics, 0x08);
2232                 hub_desc->bPwrOn2PwrGood = 1;
2233                 hub_desc->bHubContrCurrent = 0;
2234                 hub_desc->DeviceRemovable[0] = 0;
2235                 hub_desc->DeviceRemovable[1] = 0xff;
2236                 break;
2237         case UCR_GET_HUB_STATUS:
2238                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2239                             "GetHubStatus\n");
2240                 DWC_MEMSET(buf, 0, 4);
2241                 break;
2242         case UCR_GET_PORT_STATUS:
2243                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2244                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2245                             wIndex, dwc_otg_hcd->flags.d32);
2246                 if (!wIndex || wIndex > 1)
2247                         goto error;
2248
2249                 port_status = 0;
2250
2251                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2252                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2253
2254                 if (dwc_otg_hcd->flags.b.port_enable_change)
2255                         port_status |= (1 << UHF_C_PORT_ENABLE);
2256
2257                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2258                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2259
2260                 if (dwc_otg_hcd->flags.b.port_l1_change)
2261                         port_status |= (1 << UHF_C_PORT_L1);
2262
2263                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2264                         port_status |= (1 << UHF_C_PORT_RESET);
2265                 }
2266
2267                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2268                         DWC_WARN("Overcurrent change detected\n");
2269                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2270                 }
2271
2272                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2273                         /*
2274                          * The port is disconnected, which means the core is
2275                          * either in device mode or it soon will be. Just
2276                          * return 0's for the remainder of the port status
2277                          * since the port register can't be read if the core
2278                          * is in device mode.
2279                          */
2280                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2281                         break;
2282                 }
2283
2284                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2285                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2286
2287                 if (hprt0.b.prtconnsts)
2288                         port_status |= (1 << UHF_PORT_CONNECTION);
2289
2290                 if (hprt0.b.prtena)
2291                         port_status |= (1 << UHF_PORT_ENABLE);
2292
2293                 if (hprt0.b.prtsusp)
2294                         port_status |= (1 << UHF_PORT_SUSPEND);
2295
2296                 if (hprt0.b.prtovrcurract)
2297                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2298
2299                 if (hprt0.b.prtrst)
2300                         port_status |= (1 << UHF_PORT_RESET);
2301
2302                 if (hprt0.b.prtpwr)
2303                         port_status |= (1 << UHF_PORT_POWER);
2304
2305                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2306                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2307                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2308                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2309
2310                 if (hprt0.b.prttstctl)
2311                         port_status |= (1 << UHF_PORT_TEST);
2312                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2313                         port_status |= (1 << UHF_PORT_L1);
2314                 }
2315                 /*
2316                    For Synopsys HW emulation of Power down wkup_control asserts the
2317                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2318                    We intentionally tell the software that port is in L2Suspend state.
2319                    Only for STE.
2320                  */
2321                 if ((core_if->power_down == 2)
2322                     && (core_if->hibernation_suspend == 1)) {
2323                         port_status |= (1 << UHF_PORT_SUSPEND);
2324                 }
2325                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2326
2327                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2328
2329                 break;
2330         case UCR_SET_HUB_FEATURE:
2331                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2332                             "SetHubFeature\n");
2333                 /* No HUB features supported */
2334                 break;
2335         case UCR_SET_PORT_FEATURE:
2336                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2337                         goto error;
2338
2339                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2340                         /*
2341                          * The port is disconnected, which means the core is
2342                          * either in device mode or it soon will be. Just
2343                          * return without doing anything since the port
2344                          * register can't be written if the core is in device
2345                          * mode.
2346                          */
2347                         break;
2348                 }
2349
2350                 switch (wValue) {
2351                 case UHF_PORT_SUSPEND:
2352                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2353                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2354                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2355                                 goto error;
2356                         }
2357                         if (core_if->power_down == 2) {
2358                                 int timeout = 300;
2359                                 dwc_irqflags_t flags;
2360                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2361                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2362                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2363 #ifdef DWC_DEV_SRPCAP
2364                                 int32_t otg_cap_param =
2365                                     core_if->core_params->otg_cap;
2366 #endif
2367                                 DWC_PRINTF
2368                                     ("Preparing for complete power-off\n");
2369
2370                                 /* Save registers before hibernation */
2371                                 dwc_otg_save_global_regs(core_if);
2372                                 dwc_otg_save_host_regs(core_if);
2373
2374                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2375                                 hprt0.b.prtsusp = 1;
2376                                 hprt0.b.prtena = 0;
2377                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2378                                                 hprt0.d32);
2379                                 /* Spin hprt0.b.prtsusp to became 1 */
2380                                 do {
2381                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2382                                         if (hprt0.b.prtsusp) {
2383                                                 break;
2384                                         }
2385                                         dwc_mdelay(1);
2386                                 } while (--timeout);
2387                                 if (!timeout) {
2388                                         DWC_WARN("Suspend wasn't genereted\n");
2389                                 }
2390                                 dwc_udelay(10);
2391
2392                                 /*
2393                                  * We need to disable interrupts to prevent servicing of any IRQ
2394                                  * during going to hibernation
2395                                  */
2396                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2397                                 core_if->lx_state = DWC_OTG_L2;
2398 #ifdef DWC_DEV_SRPCAP
2399                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2400                                 hprt0.b.prtpwr = 0;
2401                                 hprt0.b.prtena = 0;
2402                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2403                                                 hprt0.d32);
2404 #endif
2405                                 gusbcfg.d32 =
2406                                     DWC_READ_REG32(&core_if->
2407                                                    core_global_regs->gusbcfg);
2408                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2409                                         /* ULPI interface */
2410                                         /* Suspend the Phy Clock */
2411                                         pcgcctl.d32 = 0;
2412                                         pcgcctl.b.stoppclk = 1;
2413                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2414                                                          pcgcctl.d32);
2415                                         dwc_udelay(10);
2416                                         gpwrdn.b.pmuactv = 1;
2417                                         DWC_MODIFY_REG32
2418                                             (&core_if->core_global_regs->gpwrdn,
2419                                              0, gpwrdn.d32);
2420                                 } else {
2421                                         /* UTMI+ Interface */
2422                                         gpwrdn.b.pmuactv = 1;
2423                                         DWC_MODIFY_REG32
2424                                             (&core_if->core_global_regs->gpwrdn,
2425                                              0, gpwrdn.d32);
2426                                         dwc_udelay(10);
2427                                         pcgcctl.b.stoppclk = 1;
2428                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2429                                                          pcgcctl.d32);
2430                                         dwc_udelay(10);
2431                                 }
2432 #ifdef DWC_DEV_SRPCAP
2433                                 gpwrdn.d32 = 0;
2434                                 gpwrdn.b.dis_vbus = 1;
2435                                 DWC_MODIFY_REG32(&core_if->
2436                                                  core_global_regs->gpwrdn, 0,
2437                                                  gpwrdn.d32);
2438 #endif
2439                                 gpwrdn.d32 = 0;
2440                                 gpwrdn.b.pmuintsel = 1;
2441                                 DWC_MODIFY_REG32(&core_if->
2442                                                  core_global_regs->gpwrdn, 0,
2443                                                  gpwrdn.d32);
2444                                 dwc_udelay(10);
2445
2446                                 gpwrdn.d32 = 0;
2447 #ifdef DWC_DEV_SRPCAP
2448                                 gpwrdn.b.srp_det_msk = 1;
2449 #endif
2450                                 gpwrdn.b.disconn_det_msk = 1;
2451                                 gpwrdn.b.lnstchng_msk = 1;
2452                                 gpwrdn.b.sts_chngint_msk = 1;
2453                                 DWC_MODIFY_REG32(&core_if->
2454                                                  core_global_regs->gpwrdn, 0,
2455                                                  gpwrdn.d32);
2456                                 dwc_udelay(10);
2457
2458                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2459                                 gpwrdn.d32 = 0;
2460                                 gpwrdn.b.pwrdnclmp = 1;
2461                                 DWC_MODIFY_REG32(&core_if->
2462                                                  core_global_regs->gpwrdn, 0,
2463                                                  gpwrdn.d32);
2464                                 dwc_udelay(10);
2465
2466                                 /* Switch off VDD */
2467                                 gpwrdn.d32 = 0;
2468                                 gpwrdn.b.pwrdnswtch = 1;
2469                                 DWC_MODIFY_REG32(&core_if->
2470                                                  core_global_regs->gpwrdn, 0,
2471                                                  gpwrdn.d32);
2472
2473 #ifdef DWC_DEV_SRPCAP
2474                                 if (otg_cap_param ==
2475                                     DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2476                                         core_if->pwron_timer_started = 1;
2477                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2478                                                            6000 /* 6 secs */);
2479                                 }
2480 #endif
2481                                 /* Save gpwrdn register for further usage if stschng interrupt */
2482                                 core_if->gr_backup->gpwrdn_local =
2483                                     DWC_READ_REG32(&core_if->core_global_regs->
2484                                                    gpwrdn);
2485
2486                                 /* Set flag to indicate that we are in hibernation */
2487                                 core_if->hibernation_suspend = 1;
2488                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2489                                                           flags);
2490
2491                                 DWC_PRINTF("Host hibernation completed\n");
2492                                 /* Exit from case statement */
2493                                 break;
2494
2495                         }
2496                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2497                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2498                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2499                                 gotgctl.b.hstsethnpen = 1;
2500                                 DWC_MODIFY_REG32(&core_if->
2501                                                  core_global_regs->gotgctl, 0,
2502                                                  gotgctl.d32);
2503                                 core_if->op_state = A_SUSPEND;
2504                         }
2505                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2506                         hprt0.b.prtsusp = 1;
2507                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2508                         {
2509                                 dwc_irqflags_t flags;
2510                                 /* Update lx_state */
2511                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2512                                 core_if->lx_state = DWC_OTG_L2;
2513                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2514                                                           flags);
2515                         }
2516                         /* Suspend the Phy Clock */
2517                         if (core_if->otg_ver == 0) {
2518                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2519                                 pcgcctl.b.stoppclk = 1;
2520                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2521                                                  pcgcctl.d32);
2522                                 dwc_udelay(10);
2523                         }
2524
2525                         /* For HNP the bus must be suspended for at least 200ms. */
2526                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2527                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2528                                 pcgcctl.b.stoppclk = 1;
2529                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2530                                                  0);
2531                                 dwc_mdelay(200);
2532                         }
2533
2534                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2535 #if 0
2536                         if (core_if->adp_enable) {
2537                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2538                                 gpwrdn_data_t gpwrdn;
2539
2540                                 while (gotgctl.b.asesvld == 1) {
2541                                         gotgctl.d32 =
2542                                             DWC_READ_REG32
2543                                             (&core_if->core_global_regs->gotgctl);
2544                                         dwc_mdelay(100);
2545                                 }
2546
2547                                 /* Enable Power Down Logic */
2548                                 gpwrdn.d32 = 0;
2549                                 gpwrdn.b.pmuactv = 1;
2550                                 DWC_MODIFY_REG32(&core_if->
2551                                                  core_global_regs->gpwrdn, 0,
2552                                                  gpwrdn.d32);
2553
2554                                 /* Unmask SRP detected interrupt from Power Down Logic */
2555                                 gpwrdn.d32 = 0;
2556                                 gpwrdn.b.srp_det_msk = 1;
2557                                 DWC_MODIFY_REG32(&core_if->
2558                                                  core_global_regs->gpwrdn, 0,
2559                                                  gpwrdn.d32);
2560
2561                                 dwc_otg_adp_probe_start(core_if);
2562                         }
2563 #endif
2564                         break;
2565                 case UHF_PORT_POWER:
2566                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2567                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2568                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2569                         hprt0.b.prtpwr = 1;
2570                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2571                         break;
2572                 case UHF_PORT_RESET:
2573                         if ((core_if->power_down == 2)
2574                             && (core_if->hibernation_suspend == 1)) {
2575                                 /* If we are going to exit from Hibernated
2576                                  * state via USB RESET.
2577                                  */
2578                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2579                         } else {
2580                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2581
2582                                 DWC_DEBUGPL(DBG_HCD,
2583                                             "DWC OTG HCD HUB CONTROL - "
2584                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2585                                 {
2586                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2587                                         pcgcctl.b.enbl_sleep_gating = 1;
2588                                         pcgcctl.b.stoppclk = 1;
2589                                         DWC_MODIFY_REG32(core_if->pcgcctl,
2590                                                          pcgcctl.d32, 0);
2591                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2592                                 }
2593 #ifdef CONFIG_USB_DWC_OTG_LPM
2594                                 {
2595                                         glpmcfg_data_t lpmcfg;
2596                                         lpmcfg.d32 =
2597                                             DWC_READ_REG32(&core_if->
2598                                                            core_global_regs->
2599                                                            glpmcfg);
2600                                         if (lpmcfg.b.prt_sleep_sts) {
2601                                                 lpmcfg.b.en_utmi_sleep = 0;
2602                                                 lpmcfg.b.hird_thres &=
2603                                                     (~(1 << 4));
2604                                                 DWC_WRITE_REG32(&core_if->
2605                                                                 core_global_regs->
2606                                                                 glpmcfg,
2607                                                                 lpmcfg.d32);
2608                                                 dwc_mdelay(1);
2609                                         }
2610                                 }
2611 #endif
2612                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2613                                 /* Clear suspend bit if resetting from suspended state. */
2614                                 hprt0.b.prtsusp = 0;
2615                                 /* When B-Host the Port reset bit is set in
2616                                  * the Start HCD Callback function, so that
2617                                  * the reset is started within 1ms of the HNP
2618                                  * success interrupt. */
2619                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2620                                         hprt0.b.prtpwr = 1;
2621                                         hprt0.b.prtrst = 1;
2622                                         DWC_PRINTF
2623                                             ("Indeed it is in host mode hprt0 = %08x\n",
2624                                              hprt0.d32);
2625                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2626                                                         hprt0.d32);
2627                                 }
2628                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2629                                 dwc_mdelay(60);
2630                                 hprt0.b.prtrst = 0;
2631                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2632                                                 hprt0.d32);
2633                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2634                         }
2635                         break;
2636 #ifdef DWC_HS_ELECT_TST
2637                 case UHF_PORT_TEST:
2638                         {
2639                                 uint32_t t;
2640                                 gintmsk_data_t gintmsk;
2641
2642                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2643                                 DWC_DEBUGPL(DBG_HCD,
2644                                             "DWC OTG HCD HUB CONTROL - "
2645                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2646                                             t);
2647                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2648                                 if (t < 6) {
2649                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2650                                         hprt0.b.prttstctl = t;
2651                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2652                                                         hprt0.d32);
2653                                 } else {
2654                                         /* Setup global vars with reg addresses (quick and
2655                                          * dirty hack, should be cleaned up)
2656                                          */
2657                                         global_regs = core_if->core_global_regs;
2658                                         hc_global_regs =
2659                                             core_if->host_if->host_global_regs;
2660                                         hc_regs =
2661                                             (dwc_otg_hc_regs_t *) ((char *)
2662                                                                    global_regs +
2663                                                                    0x500);
2664                                         data_fifo =
2665                                             (uint32_t *) ((char *)global_regs +
2666                                                           0x1000);
2667
2668                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2669                                                 /* Save current interrupt mask */
2670                                                 gintmsk.d32 =
2671                                                     DWC_READ_REG32
2672                                                     (&global_regs->gintmsk);
2673
2674                                                 /* Disable all interrupts while we muck with
2675                                                  * the hardware directly
2676                                                  */
2677                                                 DWC_WRITE_REG32(&global_regs->
2678                                                                 gintmsk, 0);
2679
2680                                                 /* 15 second delay per the test spec */
2681                                                 dwc_mdelay(15000);
2682
2683                                                 /* Drive suspend on the root port */
2684                                                 hprt0.d32 =
2685                                                     dwc_otg_read_hprt0(core_if);
2686                                                 hprt0.b.prtsusp = 1;
2687                                                 hprt0.b.prtres = 0;
2688                                                 DWC_WRITE_REG32(core_if->
2689                                                                 host_if->hprt0,
2690                                                                 hprt0.d32);
2691
2692                                                 /* 15 second delay per the test spec */
2693                                                 dwc_mdelay(15000);
2694
2695                                                 /* Drive resume on the root port */
2696                                                 hprt0.d32 =
2697                                                     dwc_otg_read_hprt0(core_if);
2698                                                 hprt0.b.prtsusp = 0;
2699                                                 hprt0.b.prtres = 1;
2700                                                 DWC_WRITE_REG32(core_if->
2701                                                                 host_if->hprt0,
2702                                                                 hprt0.d32);
2703                                                 dwc_mdelay(100);
2704
2705                                                 /* Clear the resume bit */
2706                                                 hprt0.b.prtres = 0;
2707                                                 DWC_WRITE_REG32(core_if->
2708                                                                 host_if->hprt0,
2709                                                                 hprt0.d32);
2710
2711                                                 /* Restore interrupts */
2712                                                 DWC_WRITE_REG32(&global_regs->
2713                                                                 gintmsk,
2714                                                                 gintmsk.d32);
2715                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2716                                                 /* Save current interrupt mask */
2717                                                 gintmsk.d32 =
2718                                                     DWC_READ_REG32
2719                                                     (&global_regs->gintmsk);
2720
2721                                                 /* Disable all interrupts while we muck with
2722                                                  * the hardware directly
2723                                                  */
2724                                                 DWC_WRITE_REG32(&global_regs->
2725                                                                 gintmsk, 0);
2726
2727                                                 /* 15 second delay per the test spec */
2728                                                 dwc_mdelay(15000);
2729
2730                                                 /* Send the Setup packet */
2731                                                 do_setup();
2732
2733                                                 /* 15 second delay so nothing else happens for awhile */
2734                                                 dwc_mdelay(15000);
2735
2736                                                 /* Restore interrupts */
2737                                                 DWC_WRITE_REG32(&global_regs->
2738                                                                 gintmsk,
2739                                                                 gintmsk.d32);
2740                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2741                                                 /* Save current interrupt mask */
2742                                                 gintmsk.d32 =
2743                                                     DWC_READ_REG32
2744                                                     (&global_regs->gintmsk);
2745
2746                                                 /* Disable all interrupts while we muck with
2747                                                  * the hardware directly
2748                                                  */
2749                                                 DWC_WRITE_REG32(&global_regs->
2750                                                                 gintmsk, 0);
2751
2752                                                 /* Send the Setup packet */
2753                                                 do_setup();
2754
2755                                                 /* 15 second delay so nothing else happens for awhile */
2756                                                 dwc_mdelay(15000);
2757
2758                                                 /* Send the In and Ack packets */
2759                                                 do_in_ack();
2760
2761                                                 /* 15 second delay so nothing else happens for awhile */
2762                                                 dwc_mdelay(15000);
2763
2764                                                 /* Restore interrupts */
2765                                                 DWC_WRITE_REG32(&global_regs->
2766                                                                 gintmsk,
2767                                                                 gintmsk.d32);
2768                                         }
2769                                 }
2770                                 break;
2771                         }
2772 #endif /* DWC_HS_ELECT_TST */
2773
2774                 case UHF_PORT_INDICATOR:
2775                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2776                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2777                         /* Not supported */
2778                         break;
2779                 default:
2780                         retval = -DWC_E_INVALID;
2781                         DWC_ERROR("DWC OTG HCD - "
2782                                   "SetPortFeature request %xh "
2783                                   "unknown or unsupported\n", wValue);
2784                         break;
2785                 }
2786                 break;
2787 #ifdef CONFIG_USB_DWC_OTG_LPM
2788         case UCR_SET_AND_TEST_PORT_FEATURE:
2789                 if (wValue != UHF_PORT_L1) {
2790                         goto error;
2791                 }
2792                 {
2793                         int portnum, hird, devaddr, remwake;
2794                         glpmcfg_data_t lpmcfg;
2795                         uint32_t time_usecs;
2796                         gintsts_data_t gintsts;
2797                         gintmsk_data_t gintmsk;
2798
2799                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2800                                 goto error;
2801                         }
2802                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2803                                 goto error;
2804                         }
2805                         /* Check if the port currently is in SLEEP state */
2806                         lpmcfg.d32 =
2807                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2808                         if (lpmcfg.b.prt_sleep_sts) {
2809                                 DWC_INFO("Port is already in sleep mode\n");
2810                                 buf[0] = 0;     /* Return success */
2811                                 break;
2812                         }
2813
2814                         portnum = wIndex & 0xf;
2815                         hird = (wIndex >> 4) & 0xf;
2816                         devaddr = (wIndex >> 8) & 0x7f;
2817                         remwake = (wIndex >> 15);
2818
2819                         if (portnum != 1) {
2820                                 retval = -DWC_E_INVALID;
2821                                 DWC_WARN
2822                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2823                                      portnum);
2824                                 break;
2825                         }
2826
2827                         DWC_PRINTF
2828                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2829                              portnum, hird, devaddr, remwake);
2830                         /* Disable LPM interrupt */
2831                         gintmsk.d32 = 0;
2832                         gintmsk.b.lpmtranrcvd = 1;
2833                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2834                                          gintmsk.d32, 0);
2835
2836                         if (dwc_otg_hcd_send_lpm
2837                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2838                                 retval = -DWC_E_INVALID;
2839                                 break;
2840                         }
2841
2842                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2843                         /* We will consider timeout if time_usecs microseconds pass,
2844                          * and we don't receive LPM transaction status.
2845                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2846                          *  core will set lpmtranrcvd bit.
2847                          */
2848                         do {
2849                                 gintsts.d32 =
2850                                     DWC_READ_REG32(&core_if->core_global_regs->
2851                                                    gintsts);
2852                                 if (gintsts.b.lpmtranrcvd) {
2853                                         break;
2854                                 }
2855                                 dwc_udelay(1);
2856                         } while (--time_usecs);
2857                         /* lpm_int bit will be cleared in LPM interrupt handler */
2858
2859                         /* Now fill status
2860                          * 0x00 - Success
2861                          * 0x10 - NYET
2862                          * 0x11 - Timeout
2863                          */
2864                         if (!gintsts.b.lpmtranrcvd) {
2865                                 buf[0] = 0x3;   /* Completion code is Timeout */
2866                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2867                         } else {
2868                                 lpmcfg.d32 =
2869                                     DWC_READ_REG32(&core_if->core_global_regs->
2870                                                    glpmcfg);
2871                                 if (lpmcfg.b.lpm_resp == 0x3) {
2872                                         /* ACK responce from the device */
2873                                         buf[0] = 0x00;  /* Success */
2874                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2875                                         /* NYET responce from the device */
2876                                         buf[0] = 0x2;
2877                                 } else {
2878                                         /* Otherwise responce with Timeout */
2879                                         buf[0] = 0x3;
2880                                 }
2881                         }
2882                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2883                                    lpmcfg.b.lpm_resp);
2884                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2885                                          gintmsk.d32);
2886
2887                         break;
2888                 }
2889 #endif /* CONFIG_USB_DWC_OTG_LPM */
2890         default:
2891 error:
2892                 retval = -DWC_E_INVALID;
2893                 DWC_WARN("DWC OTG HCD - "
2894                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2895                          typeReq, wIndex, wValue);
2896                 break;
2897         }
2898
2899         return retval;
2900 }
2901
2902 #ifdef CONFIG_USB_DWC_OTG_LPM
2903 /** Returns index of host channel to perform LPM transaction. */
2904 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2905 {
2906         dwc_otg_core_if_t *core_if = hcd->core_if;
2907         dwc_hc_t *hc;
2908         hcchar_data_t hcchar;
2909         gintmsk_data_t gintmsk = {.d32 = 0 };
2910
2911         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2912                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2913                 return -1;
2914         }
2915
2916         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2917
2918         /* Mask host channel interrupts. */
2919         gintmsk.b.hcintr = 1;
2920         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2921
2922         /* Fill fields that core needs for LPM transaction */
2923         hcchar.b.devaddr = devaddr;
2924         hcchar.b.epnum = 0;
2925         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2926         hcchar.b.mps = 64;
2927         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2928         hcchar.b.epdir = 0;     /* OUT */
2929         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2930                         hcchar.d32);
2931
2932         /* Remove the host channel from the free list. */
2933         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2934
2935         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2936
2937         return hc->hc_num;
2938 }
2939
2940 /** Release hc after performing LPM transaction */
2941 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2942 {
2943         dwc_hc_t *hc;
2944         glpmcfg_data_t lpmcfg;
2945         uint8_t hc_num;
2946
2947         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2948         hc_num = lpmcfg.b.lpm_chan_index;
2949
2950         hc = hcd->hc_ptr_array[hc_num];
2951
2952         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2953         /* Return host channel to free list */
2954         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2955 }
2956
2957 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2958                          uint8_t bRemoteWake)
2959 {
2960         glpmcfg_data_t lpmcfg;
2961         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2962         int channel;
2963
2964         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2965         if (channel < 0) {
2966                 return channel;
2967         }
2968
2969         pcgcctl.b.enbl_sleep_gating = 1;
2970         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2971
2972         /* Read LPM config register */
2973         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2974
2975         /* Program LPM transaction fields */
2976         lpmcfg.b.rem_wkup_en = bRemoteWake;
2977         lpmcfg.b.hird = hird;
2978
2979         if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2980                 lpmcfg.b.hird_thres = 0x16;
2981                 lpmcfg.b.en_besl = 1;
2982         } else {
2983                 lpmcfg.b.hird_thres = 0x1c;
2984         }
2985
2986         lpmcfg.b.lpm_chan_index = channel;
2987         lpmcfg.b.en_utmi_sleep = 1;
2988         /* Program LPM config register */
2989         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2990
2991         /* Send LPM transaction */
2992         lpmcfg.b.send_lpm = 1;
2993         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2994
2995         return 0;
2996 }
2997
2998 #endif /* CONFIG_USB_DWC_OTG_LPM */
2999
3000 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3001 {
3002         int retval;
3003
3004         if (port != 1) {
3005                 return -DWC_E_INVALID;
3006         }
3007
3008         retval = (hcd->flags.b.port_connect_status_change ||
3009                   hcd->flags.b.port_reset_change ||
3010                   hcd->flags.b.port_enable_change ||
3011                   hcd->flags.b.port_suspend_change ||
3012                   hcd->flags.b.port_over_current_change);
3013 #ifdef DEBUG
3014         if (retval) {
3015                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3016                             " Root port status changed\n");
3017                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
3018                             hcd->flags.b.port_connect_status_change);
3019                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
3020                             hcd->flags.b.port_reset_change);
3021                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
3022                             hcd->flags.b.port_enable_change);
3023                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
3024                             hcd->flags.b.port_suspend_change);
3025                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
3026                             hcd->flags.b.port_over_current_change);
3027         }
3028 #endif
3029         return retval;
3030 }
3031
3032 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3033 {
3034         hfnum_data_t hfnum;
3035         hfnum.d32 =
3036             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3037                            host_global_regs->hfnum);
3038
3039 #ifdef DEBUG_SOF
3040         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3041                     hfnum.b.frnum);
3042 #endif
3043         return hfnum.b.frnum;
3044 }
3045
3046 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3047                       struct dwc_otg_hcd_function_ops *fops)
3048 {
3049         int retval = 0;
3050
3051         hcd->fops = fops;
3052         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3053             (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3054                 dwc_otg_hcd_reinit(hcd);
3055         } else {
3056                 retval = -DWC_E_NO_DEVICE;
3057         }
3058
3059         return retval;
3060 }
3061
3062 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3063 {
3064         return hcd->priv;
3065 }
3066
3067 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3068 {
3069         hcd->priv = priv_data;
3070 }
3071
3072 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3073 {
3074         return hcd->otg_port;
3075 }
3076
3077 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3078 {
3079         uint32_t is_b_host;
3080         if (hcd->core_if->op_state == B_HOST) {
3081                 is_b_host = 1;
3082         } else {
3083                 is_b_host = 0;
3084         }
3085
3086         return is_b_host;
3087 }
3088
3089 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3090                                          int iso_desc_count, int atomic_alloc)
3091 {
3092         dwc_otg_hcd_urb_t *dwc_otg_urb;
3093         uint32_t size;
3094
3095         size =
3096             sizeof(*dwc_otg_urb) +
3097             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3098         if (atomic_alloc)
3099                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3100         else
3101                 dwc_otg_urb = DWC_ALLOC(size);
3102
3103         dwc_otg_urb->packet_count = iso_desc_count;
3104
3105         return dwc_otg_urb;
3106 }
3107
3108 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3109                                   uint8_t dev_addr, uint8_t ep_num,
3110                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3111 {
3112         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3113                               ep_type, ep_dir, mps);
3114 #if 0
3115         DWC_PRINTF
3116             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3117              dev_addr, ep_num, ep_dir, ep_type, mps);
3118 #endif
3119 }
3120
3121 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3122                                 void *urb_handle, void *buf, dwc_dma_t dma,
3123                                 uint32_t buflen, void *setup_packet,
3124                                 dwc_dma_t setup_dma, uint32_t flags,
3125                                 uint16_t interval)
3126 {
3127         dwc_otg_urb->priv = urb_handle;
3128         dwc_otg_urb->buf = buf;
3129         dwc_otg_urb->dma = dma;
3130         dwc_otg_urb->length = buflen;
3131         dwc_otg_urb->setup_packet = setup_packet;
3132         dwc_otg_urb->setup_dma = setup_dma;
3133         dwc_otg_urb->flags = flags;
3134         dwc_otg_urb->interval = interval;
3135         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3136 }
3137
3138 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3139 {
3140         return dwc_otg_urb->status;
3141 }
3142
3143 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3144 {
3145         return dwc_otg_urb->actual_length;
3146 }
3147
3148 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3149 {
3150         return dwc_otg_urb->error_count;
3151 }
3152
3153 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3154                                          int desc_num, uint32_t offset,
3155                                          uint32_t length)
3156 {
3157         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3158         dwc_otg_urb->iso_descs[desc_num].length = length;
3159 }
3160
3161 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3162                                              int desc_num)
3163 {
3164         return dwc_otg_urb->iso_descs[desc_num].status;
3165 }
3166
3167 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3168                                                     dwc_otg_urb, int desc_num)
3169 {
3170         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3171 }
3172
3173 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3174 {
3175         int allocated = 0;
3176         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3177
3178         if (qh) {
3179                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3180                         allocated = 1;
3181                 }
3182         }
3183         return allocated;
3184 }
3185
3186 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3187 {
3188         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3189         int freed = 0;
3190         DWC_ASSERT(qh, "qh is not allocated\n");
3191
3192         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3193                 freed = 1;
3194         }
3195
3196         return freed;
3197 }
3198
3199 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3200 {
3201         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3202         DWC_ASSERT(qh, "qh is not allocated\n");
3203         return qh->usecs;
3204 }
3205
3206 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3207 {
3208 #ifdef DEBUG
3209         int num_channels;
3210         int i;
3211         gnptxsts_data_t np_tx_status;
3212         hptxsts_data_t p_tx_status;
3213
3214         num_channels = hcd->core_if->core_params->host_channels;
3215         DWC_PRINTF("\n");
3216         DWC_PRINTF
3217             ("************************************************************\n");
3218         DWC_PRINTF("HCD State:\n");
3219         DWC_PRINTF("  Num channels: %d\n", num_channels);
3220         for (i = 0; i < num_channels; i++) {
3221                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3222                 DWC_PRINTF("  Channel %d:\n", i);
3223                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3224                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3225                 DWC_PRINTF("    speed: %d\n", hc->speed);
3226                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3227                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3228                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3229                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3230                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3231                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3232                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3233                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3234                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3235                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3236                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3237                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3238                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3239                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3240                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3241                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3242                 DWC_PRINTF("    requests: %d\n", hc->requests);
3243                 DWC_PRINTF("    qh: %p\n", hc->qh);
3244                 if (hc->xfer_started) {
3245                         hfnum_data_t hfnum;
3246                         hcchar_data_t hcchar;
3247                         hctsiz_data_t hctsiz;
3248                         hcint_data_t hcint;
3249                         hcintmsk_data_t hcintmsk;
3250                         hfnum.d32 =
3251                             DWC_READ_REG32(&hcd->core_if->host_if->
3252                                            host_global_regs->hfnum);
3253                         hcchar.d32 =
3254                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3255                                            hcchar);
3256                         hctsiz.d32 =
3257                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3258                                            hctsiz);
3259                         hcint.d32 =
3260                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3261                                            hcint);
3262                         hcintmsk.d32 =
3263                             DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3264                                            hcintmsk);
3265                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3266                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3267                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3268                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3269                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3270                 }
3271                 if (hc->xfer_started && hc->qh) {
3272                         dwc_otg_qtd_t *qtd;
3273                         dwc_otg_hcd_urb_t *urb;
3274
3275                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3276                                             qtd_list_entry) {
3277                                 if (!qtd->in_process)
3278                                         break;
3279
3280                                 urb = qtd->urb;
3281                                 DWC_PRINTF("    URB Info:\n");
3282                                 DWC_PRINTF("      qtd: %p, urb: %p\n", qtd,
3283                                            urb);
3284                                 if (urb) {
3285                                         DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3286                                                    dwc_otg_hcd_get_dev_addr
3287                                                    (&urb->pipe_info),
3288                                                    dwc_otg_hcd_get_ep_num
3289                                                    (&urb->pipe_info),
3290                                                    dwc_otg_hcd_is_pipe_in
3291                                                    (&urb->pipe_info) ? "IN" :
3292                                                    "OUT");
3293                                         DWC_PRINTF
3294                                             ("      Max packet size: %d\n",
3295                                              dwc_otg_hcd_get_mps
3296                                              (&urb->pipe_info));
3297                                         DWC_PRINTF
3298                                             ("      transfer_buffer: %p\n",
3299                                              urb->buf);
3300                                         DWC_PRINTF("      transfer_dma: %p\n",
3301                                                    (void *)urb->dma);
3302                                         DWC_PRINTF
3303                                             ("      transfer_buffer_length: %d\n",
3304                                              urb->length);
3305                                         DWC_PRINTF("      actual_length: %d\n",
3306                                                    urb->actual_length);
3307                                 }
3308                         }
3309                 }
3310         }
3311         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3312         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3313         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3314         np_tx_status.d32 =
3315             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3316         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3317                    np_tx_status.b.nptxqspcavail);
3318         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3319                    np_tx_status.b.nptxfspcavail);
3320         p_tx_status.d32 =
3321             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3322         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3323                    p_tx_status.b.ptxqspcavail);
3324         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3325         dwc_otg_hcd_dump_frrem(hcd);
3326         dwc_otg_dump_global_registers(hcd->core_if);
3327         dwc_otg_dump_host_registers(hcd->core_if);
3328         DWC_PRINTF
3329             ("************************************************************\n");
3330         DWC_PRINTF("\n");
3331 #endif
3332 }
3333
3334 #ifdef DEBUG
3335 void dwc_print_setup_data(uint8_t *setup)
3336 {
3337         int i;
3338         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3339                 DWC_PRINTF("Setup Data = MSB ");
3340                 for (i = 7; i >= 0; i--)
3341                         DWC_PRINTF("%02x ", setup[i]);
3342                 DWC_PRINTF("\n");
3343                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3344                            (setup[0] & 0x80) ? "Device-to-Host" :
3345                            "Host-to-Device");
3346                 DWC_PRINTF("  bmRequestType Type = ");
3347                 switch ((setup[0] & 0x60) >> 5) {
3348                 case 0:
3349                         DWC_PRINTF("Standard\n");
3350                         break;
3351                 case 1:
3352                         DWC_PRINTF("Class\n");
3353                         break;
3354                 case 2:
3355                         DWC_PRINTF("Vendor\n");
3356                         break;
3357                 case 3:
3358                         DWC_PRINTF("Reserved\n");
3359                         break;
3360                 }
3361                 DWC_PRINTF("  bmRequestType Recipient = ");
3362                 switch (setup[0] & 0x1f) {
3363                 case 0:
3364                         DWC_PRINTF("Device\n");
3365                         break;
3366                 case 1:
3367                         DWC_PRINTF("Interface\n");
3368                         break;
3369                 case 2:
3370                         DWC_PRINTF("Endpoint\n");
3371                         break;
3372                 case 3:
3373                         DWC_PRINTF("Other\n");
3374                         break;
3375                 default:
3376                         DWC_PRINTF("Reserved\n");
3377                         break;
3378                 }
3379                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3380                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3381                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3382                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3383         }
3384 }
3385 #endif
3386
3387 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3388 {
3389 #if 0
3390         DWC_PRINTF("Frame remaining at SOF:\n");
3391         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3392                    hcd->frrem_samples, hcd->frrem_accum,
3393                    (hcd->frrem_samples > 0) ?
3394                    hcd->frrem_accum / hcd->frrem_samples : 0);
3395
3396         DWC_PRINTF("\n");
3397         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3398         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3399                    hcd->core_if->hfnum_7_samples,
3400                    hcd->core_if->hfnum_7_frrem_accum,
3401                    (hcd->core_if->hfnum_7_samples >
3402                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3403                    hcd->core_if->hfnum_7_samples : 0);
3404         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3405         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3406                    hcd->core_if->hfnum_0_samples,
3407                    hcd->core_if->hfnum_0_frrem_accum,
3408                    (hcd->core_if->hfnum_0_samples >
3409                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3410                    hcd->core_if->hfnum_0_samples : 0);
3411         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3412         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3413                    hcd->core_if->hfnum_other_samples,
3414                    hcd->core_if->hfnum_other_frrem_accum,
3415                    (hcd->core_if->hfnum_other_samples >
3416                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3417                    hcd->core_if->hfnum_other_samples : 0);
3418
3419         DWC_PRINTF("\n");
3420         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3421         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3422                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3423                    (hcd->hfnum_7_samples_a > 0) ?
3424                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3425         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3426         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3427                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3428                    (hcd->hfnum_0_samples_a > 0) ?
3429                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3430         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3431         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3432                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3433                    (hcd->hfnum_other_samples_a > 0) ?
3434                    hcd->hfnum_other_frrem_accum_a /
3435                    hcd->hfnum_other_samples_a : 0);
3436
3437         DWC_PRINTF("\n");
3438         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3439         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3440                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3441                    (hcd->hfnum_7_samples_b > 0) ?
3442                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3443         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3444         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3445                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3446                    (hcd->hfnum_0_samples_b > 0) ?
3447                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3448         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3449         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3450                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3451                    (hcd->hfnum_other_samples_b > 0) ?
3452                    hcd->hfnum_other_frrem_accum_b /
3453                    hcd->hfnum_other_samples_b : 0);
3454 #endif
3455 }
3456
3457 #endif /* DWC_DEVICE_ONLY */