drivers/usb/dwc_otg_310/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #106 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /** @file
  36  * This file implements HCD Core. All code in this file is portable and doesn't
  37  * use any OS specific functions.
  38  * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
  39  * header file.
  40  */
  41
  42 #include "dwc_otg_hcd.h"
  43 #include "dwc_otg_regs.h"
  44 #include "usbdev_rk.h"
  45 #include "dwc_otg_driver.h"
  46 #include <linux/usb.h>
  47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
  48 #include <../drivers/usb/core/hcd.h>
  49 #else
  50 #include <linux/usb/hcd.h>
  51 #endif
  52
  53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
  54 {
  55         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
  56 }
  57
  58 /**
  59  * Connection timeout function.  An OTG host is required to display a
  60  * message if the device does not connect within 10 seconds.
  61  */
  62 void dwc_otg_hcd_connect_timeout(void *ptr)
  63 {
  64         dwc_otg_hcd_t *hcd;
  65         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
  66         DWC_PRINTF("Connect Timeout\n");
  67         __DWC_ERROR("Device Not Connected/Responding\n");
  68         /** Remove buspower after 10s */
  69         hcd = ptr;
  70         if (hcd->core_if->otg_ver)
  71                 dwc_otg_set_prtpower(hcd->core_if, 0);
  72 }
  73
  74 #ifdef DEBUG
  75 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
  76 {
  77         if (qh->channel != NULL) {
  78                 dwc_hc_t *hc = qh->channel;
  79                 dwc_list_link_t *item;
  80                 dwc_otg_qh_t *qh_item;
  81                 int num_channels = hcd->core_if->core_params->host_channels;
  82                 int i;
  83
  84                 dwc_otg_hc_regs_t *hc_regs;
  85                 hcchar_data_t hcchar;
  86                 hcsplt_data_t hcsplt;
  87                 hctsiz_data_t hctsiz;
  88                 uint32_t hcdma;
  89
  90                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
  91                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
  92                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
  93                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
  94                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
  95
  96                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
  97                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
  98                            hcsplt.d32);
  99                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
 100                            hcdma);
 101                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 102                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
 103                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
 104                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
 105                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
 106                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
 107                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
 108                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
 109                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
 110                 DWC_PRINTF("    qh: %p\n", hc->qh);
 111                 DWC_PRINTF("  NP inactive sched:\n");
 112                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
 113                         qh_item =
 114                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 115                         DWC_PRINTF("    %p\n", qh_item);
 116                 }
 117                 DWC_PRINTF("  NP active sched:\n");
 118                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
 119                         qh_item =
 120                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 121                         DWC_PRINTF("    %p\n", qh_item);
 122                 }
 123                 DWC_PRINTF("  Channels: \n");
 124                 for (i = 0; i < num_channels; i++) {
 125                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
 126                         DWC_PRINTF("    %2d: %p\n", i, hc);
 127                 }
 128         }
 129 }
 130 #endif /* DEBUG */
 131
 132 /**
 133  * Work queue function for starting the HCD when A-Cable is connected.
 134  * The hcd_start() must be called in a process context.
 135  */
 136 static void hcd_start_func(void *_vp)
 137 {
 138         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
 139
 140         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
 141         if (hcd) {
 142                 hcd->fops->start(hcd);
 143         }
 144 }
 145
 146 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
 147 {
 148 #ifdef DEBUG
 149         int i;
 150         int num_channels = hcd->core_if->core_params->host_channels;
 151         for (i = 0; i < num_channels; i++) {
 152                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
 153         }
 154 #endif
 155 }
 156
 157 static void del_timers(dwc_otg_hcd_t * hcd)
 158 {
 159         del_xfer_timers(hcd);
 160         DWC_TIMER_CANCEL(hcd->conn_timer);
 161 }
 162
 163 /**
 164  * Processes all the URBs in a single list of QHs. Completes them with
 165  * -ETIMEDOUT and frees the QTD.
 166  */
 167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
 168 {
 169         dwc_list_link_t *qh_item;
 170         dwc_otg_qh_t *qh;
 171         dwc_otg_qtd_t *qtd, *qtd_tmp;
 172
 173         DWC_LIST_FOREACH(qh_item, qh_list) {
 174                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
 175                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
 176                                          &qh->qtd_list, qtd_list_entry) {
 177                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 178                         if (qtd->urb != NULL) {
 179                                 hcd->fops->complete(hcd, qtd->urb->priv,
 180                                                     qtd->urb, -DWC_E_TIMEOUT);
 181                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 182                         }
 183
 184                 }
 185         }
 186 }
 187
 188 /**
 189  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 190  * and periodic schedules. The QTD associated with each URB is removed from
 191  * the schedule and freed. This function may be called when a disconnect is
 192  * detected or when the HCD is being stopped.
 193  */
 194 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
 195 {
 196         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
 197         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
 198         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
 199         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
 200         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
 201         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
 202 }
 203
 204 /**
 205  * Start the connection timer.  An OTG host is required to display a
 206  * message if the device does not connect within 10 seconds.  The
 207  * timer is deleted if a port connect interrupt occurs before the
 208  * timer expires.
 209  */
 210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
 211 {
 212         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
 213 }
 214
 215 /**
 216  * HCD Callback function for disconnect of the HCD.
 217  *
 218  * @param p void pointer to the <code>struct usb_hcd</code>
 219  */
 220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
 221 {
 222         dwc_otg_hcd_t *dwc_otg_hcd;
 223         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 224         dwc_otg_hcd = p;
 225         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
 226         return 1;
 227 }
 228
 229 /**
 230  * HCD Callback function for starting the HCD when A-Cable is
 231  * connected.
 232  *
 233  * @param p void pointer to the <code>struct usb_hcd</code>
 234  */
 235 static int32_t dwc_otg_hcd_start_cb(void *p)
 236 {
 237         dwc_otg_hcd_t *dwc_otg_hcd = p;
 238         dwc_otg_core_if_t *core_if;
 239         hprt0_data_t hprt0;
 240         uint32_t timeout = 50;
 241
 242         core_if = dwc_otg_hcd->core_if;
 243
 244         if (core_if->op_state == B_HOST) {
 245                 /*
 246                  * Reset the port.  During a HNP mode switch the reset
 247                  * needs to occur within 1ms and have a duration of at
 248                  * least 50ms.
 249                  */
 250                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
 251                 hprt0.b.prtrst = 1;
 252                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 253                 if (core_if->otg_ver) {
 254                         dwc_mdelay(60);
 255                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 256                         hprt0.b.prtrst = 0;
 257                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 258                 }
 259         }
 260         /**@todo vahrama: Check the timeout value for OTG 2.0 */
 261         if (core_if->otg_ver)
 262                 timeout = 25;
 263         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
 264                                 hcd_start_func, dwc_otg_hcd, timeout,
 265                                 "start hcd");
 266
 267         return 1;
 268 }
 269
 270 /**
 271  * HCD Callback function for disconnect of the HCD.
 272  *
 273  * @param p void pointer to the <code>struct usb_hcd</code>
 274  */
 275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
 276 {
 277         gintsts_data_t intr;
 278         dwc_otg_hcd_t *dwc_otg_hcd = p;
 279
 280         /*
 281          * Set status flags for the hub driver.
 282          */
 283         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 284         dwc_otg_hcd->flags.b.port_connect_status = 0;
 285
 286         /*
 287          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 288          * interrupt mask and status bits and disabling subsequent host
 289          * channel interrupts.
 290          */
 291         intr.d32 = 0;
 292         intr.b.nptxfempty = 1;
 293         intr.b.ptxfempty = 1;
 294         intr.b.hcintr = 1;
 295         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
 296                          intr.d32, 0);
 297         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
 298                          intr.d32, 0);
 299
 300         /*
 301          * Turn off the vbus power only if the core has transitioned to device
 302          * mode. If still in host mode, need to keep power on to detect a
 303          * reconnection.
 304          */
 305         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 306                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 307                         hprt0_data_t hprt0 = {.d32 = 0 };
 308                         DWC_PRINTF("Disconnect: PortPower off\n");
 309                         hprt0.b.prtpwr = 0;
 310                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 311                                         hprt0.d32);
 312                 }
 313                 /** Delete timers if become device */
 314                 del_timers(dwc_otg_hcd);
 315                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
 316         }
 317
 318         /* Respond with an error status to all URBs in the schedule. */
 319         kill_all_urbs(dwc_otg_hcd);
 320
 321         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 322                 /* Clean up any host channels that were in use. */
 323                 int num_channels;
 324                 int i;
 325                 dwc_hc_t *channel;
 326                 dwc_otg_hc_regs_t *hc_regs;
 327                 hcchar_data_t hcchar;
 328
 329                 DWC_PRINTF("Disconnect cb-Host\n");
 330                 if (dwc_otg_hcd->core_if->otg_ver == 1)
 331                         del_xfer_timers(dwc_otg_hcd);
 332                 else
 333                         del_timers(dwc_otg_hcd);
 334
 335                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 336
 337                 if (!dwc_otg_hcd->core_if->dma_enable) {
 338                         /* Flush out any channel requests in slave mode. */
 339                         for (i = 0; i < num_channels; i++) {
 340                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 341                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
 342                                     (channel, hc_list_entry)) {
 343                                         hc_regs =
 344                                             dwc_otg_hcd->core_if->
 345                                             host_if->hc_regs[i];
 346                                         hcchar.d32 =
 347                                             DWC_READ_REG32(&hc_regs->hcchar);
 348                                         if (hcchar.b.chen) {
 349                                                 hcchar.b.chen = 0;
 350                                                 hcchar.b.chdis = 1;
 351                                                 hcchar.b.epdir = 0;
 352                                                 DWC_WRITE_REG32
 353                                                     (&hc_regs->hcchar,
 354                                                      hcchar.d32);
 355                                         }
 356                                 }
 357                         }
 358                 }
 359
 360                 for (i = 0; i < num_channels; i++) {
 361                         channel = dwc_otg_hcd->hc_ptr_array[i];
 362                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
 363                                 hc_regs =
 364                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
 365                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
 366                                 if (hcchar.b.chen) {
 367                                         /* Halt the channel. */
 368                                         hcchar.b.chdis = 1;
 369                                         DWC_WRITE_REG32(&hc_regs->hcchar,
 370                                                         hcchar.d32);
 371                                 }
 372
 373                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
 374                                                    channel);
 375                                 DWC_CIRCLEQ_INSERT_TAIL
 376                                     (&dwc_otg_hcd->free_hc_list, channel,
 377                                      hc_list_entry);
 378                                 /*
 379                                  * Added for Descriptor DMA to prevent channel double cleanup
 380                                  * in release_channel_ddma(). Which called from ep_disable
 381                                  * when device disconnect.
 382                                  */
 383                                 channel->qh = NULL;
 384                         }
 385                 }
 386         }
 387
 388         if (dwc_otg_hcd->fops->disconnect) {
 389                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
 390         }
 391
 392         return 1;
 393 }
 394
 395 /**
 396  * HCD Callback function for stopping the HCD.
 397  *
 398  * @param p void pointer to the <code>struct usb_hcd</code>
 399  */
 400 static int32_t dwc_otg_hcd_stop_cb(void *p)
 401 {
 402         dwc_otg_hcd_t *dwc_otg_hcd = p;
 403
 404         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
 405         dwc_otg_hcd_stop(dwc_otg_hcd);
 406         return 1;
 407 }
 408
 409 #ifdef CONFIG_USB_DWC_OTG_LPM
 410 /**
 411  * HCD Callback function for sleep of HCD.
 412  *
 413  * @param p void pointer to the <code>struct usb_hcd</code>
 414  */
 415 static int dwc_otg_hcd_sleep_cb(void *p)
 416 {
 417         dwc_otg_hcd_t *hcd = p;
 418
 419         dwc_otg_hcd_free_hc_from_lpm(hcd);
 420
 421         return 0;
 422 }
 423 #endif
 424
 425 /**
 426  * HCD Callback function for Remote Wakeup.
 427  *
 428  * @param p void pointer to the <code>struct usb_hcd</code>
 429  */
 430 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd);
 431 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
 432 {
 433         dwc_otg_hcd_t *dwc_otg_hcd = p;
 434         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 435
 436         if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
 437                 dwc_otg_hcd->flags.b.port_suspend_change = 1;
 438                 usb_hcd_resume_root_hub(hcd);
 439         }
 440 #ifdef CONFIG_USB_DWC_OTG_LPM
 441         else {
 442                 dwc_otg_hcd->flags.b.port_l1_change = 1;
 443         }
 444 #endif
 445         return 0;
 446 }
 447
 448 /**
 449  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
 450  * stopped.
 451  */
 452 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
 453 {
 454         hprt0_data_t hprt0 = {.d32 = 0 };
 455         struct dwc_otg_platform_data *pldata;
 456     pldata = hcd->core_if->otg_dev->pldata;
 457
 458         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
 459
 460         /*
 461          * The root hub should be disconnected before this function is called.
 462          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 463          * and the QH lists (via ..._hcd_endpoint_disable).
 464          */
 465
 466         /* Turn off all host-specific interrupts. */
 467         dwc_otg_disable_host_interrupts(hcd->core_if);
 468
 469         /* Turn off the vbus power */
 470         DWC_PRINTF("PortPower off\n");
 471         hprt0.b.prtpwr = 0;
 472         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
 473
 474         if(pldata->power_enable)
 475             pldata->power_enable(0);
 476
 477
 478         dwc_mdelay(1);
 479 }
 480
 481 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
 482                             dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
 483                             int atomic_alloc)
 484 {
 485         dwc_irqflags_t flags;
 486         int retval = 0;
 487         dwc_otg_qtd_t *qtd;
 488         gintmsk_data_t intr_mask = {.d32 = 0 };
 489
 490         if (!hcd->flags.b.port_connect_status) {
 491                 /* No longer connected. */
 492                 DWC_ERROR("Not connected\n");
 493                 return -DWC_E_NO_DEVICE;
 494         }
 495
 496         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
 497         if (qtd == NULL) {
 498                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
 499                 return -DWC_E_NO_MEMORY;
 500         }
 501
 502         retval =
 503             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
 504
 505         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 506         if (retval < 0) {
 507                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
 508                           "Error status %d\n", retval);
 509                 dwc_otg_hcd_qtd_free(qtd);
 510         } else {
 511                 qtd->qh = *ep_handle;
 512         }
 513         intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
 514         if (!intr_mask.b.sofintr && retval == 0) {
 515                 dwc_otg_transaction_type_e tr_type;
 516                 if ((qtd->qh->ep_type == UE_BULK)
 517                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
 518                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
 519                         retval = 0;
 520                         goto out;
 521                 }
 522                 tr_type = dwc_otg_hcd_select_transactions(hcd);
 523                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 524                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
 525                 }
 526         }
 527 out:
 528         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 529         return retval;
 530 }
 531
 532 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
 533                             dwc_otg_hcd_urb_t * dwc_otg_urb)
 534 {
 535         dwc_otg_qh_t *qh;
 536         dwc_otg_qtd_t *urb_qtd;
 537
 538         urb_qtd = dwc_otg_urb->qtd;
 539         if(((uint32_t)urb_qtd&0xf0000000) == 0){
 540                 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
 541                           __func__, urb_qtd, dwc_otg_urb);
 542                 return 0;
 543         }
 544         qh = urb_qtd->qh;
 545 #ifdef DEBUG
 546         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
 547                 if (urb_qtd->in_process) {
 548                         dump_channel_info(hcd, qh);
 549                 }
 550         }
 551 #endif
 552         if (urb_qtd->in_process && qh->channel) {
 553                 /* The QTD is in process (it has been assigned to a channel). */
 554                 if (hcd->flags.b.port_connect_status) {
 555                         /*
 556                          * If still connected (i.e. in host mode), halt the
 557                          * channel so it can be used for other transfers. If
 558                          * no longer connected, the host registers can't be
 559                          * written to halt the channel since the core is in
 560                          * device mode.
 561                          */
 562                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
 563                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
 564                 }
 565         }
 566
 567         /*
 568          * Free the QTD and clean up the associated QH. Leave the QH in the
 569          * schedule if it has any remaining QTDs.
 570          */
 571
 572         if (!hcd->core_if->dma_desc_enable) {
 573                 uint8_t b = urb_qtd->in_process;
 574                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 575                 if (b) {
 576                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
 577                         qh->channel = NULL;
 578                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
 579                         dwc_otg_hcd_qh_remove(hcd, qh);
 580                 }
 581         } else {
 582                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
 583         }
 584         return 0;
 585 }
 586
 587 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
 588                                  int retry)
 589 {
 590         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 591         int retval = 0;
 592         dwc_irqflags_t flags;
 593
 594         if (retry < 0) {
 595                 retval = -DWC_E_INVALID;
 596                 goto done;
 597         }
 598
 599         if (!qh) {
 600                 retval = -DWC_E_INVALID;
 601                 goto done;
 602         }
 603
 604         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 605
 606         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
 607                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 608                 retry--;
 609                 dwc_msleep(5);
 610                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 611         }
 612
 613         dwc_otg_hcd_qh_remove(hcd, qh);
 614
 615         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 616         /*
 617          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
 618          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
 619          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
 620          * and dwc_otg_hcd_frame_list_alloc().
 621          */
 622         dwc_otg_hcd_qh_free(hcd, qh);
 623
 624 done:
 625         return retval;
 626 }
 627
 628 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
 629 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
 630 {
 631         int retval = 0;
 632         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
 633         if (!qh)
 634                 return -DWC_E_INVALID;
 635
 636         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 637         return retval;
 638 }
 639 #endif
 640
 641 /**
 642  * HCD Callback structure for handling mode switching.
 643  */
 644 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 645         .start = dwc_otg_hcd_start_cb,
 646         .stop = dwc_otg_hcd_stop_cb,
 647         .disconnect = dwc_otg_hcd_disconnect_cb,
 648         .session_start = dwc_otg_hcd_session_start_cb,
 649         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
 650 #ifdef CONFIG_USB_DWC_OTG_LPM
 651         .sleep = dwc_otg_hcd_sleep_cb,
 652 #endif
 653         .p = 0,
 654 };
 655
 656 /**
 657  * Reset tasklet function
 658  */
 659 static void reset_tasklet_func(void *data)
 660 {
 661         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
 662         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 663         hprt0_data_t hprt0;
 664
 665         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 666
 667         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 668         hprt0.b.prtrst = 1;
 669         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 670         dwc_mdelay(60);
 671
 672         hprt0.b.prtrst = 0;
 673         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 674         dwc_otg_hcd->flags.b.port_reset_change = 1;
 675 }
 676
 677 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
 678 {
 679         dwc_list_link_t *item;
 680         dwc_otg_qh_t *qh;
 681         dwc_irqflags_t flags;
 682
 683         if (!qh_list->next) {
 684                 /* The list hasn't been initialized yet. */
 685                 return;
 686         }
 687         /*
 688          * Hold spinlock here. Not needed in that case if bellow
 689          * function is being called from ISR
 690          */
 691         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
 692         /* Ensure there are no QTDs or URBs left. */
 693         kill_urbs_in_qh_list(hcd, qh_list);
 694         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
 695
 696         DWC_LIST_FOREACH(item, qh_list) {
 697                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
 698                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
 699         }
 700 }
 701
 702 /**
 703  * Exit from Hibernation if Host did not detect SRP from connected SRP capable
 704  * Device during SRP time by host power up.
 705  */
 706 void dwc_otg_hcd_power_up(void *ptr)
 707 {
 708         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 709         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
 710
 711         DWC_PRINTF("%s called\n", __FUNCTION__);
 712
 713         if (!core_if->hibernation_suspend) {
 714                 DWC_PRINTF("Already exited from Hibernation\n");
 715                 return;
 716         }
 717
 718         /* Switch on the voltage to the core */
 719         gpwrdn.b.pwrdnswtch = 1;
 720         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 721         dwc_udelay(10);
 722
 723         /* Reset the core */
 724         gpwrdn.d32 = 0;
 725         gpwrdn.b.pwrdnrstn = 1;
 726         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 727         dwc_udelay(10);
 728
 729         /* Disable power clamps */
 730         gpwrdn.d32 = 0;
 731         gpwrdn.b.pwrdnclmp = 1;
 732         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 733
 734         /* Remove reset the core signal */
 735         gpwrdn.d32 = 0;
 736         gpwrdn.b.pwrdnrstn = 1;
 737         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 738         dwc_udelay(10);
 739
 740         /* Disable PMU interrupt */
 741         gpwrdn.d32 = 0;
 742         gpwrdn.b.pmuintsel = 1;
 743         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 744
 745         core_if->hibernation_suspend = 0;
 746
 747         /* Disable PMU */
 748         gpwrdn.d32 = 0;
 749         gpwrdn.b.pmuactv = 1;
 750         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 751         dwc_udelay(10);
 752
 753         /* Enable VBUS */
 754         gpwrdn.d32 = 0;
 755         gpwrdn.b.dis_vbus = 1;
 756         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 757
 758         core_if->op_state = A_HOST;
 759         dwc_otg_core_init(core_if);
 760         dwc_otg_enable_global_interrupts(core_if);
 761         cil_hcd_start(core_if);
 762 }
 763
 764 /**
 765  * Frees secondary storage associated with the dwc_otg_hcd structure contained
 766  * in the struct usb_hcd field.
 767  */
 768 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
 769 {
 770         int i;
 771
 772         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
 773
 774         del_timers(dwc_otg_hcd);
 775
 776         /* Free memory for QH/QTD lists */
 777         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
 778         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
 779         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
 780         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
 781         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
 782         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
 783
 784         /* Free memory for the host channels. */
 785         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 786                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
 787
 788 #ifdef DEBUG
 789                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
 790                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 791                 }
 792 #endif
 793                 if (hc != NULL) {
 794                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
 795                                     i, hc);
 796                         DWC_FREE(hc);
 797                 }
 798         }
 799
 800         if (dwc_otg_hcd->core_if->dma_enable) {
 801                 if (dwc_otg_hcd->status_buf_dma) {
 802                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
 803                                      dwc_otg_hcd->status_buf,
 804                                      dwc_otg_hcd->status_buf_dma);
 805                 }
 806         } else if (dwc_otg_hcd->status_buf != NULL) {
 807                 DWC_FREE(dwc_otg_hcd->status_buf);
 808         }
 809         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
 810         /* Set core_if's lock pointer to NULL */
 811         dwc_otg_hcd->core_if->lock = NULL;
 812
 813         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
 814         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
 815
 816 #ifdef DWC_DEV_SRPCAP
 817         if (dwc_otg_hcd->core_if->power_down == 2 &&
 818             dwc_otg_hcd->core_if->pwron_timer) {
 819                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
 820         }
 821 #endif
 822         DWC_FREE(dwc_otg_hcd);
 823 }
 824
 825 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
 826 {
 827         int retval = 0;
 828         int num_channels;
 829         int i;
 830         dwc_hc_t *channel;
 831
 832         hcd->lock = DWC_SPINLOCK_ALLOC();
 833         if (!hcd->lock) {
 834                 DWC_ERROR("Could not allocate lock for pcd");
 835                 DWC_FREE(hcd);
 836                 retval = -DWC_E_NO_MEMORY;
 837                 goto out;
 838         }
 839         hcd->core_if = core_if;
 840
 841         /* Register the HCD CIL Callbacks */
 842         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
 843                                            &hcd_cil_callbacks, hcd);
 844
 845         /* Initialize the non-periodic schedule. */
 846         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
 847         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
 848
 849         /* Initialize the periodic schedule. */
 850         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
 851         DWC_LIST_INIT(&hcd->periodic_sched_ready);
 852         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
 853         DWC_LIST_INIT(&hcd->periodic_sched_queued);
 854
 855         /*
 856          * Create a host channel descriptor for each host channel implemented
 857          * in the controller. Initialize the channel descriptor array.
 858          */
 859         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
 860         num_channels = hcd->core_if->core_params->host_channels;
 861         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
 862         for (i = 0; i < num_channels; i++) {
 863                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
 864                 if (channel == NULL) {
 865                         retval = -DWC_E_NO_MEMORY;
 866                         DWC_ERROR("%s: host channel allocation failed\n",
 867                                   __func__);
 868                         dwc_otg_hcd_free(hcd);
 869                         goto out;
 870                 }
 871                 channel->hc_num = i;
 872                 hcd->hc_ptr_array[i] = channel;
 873 #ifdef DEBUG
 874                 hcd->core_if->hc_xfer_timer[i] =
 875                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
 876                                     &hcd->core_if->hc_xfer_info[i]);
 877 #endif
 878                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
 879                             channel);
 880         }
 881
 882         /* Initialize the Connection timeout timer. */
 883         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
 884                                           dwc_otg_hcd_connect_timeout, hcd);
 885
 886         /* Initialize reset tasklet. */
 887         hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
 888 #ifdef DWC_DEV_SRPCAP
 889         if (hcd->core_if->power_down == 2) {
 890                 /* Initialize Power on timer for Host power up in case hibernation */
 891                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
 892                                                                         dwc_otg_hcd_power_up, core_if);
 893         }
 894 #endif
 895
 896         /*
 897          * Allocate space for storing data on status transactions. Normally no
 898          * data is sent, but this space acts as a bit bucket. This must be
 899          * done after usb_add_hcd since that function allocates the DMA buffer
 900          * pool.
 901          */
 902         if (hcd->core_if->dma_enable) {
 903                 hcd->status_buf =
 904                     DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
 905                                   &hcd->status_buf_dma);
 906         } else {
 907                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
 908         }
 909         if (!hcd->status_buf) {
 910                 retval = -DWC_E_NO_MEMORY;
 911                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 912                 dwc_otg_hcd_free(hcd);
 913                 goto out;
 914         }
 915
 916         hcd->otg_port = 1;
 917         hcd->frame_list = NULL;
 918         hcd->frame_list_dma = 0;
 919         hcd->periodic_qh_count = 0;
 920 out:
 921         return retval;
 922 }
 923
 924 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
 925 {
 926         /* Turn off all host-specific interrupts. */
 927         dwc_otg_disable_host_interrupts(hcd->core_if);
 928
 929         dwc_otg_hcd_free(hcd);
 930 }
 931
 932 /**
 933  * Initializes dynamic portions of the DWC_otg HCD state.
 934  */
 935 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
 936 {
 937         int num_channels;
 938         int i;
 939         dwc_hc_t *channel;
 940         dwc_hc_t *channel_tmp;
 941
 942         hcd->flags.d32 = 0;
 943
 944         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
 945         hcd->non_periodic_channels = 0;
 946         hcd->periodic_channels = 0;
 947
 948         /*
 949          * Put all channels in the free channel list and clean up channel
 950          * states.
 951          */
 952         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
 953                                  &hcd->free_hc_list, hc_list_entry) {
 954                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
 955         }
 956
 957         num_channels = hcd->core_if->core_params->host_channels;
 958         for (i = 0; i < num_channels; i++) {
 959                 channel = hcd->hc_ptr_array[i];
 960                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
 961                                         hc_list_entry);
 962                 dwc_otg_hc_cleanup(hcd->core_if, channel);
 963         }
 964
 965         /* Initialize the DWC core for host mode operation. */
 966         dwc_otg_core_host_init(hcd->core_if);
 967
 968         /* Set core_if's lock pointer to the hcd->lock */
 969         hcd->core_if->lock = hcd->lock;
 970 }
 971
 972 /**
 973  * Assigns transactions from a QTD to a free host channel and initializes the
 974  * host channel to perform the transactions. The host channel is removed from
 975  * the free list.
 976  *
 977  * @param hcd The HCD state structure.
 978  * @param qh Transactions from the first QTD for this QH are selected and
 979  * assigned to a free host channel.
 980  */
 981 static int assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
 982 {
 983         dwc_hc_t *hc;
 984         dwc_otg_qtd_t *qtd;
 985         dwc_otg_hcd_urb_t *urb;
 986         void* ptr = NULL;
 987         int  retval = 0;
 988
 989         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
 990
 991         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
 992
 993         /* Remove the host channel from the free list. */
 994         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
 995
 996         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 997
 998         urb = qtd->urb;
 999         if (urb == NULL){
1000                 printk("%s : urb is NULL\n", __func__);
1001                 retval = -EINVAL;
1002                 return retval;
1003         }
1004
1005         qh->channel = hc;
1006
1007         qtd->in_process = 1;
1008
1009         /*
1010          * Use usb_pipedevice to determine device address. This address is
1011          * 0 before the SET_ADDRESS command and the correct address afterward.
1012          */
1013         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1014         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1015         hc->speed = qh->dev_speed;
1016         hc->max_packet = dwc_max_packet(qh->maxp);
1017
1018         hc->xfer_started = 0;
1019         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1020         hc->error_state = (qtd->error_count > 0);
1021         hc->halt_on_queue = 0;
1022         hc->halt_pending = 0;
1023         hc->requests = 0;
1024
1025         /*
1026          * The following values may be modified in the transfer type section
1027          * below. The xfer_len value may be reduced when the transfer is
1028          * started to accommodate the max widths of the XferSize and PktCnt
1029          * fields in the HCTSIZn register.
1030          */
1031
1032         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1033         if (hc->ep_is_in) {
1034                 hc->do_ping = 0;
1035         } else {
1036                 hc->do_ping = qh->ping_state;
1037         }
1038
1039         hc->data_pid_start = qh->data_toggle;
1040         hc->multi_count = 1;
1041
1042         if (hcd->core_if->dma_enable) {
1043                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1044
1045                 /* For non-dword aligned case */
1046                 if (((unsigned long)hc->xfer_buff & 0x3)
1047                     && !hcd->core_if->dma_desc_enable) {
1048                         ptr = (uint8_t *) urb->buf + urb->actual_length;
1049                 }
1050         } else {
1051                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1052         }
1053         hc->xfer_len = urb->length - urb->actual_length;
1054         hc->xfer_count = 0;
1055
1056         /*
1057          * Set the split attributes
1058          */
1059         hc->do_split = 0;
1060         if (qh->do_split) {
1061                 uint32_t hub_addr, port_addr;
1062                 hc->do_split = 1;
1063                 hc->xact_pos = qtd->isoc_split_pos;
1064                 hc->complete_split = qtd->complete_split;
1065                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1066                 hc->hub_addr = (uint8_t) hub_addr;
1067                 hc->port_addr = (uint8_t) port_addr;
1068         }
1069
1070         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1071         case UE_CONTROL:
1072                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1073                 switch (qtd->control_phase) {
1074                 case DWC_OTG_CONTROL_SETUP:
1075                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
1076                         hc->do_ping = 0;
1077                         hc->ep_is_in = 0;
1078                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1079                         if (hcd->core_if->dma_enable) {
1080                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1081                         } else {
1082                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1083                         }
1084                         hc->xfer_len = 8;
1085                         ptr = NULL;
1086                         break;
1087                 case DWC_OTG_CONTROL_DATA:
1088                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
1089                         hc->data_pid_start = qtd->data_toggle;
1090                         break;
1091                 case DWC_OTG_CONTROL_STATUS:
1092                         /*
1093                          * Direction is opposite of data direction or IN if no
1094                          * data.
1095                          */
1096                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
1097                         if (urb->length == 0) {
1098                                 hc->ep_is_in = 1;
1099                         } else {
1100                                 hc->ep_is_in =
1101                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1102                         }
1103                         if (hc->ep_is_in) {
1104                                 hc->do_ping = 0;
1105                         }
1106
1107                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1108
1109                         hc->xfer_len = 0;
1110                         if (hcd->core_if->dma_enable) {
1111                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1112                         } else {
1113                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1114                         }
1115                         ptr = NULL;
1116                         break;
1117                 }
1118                 break;
1119         case UE_BULK:
1120                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1121                 break;
1122         case UE_INTERRUPT:
1123                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1124                 break;
1125         case UE_ISOCHRONOUS:
1126                 {
1127                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1128
1129                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1130
1131                         if (hcd->core_if->dma_desc_enable)
1132                                 break;
1133
1134                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1135
1136                         frame_desc->status = 0;
1137
1138                         if (hcd->core_if->dma_enable) {
1139                                 hc->xfer_buff = (uint8_t *) urb->dma;
1140                         } else {
1141                                 hc->xfer_buff = (uint8_t *) urb->buf;
1142                         }
1143                         hc->xfer_buff +=
1144                             frame_desc->offset + qtd->isoc_split_offset;
1145                         hc->xfer_len =
1146                             frame_desc->length - qtd->isoc_split_offset;
1147
1148                         /* For non-dword aligned buffers */
1149                         if (((unsigned long)hc->xfer_buff & 0x3)
1150                             && hcd->core_if->dma_enable) {
1151                                 ptr =
1152                                     (uint8_t *) urb->buf + frame_desc->offset +
1153                                     qtd->isoc_split_offset;
1154                         } else
1155                                 ptr = NULL;
1156
1157                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1158                                 if (hc->xfer_len <= 188) {
1159                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1160                                 } else {
1161                                         hc->xact_pos =
1162                                             DWC_HCSPLIT_XACTPOS_BEGIN;
1163                                 }
1164                         }
1165                 }
1166                 break;
1167         }
1168         /* non DWORD-aligned buffer case */
1169         if (ptr) {
1170                 uint32_t buf_size;
1171                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1172                         buf_size = hcd->core_if->core_params->max_transfer_size;
1173                 } else {
1174                         buf_size = 4096;
1175                 }
1176                 if (!qh->dw_align_buf) {
1177                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1178                                                          &qh->dw_align_buf_dma);
1179                         if (!qh->dw_align_buf) {
1180                                 DWC_ERROR
1181                                     ("%s: Failed to allocate memory to handle "
1182                                      "non-dword aligned buffer case\n",
1183                                      __func__);
1184                                 return retval;
1185                         }
1186                 }
1187                 if (!hc->ep_is_in) {
1188                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1189                 }
1190                 hc->align_buff = qh->dw_align_buf_dma;
1191         } else {
1192                 hc->align_buff = 0;
1193         }
1194
1195         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1196             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1197                 /*
1198                  * This value may be modified when the transfer is started to
1199                  * reflect the actual transfer length.
1200                  */
1201                 hc->multi_count = dwc_hb_mult(qh->maxp);
1202         }
1203
1204         if (hcd->core_if->dma_desc_enable)
1205                 hc->desc_list_addr = qh->desc_list_dma;
1206
1207         dwc_otg_hc_init(hcd->core_if, hc);
1208         hc->qh = qh;
1209         return retval;
1210 }
1211
1212 /**
1213  * This function selects transactions from the HCD transfer schedule and
1214  * assigns them to available host channels. It is called from HCD interrupt
1215  * handler functions.
1216  *
1217  * @param hcd The HCD state structure.
1218  *
1219  * @return The types of new transactions that were assigned to host channels.
1220  */
1221 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
1222 {
1223         dwc_list_link_t *qh_ptr;
1224         dwc_otg_qh_t *qh;
1225         int num_channels;
1226         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1227         int err;
1228
1229 #ifdef DEBUG_SOF
1230         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
1231 #endif
1232
1233         /* Process entries in the periodic ready list. */
1234         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1235
1236         while (qh_ptr != &hcd->periodic_sched_ready &&
1237                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1238
1239                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1240                 assign_and_init_hc(hcd, qh);
1241
1242                 /*
1243                  * Move the QH from the periodic ready schedule to the
1244                  * periodic assigned schedule.
1245                  */
1246                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1247                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1248                                    &qh->qh_list_entry);
1249
1250                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1251         }
1252
1253         /*
1254          * Process entries in the inactive portion of the non-periodic
1255          * schedule. Some free host channels may not be used if they are
1256          * reserved for periodic transfers.
1257          */
1258         qh_ptr = hcd->non_periodic_sched_inactive.next;
1259         num_channels = hcd->core_if->core_params->host_channels;
1260         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1261                (hcd->non_periodic_channels <
1262                 num_channels - hcd->periodic_channels) &&
1263                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1264
1265                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1266
1267                 err = assign_and_init_hc(hcd, qh);
1268
1269                 /*
1270                  * Move the QH from the non-periodic inactive schedule to the
1271                  * non-periodic active schedule.
1272                  */
1273                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1274                 if (err != 0)
1275                         continue;
1276                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1277                                    &qh->qh_list_entry);
1278
1279                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1280                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1281                 } else {
1282                         ret_val = DWC_OTG_TRANSACTION_ALL;
1283                 }
1284
1285                 hcd->non_periodic_channels++;
1286         }
1287
1288         return ret_val;
1289 }
1290
1291 /**
1292  * Attempts to queue a single transaction request for a host channel
1293  * associated with either a periodic or non-periodic transfer. This function
1294  * assumes that there is space available in the appropriate request queue. For
1295  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1296  * is available in the appropriate Tx FIFO.
1297  *
1298  * @param hcd The HCD state structure.
1299  * @param hc Host channel descriptor associated with either a periodic or
1300  * non-periodic transfer.
1301  * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1302  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1303  * transfers.
1304  *
1305  * @return 1 if a request is queued and more requests may be needed to
1306  * complete the transfer, 0 if no more requests are required for this
1307  * transfer, -1 if there is insufficient space in the Tx FIFO.
1308  */
1309 static int queue_transaction(dwc_otg_hcd_t * hcd,
1310                              dwc_hc_t * hc, uint16_t fifo_dwords_avail)
1311 {
1312         int retval;
1313
1314         if (hcd->core_if->dma_enable) {
1315                 if (hcd->core_if->dma_desc_enable) {
1316                         if (!hc->xfer_started
1317                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1318                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1319                                 hc->qh->ping_state = 0;
1320                         }
1321                 } else if (!hc->xfer_started) {
1322                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1323                         hc->qh->ping_state = 0;
1324                 }
1325                 retval = 0;
1326         } else if (hc->halt_pending) {
1327                 /* Don't queue a request if the channel has been halted. */
1328                 retval = 0;
1329         } else if (hc->halt_on_queue) {
1330                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1331                 retval = 0;
1332         } else if (hc->do_ping) {
1333                 if (!hc->xfer_started) {
1334                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1335                 }
1336                 retval = 0;
1337         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1338                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1339                         if (!hc->xfer_started) {
1340                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1341                                 retval = 1;
1342                         } else {
1343                                 retval =
1344                                     dwc_otg_hc_continue_transfer(hcd->core_if,
1345                                                                  hc);
1346                         }
1347                 } else {
1348                         retval = -1;
1349                 }
1350         } else {
1351                 if (!hc->xfer_started) {
1352                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
1353                         retval = 1;
1354                 } else {
1355                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1356                 }
1357         }
1358
1359         return retval;
1360 }
1361
1362 /**
1363  * Processes periodic channels for the next frame and queues transactions for
1364  * these channels to the DWC_otg controller. After queueing transactions, the
1365  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1366  * to queue as Periodic Tx FIFO or request queue space becomes available.
1367  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1368  */
1369 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
1370 {
1371         hptxsts_data_t tx_status;
1372         dwc_list_link_t *qh_ptr;
1373         dwc_otg_qh_t *qh;
1374         int status;
1375         int no_queue_space = 0;
1376         int no_fifo_space = 0;
1377
1378         dwc_otg_host_global_regs_t *host_regs;
1379         host_regs = hcd->core_if->host_if->host_global_regs;
1380
1381         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1382 #ifdef DEBUG
1383         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1384         DWC_DEBUGPL(DBG_HCDV,
1385                     "  P Tx Req Queue Space Avail (before queue): %d\n",
1386                     tx_status.b.ptxqspcavail);
1387         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
1388                     tx_status.b.ptxfspcavail);
1389 #endif
1390
1391         qh_ptr = hcd->periodic_sched_assigned.next;
1392         while (qh_ptr != &hcd->periodic_sched_assigned) {
1393                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1394                 if (tx_status.b.ptxqspcavail == 0) {
1395                         no_queue_space = 1;
1396                         break;
1397                 }
1398
1399                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1400
1401                 /*
1402                  * Set a flag if we're queuing high-bandwidth in slave mode.
1403                  * The flag prevents any halts to get into the request queue in
1404                  * the middle of multiple high-bandwidth packets getting queued.
1405                  */
1406                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1407                         hcd->core_if->queuing_high_bandwidth = 1;
1408                 }
1409                 status =
1410                     queue_transaction(hcd, qh->channel,
1411                                       tx_status.b.ptxfspcavail);
1412                 if (status < 0) {
1413                         no_fifo_space = 1;
1414                         break;
1415                 }
1416
1417                 /*
1418                  * In Slave mode, stay on the current transfer until there is
1419                  * nothing more to do or the high-bandwidth request count is
1420                  * reached. In DMA mode, only need to queue one request. The
1421                  * controller automatically handles multiple packets for
1422                  * high-bandwidth transfers.
1423                  */
1424                 if (hcd->core_if->dma_enable || status == 0 ||
1425                     qh->channel->requests == qh->channel->multi_count) {
1426                         qh_ptr = qh_ptr->next;
1427                         /*
1428                          * Move the QH from the periodic assigned schedule to
1429                          * the periodic queued schedule.
1430                          */
1431                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1432                                            &qh->qh_list_entry);
1433
1434                         /* done queuing high bandwidth */
1435                         hcd->core_if->queuing_high_bandwidth = 0;
1436                 }
1437         }
1438
1439         if (!hcd->core_if->dma_enable) {
1440                 dwc_otg_core_global_regs_t *global_regs;
1441                 gintmsk_data_t intr_mask = {.d32 = 0 };
1442
1443                 global_regs = hcd->core_if->core_global_regs;
1444                 intr_mask.b.ptxfempty = 1;
1445 #ifdef DEBUG
1446                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1447                 DWC_DEBUGPL(DBG_HCDV,
1448                             "  P Tx Req Queue Space Avail (after queue): %d\n",
1449                             tx_status.b.ptxqspcavail);
1450                 DWC_DEBUGPL(DBG_HCDV,
1451                             "  P Tx FIFO Space Avail (after queue): %d\n",
1452                             tx_status.b.ptxfspcavail);
1453 #endif
1454                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1455                     no_queue_space || no_fifo_space) {
1456                         /*
1457                          * May need to queue more transactions as the request
1458                          * queue or Tx FIFO empties. Enable the periodic Tx
1459                          * FIFO empty interrupt. (Always use the half-empty
1460                          * level to ensure that new requests are loaded as
1461                          * soon as possible.)
1462                          */
1463                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1464                                          intr_mask.d32);
1465                 } else {
1466                         /*
1467                          * Disable the Tx FIFO empty interrupt since there are
1468                          * no more transactions that need to be queued right
1469                          * now. This function is called from interrupt
1470                          * handlers to queue more transactions as transfer
1471                          * states change.
1472                          */
1473                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1474                                          0);
1475                 }
1476         }
1477 }
1478
1479 /**
1480  * Processes active non-periodic channels and queues transactions for these
1481  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1482  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1483  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1484  * FIFO Empty interrupt is disabled.
1485  */
1486 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
1487 {
1488         gnptxsts_data_t tx_status;
1489         dwc_list_link_t *orig_qh_ptr;
1490         dwc_otg_qh_t *qh;
1491         int status;
1492         int no_queue_space = 0;
1493         int no_fifo_space = 0;
1494         int more_to_do = 0;
1495
1496         dwc_otg_core_global_regs_t *global_regs =
1497             hcd->core_if->core_global_regs;
1498
1499         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1500 #ifdef DEBUG
1501         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1502         DWC_DEBUGPL(DBG_HCDV,
1503                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
1504                     tx_status.b.nptxqspcavail);
1505         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
1506                     tx_status.b.nptxfspcavail);
1507 #endif
1508         /*
1509          * Keep track of the starting point. Skip over the start-of-list
1510          * entry.
1511          */
1512         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1513                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1514         }
1515         orig_qh_ptr = hcd->non_periodic_qh_ptr;
1516
1517         /*
1518          * Process once through the active list or until no more space is
1519          * available in the request queue or the Tx FIFO.
1520          */
1521         do {
1522                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1523                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1524                         no_queue_space = 1;
1525                         break;
1526                 }
1527
1528                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1529                                     qh_list_entry);
1530                 status =
1531                     queue_transaction(hcd, qh->channel,
1532                                       tx_status.b.nptxfspcavail);
1533
1534                 if (status > 0) {
1535                         more_to_do = 1;
1536                 } else if (status < 0) {
1537                         no_fifo_space = 1;
1538                         break;
1539                 }
1540
1541                 /* Advance to next QH, skipping start-of-list entry. */
1542                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1543                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1544                         hcd->non_periodic_qh_ptr =
1545                             hcd->non_periodic_qh_ptr->next;
1546                 }
1547
1548         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1549
1550         if (!hcd->core_if->dma_enable) {
1551                 gintmsk_data_t intr_mask = {.d32 = 0 };
1552                 intr_mask.b.nptxfempty = 1;
1553
1554 #ifdef DEBUG
1555                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1556                 DWC_DEBUGPL(DBG_HCDV,
1557                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
1558                             tx_status.b.nptxqspcavail);
1559                 DWC_DEBUGPL(DBG_HCDV,
1560                             "  NP Tx FIFO Space Avail (after queue): %d\n",
1561                             tx_status.b.nptxfspcavail);
1562 #endif
1563                 if (more_to_do || no_queue_space || no_fifo_space) {
1564                         /*
1565                          * May need to queue more transactions as the request
1566                          * queue or Tx FIFO empties. Enable the non-periodic
1567                          * Tx FIFO empty interrupt. (Always use the half-empty
1568                          * level to ensure that new requests are loaded as
1569                          * soon as possible.)
1570                          */
1571                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1572                                          intr_mask.d32);
1573                 } else {
1574                         /*
1575                          * Disable the Tx FIFO empty interrupt since there are
1576                          * no more transactions that need to be queued right
1577                          * now. This function is called from interrupt
1578                          * handlers to queue more transactions as transfer
1579                          * states change.
1580                          */
1581                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1582                                          0);
1583                 }
1584         }
1585 }
1586
1587 /**
1588  * This function processes the currently active host channels and queues
1589  * transactions for these channels to the DWC_otg controller. It is called
1590  * from HCD interrupt handler functions.
1591  *
1592  * @param hcd The HCD state structure.
1593  * @param tr_type The type(s) of transactions to queue (non-periodic,
1594  * periodic, or both).
1595  */
1596 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
1597                                     dwc_otg_transaction_type_e tr_type)
1598 {
1599 #ifdef DEBUG_SOF
1600         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1601 #endif
1602         /* Process host channels associated with periodic transfers. */
1603         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1604              tr_type == DWC_OTG_TRANSACTION_ALL) &&
1605             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1606
1607                 process_periodic_channels(hcd);
1608         }
1609
1610         /* Process host channels associated with non-periodic transfers. */
1611         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1612             tr_type == DWC_OTG_TRANSACTION_ALL) {
1613                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1614                         process_non_periodic_channels(hcd);
1615                 } else {
1616                         /*
1617                          * Ensure NP Tx FIFO empty interrupt is disabled when
1618                          * there are no non-periodic transfers to process.
1619                          */
1620                         gintmsk_data_t gintmsk = {.d32 = 0 };
1621                         gintmsk.b.nptxfempty = 1;
1622                         DWC_MODIFY_REG32(&hcd->core_if->
1623                                          core_global_regs->gintmsk, gintmsk.d32,
1624                                          0);
1625                 }
1626         }
1627 }
1628
1629 #ifdef DWC_HS_ELECT_TST
1630 /*
1631  * Quick and dirty hack to implement the HS Electrical Test
1632  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1633  *
1634  * This code was copied from our userspace app "hset". It sends a
1635  * Get Device Descriptor control sequence in two parts, first the
1636  * Setup packet by itself, followed some time later by the In and
1637  * Ack packets. Rather than trying to figure out how to add this
1638  * functionality to the normal driver code, we just hijack the
1639  * hardware, using these two function to drive the hardware
1640  * directly.
1641  */
1642
1643 static dwc_otg_core_global_regs_t *global_regs;
1644 static dwc_otg_host_global_regs_t *hc_global_regs;
1645 static dwc_otg_hc_regs_t *hc_regs;
1646 static uint32_t *data_fifo;
1647
1648 static void do_setup(void)
1649 {
1650         gintsts_data_t gintsts;
1651         hctsiz_data_t hctsiz;
1652         hcchar_data_t hcchar;
1653         haint_data_t haint;
1654         hcint_data_t hcint;
1655
1656         /* Enable HAINTs */
1657         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1658
1659         /* Enable HCINTs */
1660         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1661
1662         /* Read GINTSTS */
1663         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1664
1665         /* Read HAINT */
1666         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1667
1668         /* Read HCINT */
1669         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1670
1671         /* Read HCCHAR */
1672         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1673
1674         /* Clear HCINT */
1675         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1676
1677         /* Clear HAINT */
1678         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1679
1680         /* Clear GINTSTS */
1681         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1682
1683         /* Read GINTSTS */
1684         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1685
1686         /*
1687          * Send Setup packet (Get Device Descriptor)
1688          */
1689
1690         /* Make sure channel is disabled */
1691         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1692         if (hcchar.b.chen) {
1693                 hcchar.b.chdis = 1;
1694 //              hcchar.b.chen = 1;
1695                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1696                 //sleep(1);
1697                 dwc_mdelay(1000);
1698
1699                 /* Read GINTSTS */
1700                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1701
1702                 /* Read HAINT */
1703                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1704
1705                 /* Read HCINT */
1706                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1707
1708                 /* Read HCCHAR */
1709                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1710
1711                 /* Clear HCINT */
1712                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1713
1714                 /* Clear HAINT */
1715                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1716
1717                 /* Clear GINTSTS */
1718                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1719
1720                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1721         }
1722
1723         /* Set HCTSIZ */
1724         hctsiz.d32 = 0;
1725         hctsiz.b.xfersize = 8;
1726         hctsiz.b.pktcnt = 1;
1727         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1728         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1729
1730         /* Set HCCHAR */
1731         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1732         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1733         hcchar.b.epdir = 0;
1734         hcchar.b.epnum = 0;
1735         hcchar.b.mps = 8;
1736         hcchar.b.chen = 1;
1737         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1738
1739         /* Fill FIFO with Setup data for Get Device Descriptor */
1740         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1741         DWC_WRITE_REG32(data_fifo++, 0x01000680);
1742         DWC_WRITE_REG32(data_fifo++, 0x00080000);
1743
1744         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1745
1746         /* Wait for host channel interrupt */
1747         do {
1748                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1749         } while (gintsts.b.hcintr == 0);
1750
1751         /* Disable HCINTs */
1752         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1753
1754         /* Disable HAINTs */
1755         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1756
1757         /* Read HAINT */
1758         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1759
1760         /* Read HCINT */
1761         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1762
1763         /* Read HCCHAR */
1764         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1765
1766         /* Clear HCINT */
1767         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1768
1769         /* Clear HAINT */
1770         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1771
1772         /* Clear GINTSTS */
1773         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1774
1775         /* Read GINTSTS */
1776         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1777 }
1778
1779 static void do_in_ack(void)
1780 {
1781         gintsts_data_t gintsts;
1782         hctsiz_data_t hctsiz;
1783         hcchar_data_t hcchar;
1784         haint_data_t haint;
1785         hcint_data_t hcint;
1786         host_grxsts_data_t grxsts;
1787
1788         /* Enable HAINTs */
1789         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1790
1791         /* Enable HCINTs */
1792         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1793
1794         /* Read GINTSTS */
1795         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1796
1797         /* Read HAINT */
1798         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1799
1800         /* Read HCINT */
1801         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1802
1803         /* Read HCCHAR */
1804         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1805
1806         /* Clear HCINT */
1807         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1808
1809         /* Clear HAINT */
1810         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1811
1812         /* Clear GINTSTS */
1813         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1814
1815         /* Read GINTSTS */
1816         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1817
1818         /*
1819          * Receive Control In packet
1820          */
1821
1822         /* Make sure channel is disabled */
1823         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1824         if (hcchar.b.chen) {
1825                 hcchar.b.chdis = 1;
1826                 hcchar.b.chen = 1;
1827                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1828                 //sleep(1);
1829                 dwc_mdelay(1000);
1830
1831                 /* Read GINTSTS */
1832                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1833
1834                 /* Read HAINT */
1835                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1836
1837                 /* Read HCINT */
1838                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1839
1840                 /* Read HCCHAR */
1841                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1842
1843                 /* Clear HCINT */
1844                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1845
1846                 /* Clear HAINT */
1847                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1848
1849                 /* Clear GINTSTS */
1850                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1851
1852                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1853         }
1854
1855         /* Set HCTSIZ */
1856         hctsiz.d32 = 0;
1857         hctsiz.b.xfersize = 8;
1858         hctsiz.b.pktcnt = 1;
1859         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1860         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1861
1862         /* Set HCCHAR */
1863         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1864         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1865         hcchar.b.epdir = 1;
1866         hcchar.b.epnum = 0;
1867         hcchar.b.mps = 8;
1868         hcchar.b.chen = 1;
1869         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1870
1871         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1872
1873         /* Wait for receive status queue interrupt */
1874         do {
1875                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1876         } while (gintsts.b.rxstsqlvl == 0);
1877
1878         /* Read RXSTS */
1879         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1880
1881         /* Clear RXSTSQLVL in GINTSTS */
1882         gintsts.d32 = 0;
1883         gintsts.b.rxstsqlvl = 1;
1884         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1885
1886         switch (grxsts.b.pktsts) {
1887         case DWC_GRXSTS_PKTSTS_IN:
1888                 /* Read the data into the host buffer */
1889                 if (grxsts.b.bcnt > 0) {
1890                         int i;
1891                         int word_count = (grxsts.b.bcnt + 3) / 4;
1892
1893                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1894
1895                         for (i = 0; i < word_count; i++) {
1896                                 (void)DWC_READ_REG32(data_fifo++);
1897                         }
1898                 }
1899                 break;
1900
1901         default:
1902                 break;
1903         }
1904
1905         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1906
1907         /* Wait for receive status queue interrupt */
1908         do {
1909                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1910         } while (gintsts.b.rxstsqlvl == 0);
1911
1912         /* Read RXSTS */
1913         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1914
1915         /* Clear RXSTSQLVL in GINTSTS */
1916         gintsts.d32 = 0;
1917         gintsts.b.rxstsqlvl = 1;
1918         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1919
1920         switch (grxsts.b.pktsts) {
1921         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1922                 break;
1923
1924         default:
1925                 break;
1926         }
1927
1928         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1929
1930         /* Wait for host channel interrupt */
1931         do {
1932                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1933         } while (gintsts.b.hcintr == 0);
1934
1935         /* Read HAINT */
1936         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1937
1938         /* Read HCINT */
1939         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1940
1941         /* Read HCCHAR */
1942         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1943
1944         /* Clear HCINT */
1945         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1946
1947         /* Clear HAINT */
1948         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1949
1950         /* Clear GINTSTS */
1951         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1952
1953         /* Read GINTSTS */
1954         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1955
1956 //      usleep(100000);
1957 //      mdelay(100);
1958         dwc_mdelay(1);
1959
1960         /*
1961          * Send handshake packet
1962          */
1963
1964         /* Read HAINT */
1965         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1966
1967         /* Read HCINT */
1968         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1969
1970         /* Read HCCHAR */
1971         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1972
1973         /* Clear HCINT */
1974         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1975
1976         /* Clear HAINT */
1977         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1978
1979         /* Clear GINTSTS */
1980         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1981
1982         /* Read GINTSTS */
1983         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1984
1985         /* Make sure channel is disabled */
1986         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1987         if (hcchar.b.chen) {
1988                 hcchar.b.chdis = 1;
1989                 hcchar.b.chen = 1;
1990                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1991                 //sleep(1);
1992                 dwc_mdelay(1000);
1993
1994                 /* Read GINTSTS */
1995                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1996
1997                 /* Read HAINT */
1998                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1999
2000                 /* Read HCINT */
2001                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2002
2003                 /* Read HCCHAR */
2004                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2005
2006                 /* Clear HCINT */
2007                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2008
2009                 /* Clear HAINT */
2010                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2011
2012                 /* Clear GINTSTS */
2013                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2014
2015                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2016         }
2017
2018         /* Set HCTSIZ */
2019         hctsiz.d32 = 0;
2020         hctsiz.b.xfersize = 0;
2021         hctsiz.b.pktcnt = 1;
2022         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2023         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2024
2025         /* Set HCCHAR */
2026         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2027         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2028         hcchar.b.epdir = 0;
2029         hcchar.b.epnum = 0;
2030         hcchar.b.mps = 8;
2031         hcchar.b.chen = 1;
2032         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2033
2034         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2035
2036         /* Wait for host channel interrupt */
2037         do {
2038                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2039         } while (gintsts.b.hcintr == 0);
2040
2041         /* Disable HCINTs */
2042         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2043
2044         /* Disable HAINTs */
2045         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2046
2047         /* Read HAINT */
2048         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2049
2050         /* Read HCINT */
2051         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2052
2053         /* Read HCCHAR */
2054         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2055
2056         /* Clear HCINT */
2057         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2058
2059         /* Clear HAINT */
2060         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2061
2062         /* Clear GINTSTS */
2063         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2064
2065         /* Read GINTSTS */
2066         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2067 }
2068 #endif
2069
2070 /** Handles hub class-specific requests. */
2071 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
2072                             uint16_t typeReq,
2073                             uint16_t wValue,
2074                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
2075 {
2076         int retval = 0;
2077
2078         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2079         usb_hub_descriptor_t *hub_desc;
2080         hprt0_data_t hprt0 = {.d32 = 0 };
2081
2082         uint32_t port_status;
2083
2084         switch (typeReq) {
2085         case UCR_CLEAR_HUB_FEATURE:
2086                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2087                             "ClearHubFeature 0x%x\n", wValue);
2088                 switch (wValue) {
2089                 case UHF_C_HUB_LOCAL_POWER:
2090                 case UHF_C_HUB_OVER_CURRENT:
2091                         /* Nothing required here */
2092                         break;
2093                 default:
2094                         retval = -DWC_E_INVALID;
2095                         DWC_ERROR("DWC OTG HCD - "
2096                                   "ClearHubFeature request %xh unknown\n",
2097                                   wValue);
2098                 }
2099                 break;
2100         case UCR_CLEAR_PORT_FEATURE:
2101 #ifdef CONFIG_USB_DWC_OTG_LPM
2102                 if (wValue != UHF_PORT_L1)
2103 #endif
2104                         if (!wIndex || wIndex > 1)
2105                                 goto error;
2106
2107                 switch (wValue) {
2108                 case UHF_PORT_ENABLE:
2109                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2110                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2111                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2112                         hprt0.b.prtena = 1;
2113                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2114                         break;
2115                 case UHF_PORT_SUSPEND:
2116 #if 0//def CONFIG_PM_RUNTIME
2117                         break;
2118 #endif
2119                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2120                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2121
2122                         if (core_if->power_down == 2) {
2123                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2124                         } else {
2125                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2126                                 dwc_mdelay(5);
2127
2128                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2129                                 hprt0.b.prtres = 1;
2130                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2131                                 hprt0.b.prtsusp = 0;
2132                                 /* Clear Resume bit */
2133                                 dwc_mdelay(100);
2134                                 hprt0.b.prtres = 0;
2135                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2136                         }
2137                         break;
2138 #ifdef CONFIG_USB_DWC_OTG_LPM
2139                 case UHF_PORT_L1:
2140                         {
2141                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2142                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2143
2144                                 lpmcfg.d32 =
2145                                     DWC_READ_REG32(&core_if->
2146                                                    core_global_regs->glpmcfg);
2147                                 lpmcfg.b.en_utmi_sleep = 0;
2148                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2149                                 lpmcfg.b.prt_sleep_sts = 1;
2150                                 DWC_WRITE_REG32(&core_if->
2151                                                 core_global_regs->glpmcfg,
2152                                                 lpmcfg.d32);
2153
2154                                 /* Clear Enbl_L1Gating bit. */
2155                                 pcgcctl.b.enbl_sleep_gating = 1;
2156                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2157                                                  0);
2158
2159                                 dwc_mdelay(5);
2160
2161                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2162                                 hprt0.b.prtres = 1;
2163                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2164                                                 hprt0.d32);
2165                                 /* This bit will be cleared in wakeup interrupt handle */
2166                                 break;
2167                         }
2168 #endif
2169                 case UHF_PORT_POWER:
2170                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2171                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
2172                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2173                         hprt0.b.prtpwr = 0;
2174                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2175                         break;
2176                 case UHF_PORT_INDICATOR:
2177                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2178                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2179                         /* Port inidicator not supported */
2180                         break;
2181                 case UHF_C_PORT_CONNECTION:
2182                         /* Clears drivers internal connect status change
2183                          * flag */
2184                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2185                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2186                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2187                         break;
2188                 case UHF_C_PORT_RESET:
2189                         /* Clears the driver's internal Port Reset Change
2190                          * flag */
2191                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2192                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2193                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2194                         break;
2195                 case UHF_C_PORT_ENABLE:
2196                         /* Clears the driver's internal Port
2197                          * Enable/Disable Change flag */
2198                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2199                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2200                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2201                         break;
2202                 case UHF_C_PORT_SUSPEND:
2203                         /* Clears the driver's internal Port Suspend
2204                          * Change flag, which is set when resume signaling on
2205                          * the host port is complete */
2206                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2207                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2208                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2209                         break;
2210 #ifdef CONFIG_USB_DWC_OTG_LPM
2211                 case UHF_C_PORT_L1:
2212                         dwc_otg_hcd->flags.b.port_l1_change = 0;
2213                         break;
2214 #endif
2215                 case UHF_C_PORT_OVER_CURRENT:
2216                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2217                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2218                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2219                         break;
2220                 default:
2221                         retval = -DWC_E_INVALID;
2222                         DWC_ERROR("DWC OTG HCD - "
2223                                   "ClearPortFeature request %xh "
2224                                   "unknown or unsupported\n", wValue);
2225                 }
2226                 break;
2227         case UCR_GET_HUB_DESCRIPTOR:
2228                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2229                             "GetHubDescriptor\n");
2230                 hub_desc = (usb_hub_descriptor_t *) buf;
2231                 hub_desc->bDescLength = 9;
2232                 hub_desc->bDescriptorType = 0x29;
2233                 hub_desc->bNbrPorts = 1;
2234                 USETW(hub_desc->wHubCharacteristics, 0x08);
2235                 hub_desc->bPwrOn2PwrGood = 1;
2236                 hub_desc->bHubContrCurrent = 0;
2237                 hub_desc->DeviceRemovable[0] = 0;
2238                 hub_desc->DeviceRemovable[1] = 0xff;
2239                 break;
2240         case UCR_GET_HUB_STATUS:
2241                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2242                             "GetHubStatus\n");
2243                 DWC_MEMSET(buf, 0, 4);
2244                 break;
2245         case UCR_GET_PORT_STATUS:
2246                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2247                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2248                             wIndex, dwc_otg_hcd->flags.d32);
2249                 if (!wIndex || wIndex > 1)
2250                         goto error;
2251
2252                 port_status = 0;
2253
2254                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2255                         port_status |= (1 << UHF_C_PORT_CONNECTION);
2256
2257                 if (dwc_otg_hcd->flags.b.port_enable_change)
2258                         port_status |= (1 << UHF_C_PORT_ENABLE);
2259
2260                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2261                         port_status |= (1 << UHF_C_PORT_SUSPEND);
2262
2263                 if (dwc_otg_hcd->flags.b.port_l1_change)
2264                         port_status |= (1 << UHF_C_PORT_L1);
2265
2266                 if (dwc_otg_hcd->flags.b.port_reset_change) {
2267                         port_status |= (1 << UHF_C_PORT_RESET);
2268                 }
2269
2270                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2271                         DWC_WARN("Overcurrent change detected\n");
2272                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2273                 }
2274
2275                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2276                         /*
2277                          * The port is disconnected, which means the core is
2278                          * either in device mode or it soon will be. Just
2279                          * return 0's for the remainder of the port status
2280                          * since the port register can't be read if the core
2281                          * is in device mode.
2282                          */
2283                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2284                         break;
2285                 }
2286
2287                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2288                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2289
2290                 if (hprt0.b.prtconnsts)
2291                         port_status |= (1 << UHF_PORT_CONNECTION);
2292
2293                 if (hprt0.b.prtena)
2294                         port_status |= (1 << UHF_PORT_ENABLE);
2295
2296                 if (hprt0.b.prtsusp)
2297                         port_status |= (1 << UHF_PORT_SUSPEND);
2298
2299                 if (hprt0.b.prtovrcurract)
2300                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
2301
2302                 if (hprt0.b.prtrst)
2303                         port_status |= (1 << UHF_PORT_RESET);
2304
2305                 if (hprt0.b.prtpwr)
2306                         port_status |= (1 << UHF_PORT_POWER);
2307
2308                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2309                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
2310                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2311                         port_status |= (1 << UHF_PORT_LOW_SPEED);
2312
2313                 if (hprt0.b.prttstctl)
2314                         port_status |= (1 << UHF_PORT_TEST);
2315                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2316                         port_status |= (1 << UHF_PORT_L1);
2317                 }
2318                 /*
2319                    For Synopsys HW emulation of Power down wkup_control asserts the
2320                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2321                    We intentionally tell the software that port is in L2Suspend state.
2322                    Only for STE.
2323                 */
2324                 if ((core_if->power_down == 2)
2325                     && (core_if->hibernation_suspend == 1)) {
2326                         port_status |= (1 << UHF_PORT_SUSPEND);
2327                 }
2328                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2329
2330                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2331
2332                 break;
2333         case UCR_SET_HUB_FEATURE:
2334                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2335                             "SetHubFeature\n");
2336                 /* No HUB features supported */
2337                 break;
2338         case UCR_SET_PORT_FEATURE:
2339                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2340                         goto error;
2341
2342                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2343                         /*
2344                          * The port is disconnected, which means the core is
2345                          * either in device mode or it soon will be. Just
2346                          * return without doing anything since the port
2347                          * register can't be written if the core is in device
2348                          * mode.
2349                          */
2350                         break;
2351                 }
2352
2353                 switch (wValue) {
2354                 case UHF_PORT_SUSPEND:
2355 #if 0//def CONFIG_PM_RUNTIME
2356                         break;
2357 #endif
2358                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2359                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2360                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2361                                 goto error;
2362                         }
2363                         if (core_if->power_down == 2) {
2364                                 int timeout = 300;
2365                                 dwc_irqflags_t flags;
2366                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2367                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2368                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2369 #ifdef DWC_DEV_SRPCAP
2370                                 int32_t otg_cap_param = core_if->core_params->otg_cap;
2371 #endif
2372                                 DWC_PRINTF("Preparing for complete power-off\n");
2373
2374                                 /* Save registers before hibernation */
2375                                 dwc_otg_save_global_regs(core_if);
2376                                 dwc_otg_save_host_regs(core_if);
2377
2378                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2379                                 hprt0.b.prtsusp = 1;
2380                                 hprt0.b.prtena = 0;
2381                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2382                                 /* Spin hprt0.b.prtsusp to became 1 */
2383                                 do {
2384                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2385                                         if (hprt0.b.prtsusp) {
2386                                                 break;
2387                                         }
2388                                         dwc_mdelay(1);
2389                                 } while (--timeout);
2390                                 if (!timeout) {
2391                                         DWC_WARN("Suspend wasn't genereted\n");
2392                                 }
2393                                 dwc_udelay(10);
2394
2395                                 /*
2396                                  * We need to disable interrupts to prevent servicing of any IRQ
2397                                  * during going to hibernation
2398                                  */
2399                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2400                                 core_if->lx_state = DWC_OTG_L2;
2401 #ifdef DWC_DEV_SRPCAP
2402                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2403                                 hprt0.b.prtpwr = 0;
2404                                 hprt0.b.prtena = 0;
2405                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
2406                                                 hprt0.d32);
2407 #endif
2408                                 gusbcfg.d32 =
2409                                     DWC_READ_REG32(&core_if->core_global_regs->
2410                                                    gusbcfg);
2411                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2412                                         /* ULPI interface */
2413                                         /* Suspend the Phy Clock */
2414                                         pcgcctl.d32 = 0;
2415                                         pcgcctl.b.stoppclk = 1;
2416                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2417                                                          pcgcctl.d32);
2418                                         dwc_udelay(10);
2419                                         gpwrdn.b.pmuactv = 1;
2420                                         DWC_MODIFY_REG32(&core_if->
2421                                                          core_global_regs->
2422                                                          gpwrdn, 0, gpwrdn.d32);
2423                                 } else {
2424                                         /* UTMI+ Interface */
2425                                         gpwrdn.b.pmuactv = 1;
2426                                         DWC_MODIFY_REG32(&core_if->
2427                                                          core_global_regs->
2428                                                          gpwrdn, 0, gpwrdn.d32);
2429                                         dwc_udelay(10);
2430                                         pcgcctl.b.stoppclk = 1;
2431                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
2432                                         dwc_udelay(10);
2433                                 }
2434 #ifdef DWC_DEV_SRPCAP
2435                                 gpwrdn.d32 = 0;
2436                                 gpwrdn.b.dis_vbus = 1;
2437                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2438                                                  gpwrdn, 0, gpwrdn.d32);
2439 #endif
2440                                 gpwrdn.d32 = 0;
2441                                 gpwrdn.b.pmuintsel = 1;
2442                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2443                                                  gpwrdn, 0, gpwrdn.d32);
2444                                 dwc_udelay(10);
2445
2446                                 gpwrdn.d32 = 0;
2447 #ifdef DWC_DEV_SRPCAP
2448                                 gpwrdn.b.srp_det_msk = 1;
2449 #endif
2450                                 gpwrdn.b.disconn_det_msk = 1;
2451                                 gpwrdn.b.lnstchng_msk = 1;
2452                                 gpwrdn.b.sts_chngint_msk = 1;
2453                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2454                                                  gpwrdn, 0, gpwrdn.d32);
2455                                 dwc_udelay(10);
2456
2457                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2458                                 gpwrdn.d32 = 0;
2459                                 gpwrdn.b.pwrdnclmp = 1;
2460                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2461                                                  gpwrdn, 0, gpwrdn.d32);
2462                                 dwc_udelay(10);
2463
2464                                 /* Switch off VDD */
2465                                 gpwrdn.d32 = 0;
2466                                 gpwrdn.b.pwrdnswtch = 1;
2467                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2468                                                  gpwrdn, 0, gpwrdn.d32);
2469
2470 #ifdef DWC_DEV_SRPCAP
2471                                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
2472                                 {
2473                                         core_if->pwron_timer_started = 1;
2474                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
2475                                 }
2476 #endif
2477                                 /* Save gpwrdn register for further usage if stschng interrupt */
2478                                 core_if->gr_backup->gpwrdn_local =
2479                                                 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
2480
2481                                 /* Set flag to indicate that we are in hibernation */
2482                                 core_if->hibernation_suspend = 1;
2483                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
2484
2485                                 DWC_PRINTF("Host hibernation completed\n");
2486                                 // Exit from case statement
2487                                 break;
2488
2489                         }
2490                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2491                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2492                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2493                                 gotgctl.b.hstsethnpen = 1;
2494                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2495                                                  gotgctl, 0, gotgctl.d32);
2496                                 core_if->op_state = A_SUSPEND;
2497                         }
2498                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2499                         hprt0.b.prtsusp = 1;
2500                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2501                         {
2502                                 dwc_irqflags_t flags;
2503                                 /* Update lx_state */
2504                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2505                                 core_if->lx_state = DWC_OTG_L2;
2506                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
2507                         }
2508                         /* Suspend the Phy Clock */
2509                         if (core_if->otg_ver == 0) {
2510                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2511                                 pcgcctl.b.stoppclk = 1;
2512                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2513                                                  pcgcctl.d32);
2514                                 dwc_udelay(10);
2515                         }
2516
2517                         /* For HNP the bus must be suspended for at least 200ms. */
2518                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2519                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2520                                 pcgcctl.b.stoppclk = 1;
2521                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2522                                 dwc_mdelay(200);
2523                         }
2524
2525                         /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2526 #if 0 //vahrama !!!!!!!!!!!!!!!!!!
2527                         if (core_if->adp_enable) {
2528                                 gotgctl_data_t gotgctl = {.d32 = 0 };
2529                                 gpwrdn_data_t gpwrdn;
2530
2531                                 while (gotgctl.b.asesvld == 1) {
2532                                         gotgctl.d32 =
2533                                             DWC_READ_REG32(&core_if->
2534                                                            core_global_regs->
2535                                                            gotgctl);
2536                                         dwc_mdelay(100);
2537                                 }
2538
2539                                 /* Enable Power Down Logic */
2540                                 gpwrdn.d32 = 0;
2541                                 gpwrdn.b.pmuactv = 1;
2542                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2543                                                  gpwrdn, 0, gpwrdn.d32);
2544
2545                                 /* Unmask SRP detected interrupt from Power Down Logic */
2546                                 gpwrdn.d32 = 0;
2547                                 gpwrdn.b.srp_det_msk = 1;
2548                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
2549                                                  gpwrdn, 0, gpwrdn.d32);
2550
2551                                 dwc_otg_adp_probe_start(core_if);
2552                         }
2553 #endif
2554                         break;
2555                 case UHF_PORT_POWER:
2556                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2557                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
2558                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2559                         hprt0.b.prtpwr = 1;
2560                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2561                         break;
2562                 case UHF_PORT_RESET:
2563                         if ((core_if->power_down == 2)
2564                             && (core_if->hibernation_suspend == 1)) {
2565                                 /* If we are going to exit from Hibernated
2566                                  * state via USB RESET.
2567                                  */
2568                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2569                         } else {
2570                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2571
2572                                 DWC_DEBUGPL(DBG_HCD,
2573                                             "DWC OTG HCD HUB CONTROL - "
2574                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
2575                                 {
2576                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2577                                         pcgcctl.b.enbl_sleep_gating = 1;
2578                                         pcgcctl.b.stoppclk = 1;
2579                                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2580                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
2581                                 }
2582 #ifdef CONFIG_USB_DWC_OTG_LPM
2583                                 {
2584                                         glpmcfg_data_t lpmcfg;
2585                                         lpmcfg.d32 =
2586                                                 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2587                                         if (lpmcfg.b.prt_sleep_sts) {
2588                                                 lpmcfg.b.en_utmi_sleep = 0;
2589                                                 lpmcfg.b.hird_thres &= (~(1 << 4));
2590                                                 DWC_WRITE_REG32
2591                                                     (&core_if->core_global_regs->glpmcfg,
2592                                                      lpmcfg.d32);
2593                                                 dwc_mdelay(1);
2594                                         }
2595                                 }
2596 #endif
2597                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2598                                 /* Clear suspend bit if resetting from suspended state. */
2599                                 hprt0.b.prtsusp = 0;
2600                                 /* When B-Host the Port reset bit is set in
2601                                  * the Start HCD Callback function, so that
2602                                  * the reset is started within 1ms of the HNP
2603                                  * success interrupt. */
2604                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2605                                         hprt0.b.prtpwr = 1;
2606                                         hprt0.b.prtrst = 1;
2607                                         DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
2608                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2609                                                         hprt0.d32);
2610                                 }
2611                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2612                                 dwc_mdelay(60);
2613                                 hprt0.b.prtrst = 0;
2614                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2615                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2616                         }
2617                         break;
2618 #ifdef DWC_HS_ELECT_TST
2619                 case UHF_PORT_TEST:
2620                         {
2621                                 uint32_t t;
2622                                 gintmsk_data_t gintmsk;
2623
2624                                 t = (wIndex >> 8);      /* MSB wIndex USB */
2625                                 DWC_DEBUGPL(DBG_HCD,
2626                                             "DWC OTG HCD HUB CONTROL - "
2627                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2628                                             t);
2629                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2630                                 if (t < 6) {
2631                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
2632                                         hprt0.b.prttstctl = t;
2633                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
2634                                                         hprt0.d32);
2635                                 } else {
2636                                         /* Setup global vars with reg addresses (quick and
2637                                          * dirty hack, should be cleaned up)
2638                                          */
2639                                         global_regs = core_if->core_global_regs;
2640                                         hc_global_regs =
2641                                             core_if->host_if->host_global_regs;
2642                                         hc_regs =
2643                                             (dwc_otg_hc_regs_t *) ((char *)
2644                                                                    global_regs +
2645                                                                    0x500);
2646                                         data_fifo =
2647                                             (uint32_t *) ((char *)global_regs +
2648                                                           0x1000);
2649
2650                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
2651                                                 /* Save current interrupt mask */
2652                                                 gintmsk.d32 =
2653                                                     DWC_READ_REG32
2654                                                     (&global_regs->gintmsk);
2655
2656                                                 /* Disable all interrupts while we muck with
2657                                                  * the hardware directly
2658                                                  */
2659                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2660
2661                                                 /* 15 second delay per the test spec */
2662                                                 dwc_mdelay(15000);
2663
2664                                                 /* Drive suspend on the root port */
2665                                                 hprt0.d32 =
2666                                                     dwc_otg_read_hprt0(core_if);
2667                                                 hprt0.b.prtsusp = 1;
2668                                                 hprt0.b.prtres = 0;
2669                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2670
2671                                                 /* 15 second delay per the test spec */
2672                                                 dwc_mdelay(15000);
2673
2674                                                 /* Drive resume on the root port */
2675                                                 hprt0.d32 =
2676                                                     dwc_otg_read_hprt0(core_if);
2677                                                 hprt0.b.prtsusp = 0;
2678                                                 hprt0.b.prtres = 1;
2679                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2680                                                 dwc_mdelay(100);
2681
2682                                                 /* Clear the resume bit */
2683                                                 hprt0.b.prtres = 0;
2684                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2685
2686                                                 /* Restore interrupts */
2687                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2688                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2689                                                 /* Save current interrupt mask */
2690                                                 gintmsk.d32 =
2691                                                     DWC_READ_REG32
2692                                                     (&global_regs->gintmsk);
2693
2694                                                 /* Disable all interrupts while we muck with
2695                                                  * the hardware directly
2696                                                  */
2697                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2698
2699                                                 /* 15 second delay per the test spec */
2700                                                 dwc_mdelay(15000);
2701
2702                                                 /* Send the Setup packet */
2703                                                 do_setup();
2704
2705                                                 /* 15 second delay so nothing else happens for awhile */
2706                                                 dwc_mdelay(15000);
2707
2708                                                 /* Restore interrupts */
2709                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2710                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2711                                                 /* Save current interrupt mask */
2712                                                 gintmsk.d32 =
2713                                                     DWC_READ_REG32
2714                                                     (&global_regs->gintmsk);
2715
2716                                                 /* Disable all interrupts while we muck with
2717                                                  * the hardware directly
2718                                                  */
2719                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2720
2721                                                 /* Send the Setup packet */
2722                                                 do_setup();
2723
2724                                                 /* 15 second delay so nothing else happens for awhile */
2725                                                 dwc_mdelay(15000);
2726
2727                                                 /* Send the In and Ack packets */
2728                                                 do_in_ack();
2729
2730                                                 /* 15 second delay so nothing else happens for awhile */
2731                                                 dwc_mdelay(15000);
2732
2733                                                 /* Restore interrupts */
2734                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2735                                         }
2736                                 }
2737                                 break;
2738                         }
2739 #endif /* DWC_HS_ELECT_TST */
2740
2741                 case UHF_PORT_INDICATOR:
2742                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2743                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2744                         /* Not supported */
2745                         break;
2746                 default:
2747                         retval = -DWC_E_INVALID;
2748                         DWC_ERROR("DWC OTG HCD - "
2749                                   "SetPortFeature request %xh "
2750                                   "unknown or unsupported\n", wValue);
2751                         break;
2752                 }
2753                 break;
2754 #ifdef CONFIG_USB_DWC_OTG_LPM
2755         case UCR_SET_AND_TEST_PORT_FEATURE:
2756                 if (wValue != UHF_PORT_L1) {
2757                         goto error;
2758                 }
2759                 {
2760                         int portnum, hird, devaddr, remwake;
2761                         glpmcfg_data_t lpmcfg;
2762                         uint32_t time_usecs;
2763                         gintsts_data_t gintsts;
2764                         gintmsk_data_t gintmsk;
2765
2766                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
2767                                 goto error;
2768                         }
2769                         if (wValue != UHF_PORT_L1 || wLength != 1) {
2770                                 goto error;
2771                         }
2772                         /* Check if the port currently is in SLEEP state */
2773                         lpmcfg.d32 =
2774                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2775                         if (lpmcfg.b.prt_sleep_sts) {
2776                                 DWC_INFO("Port is already in sleep mode\n");
2777                                 buf[0] = 0;     /* Return success */
2778                                 break;
2779                         }
2780
2781                         portnum = wIndex & 0xf;
2782                         hird = (wIndex >> 4) & 0xf;
2783                         devaddr = (wIndex >> 8) & 0x7f;
2784                         remwake = (wIndex >> 15);
2785
2786                         if (portnum != 1) {
2787                                 retval = -DWC_E_INVALID;
2788                                 DWC_WARN
2789                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
2790                                      portnum);
2791                                 break;
2792                         }
2793
2794                         DWC_PRINTF
2795                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2796                              portnum, hird, devaddr, remwake);
2797                         /* Disable LPM interrupt */
2798                         gintmsk.d32 = 0;
2799                         gintmsk.b.lpmtranrcvd = 1;
2800                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2801                                          gintmsk.d32, 0);
2802
2803                         if (dwc_otg_hcd_send_lpm
2804                             (dwc_otg_hcd, devaddr, hird, remwake)) {
2805                                 retval = -DWC_E_INVALID;
2806                                 break;
2807                         }
2808
2809                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2810                         /* We will consider timeout if time_usecs microseconds pass,
2811                          * and we don't receive LPM transaction status.
2812                          * After receiving non-error responce(ACK/NYET/STALL) from device,
2813                          *  core will set lpmtranrcvd bit.
2814                          */
2815                         do {
2816                                 gintsts.d32 =
2817                                     DWC_READ_REG32(&core_if->core_global_regs->gintsts);
2818                                 if (gintsts.b.lpmtranrcvd) {
2819                                         break;
2820                                 }
2821                                 dwc_udelay(1);
2822                         } while (--time_usecs);
2823                         /* lpm_int bit will be cleared in LPM interrupt handler */
2824
2825                         /* Now fill status
2826                          * 0x00 - Success
2827                          * 0x10 - NYET
2828                          * 0x11 - Timeout
2829                          */
2830                         if (!gintsts.b.lpmtranrcvd) {
2831                                 buf[0] = 0x3;   /* Completion code is Timeout */
2832                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2833                         } else {
2834                                 lpmcfg.d32 =
2835                                     DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2836                                 if (lpmcfg.b.lpm_resp == 0x3) {
2837                                         /* ACK responce from the device */
2838                                         buf[0] = 0x00;  /* Success */
2839                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
2840                                         /* NYET responce from the device */
2841                                         buf[0] = 0x2;
2842                                 } else {
2843                                         /* Otherwise responce with Timeout */
2844                                         buf[0] = 0x3;
2845                                 }
2846                         }
2847                         DWC_PRINTF("Device responce to LPM trans is %x\n",
2848                                    lpmcfg.b.lpm_resp);
2849                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2850                                          gintmsk.d32);
2851
2852                         break;
2853                 }
2854 #endif /* CONFIG_USB_DWC_OTG_LPM */
2855         default:
2856 error:
2857                 retval = -DWC_E_INVALID;
2858                 DWC_WARN("DWC OTG HCD - "
2859                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2860                          typeReq, wIndex, wValue);
2861                 break;
2862         }
2863
2864         return retval;
2865 }
2866
2867 #ifdef CONFIG_USB_DWC_OTG_LPM
2868 /** Returns index of host channel to perform LPM transaction. */
2869 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
2870 {
2871         dwc_otg_core_if_t *core_if = hcd->core_if;
2872         dwc_hc_t *hc;
2873         hcchar_data_t hcchar;
2874         gintmsk_data_t gintmsk = {.d32 = 0 };
2875
2876         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2877                 DWC_PRINTF("No free channel to select for LPM transaction\n");
2878                 return -1;
2879         }
2880
2881         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2882
2883         /* Mask host channel interrupts. */
2884         gintmsk.b.hcintr = 1;
2885         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2886
2887         /* Fill fields that core needs for LPM transaction */
2888         hcchar.b.devaddr = devaddr;
2889         hcchar.b.epnum = 0;
2890         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2891         hcchar.b.mps = 64;
2892         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2893         hcchar.b.epdir = 0;     /* OUT */
2894         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2895                         hcchar.d32);
2896
2897         /* Remove the host channel from the free list. */
2898         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2899
2900         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2901
2902         return hc->hc_num;
2903 }
2904
2905 /** Release hc after performing LPM transaction */
2906 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
2907 {
2908         dwc_hc_t *hc;
2909         glpmcfg_data_t lpmcfg;
2910         uint8_t hc_num;
2911
2912         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2913         hc_num = lpmcfg.b.lpm_chan_index;
2914
2915         hc = hcd->hc_ptr_array[hc_num];
2916
2917         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2918         /* Return host channel to free list */
2919         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2920 }
2921
2922 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
2923                          uint8_t bRemoteWake)
2924 {
2925         glpmcfg_data_t lpmcfg;
2926         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2927         int channel;
2928
2929         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2930         if (channel < 0) {
2931                 return channel;
2932         }
2933
2934         pcgcctl.b.enbl_sleep_gating = 1;
2935         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2936
2937         /* Read LPM config register */
2938         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2939
2940         /* Program LPM transaction fields */
2941         lpmcfg.b.rem_wkup_en = bRemoteWake;
2942         lpmcfg.b.hird = hird;
2943
2944         if(dwc_otg_get_param_besl_enable(hcd->core_if)) {
2945                 lpmcfg.b.hird_thres = 0x16;
2946                 lpmcfg.b.en_besl = 1;
2947         } else {
2948                 lpmcfg.b.hird_thres = 0x1c;
2949         }
2950
2951         lpmcfg.b.lpm_chan_index = channel;
2952         lpmcfg.b.en_utmi_sleep = 1;
2953         /* Program LPM config register */
2954         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2955
2956         /* Send LPM transaction */
2957         lpmcfg.b.send_lpm = 1;
2958         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2959
2960         return 0;
2961 }
2962
2963 #endif /* CONFIG_USB_DWC_OTG_LPM */
2964
2965 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
2966 {
2967         int retval;
2968
2969         if (port != 1) {
2970                 return -DWC_E_INVALID;
2971         }
2972
2973         retval = (hcd->flags.b.port_connect_status_change ||
2974                   hcd->flags.b.port_reset_change ||
2975                   hcd->flags.b.port_enable_change ||
2976                   hcd->flags.b.port_suspend_change ||
2977                   hcd->flags.b.port_over_current_change);
2978 #ifdef DEBUG
2979         if (retval) {
2980                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
2981                             " Root port status changed\n");
2982                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
2983                             hcd->flags.b.port_connect_status_change);
2984                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
2985                             hcd->flags.b.port_reset_change);
2986                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
2987                             hcd->flags.b.port_enable_change);
2988                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
2989                             hcd->flags.b.port_suspend_change);
2990                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
2991                             hcd->flags.b.port_over_current_change);
2992         }
2993 #endif
2994         return retval;
2995 }
2996
2997 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
2998 {
2999         hfnum_data_t hfnum;
3000         hfnum.d32 =
3001             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
3002                            hfnum);
3003
3004 #ifdef DEBUG_SOF
3005         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3006                     hfnum.b.frnum);
3007 #endif
3008         return hfnum.b.frnum;
3009 }
3010
3011 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
3012                       struct dwc_otg_hcd_function_ops *fops)
3013 {
3014         int retval = 0;
3015
3016         hcd->fops = fops;
3017         if (!dwc_otg_is_device_mode(hcd->core_if) &&
3018                 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3019                 dwc_otg_hcd_reinit(hcd);
3020         } else {
3021                 retval = -DWC_E_NO_DEVICE;
3022         }
3023
3024         return retval;
3025 }
3026
3027 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
3028 {
3029         return hcd->priv;
3030 }
3031
3032 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
3033 {
3034         hcd->priv = priv_data;
3035 }
3036
3037 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
3038 {
3039         return hcd->otg_port;
3040 }
3041
3042 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
3043 {
3044         uint32_t is_b_host;
3045         if (hcd->core_if->op_state == B_HOST) {
3046                 is_b_host = 1;
3047         } else {
3048                 is_b_host = 0;
3049         }
3050
3051         return is_b_host;
3052 }
3053
3054 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
3055                                          int iso_desc_count, int atomic_alloc)
3056 {
3057         dwc_otg_hcd_urb_t *dwc_otg_urb;
3058         uint32_t size;
3059
3060         size =
3061             sizeof(*dwc_otg_urb) +
3062             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3063         if (atomic_alloc)
3064                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3065         else
3066                 dwc_otg_urb = DWC_ALLOC(size);
3067
3068         dwc_otg_urb->packet_count = iso_desc_count;
3069
3070         return dwc_otg_urb;
3071 }
3072
3073 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
3074                                   uint8_t dev_addr, uint8_t ep_num,
3075                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3076 {
3077         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3078                               ep_type, ep_dir, mps);
3079 #if 0
3080         DWC_PRINTF
3081             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3082              dev_addr, ep_num, ep_dir, ep_type, mps);
3083 #endif
3084 }
3085
3086 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
3087                                 void *urb_handle, void *buf, dwc_dma_t dma,
3088                                 uint32_t buflen, void *setup_packet,
3089                                 dwc_dma_t setup_dma, uint32_t flags,
3090                                 uint16_t interval)
3091 {
3092         dwc_otg_urb->priv = urb_handle;
3093         dwc_otg_urb->buf = buf;
3094         dwc_otg_urb->dma = dma;
3095         dwc_otg_urb->length = buflen;
3096         dwc_otg_urb->setup_packet = setup_packet;
3097         dwc_otg_urb->setup_dma = setup_dma;
3098         dwc_otg_urb->flags = flags;
3099         dwc_otg_urb->interval = interval;
3100         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3101 }
3102
3103 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
3104 {
3105         return dwc_otg_urb->status;
3106 }
3107
3108 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
3109 {
3110         return dwc_otg_urb->actual_length;
3111 }
3112
3113 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
3114 {
3115         return dwc_otg_urb->error_count;
3116 }
3117
3118 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
3119                                          int desc_num, uint32_t offset,
3120                                          uint32_t length)
3121 {
3122         dwc_otg_urb->iso_descs[desc_num].offset = offset;
3123         dwc_otg_urb->iso_descs[desc_num].length = length;
3124 }
3125
3126 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
3127                                              int desc_num)
3128 {
3129         return dwc_otg_urb->iso_descs[desc_num].status;
3130 }
3131
3132 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3133                                                     dwc_otg_urb, int desc_num)
3134 {
3135         return dwc_otg_urb->iso_descs[desc_num].actual_length;
3136 }
3137
3138 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
3139 {
3140         int allocated = 0;
3141         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3142
3143         if (qh) {
3144                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3145                         allocated = 1;
3146                 }
3147         }
3148         return allocated;
3149 }
3150
3151 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
3152 {
3153         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3154         int freed = 0;
3155         DWC_ASSERT(qh, "qh is not allocated\n");
3156
3157         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3158                 freed = 1;
3159         }
3160
3161         return freed;
3162 }
3163
3164 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
3165 {
3166         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3167         DWC_ASSERT(qh, "qh is not allocated\n");
3168         return qh->usecs;
3169 }
3170
3171 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
3172 {
3173 #ifdef DEBUG
3174         int num_channels;
3175         int i;
3176         gnptxsts_data_t np_tx_status;
3177         hptxsts_data_t p_tx_status;
3178
3179         num_channels = hcd->core_if->core_params->host_channels;
3180         DWC_PRINTF("\n");
3181         DWC_PRINTF
3182             ("************************************************************\n");
3183         DWC_PRINTF("HCD State:\n");
3184         DWC_PRINTF("  Num channels: %d\n", num_channels);
3185         for (i = 0; i < num_channels; i++) {
3186                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3187                 DWC_PRINTF("  Channel %d:\n", i);
3188                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3189                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
3190                 DWC_PRINTF("    speed: %d\n", hc->speed);
3191                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
3192                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
3193                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
3194                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
3195                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
3196                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
3197                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
3198                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
3199                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
3200                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
3201                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
3202                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
3203                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
3204                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
3205                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
3206                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
3207                 DWC_PRINTF("    requests: %d\n", hc->requests);
3208                 DWC_PRINTF("    qh: %p\n", hc->qh);
3209                 if (hc->xfer_started) {
3210                         hfnum_data_t hfnum;
3211                         hcchar_data_t hcchar;
3212                         hctsiz_data_t hctsiz;
3213                         hcint_data_t hcint;
3214                         hcintmsk_data_t hcintmsk;
3215                         hfnum.d32 =
3216                             DWC_READ_REG32(&hcd->core_if->
3217                                            host_if->host_global_regs->hfnum);
3218                         hcchar.d32 =
3219                             DWC_READ_REG32(&hcd->core_if->host_if->
3220                                            hc_regs[i]->hcchar);
3221                         hctsiz.d32 =
3222                             DWC_READ_REG32(&hcd->core_if->host_if->
3223                                            hc_regs[i]->hctsiz);
3224                         hcint.d32 =
3225                             DWC_READ_REG32(&hcd->core_if->host_if->
3226                                            hc_regs[i]->hcint);
3227                         hcintmsk.d32 =
3228                             DWC_READ_REG32(&hcd->core_if->host_if->
3229                                            hc_regs[i]->hcintmsk);
3230                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
3231                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
3232                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
3233                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
3234                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3235                 }
3236                 if (hc->xfer_started && hc->qh) {
3237                         dwc_otg_qtd_t *qtd;
3238                         dwc_otg_hcd_urb_t *urb;
3239
3240                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
3241                                 if (!qtd->in_process)
3242                                         break;
3243
3244                                 urb = qtd->urb;
3245                         DWC_PRINTF("    URB Info:\n");
3246                         DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
3247                         if (urb) {
3248                                 DWC_PRINTF("      Dev: %d, EP: %d %s\n",
3249                                            dwc_otg_hcd_get_dev_addr(&urb->
3250                                                                     pipe_info),
3251                                            dwc_otg_hcd_get_ep_num(&urb->
3252                                                                   pipe_info),
3253                                            dwc_otg_hcd_is_pipe_in(&urb->
3254                                                                   pipe_info) ?
3255                                            "IN" : "OUT");
3256                                 DWC_PRINTF("      Max packet size: %d\n",
3257                                            dwc_otg_hcd_get_mps(&urb->
3258                                                                pipe_info));
3259                                 DWC_PRINTF("      transfer_buffer: %p\n",
3260                                            urb->buf);
3261                                 DWC_PRINTF("      transfer_dma: %p\n",
3262                                            (void *)urb->dma);
3263                                 DWC_PRINTF("      transfer_buffer_length: %d\n",
3264                                            urb->length);
3265                                         DWC_PRINTF("      actual_length: %d\n",
3266                                                    urb->actual_length);
3267                                 }
3268                         }
3269                 }
3270         }
3271         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
3272         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
3273         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
3274         np_tx_status.d32 =
3275             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3276         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
3277                    np_tx_status.b.nptxqspcavail);
3278         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
3279                    np_tx_status.b.nptxfspcavail);
3280         p_tx_status.d32 =
3281             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3282         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
3283                    p_tx_status.b.ptxqspcavail);
3284         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3285         dwc_otg_hcd_dump_frrem(hcd);
3286         dwc_otg_dump_global_registers(hcd->core_if);
3287         dwc_otg_dump_host_registers(hcd->core_if);
3288         DWC_PRINTF
3289             ("************************************************************\n");
3290         DWC_PRINTF("\n");
3291 #endif
3292 }
3293
3294 #ifdef DEBUG
3295 void dwc_print_setup_data(uint8_t * setup)
3296 {
3297         int i;
3298         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3299                 DWC_PRINTF("Setup Data = MSB ");
3300                 for (i = 7; i >= 0; i--)
3301                         DWC_PRINTF("%02x ", setup[i]);
3302                 DWC_PRINTF("\n");
3303                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
3304                            (setup[0] & 0x80) ? "Device-to-Host" :
3305                            "Host-to-Device");
3306                 DWC_PRINTF("  bmRequestType Type = ");
3307                 switch ((setup[0] & 0x60) >> 5) {
3308                 case 0:
3309                         DWC_PRINTF("Standard\n");
3310                         break;
3311                 case 1:
3312                         DWC_PRINTF("Class\n");
3313                         break;
3314                 case 2:
3315                         DWC_PRINTF("Vendor\n");
3316                         break;
3317                 case 3:
3318                         DWC_PRINTF("Reserved\n");
3319                         break;
3320                 }
3321                 DWC_PRINTF("  bmRequestType Recipient = ");
3322                 switch (setup[0] & 0x1f) {
3323                 case 0:
3324                         DWC_PRINTF("Device\n");
3325                         break;
3326                 case 1:
3327                         DWC_PRINTF("Interface\n");
3328                         break;
3329                 case 2:
3330                         DWC_PRINTF("Endpoint\n");
3331                         break;
3332                 case 3:
3333                         DWC_PRINTF("Other\n");
3334                         break;
3335                 default:
3336                         DWC_PRINTF("Reserved\n");
3337                         break;
3338                 }
3339                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
3340                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
3341                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
3342                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
3343         }
3344 }
3345 #endif
3346
3347 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
3348 {
3349 #if 0
3350         DWC_PRINTF("Frame remaining at SOF:\n");
3351         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3352                    hcd->frrem_samples, hcd->frrem_accum,
3353                    (hcd->frrem_samples > 0) ?
3354                    hcd->frrem_accum / hcd->frrem_samples : 0);
3355
3356         DWC_PRINTF("\n");
3357         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3358         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3359                    hcd->core_if->hfnum_7_samples,
3360                    hcd->core_if->hfnum_7_frrem_accum,
3361                    (hcd->core_if->hfnum_7_samples >
3362                     0) ? hcd->core_if->hfnum_7_frrem_accum /
3363                    hcd->core_if->hfnum_7_samples : 0);
3364         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3365         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3366                    hcd->core_if->hfnum_0_samples,
3367                    hcd->core_if->hfnum_0_frrem_accum,
3368                    (hcd->core_if->hfnum_0_samples >
3369                     0) ? hcd->core_if->hfnum_0_frrem_accum /
3370                    hcd->core_if->hfnum_0_samples : 0);
3371         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3372         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3373                    hcd->core_if->hfnum_other_samples,
3374                    hcd->core_if->hfnum_other_frrem_accum,
3375                    (hcd->core_if->hfnum_other_samples >
3376                     0) ? hcd->core_if->hfnum_other_frrem_accum /
3377                    hcd->core_if->hfnum_other_samples : 0);
3378
3379         DWC_PRINTF("\n");
3380         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3381         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3382                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3383                    (hcd->hfnum_7_samples_a > 0) ?
3384                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3385         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3386         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3387                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3388                    (hcd->hfnum_0_samples_a > 0) ?
3389                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3390         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3391         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3392                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3393                    (hcd->hfnum_other_samples_a > 0) ?
3394                    hcd->hfnum_other_frrem_accum_a /
3395                    hcd->hfnum_other_samples_a : 0);
3396
3397         DWC_PRINTF("\n");
3398         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3399         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3400                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3401                    (hcd->hfnum_7_samples_b > 0) ?
3402                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3403         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3404         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3405                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3406                    (hcd->hfnum_0_samples_b > 0) ?
3407                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3408         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3409         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
3410                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3411                    (hcd->hfnum_other_samples_b > 0) ?
3412                    hcd->hfnum_other_frrem_accum_b /
3413                    hcd->hfnum_other_samples_b : 0);
3414 #endif
3415 }
3416
3417 #endif /* DWC_DEVICE_ONLY */