1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t *hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
178 if (qtd->urb != NULL) {
179 hcd->fops->complete(hcd, qtd->urb->priv,
180 qtd->urb, -DWC_E_SHUTDOWN);
181 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
191 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
192 * and periodic schedules. The QTD associated with each URB is removed from
193 * the schedule and freed. This function may be called when a disconnect is
194 * detected or when the HCD is being stopped.
196 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
198 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
199 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
200 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
201 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
202 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
203 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
207 * Start the connection timer. An OTG host is required to display a
208 * message if the device does not connect within 10 seconds. The
209 * timer is deleted if a port connect interrupt occurs before the
212 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
214 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
218 * HCD Callback function for disconnect of the HCD.
220 * @param p void pointer to the <code>struct usb_hcd</code>
222 static int32_t dwc_otg_hcd_session_start_cb(void *p)
224 dwc_otg_hcd_t *dwc_otg_hcd;
225 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
227 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
232 * HCD Callback function for starting the HCD when A-Cable is
235 * @param p void pointer to the <code>struct usb_hcd</code>
237 static int32_t dwc_otg_hcd_start_cb(void *p)
239 dwc_otg_hcd_t *dwc_otg_hcd = p;
240 dwc_otg_core_if_t *core_if;
242 uint32_t timeout = 50;
244 core_if = dwc_otg_hcd->core_if;
246 if (core_if->op_state == B_HOST) {
248 * Reset the port. During a HNP mode switch the reset
249 * needs to occur within 1ms and have a duration of at
252 hprt0.d32 = dwc_otg_read_hprt0(core_if);
254 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
255 if (core_if->otg_ver) {
257 hprt0.d32 = dwc_otg_read_hprt0(core_if);
259 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
262 /**@todo vahrama: Check the timeout value for OTG 2.0 */
263 if (core_if->otg_ver)
265 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
266 hcd_start_func, dwc_otg_hcd, timeout,
273 * HCD Callback function for disconnect of the HCD.
275 * @param p void pointer to the <code>struct usb_hcd</code>
277 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
280 dwc_otg_hcd_t *dwc_otg_hcd = p;
283 dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
284 dwc_otg_hcd->non_periodic_channels = 0;
285 dwc_otg_hcd->periodic_channels = 0;
286 dwc_otg_hcd->frame_number =0;
288 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
289 /* In some case, we don't disconnect a usb device, but
290 * disconnect intr was triggered, so check hprt0 here. */
291 if (((!hprt0.b.prtenchng)
292 && (!hprt0.b.prtconndet)
293 && hprt0.b.prtconnsts)
294 || !hprt0.b.prtenchng) {
295 DWC_PRINTF("%s: Invalid disconnect interrupt "
296 "hprt0 = 0x%08x\n", __func__, hprt0.d32);
300 * Set status flags for the hub driver.
302 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
303 dwc_otg_hcd->flags.b.port_connect_status = 0;
306 * Shutdown any transfers in process by clearing the Tx FIFO Empty
307 * interrupt mask and status bits and disabling subsequent host
308 * channel interrupts.
311 intr.b.nptxfempty = 1;
312 intr.b.ptxfempty = 1;
314 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
316 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
320 * Turn off the vbus power only if the core has transitioned to device
321 * mode. If still in host mode, need to keep power on to detect a
324 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
325 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
326 hprt0_data_t hprt0 = {.d32 = 0 };
327 DWC_PRINTF("Disconnect: PortPower off\n");
329 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
332 /** Delete timers if become device */
333 del_timers(dwc_otg_hcd);
334 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
338 /* Respond with an error status to all URBs in the schedule. */
339 kill_all_urbs(dwc_otg_hcd);
341 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
342 /* Clean up any host channels that were in use. */
346 dwc_otg_hc_regs_t *hc_regs;
347 hcchar_data_t hcchar;
349 DWC_PRINTF("Disconnect cb-Host\n");
350 if (dwc_otg_hcd->core_if->otg_ver == 1)
351 del_xfer_timers(dwc_otg_hcd);
353 del_timers(dwc_otg_hcd);
355 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
357 if (!dwc_otg_hcd->core_if->dma_enable) {
358 /* Flush out any channel requests in slave mode. */
359 for (i = 0; i < num_channels; i++) {
360 channel = dwc_otg_hcd->hc_ptr_array[i];
361 if (DWC_CIRCLEQ_EMPTY_ENTRY
362 (channel, hc_list_entry)) {
364 dwc_otg_hcd->core_if->host_if->
367 DWC_READ_REG32(&hc_regs->hcchar);
380 for (i = 0; i < num_channels; i++) {
381 channel = dwc_otg_hcd->hc_ptr_array[i];
382 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
384 dwc_otg_hcd->core_if->host_if->hc_regs[i];
385 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
387 /* Halt the channel. */
389 DWC_WRITE_REG32(&hc_regs->hcchar,
393 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
395 DWC_CIRCLEQ_INSERT_TAIL
396 (&dwc_otg_hcd->free_hc_list, channel,
399 * Added for Descriptor DMA to prevent channel double cleanup
400 * in release_channel_ddma(). Which called from ep_disable
401 * when device disconnect.
409 if (dwc_otg_hcd->fops->disconnect) {
410 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
417 * HCD Callback function for stopping the HCD.
419 * @param p void pointer to the <code>struct usb_hcd</code>
421 static int32_t dwc_otg_hcd_stop_cb(void *p)
423 dwc_otg_hcd_t *dwc_otg_hcd = p;
425 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
426 dwc_otg_hcd_stop(dwc_otg_hcd);
430 #ifdef CONFIG_USB_DWC_OTG_LPM
432 * HCD Callback function for sleep of HCD.
434 * @param p void pointer to the <code>struct usb_hcd</code>
436 static int dwc_otg_hcd_sleep_cb(void *p)
438 dwc_otg_hcd_t *hcd = p;
440 dwc_otg_hcd_free_hc_from_lpm(hcd);
447 * HCD Callback function for Remote Wakeup.
449 * @param p void pointer to the <code>struct usb_hcd</code>
451 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
453 dwc_otg_hcd_t *dwc_otg_hcd = p;
454 struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
456 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
457 dwc_otg_hcd->flags.b.port_suspend_change = 1;
458 usb_hcd_resume_root_hub(hcd);
460 #ifdef CONFIG_USB_DWC_OTG_LPM
462 dwc_otg_hcd->flags.b.port_l1_change = 1;
469 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
472 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
474 hprt0_data_t hprt0 = {.d32 = 0 };
475 struct dwc_otg_platform_data *pldata;
476 dwc_irqflags_t flags;
478 pldata = hcd->core_if->otg_dev->pldata;
479 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
482 * The root hub should be disconnected before this function is called.
483 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
484 * and the QH lists (via ..._hcd_endpoint_disable).
486 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
488 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
491 * Set status flags for the hub driver.
493 hcd->flags.b.port_connect_status_change = 1;
494 hcd->flags.b.port_connect_status = 0;
496 /* Turn off all host-specific interrupts. */
497 dwc_otg_disable_host_interrupts(hcd->core_if);
499 /* Turn off the vbus power */
500 DWC_PRINTF("PortPower off\n");
502 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
504 if (pldata->power_enable)
505 pldata->power_enable(0);
510 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
511 dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
514 dwc_irqflags_t flags;
517 gintmsk_data_t intr_mask = {.d32 = 0 };
519 if (!hcd->flags.b.port_connect_status) {
520 /* No longer connected. */
521 DWC_DEBUG("Not connected\n");
522 return -DWC_E_NO_DEVICE;
525 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
527 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
528 return -DWC_E_NO_MEMORY;
530 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
532 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
535 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
536 "Error status %d\n", retval);
537 dwc_otg_hcd_qtd_free(qtd);
540 DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
541 if (!intr_mask.b.sofintr && retval == 0) {
542 dwc_otg_transaction_type_e tr_type;
543 if ((qtd->qh->ep_type == UE_BULK)
544 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
545 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
549 tr_type = dwc_otg_hcd_select_transactions(hcd);
550 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
551 dwc_otg_hcd_queue_transactions(hcd, tr_type);
555 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
559 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
560 dwc_otg_hcd_urb_t *dwc_otg_urb)
563 dwc_otg_qtd_t *urb_qtd;
565 urb_qtd = dwc_otg_urb->qtd;
567 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
568 __func__, urb_qtd, dwc_otg_urb);
573 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
574 if (urb_qtd->in_process) {
575 dump_channel_info(hcd, qh);
579 if (urb_qtd->in_process && qh->channel) {
580 /* The QTD is in process (it has been assigned to a channel). */
581 if (hcd->flags.b.port_connect_status) {
583 * If still connected (i.e. in host mode), halt the
584 * channel so it can be used for other transfers. If
585 * no longer connected, the host registers can't be
586 * written to halt the channel since the core is in
589 dwc_otg_hc_halt(hcd->core_if, qh->channel,
590 DWC_OTG_HC_XFER_URB_DEQUEUE);
595 * Free the QTD and clean up the associated QH. Leave the QH in the
596 * schedule if it has any remaining QTDs.
599 if (!hcd->core_if->dma_desc_enable) {
600 uint8_t b = urb_qtd->in_process;
601 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
603 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
605 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
606 dwc_otg_hcd_qh_remove(hcd, qh);
609 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
614 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
617 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
619 dwc_irqflags_t flags;
622 retval = -DWC_E_INVALID;
627 retval = -DWC_E_INVALID;
631 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
633 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
634 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
637 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
640 dwc_otg_hcd_qh_remove(hcd, qh);
642 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
644 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
645 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
646 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
647 * and dwc_otg_hcd_frame_list_alloc().
649 dwc_otg_hcd_qh_free(hcd, qh);
655 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
656 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
659 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
661 return -DWC_E_INVALID;
663 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
669 * HCD Callback structure for handling mode switching.
671 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
672 .start = dwc_otg_hcd_start_cb,
673 .stop = dwc_otg_hcd_stop_cb,
674 .disconnect = dwc_otg_hcd_disconnect_cb,
675 .session_start = dwc_otg_hcd_session_start_cb,
676 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
677 #ifdef CONFIG_USB_DWC_OTG_LPM
678 .sleep = dwc_otg_hcd_sleep_cb,
684 * Reset tasklet function
686 static void reset_tasklet_func(void *data)
688 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
689 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
692 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
694 hprt0.d32 = dwc_otg_read_hprt0(core_if);
696 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
700 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
701 dwc_otg_hcd->flags.b.port_reset_change = 1;
704 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
706 dwc_list_link_t *item;
708 dwc_irqflags_t flags;
710 if (!qh_list->next) {
711 /* The list hasn't been initialized yet. */
715 * Hold spinlock here. Not needed in that case if bellow
716 * function is being called from ISR
718 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
719 /* Ensure there are no QTDs or URBs left. */
720 kill_urbs_in_qh_list(hcd, qh_list);
721 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
723 DWC_LIST_FOREACH(item, qh_list) {
724 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
725 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
730 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
731 * Device during SRP time by host power up.
733 void dwc_otg_hcd_power_up(void *ptr)
735 gpwrdn_data_t gpwrdn = {.d32 = 0 };
736 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
738 DWC_PRINTF("%s called\n", __FUNCTION__);
740 if (!core_if->hibernation_suspend) {
741 DWC_PRINTF("Already exited from Hibernation\n");
745 /* Switch on the voltage to the core */
746 gpwrdn.b.pwrdnswtch = 1;
747 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
752 gpwrdn.b.pwrdnrstn = 1;
753 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
756 /* Disable power clamps */
758 gpwrdn.b.pwrdnclmp = 1;
759 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
761 /* Remove reset the core signal */
763 gpwrdn.b.pwrdnrstn = 1;
764 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
767 /* Disable PMU interrupt */
769 gpwrdn.b.pmuintsel = 1;
770 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
772 core_if->hibernation_suspend = 0;
776 gpwrdn.b.pmuactv = 1;
777 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
782 gpwrdn.b.dis_vbus = 1;
783 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
785 core_if->op_state = A_HOST;
786 dwc_otg_core_init(core_if);
787 dwc_otg_enable_global_interrupts(core_if);
788 cil_hcd_start(core_if);
792 * Frees secondary storage associated with the dwc_otg_hcd structure contained
793 * in the struct usb_hcd field.
795 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
799 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
801 del_timers(dwc_otg_hcd);
803 /* Free memory for QH/QTD lists */
804 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
805 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
806 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
807 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
808 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
809 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
811 /* Free memory for the host channels. */
812 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
813 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
816 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
817 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
821 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
827 if (dwc_otg_hcd->core_if->dma_enable) {
828 if (dwc_otg_hcd->status_buf_dma) {
829 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
830 dwc_otg_hcd->status_buf,
831 dwc_otg_hcd->status_buf_dma);
833 } else if (dwc_otg_hcd->status_buf != NULL) {
834 DWC_FREE(dwc_otg_hcd->status_buf);
836 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
837 /* Set core_if's lock pointer to NULL */
838 dwc_otg_hcd->core_if->lock = NULL;
840 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
841 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
843 #ifdef DWC_DEV_SRPCAP
844 if (dwc_otg_hcd->core_if->power_down == 2 &&
845 dwc_otg_hcd->core_if->pwron_timer) {
846 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
849 DWC_FREE(dwc_otg_hcd);
852 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
859 hcd->lock = DWC_SPINLOCK_ALLOC();
861 DWC_ERROR("Could not allocate lock for pcd");
863 retval = -DWC_E_NO_MEMORY;
866 hcd->core_if = core_if;
868 /* Register the HCD CIL Callbacks */
869 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
870 &hcd_cil_callbacks, hcd);
872 /* Initialize the non-periodic schedule. */
873 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
874 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
876 /* Initialize the periodic schedule. */
877 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
878 DWC_LIST_INIT(&hcd->periodic_sched_ready);
879 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
880 DWC_LIST_INIT(&hcd->periodic_sched_queued);
883 * Create a host channel descriptor for each host channel implemented
884 * in the controller. Initialize the channel descriptor array.
886 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
887 num_channels = hcd->core_if->core_params->host_channels;
888 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
889 for (i = 0; i < num_channels; i++) {
890 channel = DWC_ALLOC(sizeof(dwc_hc_t));
891 if (channel == NULL) {
892 retval = -DWC_E_NO_MEMORY;
893 DWC_ERROR("%s: host channel allocation failed\n",
895 dwc_otg_hcd_free(hcd);
899 hcd->hc_ptr_array[i] = channel;
901 hcd->core_if->hc_xfer_timer[i] =
902 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
903 &hcd->core_if->hc_xfer_info[i]);
905 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
909 /* Initialize the Connection timeout timer. */
910 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
911 dwc_otg_hcd_connect_timeout, hcd);
913 /* Initialize reset tasklet. */
915 DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
916 #ifdef DWC_DEV_SRPCAP
917 if (hcd->core_if->power_down == 2) {
918 /* Initialize Power on timer for Host power up in case hibernation */
919 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
920 dwc_otg_hcd_power_up,
926 * Allocate space for storing data on status transactions. Normally no
927 * data is sent, but this space acts as a bit bucket. This must be
928 * done after usb_add_hcd since that function allocates the DMA buffer
931 if (hcd->core_if->dma_enable) {
933 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
934 &hcd->status_buf_dma);
936 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
938 if (!hcd->status_buf) {
939 retval = -DWC_E_NO_MEMORY;
940 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
941 dwc_otg_hcd_free(hcd);
946 hcd->frame_list = NULL;
947 hcd->frame_list_dma = 0;
948 hcd->periodic_qh_count = 0;
953 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
955 /* Turn off all host-specific interrupts. */
956 dwc_otg_disable_host_interrupts(hcd->core_if);
958 dwc_otg_hcd_free(hcd);
962 * Initializes dynamic portions of the DWC_otg HCD state.
964 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
969 dwc_hc_t *channel_tmp;
970 dwc_irqflags_t flags;
971 dwc_spinlock_t *temp_lock;
974 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
975 hcd->non_periodic_channels = 0;
976 hcd->periodic_channels = 0;
978 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
980 * Put all channels in the free channel list and clean up channel
983 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
984 &hcd->free_hc_list, hc_list_entry) {
985 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
988 num_channels = hcd->core_if->core_params->host_channels;
989 for (i = 0; i < num_channels; i++) {
990 channel = hcd->hc_ptr_array[i];
991 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
993 dwc_otg_hc_cleanup(hcd->core_if, channel);
995 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
996 /* Initialize the DWC core for host mode operation. */
997 dwc_otg_core_host_init(hcd->core_if);
999 /* Set core_if's lock pointer to the hcd->lock */
1000 /* Should get this lock before modify it */
1001 if (hcd->core_if->lock) {
1002 DWC_SPINLOCK_IRQSAVE(hcd->core_if->lock, &flags);
1003 temp_lock = hcd->core_if->lock;
1004 hcd->core_if->lock = hcd->lock;
1005 DWC_SPINUNLOCK_IRQRESTORE(temp_lock, flags);
1007 hcd->core_if->lock = hcd->lock;
1012 * Assigns transactions from a QTD to a free host channel and initializes the
1013 * host channel to perform the transactions. The host channel is removed from
1016 * @param hcd The HCD state structure.
1017 * @param qh Transactions from the first QTD for this QH are selected and
1018 * assigned to a free host channel.
1020 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1024 dwc_otg_hcd_urb_t *urb;
1028 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1030 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1032 /* Remove the host channel from the free list. */
1033 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1035 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1039 printk("%s : urb is NULL\n", __func__);
1046 qtd->in_process = 1;
1049 * Use usb_pipedevice to determine device address. This address is
1050 * 0 before the SET_ADDRESS command and the correct address afterward.
1052 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1053 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1054 hc->speed = qh->dev_speed;
1055 hc->max_packet = dwc_max_packet(qh->maxp);
1057 hc->xfer_started = 0;
1058 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1059 hc->error_state = (qtd->error_count > 0);
1060 hc->halt_on_queue = 0;
1061 hc->halt_pending = 0;
1065 * The following values may be modified in the transfer type section
1066 * below. The xfer_len value may be reduced when the transfer is
1067 * started to accommodate the max widths of the XferSize and PktCnt
1068 * fields in the HCTSIZn register.
1071 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1075 hc->do_ping = qh->ping_state;
1077 hc->data_pid_start = qh->data_toggle;
1078 hc->multi_count = 1;
1080 if (hcd->core_if->dma_enable) {
1081 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1083 /* For non-dword aligned case */
1084 if (((unsigned long)hc->xfer_buff & 0x3)
1085 && !hcd->core_if->dma_desc_enable) {
1086 ptr = (uint8_t *) urb->buf + urb->actual_length;
1089 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1091 hc->xfer_len = urb->length - urb->actual_length;
1095 * Set the split attributes
1100 uint32_t hub_addr, port_addr;
1102 hc->xact_pos = qtd->isoc_split_pos;
1103 hc->complete_split = qtd->complete_split;
1104 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1105 hc->hub_addr = (uint8_t) hub_addr;
1106 hc->port_addr = (uint8_t) port_addr;
1109 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1111 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1112 switch (qtd->control_phase) {
1113 case DWC_OTG_CONTROL_SETUP:
1114 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1117 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1118 if (hcd->core_if->dma_enable)
1119 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1121 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1126 case DWC_OTG_CONTROL_DATA:
1127 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1128 hc->data_pid_start = qtd->data_toggle;
1130 case DWC_OTG_CONTROL_STATUS:
1132 * Direction is opposite of data direction or IN if no
1135 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1136 if (urb->length == 0) {
1140 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1145 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1148 if (hcd->core_if->dma_enable)
1149 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1151 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1158 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1161 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1163 case UE_ISOCHRONOUS:
1165 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1167 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1169 if (hcd->core_if->dma_desc_enable)
1172 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1174 frame_desc->status = 0;
1176 if (hcd->core_if->dma_enable) {
1177 hc->xfer_buff = (uint8_t *) urb->dma;
1179 hc->xfer_buff = (uint8_t *) urb->buf;
1182 frame_desc->offset + qtd->isoc_split_offset;
1184 frame_desc->length - qtd->isoc_split_offset;
1186 /* For non-dword aligned buffers */
1187 if (((unsigned long)hc->xfer_buff & 0x3)
1188 && hcd->core_if->dma_enable) {
1190 (uint8_t *) urb->buf + frame_desc->offset +
1191 qtd->isoc_split_offset;
1195 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1196 if (hc->xfer_len <= 188) {
1197 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1200 DWC_HCSPLIT_XACTPOS_BEGIN;
1206 /* non DWORD-aligned buffer case */
1209 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1210 buf_size = hcd->core_if->core_params->max_transfer_size;
1214 if (!qh->dw_align_buf) {
1215 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1218 if (!qh->dw_align_buf) {
1220 ("%s: Failed to allocate memory to handle "
1221 "non-dword aligned buffer case\n",
1226 if (!hc->ep_is_in) {
1227 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1229 hc->align_buff = qh->dw_align_buf_dma;
1234 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1235 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1237 * This value may be modified when the transfer is started to
1238 * reflect the actual transfer length.
1240 hc->multi_count = dwc_hb_mult(qh->maxp);
1243 if (hcd->core_if->dma_desc_enable)
1244 hc->desc_list_addr = qh->desc_list_dma;
1246 dwc_otg_hc_init(hcd->core_if, hc);
1252 * This function selects transactions from the HCD transfer schedule and
1253 * assigns them to available host channels. It is called from HCD interrupt
1254 * handler functions.
1256 * @param hcd The HCD state structure.
1258 * @return The types of new transactions that were assigned to host channels.
1260 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1262 dwc_list_link_t *qh_ptr;
1265 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1269 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1272 /* Process entries in the periodic ready list. */
1273 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1275 while (qh_ptr != &hcd->periodic_sched_ready &&
1276 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1278 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1279 assign_and_init_hc(hcd, qh);
1282 * Move the QH from the periodic ready schedule to the
1283 * periodic assigned schedule.
1285 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1286 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1287 &qh->qh_list_entry);
1289 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1293 * Process entries in the inactive portion of the non-periodic
1294 * schedule. Some free host channels may not be used if they are
1295 * reserved for periodic transfers.
1297 qh_ptr = hcd->non_periodic_sched_inactive.next;
1298 num_channels = hcd->core_if->core_params->host_channels;
1299 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1300 (hcd->non_periodic_channels <
1301 num_channels - hcd->periodic_channels) &&
1302 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1304 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1306 err = assign_and_init_hc(hcd, qh);
1309 * Move the QH from the non-periodic inactive schedule to the
1310 * non-periodic active schedule.
1312 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1315 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1316 &qh->qh_list_entry);
1318 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1319 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1321 ret_val = DWC_OTG_TRANSACTION_ALL;
1324 hcd->non_periodic_channels++;
1331 * Attempts to queue a single transaction request for a host channel
1332 * associated with either a periodic or non-periodic transfer. This function
1333 * assumes that there is space available in the appropriate request queue. For
1334 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1335 * is available in the appropriate Tx FIFO.
1337 * @param hcd The HCD state structure.
1338 * @param hc Host channel descriptor associated with either a periodic or
1339 * non-periodic transfer.
1340 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1341 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1344 * @return 1 if a request is queued and more requests may be needed to
1345 * complete the transfer, 0 if no more requests are required for this
1346 * transfer, -1 if there is insufficient space in the Tx FIFO.
1348 static int queue_transaction(dwc_otg_hcd_t *hcd,
1349 dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1353 if (hcd->core_if->dma_enable) {
1354 if (hcd->core_if->dma_desc_enable) {
1355 if (!hc->xfer_started
1356 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1357 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1358 hc->qh->ping_state = 0;
1360 } else if (!hc->xfer_started) {
1361 if (!hc || !(hc->qh))
1363 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1364 hc->qh->ping_state = 0;
1367 } else if (hc->halt_pending) {
1368 /* Don't queue a request if the channel has been halted. */
1370 } else if (hc->halt_on_queue) {
1371 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1373 } else if (hc->do_ping) {
1374 if (!hc->xfer_started) {
1375 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1378 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1379 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1380 if (!hc->xfer_started) {
1381 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1385 dwc_otg_hc_continue_transfer(hcd->core_if,
1392 if (!hc->xfer_started) {
1393 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1396 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1404 * Processes periodic channels for the next frame and queues transactions for
1405 * these channels to the DWC_otg controller. After queueing transactions, the
1406 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1407 * to queue as Periodic Tx FIFO or request queue space becomes available.
1408 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1410 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1412 hptxsts_data_t tx_status;
1413 dwc_list_link_t *qh_ptr;
1416 int no_queue_space = 0;
1417 int no_fifo_space = 0;
1419 dwc_otg_host_global_regs_t *host_regs;
1420 host_regs = hcd->core_if->host_if->host_global_regs;
1422 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1424 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1425 DWC_DEBUGPL(DBG_HCDV,
1426 " P Tx Req Queue Space Avail (before queue): %d\n",
1427 tx_status.b.ptxqspcavail);
1428 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1429 tx_status.b.ptxfspcavail);
1432 qh_ptr = hcd->periodic_sched_assigned.next;
1433 while (qh_ptr != &hcd->periodic_sched_assigned) {
1434 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1435 if (tx_status.b.ptxqspcavail == 0) {
1440 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1443 * Set a flag if we're queuing high-bandwidth in slave mode.
1444 * The flag prevents any halts to get into the request queue in
1445 * the middle of multiple high-bandwidth packets getting queued.
1447 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1448 hcd->core_if->queuing_high_bandwidth = 1;
1451 queue_transaction(hcd, qh->channel,
1452 tx_status.b.ptxfspcavail);
1459 * In Slave mode, stay on the current transfer until there is
1460 * nothing more to do or the high-bandwidth request count is
1461 * reached. In DMA mode, only need to queue one request. The
1462 * controller automatically handles multiple packets for
1463 * high-bandwidth transfers.
1465 if (hcd->core_if->dma_enable || status == 0 ||
1466 qh->channel->requests == qh->channel->multi_count) {
1467 qh_ptr = qh_ptr->next;
1469 * Move the QH from the periodic assigned schedule to
1470 * the periodic queued schedule.
1472 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1473 &qh->qh_list_entry);
1475 /* done queuing high bandwidth */
1476 hcd->core_if->queuing_high_bandwidth = 0;
1480 if (!hcd->core_if->dma_enable) {
1481 dwc_otg_core_global_regs_t *global_regs;
1482 gintmsk_data_t intr_mask = {.d32 = 0 };
1484 global_regs = hcd->core_if->core_global_regs;
1485 intr_mask.b.ptxfempty = 1;
1487 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1488 DWC_DEBUGPL(DBG_HCDV,
1489 " P Tx Req Queue Space Avail (after queue): %d\n",
1490 tx_status.b.ptxqspcavail);
1491 DWC_DEBUGPL(DBG_HCDV,
1492 " P Tx FIFO Space Avail (after queue): %d\n",
1493 tx_status.b.ptxfspcavail);
1495 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1496 no_queue_space || no_fifo_space) {
1498 * May need to queue more transactions as the request
1499 * queue or Tx FIFO empties. Enable the periodic Tx
1500 * FIFO empty interrupt. (Always use the half-empty
1501 * level to ensure that new requests are loaded as
1502 * soon as possible.)
1504 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1508 * Disable the Tx FIFO empty interrupt since there are
1509 * no more transactions that need to be queued right
1510 * now. This function is called from interrupt
1511 * handlers to queue more transactions as transfer
1514 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1521 * Processes active non-periodic channels and queues transactions for these
1522 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1523 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1524 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1525 * FIFO Empty interrupt is disabled.
1527 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1529 gnptxsts_data_t tx_status;
1530 dwc_list_link_t *orig_qh_ptr;
1533 int no_queue_space = 0;
1534 int no_fifo_space = 0;
1537 dwc_otg_core_global_regs_t *global_regs =
1538 hcd->core_if->core_global_regs;
1540 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1542 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1543 DWC_DEBUGPL(DBG_HCDV,
1544 " NP Tx Req Queue Space Avail (before queue): %d\n",
1545 tx_status.b.nptxqspcavail);
1546 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1547 tx_status.b.nptxfspcavail);
1550 * Keep track of the starting point. Skip over the start-of-list
1553 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1554 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1556 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1559 * Process once through the active list or until no more space is
1560 * available in the request queue or the Tx FIFO.
1563 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1564 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1569 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1572 queue_transaction(hcd, qh->channel,
1573 tx_status.b.nptxfspcavail);
1577 } else if (status < 0) {
1582 /* Advance to next QH, skipping start-of-list entry. */
1583 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1584 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1585 hcd->non_periodic_qh_ptr =
1586 hcd->non_periodic_qh_ptr->next;
1589 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1591 if (!hcd->core_if->dma_enable) {
1592 gintmsk_data_t intr_mask = {.d32 = 0 };
1593 intr_mask.b.nptxfempty = 1;
1596 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1597 DWC_DEBUGPL(DBG_HCDV,
1598 " NP Tx Req Queue Space Avail (after queue): %d\n",
1599 tx_status.b.nptxqspcavail);
1600 DWC_DEBUGPL(DBG_HCDV,
1601 " NP Tx FIFO Space Avail (after queue): %d\n",
1602 tx_status.b.nptxfspcavail);
1604 if (more_to_do || no_queue_space || no_fifo_space) {
1606 * May need to queue more transactions as the request
1607 * queue or Tx FIFO empties. Enable the non-periodic
1608 * Tx FIFO empty interrupt. (Always use the half-empty
1609 * level to ensure that new requests are loaded as
1610 * soon as possible.)
1612 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1616 * Disable the Tx FIFO empty interrupt since there are
1617 * no more transactions that need to be queued right
1618 * now. This function is called from interrupt
1619 * handlers to queue more transactions as transfer
1622 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1629 * This function processes the currently active host channels and queues
1630 * transactions for these channels to the DWC_otg controller. It is called
1631 * from HCD interrupt handler functions.
1633 * @param hcd The HCD state structure.
1634 * @param tr_type The type(s) of transactions to queue (non-periodic,
1635 * periodic, or both).
1637 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1638 dwc_otg_transaction_type_e tr_type)
1641 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1643 /* Process host channels associated with periodic transfers. */
1644 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1645 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1646 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1648 process_periodic_channels(hcd);
1651 /* Process host channels associated with non-periodic transfers. */
1652 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1653 tr_type == DWC_OTG_TRANSACTION_ALL) {
1654 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1655 process_non_periodic_channels(hcd);
1658 * Ensure NP Tx FIFO empty interrupt is disabled when
1659 * there are no non-periodic transfers to process.
1661 gintmsk_data_t gintmsk = {.d32 = 0 };
1662 gintmsk.b.nptxfempty = 1;
1663 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1664 gintmsk, gintmsk.d32, 0);
1669 #ifdef DWC_HS_ELECT_TST
1671 * Quick and dirty hack to implement the HS Electrical Test
1672 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1674 * This code was copied from our userspace app "hset". It sends a
1675 * Get Device Descriptor control sequence in two parts, first the
1676 * Setup packet by itself, followed some time later by the In and
1677 * Ack packets. Rather than trying to figure out how to add this
1678 * functionality to the normal driver code, we just hijack the
1679 * hardware, using these two function to drive the hardware
1683 static dwc_otg_core_global_regs_t *global_regs;
1684 static dwc_otg_host_global_regs_t *hc_global_regs;
1685 static dwc_otg_hc_regs_t *hc_regs;
1686 static uint32_t *data_fifo;
1688 static void do_setup(void)
1690 gintsts_data_t gintsts;
1691 hctsiz_data_t hctsiz;
1692 hcchar_data_t hcchar;
1697 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1700 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1703 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1706 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1709 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1712 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1715 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1718 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1721 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1724 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1727 * Send Setup packet (Get Device Descriptor)
1730 /* Make sure channel is disabled */
1731 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1732 if (hcchar.b.chen) {
1734 /* hcchar.b.chen = 1; */
1735 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1740 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1743 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1746 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1749 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1752 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1755 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1758 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1760 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1765 hctsiz.b.xfersize = 8;
1766 hctsiz.b.pktcnt = 1;
1767 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1768 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1771 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1772 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1777 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1779 /* Fill FIFO with Setup data for Get Device Descriptor */
1780 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1781 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1782 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1784 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1786 /* Wait for host channel interrupt */
1788 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1789 } while (gintsts.b.hcintr == 0);
1791 /* Disable HCINTs */
1792 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1794 /* Disable HAINTs */
1795 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1798 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1801 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1804 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1807 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1810 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1813 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1816 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1819 static void do_in_ack(void)
1821 gintsts_data_t gintsts;
1822 hctsiz_data_t hctsiz;
1823 hcchar_data_t hcchar;
1826 host_grxsts_data_t grxsts;
1829 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1832 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1835 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1838 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1841 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1844 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1847 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1850 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1853 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1856 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1859 * Receive Control In packet
1862 /* Make sure channel is disabled */
1863 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1864 if (hcchar.b.chen) {
1867 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1872 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1875 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1878 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1881 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1884 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1887 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1890 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1892 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1897 hctsiz.b.xfersize = 8;
1898 hctsiz.b.pktcnt = 1;
1899 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1900 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1903 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1904 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1909 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1911 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1913 /* Wait for receive status queue interrupt */
1915 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1916 } while (gintsts.b.rxstsqlvl == 0);
1919 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1921 /* Clear RXSTSQLVL in GINTSTS */
1923 gintsts.b.rxstsqlvl = 1;
1924 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1926 switch (grxsts.b.pktsts) {
1927 case DWC_GRXSTS_PKTSTS_IN:
1928 /* Read the data into the host buffer */
1929 if (grxsts.b.bcnt > 0) {
1931 int word_count = (grxsts.b.bcnt + 3) / 4;
1933 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1935 for (i = 0; i < word_count; i++) {
1936 (void)DWC_READ_REG32(data_fifo++);
1945 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1947 /* Wait for receive status queue interrupt */
1949 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1950 } while (gintsts.b.rxstsqlvl == 0);
1953 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1955 /* Clear RXSTSQLVL in GINTSTS */
1957 gintsts.b.rxstsqlvl = 1;
1958 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1960 switch (grxsts.b.pktsts) {
1961 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1968 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1970 /* Wait for host channel interrupt */
1972 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1973 } while (gintsts.b.hcintr == 0);
1976 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1979 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1982 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1985 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1988 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1991 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1994 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1996 /* usleep(100000); */
2001 * Send handshake packet
2005 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2008 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2011 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2014 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2017 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2020 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2023 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2025 /* Make sure channel is disabled */
2026 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2027 if (hcchar.b.chen) {
2030 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2035 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2038 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2041 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2044 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2047 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2050 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2053 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2055 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2060 hctsiz.b.xfersize = 0;
2061 hctsiz.b.pktcnt = 1;
2062 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2063 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2066 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2067 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2072 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2074 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2076 /* Wait for host channel interrupt */
2078 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2079 } while (gintsts.b.hcintr == 0);
2081 /* Disable HCINTs */
2082 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2084 /* Disable HAINTs */
2085 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2088 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2091 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2094 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2097 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2100 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2103 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2106 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2110 /** Handles hub class-specific requests. */
2111 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2114 uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2118 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2119 usb_hub_descriptor_t *hub_desc;
2120 hprt0_data_t hprt0 = {.d32 = 0 };
2122 uint32_t port_status;
2125 case UCR_CLEAR_HUB_FEATURE:
2126 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2127 "ClearHubFeature 0x%x\n", wValue);
2129 case UHF_C_HUB_LOCAL_POWER:
2130 case UHF_C_HUB_OVER_CURRENT:
2131 /* Nothing required here */
2134 retval = -DWC_E_INVALID;
2135 DWC_ERROR("DWC OTG HCD - "
2136 "ClearHubFeature request %xh unknown\n",
2140 case UCR_CLEAR_PORT_FEATURE:
2141 #ifdef CONFIG_USB_DWC_OTG_LPM
2142 if (wValue != UHF_PORT_L1)
2144 if (!wIndex || wIndex > 1)
2148 case UHF_PORT_ENABLE:
2149 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2150 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2151 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2153 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2155 case UHF_PORT_SUSPEND:
2156 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2157 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2159 if (core_if->power_down == 2) {
2160 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2162 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2165 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2167 DWC_WRITE_REG32(core_if->host_if->hprt0,
2169 hprt0.b.prtsusp = 0;
2170 /* Clear Resume bit */
2173 DWC_WRITE_REG32(core_if->host_if->hprt0,
2177 #ifdef CONFIG_USB_DWC_OTG_LPM
2180 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2181 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2184 DWC_READ_REG32(&core_if->core_global_regs->
2186 lpmcfg.b.en_utmi_sleep = 0;
2187 lpmcfg.b.hird_thres &= (~(1 << 4));
2188 lpmcfg.b.prt_sleep_sts = 1;
2189 DWC_WRITE_REG32(&core_if->core_global_regs->
2190 glpmcfg, lpmcfg.d32);
2192 /* Clear Enbl_L1Gating bit. */
2193 pcgcctl.b.enbl_sleep_gating = 1;
2194 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2199 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2201 DWC_WRITE_REG32(core_if->host_if->hprt0,
2203 /* This bit will be cleared in wakeup interrupt handle */
2207 case UHF_PORT_POWER:
2208 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2209 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2210 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2212 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2214 case UHF_PORT_INDICATOR:
2215 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2216 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2217 /* Port inidicator not supported */
2219 case UHF_C_PORT_CONNECTION:
2220 /* Clears drivers internal connect status change
2222 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2223 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2224 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2226 case UHF_C_PORT_RESET:
2227 /* Clears the driver's internal Port Reset Change
2229 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2230 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2231 dwc_otg_hcd->flags.b.port_reset_change = 0;
2233 case UHF_C_PORT_ENABLE:
2234 /* Clears the driver's internal Port
2235 * Enable/Disable Change flag */
2236 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2237 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2238 dwc_otg_hcd->flags.b.port_enable_change = 0;
2240 case UHF_C_PORT_SUSPEND:
2241 /* Clears the driver's internal Port Suspend
2242 * Change flag, which is set when resume signaling on
2243 * the host port is complete */
2244 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2245 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2246 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2248 #ifdef CONFIG_USB_DWC_OTG_LPM
2250 dwc_otg_hcd->flags.b.port_l1_change = 0;
2253 case UHF_C_PORT_OVER_CURRENT:
2254 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2255 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2256 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2259 retval = -DWC_E_INVALID;
2260 DWC_ERROR("DWC OTG HCD - "
2261 "ClearPortFeature request %xh "
2262 "unknown or unsupported\n", wValue);
2265 case UCR_GET_HUB_DESCRIPTOR:
2266 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2267 "GetHubDescriptor\n");
2268 hub_desc = (usb_hub_descriptor_t *) buf;
2269 hub_desc->bDescLength = 9;
2270 hub_desc->bDescriptorType = 0x29;
2271 hub_desc->bNbrPorts = 1;
2272 USETW(hub_desc->wHubCharacteristics, 0x08);
2273 hub_desc->bPwrOn2PwrGood = 1;
2274 hub_desc->bHubContrCurrent = 0;
2275 hub_desc->DeviceRemovable[0] = 0;
2276 hub_desc->DeviceRemovable[1] = 0xff;
2278 case UCR_GET_HUB_STATUS:
2279 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2281 DWC_MEMSET(buf, 0, 4);
2283 case UCR_GET_PORT_STATUS:
2284 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2285 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2286 wIndex, dwc_otg_hcd->flags.d32);
2287 if (!wIndex || wIndex > 1)
2292 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2293 port_status |= (1 << UHF_C_PORT_CONNECTION);
2295 if (dwc_otg_hcd->flags.b.port_enable_change)
2296 port_status |= (1 << UHF_C_PORT_ENABLE);
2298 if (dwc_otg_hcd->flags.b.port_suspend_change)
2299 port_status |= (1 << UHF_C_PORT_SUSPEND);
2301 if (dwc_otg_hcd->flags.b.port_l1_change)
2302 port_status |= (1 << UHF_C_PORT_L1);
2304 if (dwc_otg_hcd->flags.b.port_reset_change) {
2305 port_status |= (1 << UHF_C_PORT_RESET);
2308 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2309 DWC_WARN("Overcurrent change detected\n");
2310 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2313 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2315 * The port is disconnected, which means the core is
2316 * either in device mode or it soon will be. Just
2317 * return 0's for the remainder of the port status
2318 * since the port register can't be read if the core
2319 * is in device mode.
2321 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2325 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2326 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2328 if (hprt0.b.prtconnsts)
2329 port_status |= (1 << UHF_PORT_CONNECTION);
2332 port_status |= (1 << UHF_PORT_ENABLE);
2334 if (hprt0.b.prtsusp)
2335 port_status |= (1 << UHF_PORT_SUSPEND);
2337 if (hprt0.b.prtovrcurract)
2338 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2341 port_status |= (1 << UHF_PORT_RESET);
2344 port_status |= (1 << UHF_PORT_POWER);
2346 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2347 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2348 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2349 port_status |= (1 << UHF_PORT_LOW_SPEED);
2351 if (hprt0.b.prttstctl)
2352 port_status |= (1 << UHF_PORT_TEST);
2353 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2354 port_status |= (1 << UHF_PORT_L1);
2357 For Synopsys HW emulation of Power down wkup_control asserts the
2358 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2359 We intentionally tell the software that port is in L2Suspend state.
2362 if ((core_if->power_down == 2)
2363 && (core_if->hibernation_suspend == 1)) {
2364 port_status |= (1 << UHF_PORT_SUSPEND);
2366 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2368 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2371 case UCR_SET_HUB_FEATURE:
2372 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2374 /* No HUB features supported */
2376 case UCR_SET_PORT_FEATURE:
2377 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2380 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2382 * The port is disconnected, which means the core is
2383 * either in device mode or it soon will be. Just
2384 * return without doing anything since the port
2385 * register can't be written if the core is in device
2392 case UHF_PORT_SUSPEND:
2393 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2394 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2395 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2398 if (core_if->power_down == 2) {
2400 dwc_irqflags_t flags;
2401 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2402 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2403 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2404 #ifdef DWC_DEV_SRPCAP
2405 int32_t otg_cap_param =
2406 core_if->core_params->otg_cap;
2409 ("Preparing for complete power-off\n");
2411 /* Save registers before hibernation */
2412 dwc_otg_save_global_regs(core_if);
2413 dwc_otg_save_host_regs(core_if);
2415 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2416 hprt0.b.prtsusp = 1;
2418 DWC_WRITE_REG32(core_if->host_if->hprt0,
2420 /* Spin hprt0.b.prtsusp to became 1 */
2422 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2423 if (hprt0.b.prtsusp) {
2427 } while (--timeout);
2429 DWC_WARN("Suspend wasn't genereted\n");
2434 * We need to disable interrupts to prevent servicing of any IRQ
2435 * during going to hibernation
2437 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2438 core_if->lx_state = DWC_OTG_L2;
2439 #ifdef DWC_DEV_SRPCAP
2440 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2443 DWC_WRITE_REG32(core_if->host_if->hprt0,
2447 DWC_READ_REG32(&core_if->
2448 core_global_regs->gusbcfg);
2449 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2450 /* ULPI interface */
2451 /* Suspend the Phy Clock */
2453 pcgcctl.b.stoppclk = 1;
2454 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2457 gpwrdn.b.pmuactv = 1;
2459 (&core_if->core_global_regs->gpwrdn,
2462 /* UTMI+ Interface */
2463 gpwrdn.b.pmuactv = 1;
2465 (&core_if->core_global_regs->gpwrdn,
2468 pcgcctl.b.stoppclk = 1;
2469 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2473 #ifdef DWC_DEV_SRPCAP
2475 gpwrdn.b.dis_vbus = 1;
2476 DWC_MODIFY_REG32(&core_if->
2477 core_global_regs->gpwrdn, 0,
2481 gpwrdn.b.pmuintsel = 1;
2482 DWC_MODIFY_REG32(&core_if->
2483 core_global_regs->gpwrdn, 0,
2488 #ifdef DWC_DEV_SRPCAP
2489 gpwrdn.b.srp_det_msk = 1;
2491 gpwrdn.b.disconn_det_msk = 1;
2492 gpwrdn.b.lnstchng_msk = 1;
2493 gpwrdn.b.sts_chngint_msk = 1;
2494 DWC_MODIFY_REG32(&core_if->
2495 core_global_regs->gpwrdn, 0,
2499 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2501 gpwrdn.b.pwrdnclmp = 1;
2502 DWC_MODIFY_REG32(&core_if->
2503 core_global_regs->gpwrdn, 0,
2507 /* Switch off VDD */
2509 gpwrdn.b.pwrdnswtch = 1;
2510 DWC_MODIFY_REG32(&core_if->
2511 core_global_regs->gpwrdn, 0,
2514 #ifdef DWC_DEV_SRPCAP
2515 if (otg_cap_param ==
2516 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2517 core_if->pwron_timer_started = 1;
2518 DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2522 /* Save gpwrdn register for further usage if stschng interrupt */
2523 core_if->gr_backup->gpwrdn_local =
2524 DWC_READ_REG32(&core_if->core_global_regs->
2527 /* Set flag to indicate that we are in hibernation */
2528 core_if->hibernation_suspend = 1;
2529 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2532 DWC_PRINTF("Host hibernation completed\n");
2533 /* Exit from case statement */
2537 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2538 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2539 gotgctl_data_t gotgctl = {.d32 = 0 };
2540 gotgctl.b.hstsethnpen = 1;
2541 DWC_MODIFY_REG32(&core_if->
2542 core_global_regs->gotgctl, 0,
2544 core_if->op_state = A_SUSPEND;
2546 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2547 hprt0.b.prtsusp = 1;
2548 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2550 dwc_irqflags_t flags;
2551 /* Update lx_state */
2552 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2553 core_if->lx_state = DWC_OTG_L2;
2554 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2557 /* Suspend the Phy Clock */
2558 if (core_if->otg_ver == 0) {
2559 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2560 pcgcctl.b.stoppclk = 1;
2561 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2566 /* For HNP the bus must be suspended for at least 200ms. */
2567 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2568 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2569 pcgcctl.b.stoppclk = 1;
2570 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2575 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2577 if (core_if->adp_enable) {
2578 gotgctl_data_t gotgctl = {.d32 = 0 };
2579 gpwrdn_data_t gpwrdn;
2581 while (gotgctl.b.asesvld == 1) {
2584 (&core_if->core_global_regs->gotgctl);
2588 /* Enable Power Down Logic */
2590 gpwrdn.b.pmuactv = 1;
2591 DWC_MODIFY_REG32(&core_if->
2592 core_global_regs->gpwrdn, 0,
2595 /* Unmask SRP detected interrupt from Power Down Logic */
2597 gpwrdn.b.srp_det_msk = 1;
2598 DWC_MODIFY_REG32(&core_if->
2599 core_global_regs->gpwrdn, 0,
2602 dwc_otg_adp_probe_start(core_if);
2606 case UHF_PORT_POWER:
2607 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2608 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2609 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2611 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2613 case UHF_PORT_RESET:
2614 if ((core_if->power_down == 2)
2615 && (core_if->hibernation_suspend == 1)) {
2616 /* If we are going to exit from Hibernated
2617 * state via USB RESET.
2619 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2621 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2623 DWC_DEBUGPL(DBG_HCD,
2624 "DWC OTG HCD HUB CONTROL - "
2625 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2627 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2628 pcgcctl.b.enbl_sleep_gating = 1;
2629 pcgcctl.b.stoppclk = 1;
2630 DWC_MODIFY_REG32(core_if->pcgcctl,
2632 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2634 #ifdef CONFIG_USB_DWC_OTG_LPM
2636 glpmcfg_data_t lpmcfg;
2638 DWC_READ_REG32(&core_if->
2641 if (lpmcfg.b.prt_sleep_sts) {
2642 lpmcfg.b.en_utmi_sleep = 0;
2643 lpmcfg.b.hird_thres &=
2645 DWC_WRITE_REG32(&core_if->
2653 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2654 /* Clear suspend bit if resetting from suspended state. */
2655 hprt0.b.prtsusp = 0;
2656 /* When B-Host the Port reset bit is set in
2657 * the Start HCD Callback function, so that
2658 * the reset is started within 1ms of the HNP
2659 * success interrupt. */
2660 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2664 ("Indeed it is in host mode hprt0 = %08x\n",
2666 DWC_WRITE_REG32(core_if->host_if->hprt0,
2669 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2672 DWC_WRITE_REG32(core_if->host_if->hprt0,
2674 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2677 #ifdef DWC_HS_ELECT_TST
2681 gintmsk_data_t gintmsk;
2683 t = (wIndex >> 8); /* MSB wIndex USB */
2684 DWC_DEBUGPL(DBG_HCD,
2685 "DWC OTG HCD HUB CONTROL - "
2686 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2688 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2690 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2691 hprt0.b.prttstctl = t;
2692 DWC_WRITE_REG32(core_if->host_if->hprt0,
2695 /* Setup global vars with reg addresses (quick and
2696 * dirty hack, should be cleaned up)
2698 global_regs = core_if->core_global_regs;
2700 core_if->host_if->host_global_regs;
2702 (dwc_otg_hc_regs_t *) ((char *)
2706 (uint32_t *) ((char *)global_regs +
2709 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2710 /* Save current interrupt mask */
2713 (&global_regs->gintmsk);
2715 /* Disable all interrupts while we muck with
2716 * the hardware directly
2718 DWC_WRITE_REG32(&global_regs->
2721 /* 15 second delay per the test spec */
2724 /* Drive suspend on the root port */
2726 dwc_otg_read_hprt0(core_if);
2727 hprt0.b.prtsusp = 1;
2729 DWC_WRITE_REG32(core_if->
2733 /* 15 second delay per the test spec */
2736 /* Drive resume on the root port */
2738 dwc_otg_read_hprt0(core_if);
2739 hprt0.b.prtsusp = 0;
2741 DWC_WRITE_REG32(core_if->
2746 /* Clear the resume bit */
2748 DWC_WRITE_REG32(core_if->
2752 /* Restore interrupts */
2753 DWC_WRITE_REG32(&global_regs->
2756 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2757 /* Save current interrupt mask */
2760 (&global_regs->gintmsk);
2762 /* Disable all interrupts while we muck with
2763 * the hardware directly
2765 DWC_WRITE_REG32(&global_regs->
2768 /* 15 second delay per the test spec */
2771 /* Send the Setup packet */
2774 /* 15 second delay so nothing else happens for awhile */
2777 /* Restore interrupts */
2778 DWC_WRITE_REG32(&global_regs->
2781 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2782 /* Save current interrupt mask */
2785 (&global_regs->gintmsk);
2787 /* Disable all interrupts while we muck with
2788 * the hardware directly
2790 DWC_WRITE_REG32(&global_regs->
2793 /* Send the Setup packet */
2796 /* 15 second delay so nothing else happens for awhile */
2799 /* Send the In and Ack packets */
2802 /* 15 second delay so nothing else happens for awhile */
2805 /* Restore interrupts */
2806 DWC_WRITE_REG32(&global_regs->
2813 #endif /* DWC_HS_ELECT_TST */
2815 case UHF_PORT_INDICATOR:
2816 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2817 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2821 retval = -DWC_E_INVALID;
2822 DWC_ERROR("DWC OTG HCD - "
2823 "SetPortFeature request %xh "
2824 "unknown or unsupported\n", wValue);
2828 #ifdef CONFIG_USB_DWC_OTG_LPM
2829 case UCR_SET_AND_TEST_PORT_FEATURE:
2830 if (wValue != UHF_PORT_L1) {
2834 int portnum, hird, devaddr, remwake;
2835 glpmcfg_data_t lpmcfg;
2836 uint32_t time_usecs;
2837 gintsts_data_t gintsts;
2838 gintmsk_data_t gintmsk;
2840 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2843 if (wValue != UHF_PORT_L1 || wLength != 1) {
2846 /* Check if the port currently is in SLEEP state */
2848 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2849 if (lpmcfg.b.prt_sleep_sts) {
2850 DWC_INFO("Port is already in sleep mode\n");
2851 buf[0] = 0; /* Return success */
2855 portnum = wIndex & 0xf;
2856 hird = (wIndex >> 4) & 0xf;
2857 devaddr = (wIndex >> 8) & 0x7f;
2858 remwake = (wIndex >> 15);
2861 retval = -DWC_E_INVALID;
2863 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2869 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2870 portnum, hird, devaddr, remwake);
2871 /* Disable LPM interrupt */
2873 gintmsk.b.lpmtranrcvd = 1;
2874 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2877 if (dwc_otg_hcd_send_lpm
2878 (dwc_otg_hcd, devaddr, hird, remwake)) {
2879 retval = -DWC_E_INVALID;
2883 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2884 /* We will consider timeout if time_usecs microseconds pass,
2885 * and we don't receive LPM transaction status.
2886 * After receiving non-error responce(ACK/NYET/STALL) from device,
2887 * core will set lpmtranrcvd bit.
2891 DWC_READ_REG32(&core_if->core_global_regs->
2893 if (gintsts.b.lpmtranrcvd) {
2897 } while (--time_usecs);
2898 /* lpm_int bit will be cleared in LPM interrupt handler */
2905 if (!gintsts.b.lpmtranrcvd) {
2906 buf[0] = 0x3; /* Completion code is Timeout */
2907 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2910 DWC_READ_REG32(&core_if->core_global_regs->
2912 if (lpmcfg.b.lpm_resp == 0x3) {
2913 /* ACK responce from the device */
2914 buf[0] = 0x00; /* Success */
2915 } else if (lpmcfg.b.lpm_resp == 0x2) {
2916 /* NYET responce from the device */
2919 /* Otherwise responce with Timeout */
2923 DWC_PRINTF("Device responce to LPM trans is %x\n",
2925 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2930 #endif /* CONFIG_USB_DWC_OTG_LPM */
2933 retval = -DWC_E_INVALID;
2934 DWC_WARN("DWC OTG HCD - "
2935 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2936 typeReq, wIndex, wValue);
2943 #ifdef CONFIG_USB_DWC_OTG_LPM
2944 /** Returns index of host channel to perform LPM transaction. */
2945 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2947 dwc_otg_core_if_t *core_if = hcd->core_if;
2949 hcchar_data_t hcchar;
2950 gintmsk_data_t gintmsk = {.d32 = 0 };
2952 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2953 DWC_PRINTF("No free channel to select for LPM transaction\n");
2957 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2959 /* Mask host channel interrupts. */
2960 gintmsk.b.hcintr = 1;
2961 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2963 /* Fill fields that core needs for LPM transaction */
2964 hcchar.b.devaddr = devaddr;
2966 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2968 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2969 hcchar.b.epdir = 0; /* OUT */
2970 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2973 /* Remove the host channel from the free list. */
2974 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2976 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2981 /** Release hc after performing LPM transaction */
2982 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2985 glpmcfg_data_t lpmcfg;
2988 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2989 hc_num = lpmcfg.b.lpm_chan_index;
2991 hc = hcd->hc_ptr_array[hc_num];
2993 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2994 /* Return host channel to free list */
2995 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2998 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2999 uint8_t bRemoteWake)
3001 glpmcfg_data_t lpmcfg;
3002 pcgcctl_data_t pcgcctl = {.d32 = 0 };
3005 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
3010 pcgcctl.b.enbl_sleep_gating = 1;
3011 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
3013 /* Read LPM config register */
3014 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
3016 /* Program LPM transaction fields */
3017 lpmcfg.b.rem_wkup_en = bRemoteWake;
3018 lpmcfg.b.hird = hird;
3020 if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
3021 lpmcfg.b.hird_thres = 0x16;
3022 lpmcfg.b.en_besl = 1;
3024 lpmcfg.b.hird_thres = 0x1c;
3027 lpmcfg.b.lpm_chan_index = channel;
3028 lpmcfg.b.en_utmi_sleep = 1;
3029 /* Program LPM config register */
3030 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3032 /* Send LPM transaction */
3033 lpmcfg.b.send_lpm = 1;
3034 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3039 #endif /* CONFIG_USB_DWC_OTG_LPM */
3041 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3046 return -DWC_E_INVALID;
3049 retval = (hcd->flags.b.port_connect_status_change ||
3050 hcd->flags.b.port_reset_change ||
3051 hcd->flags.b.port_enable_change ||
3052 hcd->flags.b.port_suspend_change ||
3053 hcd->flags.b.port_over_current_change);
3056 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3057 " Root port status changed\n");
3058 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
3059 hcd->flags.b.port_connect_status_change);
3060 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
3061 hcd->flags.b.port_reset_change);
3062 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
3063 hcd->flags.b.port_enable_change);
3064 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
3065 hcd->flags.b.port_suspend_change);
3066 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
3067 hcd->flags.b.port_over_current_change);
3073 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3077 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3078 host_global_regs->hfnum);
3081 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3084 return hfnum.b.frnum;
3087 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3088 struct dwc_otg_hcd_function_ops *fops)
3093 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3094 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3095 dwc_otg_hcd_reinit(hcd);
3097 retval = -DWC_E_NO_DEVICE;
3103 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3108 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3110 hcd->priv = priv_data;
3113 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3115 return hcd->otg_port;
3118 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3121 if (hcd->core_if->op_state == B_HOST) {
3130 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3131 int iso_desc_count, int atomic_alloc)
3133 dwc_otg_hcd_urb_t *dwc_otg_urb;
3137 sizeof(*dwc_otg_urb) +
3138 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3140 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3142 dwc_otg_urb = DWC_ALLOC(size);
3144 dwc_otg_urb->packet_count = iso_desc_count;
3149 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3150 uint8_t dev_addr, uint8_t ep_num,
3151 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3153 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3154 ep_type, ep_dir, mps);
3157 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3158 dev_addr, ep_num, ep_dir, ep_type, mps);
3162 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3163 void *urb_handle, void *buf, dwc_dma_t dma,
3164 uint32_t buflen, void *setup_packet,
3165 dwc_dma_t setup_dma, uint32_t flags,
3168 dwc_otg_urb->priv = urb_handle;
3169 dwc_otg_urb->buf = buf;
3170 dwc_otg_urb->dma = dma;
3171 dwc_otg_urb->length = buflen;
3172 dwc_otg_urb->setup_packet = setup_packet;
3173 dwc_otg_urb->setup_dma = setup_dma;
3174 dwc_otg_urb->flags = flags;
3175 dwc_otg_urb->interval = interval;
3176 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3179 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3181 return dwc_otg_urb->status;
3184 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3186 return dwc_otg_urb->actual_length;
3189 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3191 return dwc_otg_urb->error_count;
3194 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3195 int desc_num, uint32_t offset,
3198 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3199 dwc_otg_urb->iso_descs[desc_num].length = length;
3202 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3205 return dwc_otg_urb->iso_descs[desc_num].status;
3208 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3209 dwc_otg_urb, int desc_num)
3211 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3214 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3217 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3220 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3227 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3229 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3231 DWC_ASSERT(qh, "qh is not allocated\n");
3233 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3240 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3242 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3243 DWC_ASSERT(qh, "qh is not allocated\n");
3247 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3252 gnptxsts_data_t np_tx_status;
3253 hptxsts_data_t p_tx_status;
3255 num_channels = hcd->core_if->core_params->host_channels;
3258 ("************************************************************\n");
3259 DWC_PRINTF("HCD State:\n");
3260 DWC_PRINTF(" Num channels: %d\n", num_channels);
3261 for (i = 0; i < num_channels; i++) {
3262 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3263 DWC_PRINTF(" Channel %d:\n", i);
3264 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3265 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3266 DWC_PRINTF(" speed: %d\n", hc->speed);
3267 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3268 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3269 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3270 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3271 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3272 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3273 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3274 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3275 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3276 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3277 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3278 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3279 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3280 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3281 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3282 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3283 DWC_PRINTF(" requests: %d\n", hc->requests);
3284 DWC_PRINTF(" qh: %p\n", hc->qh);
3285 if (hc->xfer_started) {
3287 hcchar_data_t hcchar;
3288 hctsiz_data_t hctsiz;
3290 hcintmsk_data_t hcintmsk;
3292 DWC_READ_REG32(&hcd->core_if->host_if->
3293 host_global_regs->hfnum);
3295 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3298 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3301 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3304 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3306 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3307 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3308 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3309 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3310 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3312 if (hc->xfer_started && hc->qh) {
3314 dwc_otg_hcd_urb_t *urb;
3316 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3318 if (!qtd->in_process)
3322 DWC_PRINTF(" URB Info:\n");
3323 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd,
3326 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3327 dwc_otg_hcd_get_dev_addr
3329 dwc_otg_hcd_get_ep_num
3331 dwc_otg_hcd_is_pipe_in
3332 (&urb->pipe_info) ? "IN" :
3335 (" Max packet size: %d\n",
3339 (" transfer_buffer: %p\n",
3341 DWC_PRINTF(" transfer_dma: %p\n",
3344 (" transfer_buffer_length: %d\n",
3346 DWC_PRINTF(" actual_length: %d\n",
3347 urb->actual_length);
3352 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3353 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3354 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3356 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3357 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3358 np_tx_status.b.nptxqspcavail);
3359 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3360 np_tx_status.b.nptxfspcavail);
3362 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3363 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3364 p_tx_status.b.ptxqspcavail);
3365 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3366 dwc_otg_hcd_dump_frrem(hcd);
3367 dwc_otg_dump_global_registers(hcd->core_if);
3368 dwc_otg_dump_host_registers(hcd->core_if);
3370 ("************************************************************\n");
3376 void dwc_print_setup_data(uint8_t *setup)
3379 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3380 DWC_PRINTF("Setup Data = MSB ");
3381 for (i = 7; i >= 0; i--)
3382 DWC_PRINTF("%02x ", setup[i]);
3384 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3385 (setup[0] & 0x80) ? "Device-to-Host" :
3387 DWC_PRINTF(" bmRequestType Type = ");
3388 switch ((setup[0] & 0x60) >> 5) {
3390 DWC_PRINTF("Standard\n");
3393 DWC_PRINTF("Class\n");
3396 DWC_PRINTF("Vendor\n");
3399 DWC_PRINTF("Reserved\n");
3402 DWC_PRINTF(" bmRequestType Recipient = ");
3403 switch (setup[0] & 0x1f) {
3405 DWC_PRINTF("Device\n");
3408 DWC_PRINTF("Interface\n");
3411 DWC_PRINTF("Endpoint\n");
3414 DWC_PRINTF("Other\n");
3417 DWC_PRINTF("Reserved\n");
3420 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3421 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3422 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3423 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3428 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3431 DWC_PRINTF("Frame remaining at SOF:\n");
3432 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3433 hcd->frrem_samples, hcd->frrem_accum,
3434 (hcd->frrem_samples > 0) ?
3435 hcd->frrem_accum / hcd->frrem_samples : 0);
3438 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3439 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3440 hcd->core_if->hfnum_7_samples,
3441 hcd->core_if->hfnum_7_frrem_accum,
3442 (hcd->core_if->hfnum_7_samples >
3443 0) ? hcd->core_if->hfnum_7_frrem_accum /
3444 hcd->core_if->hfnum_7_samples : 0);
3445 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3446 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3447 hcd->core_if->hfnum_0_samples,
3448 hcd->core_if->hfnum_0_frrem_accum,
3449 (hcd->core_if->hfnum_0_samples >
3450 0) ? hcd->core_if->hfnum_0_frrem_accum /
3451 hcd->core_if->hfnum_0_samples : 0);
3452 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3453 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3454 hcd->core_if->hfnum_other_samples,
3455 hcd->core_if->hfnum_other_frrem_accum,
3456 (hcd->core_if->hfnum_other_samples >
3457 0) ? hcd->core_if->hfnum_other_frrem_accum /
3458 hcd->core_if->hfnum_other_samples : 0);
3461 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3462 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3463 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3464 (hcd->hfnum_7_samples_a > 0) ?
3465 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3466 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3467 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3468 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3469 (hcd->hfnum_0_samples_a > 0) ?
3470 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3471 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3472 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3473 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3474 (hcd->hfnum_other_samples_a > 0) ?
3475 hcd->hfnum_other_frrem_accum_a /
3476 hcd->hfnum_other_samples_a : 0);
3479 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3480 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3481 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3482 (hcd->hfnum_7_samples_b > 0) ?
3483 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3484 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3485 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3486 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3487 (hcd->hfnum_0_samples_b > 0) ?
3488 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3489 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3490 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3491 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3492 (hcd->hfnum_other_samples_b > 0) ?
3493 hcd->hfnum_other_frrem_accum_b /
3494 hcd->hfnum_other_samples_b : 0);
3498 #endif /* DWC_DEVICE_ONLY */