1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
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18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t *hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
178 if (qtd->urb != NULL) {
179 hcd->fops->complete(hcd, qtd->urb->priv,
180 qtd->urb, -DWC_E_SHUTDOWN);
181 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
189 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
190 * and periodic schedules. The QTD associated with each URB is removed from
191 * the schedule and freed. This function may be called when a disconnect is
192 * detected or when the HCD is being stopped.
194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
196 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
197 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
198 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
199 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
200 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
201 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
205 * Start the connection timer. An OTG host is required to display a
206 * message if the device does not connect within 10 seconds. The
207 * timer is deleted if a port connect interrupt occurs before the
210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
212 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
216 * HCD Callback function for disconnect of the HCD.
218 * @param p void pointer to the <code>struct usb_hcd</code>
220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
222 dwc_otg_hcd_t *dwc_otg_hcd;
223 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
225 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
230 * HCD Callback function for starting the HCD when A-Cable is
233 * @param p void pointer to the <code>struct usb_hcd</code>
235 static int32_t dwc_otg_hcd_start_cb(void *p)
237 dwc_otg_hcd_t *dwc_otg_hcd = p;
238 dwc_otg_core_if_t *core_if;
240 uint32_t timeout = 50;
242 core_if = dwc_otg_hcd->core_if;
244 if (core_if->op_state == B_HOST) {
246 * Reset the port. During a HNP mode switch the reset
247 * needs to occur within 1ms and have a duration of at
250 hprt0.d32 = dwc_otg_read_hprt0(core_if);
252 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
253 if (core_if->otg_ver) {
255 hprt0.d32 = dwc_otg_read_hprt0(core_if);
257 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
260 /**@todo vahrama: Check the timeout value for OTG 2.0 */
261 if (core_if->otg_ver)
263 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
264 hcd_start_func, dwc_otg_hcd, timeout,
271 * HCD Callback function for disconnect of the HCD.
273 * @param p void pointer to the <code>struct usb_hcd</code>
275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
278 dwc_otg_hcd_t *dwc_otg_hcd = p;
281 dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
282 dwc_otg_hcd->non_periodic_channels = 0;
283 dwc_otg_hcd->periodic_channels = 0;
285 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
286 /* In some case, we don't disconnect a usb device, but
287 * disconnect intr was triggered, so check hprt0 here. */
288 if ((!hprt0.b.prtenchng)
289 && (hprt0.d32 != 0x1000)
290 && (hprt0.d32 != 0x1100)) {
291 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
295 * Set status flags for the hub driver.
297 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
298 dwc_otg_hcd->flags.b.port_connect_status = 0;
301 * Shutdown any transfers in process by clearing the Tx FIFO Empty
302 * interrupt mask and status bits and disabling subsequent host
303 * channel interrupts.
306 intr.b.nptxfempty = 1;
307 intr.b.ptxfempty = 1;
309 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
311 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
315 * Turn off the vbus power only if the core has transitioned to device
316 * mode. If still in host mode, need to keep power on to detect a
319 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
320 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
321 hprt0_data_t hprt0 = {.d32 = 0 };
322 DWC_PRINTF("Disconnect: PortPower off\n");
324 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
327 /** Delete timers if become device */
328 del_timers(dwc_otg_hcd);
329 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
333 /* Respond with an error status to all URBs in the schedule. */
334 kill_all_urbs(dwc_otg_hcd);
336 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
337 /* Clean up any host channels that were in use. */
341 dwc_otg_hc_regs_t *hc_regs;
342 hcchar_data_t hcchar;
344 DWC_PRINTF("Disconnect cb-Host\n");
345 if (dwc_otg_hcd->core_if->otg_ver == 1)
346 del_xfer_timers(dwc_otg_hcd);
348 del_timers(dwc_otg_hcd);
350 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
352 if (!dwc_otg_hcd->core_if->dma_enable) {
353 /* Flush out any channel requests in slave mode. */
354 for (i = 0; i < num_channels; i++) {
355 channel = dwc_otg_hcd->hc_ptr_array[i];
356 if (DWC_CIRCLEQ_EMPTY_ENTRY
357 (channel, hc_list_entry)) {
359 dwc_otg_hcd->core_if->host_if->
362 DWC_READ_REG32(&hc_regs->hcchar);
375 for (i = 0; i < num_channels; i++) {
376 channel = dwc_otg_hcd->hc_ptr_array[i];
377 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
379 dwc_otg_hcd->core_if->host_if->hc_regs[i];
380 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
382 /* Halt the channel. */
384 DWC_WRITE_REG32(&hc_regs->hcchar,
388 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
390 DWC_CIRCLEQ_INSERT_TAIL
391 (&dwc_otg_hcd->free_hc_list, channel,
394 * Added for Descriptor DMA to prevent channel double cleanup
395 * in release_channel_ddma(). Which called from ep_disable
396 * when device disconnect.
404 if (dwc_otg_hcd->fops->disconnect) {
405 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
412 * HCD Callback function for stopping the HCD.
414 * @param p void pointer to the <code>struct usb_hcd</code>
416 static int32_t dwc_otg_hcd_stop_cb(void *p)
418 dwc_otg_hcd_t *dwc_otg_hcd = p;
420 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
421 dwc_otg_hcd_stop(dwc_otg_hcd);
425 #ifdef CONFIG_USB_DWC_OTG_LPM
427 * HCD Callback function for sleep of HCD.
429 * @param p void pointer to the <code>struct usb_hcd</code>
431 static int dwc_otg_hcd_sleep_cb(void *p)
433 dwc_otg_hcd_t *hcd = p;
435 dwc_otg_hcd_free_hc_from_lpm(hcd);
442 * HCD Callback function for Remote Wakeup.
444 * @param p void pointer to the <code>struct usb_hcd</code>
446 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd);
447 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
449 dwc_otg_hcd_t *dwc_otg_hcd = p;
450 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
452 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
453 dwc_otg_hcd->flags.b.port_suspend_change = 1;
454 usb_hcd_resume_root_hub(hcd);
456 #ifdef CONFIG_USB_DWC_OTG_LPM
458 dwc_otg_hcd->flags.b.port_l1_change = 1;
465 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
468 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
470 hprt0_data_t hprt0 = {.d32 = 0 };
471 struct dwc_otg_platform_data *pldata;
472 pldata = hcd->core_if->otg_dev->pldata;
474 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
477 * The root hub should be disconnected before this function is called.
478 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
479 * and the QH lists (via ..._hcd_endpoint_disable).
482 /* Turn off all host-specific interrupts. */
483 dwc_otg_disable_host_interrupts(hcd->core_if);
485 /* Turn off the vbus power */
486 DWC_PRINTF("PortPower off\n");
488 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
490 if (pldata->power_enable)
491 pldata->power_enable(0);
496 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
497 dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
500 dwc_irqflags_t flags;
503 gintmsk_data_t intr_mask = {.d32 = 0 };
505 if (!hcd->flags.b.port_connect_status) {
506 /* No longer connected. */
507 DWC_DEBUG("Not connected\n");
508 return -DWC_E_NO_DEVICE;
511 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
513 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
514 return -DWC_E_NO_MEMORY;
518 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle,
521 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
523 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
524 "Error status %d\n", retval);
525 dwc_otg_hcd_qtd_free(qtd);
528 DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
529 if (!intr_mask.b.sofintr && retval == 0) {
530 dwc_otg_transaction_type_e tr_type;
531 if ((qtd->qh->ep_type == UE_BULK)
532 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
533 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
537 tr_type = dwc_otg_hcd_select_transactions(hcd);
538 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
539 dwc_otg_hcd_queue_transactions(hcd, tr_type);
543 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
547 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
548 dwc_otg_hcd_urb_t *dwc_otg_urb)
551 dwc_otg_qtd_t *urb_qtd;
553 urb_qtd = dwc_otg_urb->qtd;
554 if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
555 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
556 __func__, urb_qtd, dwc_otg_urb);
561 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
562 if (urb_qtd->in_process) {
563 dump_channel_info(hcd, qh);
567 if (urb_qtd->in_process && qh->channel) {
568 /* The QTD is in process (it has been assigned to a channel). */
569 if (hcd->flags.b.port_connect_status) {
571 * If still connected (i.e. in host mode), halt the
572 * channel so it can be used for other transfers. If
573 * no longer connected, the host registers can't be
574 * written to halt the channel since the core is in
577 dwc_otg_hc_halt(hcd->core_if, qh->channel,
578 DWC_OTG_HC_XFER_URB_DEQUEUE);
583 * Free the QTD and clean up the associated QH. Leave the QH in the
584 * schedule if it has any remaining QTDs.
587 if (!hcd->core_if->dma_desc_enable) {
588 uint8_t b = urb_qtd->in_process;
589 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
591 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
593 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
594 dwc_otg_hcd_qh_remove(hcd, qh);
597 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
602 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
605 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
607 dwc_irqflags_t flags;
610 retval = -DWC_E_INVALID;
615 retval = -DWC_E_INVALID;
619 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
621 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
622 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
625 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
628 dwc_otg_hcd_qh_remove(hcd, qh);
630 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
632 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
633 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
634 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
635 * and dwc_otg_hcd_frame_list_alloc().
637 dwc_otg_hcd_qh_free(hcd, qh);
643 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
644 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
647 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
649 return -DWC_E_INVALID;
651 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
657 * HCD Callback structure for handling mode switching.
659 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
660 .start = dwc_otg_hcd_start_cb,
661 .stop = dwc_otg_hcd_stop_cb,
662 .disconnect = dwc_otg_hcd_disconnect_cb,
663 .session_start = dwc_otg_hcd_session_start_cb,
664 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
665 #ifdef CONFIG_USB_DWC_OTG_LPM
666 .sleep = dwc_otg_hcd_sleep_cb,
672 * Reset tasklet function
674 static void reset_tasklet_func(void *data)
676 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
677 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
680 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
682 hprt0.d32 = dwc_otg_read_hprt0(core_if);
684 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
688 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
689 dwc_otg_hcd->flags.b.port_reset_change = 1;
692 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
694 dwc_list_link_t *item;
696 dwc_irqflags_t flags;
698 if (!qh_list->next) {
699 /* The list hasn't been initialized yet. */
703 * Hold spinlock here. Not needed in that case if bellow
704 * function is being called from ISR
706 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
707 /* Ensure there are no QTDs or URBs left. */
708 kill_urbs_in_qh_list(hcd, qh_list);
709 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
711 DWC_LIST_FOREACH(item, qh_list) {
712 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
713 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
718 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
719 * Device during SRP time by host power up.
721 void dwc_otg_hcd_power_up(void *ptr)
723 gpwrdn_data_t gpwrdn = {.d32 = 0 };
724 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
726 DWC_PRINTF("%s called\n", __FUNCTION__);
728 if (!core_if->hibernation_suspend) {
729 DWC_PRINTF("Already exited from Hibernation\n");
733 /* Switch on the voltage to the core */
734 gpwrdn.b.pwrdnswtch = 1;
735 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
740 gpwrdn.b.pwrdnrstn = 1;
741 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
744 /* Disable power clamps */
746 gpwrdn.b.pwrdnclmp = 1;
747 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
749 /* Remove reset the core signal */
751 gpwrdn.b.pwrdnrstn = 1;
752 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
755 /* Disable PMU interrupt */
757 gpwrdn.b.pmuintsel = 1;
758 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
760 core_if->hibernation_suspend = 0;
764 gpwrdn.b.pmuactv = 1;
765 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
770 gpwrdn.b.dis_vbus = 1;
771 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
773 core_if->op_state = A_HOST;
774 dwc_otg_core_init(core_if);
775 dwc_otg_enable_global_interrupts(core_if);
776 cil_hcd_start(core_if);
780 * Frees secondary storage associated with the dwc_otg_hcd structure contained
781 * in the struct usb_hcd field.
783 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
787 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
789 del_timers(dwc_otg_hcd);
791 /* Free memory for QH/QTD lists */
792 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
793 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
794 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
795 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
796 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
797 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
799 /* Free memory for the host channels. */
800 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
801 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
804 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
805 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
809 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
815 if (dwc_otg_hcd->core_if->dma_enable) {
816 if (dwc_otg_hcd->status_buf_dma) {
817 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
818 dwc_otg_hcd->status_buf,
819 dwc_otg_hcd->status_buf_dma);
821 } else if (dwc_otg_hcd->status_buf != NULL) {
822 DWC_FREE(dwc_otg_hcd->status_buf);
824 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
825 /* Set core_if's lock pointer to NULL */
826 dwc_otg_hcd->core_if->lock = NULL;
828 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
829 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
831 #ifdef DWC_DEV_SRPCAP
832 if (dwc_otg_hcd->core_if->power_down == 2 &&
833 dwc_otg_hcd->core_if->pwron_timer) {
834 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
837 DWC_FREE(dwc_otg_hcd);
840 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
847 hcd->lock = DWC_SPINLOCK_ALLOC();
849 DWC_ERROR("Could not allocate lock for pcd");
851 retval = -DWC_E_NO_MEMORY;
854 hcd->core_if = core_if;
856 /* Register the HCD CIL Callbacks */
857 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
858 &hcd_cil_callbacks, hcd);
860 /* Initialize the non-periodic schedule. */
861 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
862 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
864 /* Initialize the periodic schedule. */
865 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
866 DWC_LIST_INIT(&hcd->periodic_sched_ready);
867 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
868 DWC_LIST_INIT(&hcd->periodic_sched_queued);
871 * Create a host channel descriptor for each host channel implemented
872 * in the controller. Initialize the channel descriptor array.
874 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
875 num_channels = hcd->core_if->core_params->host_channels;
876 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
877 for (i = 0; i < num_channels; i++) {
878 channel = DWC_ALLOC(sizeof(dwc_hc_t));
879 if (channel == NULL) {
880 retval = -DWC_E_NO_MEMORY;
881 DWC_ERROR("%s: host channel allocation failed\n",
883 dwc_otg_hcd_free(hcd);
887 hcd->hc_ptr_array[i] = channel;
889 hcd->core_if->hc_xfer_timer[i] =
890 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
891 &hcd->core_if->hc_xfer_info[i]);
893 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
897 /* Initialize the Connection timeout timer. */
898 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
899 dwc_otg_hcd_connect_timeout, hcd);
901 /* Initialize reset tasklet. */
903 DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
904 #ifdef DWC_DEV_SRPCAP
905 if (hcd->core_if->power_down == 2) {
906 /* Initialize Power on timer for Host power up in case hibernation */
907 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
908 dwc_otg_hcd_power_up,
914 * Allocate space for storing data on status transactions. Normally no
915 * data is sent, but this space acts as a bit bucket. This must be
916 * done after usb_add_hcd since that function allocates the DMA buffer
919 if (hcd->core_if->dma_enable) {
921 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
922 &hcd->status_buf_dma);
924 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
926 if (!hcd->status_buf) {
927 retval = -DWC_E_NO_MEMORY;
928 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
929 dwc_otg_hcd_free(hcd);
934 hcd->frame_list = NULL;
935 hcd->frame_list_dma = 0;
936 hcd->periodic_qh_count = 0;
941 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
943 /* Turn off all host-specific interrupts. */
944 dwc_otg_disable_host_interrupts(hcd->core_if);
946 dwc_otg_hcd_free(hcd);
950 * Initializes dynamic portions of the DWC_otg HCD state.
952 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
957 dwc_hc_t *channel_tmp;
961 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
962 hcd->non_periodic_channels = 0;
963 hcd->periodic_channels = 0;
966 * Put all channels in the free channel list and clean up channel
969 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
970 &hcd->free_hc_list, hc_list_entry) {
971 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
974 num_channels = hcd->core_if->core_params->host_channels;
975 for (i = 0; i < num_channels; i++) {
976 channel = hcd->hc_ptr_array[i];
977 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
979 dwc_otg_hc_cleanup(hcd->core_if, channel);
982 /* Initialize the DWC core for host mode operation. */
983 dwc_otg_core_host_init(hcd->core_if);
985 /* Set core_if's lock pointer to the hcd->lock */
986 hcd->core_if->lock = hcd->lock;
990 * Assigns transactions from a QTD to a free host channel and initializes the
991 * host channel to perform the transactions. The host channel is removed from
994 * @param hcd The HCD state structure.
995 * @param qh Transactions from the first QTD for this QH are selected and
996 * assigned to a free host channel.
998 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1002 dwc_otg_hcd_urb_t *urb;
1006 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1008 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1010 /* Remove the host channel from the free list. */
1011 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1013 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1017 printk("%s : urb is NULL\n", __func__);
1024 qtd->in_process = 1;
1027 * Use usb_pipedevice to determine device address. This address is
1028 * 0 before the SET_ADDRESS command and the correct address afterward.
1030 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1031 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1032 hc->speed = qh->dev_speed;
1033 hc->max_packet = dwc_max_packet(qh->maxp);
1035 hc->xfer_started = 0;
1036 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1037 hc->error_state = (qtd->error_count > 0);
1038 hc->halt_on_queue = 0;
1039 hc->halt_pending = 0;
1043 * The following values may be modified in the transfer type section
1044 * below. The xfer_len value may be reduced when the transfer is
1045 * started to accommodate the max widths of the XferSize and PktCnt
1046 * fields in the HCTSIZn register.
1049 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1053 hc->do_ping = qh->ping_state;
1055 hc->data_pid_start = qh->data_toggle;
1056 hc->multi_count = 1;
1058 if (hcd->core_if->dma_enable) {
1059 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1061 /* For non-dword aligned case */
1062 if (((unsigned long)hc->xfer_buff & 0x3)
1063 && !hcd->core_if->dma_desc_enable) {
1064 ptr = (uint8_t *) urb->buf + urb->actual_length;
1067 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1069 hc->xfer_len = urb->length - urb->actual_length;
1073 * Set the split attributes
1077 uint32_t hub_addr, port_addr;
1079 hc->xact_pos = qtd->isoc_split_pos;
1080 hc->complete_split = qtd->complete_split;
1081 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1082 hc->hub_addr = (uint8_t) hub_addr;
1083 hc->port_addr = (uint8_t) port_addr;
1086 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1088 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1089 switch (qtd->control_phase) {
1090 case DWC_OTG_CONTROL_SETUP:
1091 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1094 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1095 if (hcd->core_if->dma_enable)
1096 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1098 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1103 case DWC_OTG_CONTROL_DATA:
1104 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1105 hc->data_pid_start = qtd->data_toggle;
1107 case DWC_OTG_CONTROL_STATUS:
1109 * Direction is opposite of data direction or IN if no
1112 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1113 if (urb->length == 0) {
1117 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1122 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1125 if (hcd->core_if->dma_enable)
1126 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1128 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1135 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1138 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1140 case UE_ISOCHRONOUS:
1142 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1144 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1146 if (hcd->core_if->dma_desc_enable)
1149 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1151 frame_desc->status = 0;
1153 if (hcd->core_if->dma_enable) {
1154 hc->xfer_buff = (uint8_t *) urb->dma;
1156 hc->xfer_buff = (uint8_t *) urb->buf;
1159 frame_desc->offset + qtd->isoc_split_offset;
1161 frame_desc->length - qtd->isoc_split_offset;
1163 /* For non-dword aligned buffers */
1164 if (((unsigned long)hc->xfer_buff & 0x3)
1165 && hcd->core_if->dma_enable) {
1167 (uint8_t *) urb->buf + frame_desc->offset +
1168 qtd->isoc_split_offset;
1172 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1173 if (hc->xfer_len <= 188) {
1174 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1177 DWC_HCSPLIT_XACTPOS_BEGIN;
1183 /* non DWORD-aligned buffer case */
1186 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1187 buf_size = hcd->core_if->core_params->max_transfer_size;
1191 if (!qh->dw_align_buf) {
1192 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1195 if (!qh->dw_align_buf) {
1197 ("%s: Failed to allocate memory to handle "
1198 "non-dword aligned buffer case\n",
1203 if (!hc->ep_is_in) {
1204 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1206 hc->align_buff = qh->dw_align_buf_dma;
1211 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1212 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1214 * This value may be modified when the transfer is started to
1215 * reflect the actual transfer length.
1217 hc->multi_count = dwc_hb_mult(qh->maxp);
1220 if (hcd->core_if->dma_desc_enable)
1221 hc->desc_list_addr = qh->desc_list_dma;
1223 dwc_otg_hc_init(hcd->core_if, hc);
1229 * This function selects transactions from the HCD transfer schedule and
1230 * assigns them to available host channels. It is called from HCD interrupt
1231 * handler functions.
1233 * @param hcd The HCD state structure.
1235 * @return The types of new transactions that were assigned to host channels.
1237 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1239 dwc_list_link_t *qh_ptr;
1242 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1246 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1249 /* Process entries in the periodic ready list. */
1250 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1252 while (qh_ptr != &hcd->periodic_sched_ready &&
1253 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1255 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1256 assign_and_init_hc(hcd, qh);
1259 * Move the QH from the periodic ready schedule to the
1260 * periodic assigned schedule.
1262 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1263 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1264 &qh->qh_list_entry);
1266 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1270 * Process entries in the inactive portion of the non-periodic
1271 * schedule. Some free host channels may not be used if they are
1272 * reserved for periodic transfers.
1274 qh_ptr = hcd->non_periodic_sched_inactive.next;
1275 num_channels = hcd->core_if->core_params->host_channels;
1276 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1277 (hcd->non_periodic_channels <
1278 num_channels - hcd->periodic_channels) &&
1279 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1281 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1283 err = assign_and_init_hc(hcd, qh);
1286 * Move the QH from the non-periodic inactive schedule to the
1287 * non-periodic active schedule.
1289 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1292 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1293 &qh->qh_list_entry);
1295 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1296 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1298 ret_val = DWC_OTG_TRANSACTION_ALL;
1301 hcd->non_periodic_channels++;
1308 * Attempts to queue a single transaction request for a host channel
1309 * associated with either a periodic or non-periodic transfer. This function
1310 * assumes that there is space available in the appropriate request queue. For
1311 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1312 * is available in the appropriate Tx FIFO.
1314 * @param hcd The HCD state structure.
1315 * @param hc Host channel descriptor associated with either a periodic or
1316 * non-periodic transfer.
1317 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1318 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1321 * @return 1 if a request is queued and more requests may be needed to
1322 * complete the transfer, 0 if no more requests are required for this
1323 * transfer, -1 if there is insufficient space in the Tx FIFO.
1325 static int queue_transaction(dwc_otg_hcd_t *hcd,
1326 dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1330 if (hcd->core_if->dma_enable) {
1331 if (hcd->core_if->dma_desc_enable) {
1332 if (!hc->xfer_started
1333 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1334 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1335 hc->qh->ping_state = 0;
1337 } else if (!hc->xfer_started) {
1338 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1339 hc->qh->ping_state = 0;
1342 } else if (hc->halt_pending) {
1343 /* Don't queue a request if the channel has been halted. */
1345 } else if (hc->halt_on_queue) {
1346 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1348 } else if (hc->do_ping) {
1349 if (!hc->xfer_started) {
1350 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1353 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1354 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1355 if (!hc->xfer_started) {
1356 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1360 dwc_otg_hc_continue_transfer(hcd->core_if,
1367 if (!hc->xfer_started) {
1368 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1371 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1379 * Processes periodic channels for the next frame and queues transactions for
1380 * these channels to the DWC_otg controller. After queueing transactions, the
1381 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1382 * to queue as Periodic Tx FIFO or request queue space becomes available.
1383 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1385 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1387 hptxsts_data_t tx_status;
1388 dwc_list_link_t *qh_ptr;
1391 int no_queue_space = 0;
1392 int no_fifo_space = 0;
1394 dwc_otg_host_global_regs_t *host_regs;
1395 host_regs = hcd->core_if->host_if->host_global_regs;
1397 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1399 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1400 DWC_DEBUGPL(DBG_HCDV,
1401 " P Tx Req Queue Space Avail (before queue): %d\n",
1402 tx_status.b.ptxqspcavail);
1403 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1404 tx_status.b.ptxfspcavail);
1407 qh_ptr = hcd->periodic_sched_assigned.next;
1408 while (qh_ptr != &hcd->periodic_sched_assigned) {
1409 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1410 if (tx_status.b.ptxqspcavail == 0) {
1415 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1418 * Set a flag if we're queuing high-bandwidth in slave mode.
1419 * The flag prevents any halts to get into the request queue in
1420 * the middle of multiple high-bandwidth packets getting queued.
1422 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1423 hcd->core_if->queuing_high_bandwidth = 1;
1426 queue_transaction(hcd, qh->channel,
1427 tx_status.b.ptxfspcavail);
1434 * In Slave mode, stay on the current transfer until there is
1435 * nothing more to do or the high-bandwidth request count is
1436 * reached. In DMA mode, only need to queue one request. The
1437 * controller automatically handles multiple packets for
1438 * high-bandwidth transfers.
1440 if (hcd->core_if->dma_enable || status == 0 ||
1441 qh->channel->requests == qh->channel->multi_count) {
1442 qh_ptr = qh_ptr->next;
1444 * Move the QH from the periodic assigned schedule to
1445 * the periodic queued schedule.
1447 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1448 &qh->qh_list_entry);
1450 /* done queuing high bandwidth */
1451 hcd->core_if->queuing_high_bandwidth = 0;
1455 if (!hcd->core_if->dma_enable) {
1456 dwc_otg_core_global_regs_t *global_regs;
1457 gintmsk_data_t intr_mask = {.d32 = 0 };
1459 global_regs = hcd->core_if->core_global_regs;
1460 intr_mask.b.ptxfempty = 1;
1462 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1463 DWC_DEBUGPL(DBG_HCDV,
1464 " P Tx Req Queue Space Avail (after queue): %d\n",
1465 tx_status.b.ptxqspcavail);
1466 DWC_DEBUGPL(DBG_HCDV,
1467 " P Tx FIFO Space Avail (after queue): %d\n",
1468 tx_status.b.ptxfspcavail);
1470 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1471 no_queue_space || no_fifo_space) {
1473 * May need to queue more transactions as the request
1474 * queue or Tx FIFO empties. Enable the periodic Tx
1475 * FIFO empty interrupt. (Always use the half-empty
1476 * level to ensure that new requests are loaded as
1477 * soon as possible.)
1479 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1483 * Disable the Tx FIFO empty interrupt since there are
1484 * no more transactions that need to be queued right
1485 * now. This function is called from interrupt
1486 * handlers to queue more transactions as transfer
1489 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1496 * Processes active non-periodic channels and queues transactions for these
1497 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1498 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1499 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1500 * FIFO Empty interrupt is disabled.
1502 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1504 gnptxsts_data_t tx_status;
1505 dwc_list_link_t *orig_qh_ptr;
1508 int no_queue_space = 0;
1509 int no_fifo_space = 0;
1512 dwc_otg_core_global_regs_t *global_regs =
1513 hcd->core_if->core_global_regs;
1515 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1517 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1518 DWC_DEBUGPL(DBG_HCDV,
1519 " NP Tx Req Queue Space Avail (before queue): %d\n",
1520 tx_status.b.nptxqspcavail);
1521 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1522 tx_status.b.nptxfspcavail);
1525 * Keep track of the starting point. Skip over the start-of-list
1528 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1529 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1531 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1534 * Process once through the active list or until no more space is
1535 * available in the request queue or the Tx FIFO.
1538 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1539 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1544 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1547 queue_transaction(hcd, qh->channel,
1548 tx_status.b.nptxfspcavail);
1552 } else if (status < 0) {
1557 /* Advance to next QH, skipping start-of-list entry. */
1558 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1559 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1560 hcd->non_periodic_qh_ptr =
1561 hcd->non_periodic_qh_ptr->next;
1564 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1566 if (!hcd->core_if->dma_enable) {
1567 gintmsk_data_t intr_mask = {.d32 = 0 };
1568 intr_mask.b.nptxfempty = 1;
1571 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1572 DWC_DEBUGPL(DBG_HCDV,
1573 " NP Tx Req Queue Space Avail (after queue): %d\n",
1574 tx_status.b.nptxqspcavail);
1575 DWC_DEBUGPL(DBG_HCDV,
1576 " NP Tx FIFO Space Avail (after queue): %d\n",
1577 tx_status.b.nptxfspcavail);
1579 if (more_to_do || no_queue_space || no_fifo_space) {
1581 * May need to queue more transactions as the request
1582 * queue or Tx FIFO empties. Enable the non-periodic
1583 * Tx FIFO empty interrupt. (Always use the half-empty
1584 * level to ensure that new requests are loaded as
1585 * soon as possible.)
1587 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1591 * Disable the Tx FIFO empty interrupt since there are
1592 * no more transactions that need to be queued right
1593 * now. This function is called from interrupt
1594 * handlers to queue more transactions as transfer
1597 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1604 * This function processes the currently active host channels and queues
1605 * transactions for these channels to the DWC_otg controller. It is called
1606 * from HCD interrupt handler functions.
1608 * @param hcd The HCD state structure.
1609 * @param tr_type The type(s) of transactions to queue (non-periodic,
1610 * periodic, or both).
1612 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1613 dwc_otg_transaction_type_e tr_type)
1616 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1618 /* Process host channels associated with periodic transfers. */
1619 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1620 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1621 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1623 process_periodic_channels(hcd);
1626 /* Process host channels associated with non-periodic transfers. */
1627 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1628 tr_type == DWC_OTG_TRANSACTION_ALL) {
1629 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1630 process_non_periodic_channels(hcd);
1633 * Ensure NP Tx FIFO empty interrupt is disabled when
1634 * there are no non-periodic transfers to process.
1636 gintmsk_data_t gintmsk = {.d32 = 0 };
1637 gintmsk.b.nptxfempty = 1;
1638 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1639 gintmsk, gintmsk.d32, 0);
1644 #ifdef DWC_HS_ELECT_TST
1646 * Quick and dirty hack to implement the HS Electrical Test
1647 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1649 * This code was copied from our userspace app "hset". It sends a
1650 * Get Device Descriptor control sequence in two parts, first the
1651 * Setup packet by itself, followed some time later by the In and
1652 * Ack packets. Rather than trying to figure out how to add this
1653 * functionality to the normal driver code, we just hijack the
1654 * hardware, using these two function to drive the hardware
1658 static dwc_otg_core_global_regs_t *global_regs;
1659 static dwc_otg_host_global_regs_t *hc_global_regs;
1660 static dwc_otg_hc_regs_t *hc_regs;
1661 static uint32_t *data_fifo;
1663 static void do_setup(void)
1665 gintsts_data_t gintsts;
1666 hctsiz_data_t hctsiz;
1667 hcchar_data_t hcchar;
1672 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1675 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1678 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1681 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1684 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1687 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1690 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1693 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1696 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1699 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1702 * Send Setup packet (Get Device Descriptor)
1705 /* Make sure channel is disabled */
1706 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1707 if (hcchar.b.chen) {
1709 /* hcchar.b.chen = 1; */
1710 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1715 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1718 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1721 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1724 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1727 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1730 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1733 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1735 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1740 hctsiz.b.xfersize = 8;
1741 hctsiz.b.pktcnt = 1;
1742 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1743 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1746 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1747 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1752 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1754 /* Fill FIFO with Setup data for Get Device Descriptor */
1755 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1756 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1757 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1759 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1761 /* Wait for host channel interrupt */
1763 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1764 } while (gintsts.b.hcintr == 0);
1766 /* Disable HCINTs */
1767 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1769 /* Disable HAINTs */
1770 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1773 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1776 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1779 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1782 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1785 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1788 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1791 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1794 static void do_in_ack(void)
1796 gintsts_data_t gintsts;
1797 hctsiz_data_t hctsiz;
1798 hcchar_data_t hcchar;
1801 host_grxsts_data_t grxsts;
1804 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1807 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1810 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1813 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1816 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1819 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1822 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1825 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1828 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1831 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1834 * Receive Control In packet
1837 /* Make sure channel is disabled */
1838 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1839 if (hcchar.b.chen) {
1842 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1847 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1850 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1853 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1856 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1859 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1862 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1865 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1867 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1872 hctsiz.b.xfersize = 8;
1873 hctsiz.b.pktcnt = 1;
1874 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1875 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1878 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1879 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1884 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1886 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1888 /* Wait for receive status queue interrupt */
1890 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1891 } while (gintsts.b.rxstsqlvl == 0);
1894 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1896 /* Clear RXSTSQLVL in GINTSTS */
1898 gintsts.b.rxstsqlvl = 1;
1899 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1901 switch (grxsts.b.pktsts) {
1902 case DWC_GRXSTS_PKTSTS_IN:
1903 /* Read the data into the host buffer */
1904 if (grxsts.b.bcnt > 0) {
1906 int word_count = (grxsts.b.bcnt + 3) / 4;
1908 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1910 for (i = 0; i < word_count; i++) {
1911 (void)DWC_READ_REG32(data_fifo++);
1920 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1922 /* Wait for receive status queue interrupt */
1924 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1925 } while (gintsts.b.rxstsqlvl == 0);
1928 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1930 /* Clear RXSTSQLVL in GINTSTS */
1932 gintsts.b.rxstsqlvl = 1;
1933 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1935 switch (grxsts.b.pktsts) {
1936 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1943 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1945 /* Wait for host channel interrupt */
1947 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1948 } while (gintsts.b.hcintr == 0);
1951 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1954 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1957 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1960 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1963 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1966 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1969 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1971 /* usleep(100000); */
1976 * Send handshake packet
1980 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1983 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1986 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1989 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1992 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1995 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1998 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2000 /* Make sure channel is disabled */
2001 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2002 if (hcchar.b.chen) {
2005 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2010 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2013 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2016 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2019 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2022 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2025 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2028 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2030 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2035 hctsiz.b.xfersize = 0;
2036 hctsiz.b.pktcnt = 1;
2037 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2038 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2041 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2042 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2047 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2049 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2051 /* Wait for host channel interrupt */
2053 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2054 } while (gintsts.b.hcintr == 0);
2056 /* Disable HCINTs */
2057 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2059 /* Disable HAINTs */
2060 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2063 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2066 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2069 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2072 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2075 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2078 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2081 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2085 /** Handles hub class-specific requests. */
2086 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2089 uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2093 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2094 usb_hub_descriptor_t *hub_desc;
2095 hprt0_data_t hprt0 = {.d32 = 0 };
2097 uint32_t port_status;
2100 case UCR_CLEAR_HUB_FEATURE:
2101 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2102 "ClearHubFeature 0x%x\n", wValue);
2104 case UHF_C_HUB_LOCAL_POWER:
2105 case UHF_C_HUB_OVER_CURRENT:
2106 /* Nothing required here */
2109 retval = -DWC_E_INVALID;
2110 DWC_ERROR("DWC OTG HCD - "
2111 "ClearHubFeature request %xh unknown\n",
2115 case UCR_CLEAR_PORT_FEATURE:
2116 #ifdef CONFIG_USB_DWC_OTG_LPM
2117 if (wValue != UHF_PORT_L1)
2119 if (!wIndex || wIndex > 1)
2123 case UHF_PORT_ENABLE:
2124 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2125 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2126 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2128 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2130 case UHF_PORT_SUSPEND:
2131 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2132 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2134 if (core_if->power_down == 2) {
2135 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2137 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2140 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2142 DWC_WRITE_REG32(core_if->host_if->hprt0,
2144 hprt0.b.prtsusp = 0;
2145 /* Clear Resume bit */
2148 DWC_WRITE_REG32(core_if->host_if->hprt0,
2152 #ifdef CONFIG_USB_DWC_OTG_LPM
2155 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2156 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2159 DWC_READ_REG32(&core_if->core_global_regs->
2161 lpmcfg.b.en_utmi_sleep = 0;
2162 lpmcfg.b.hird_thres &= (~(1 << 4));
2163 lpmcfg.b.prt_sleep_sts = 1;
2164 DWC_WRITE_REG32(&core_if->core_global_regs->
2165 glpmcfg, lpmcfg.d32);
2167 /* Clear Enbl_L1Gating bit. */
2168 pcgcctl.b.enbl_sleep_gating = 1;
2169 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2174 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2176 DWC_WRITE_REG32(core_if->host_if->hprt0,
2178 /* This bit will be cleared in wakeup interrupt handle */
2182 case UHF_PORT_POWER:
2183 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2184 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2185 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2187 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2189 case UHF_PORT_INDICATOR:
2190 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2191 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2192 /* Port inidicator not supported */
2194 case UHF_C_PORT_CONNECTION:
2195 /* Clears drivers internal connect status change
2197 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2198 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2199 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2201 case UHF_C_PORT_RESET:
2202 /* Clears the driver's internal Port Reset Change
2204 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2205 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2206 dwc_otg_hcd->flags.b.port_reset_change = 0;
2208 case UHF_C_PORT_ENABLE:
2209 /* Clears the driver's internal Port
2210 * Enable/Disable Change flag */
2211 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2212 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2213 dwc_otg_hcd->flags.b.port_enable_change = 0;
2215 case UHF_C_PORT_SUSPEND:
2216 /* Clears the driver's internal Port Suspend
2217 * Change flag, which is set when resume signaling on
2218 * the host port is complete */
2219 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2220 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2221 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2223 #ifdef CONFIG_USB_DWC_OTG_LPM
2225 dwc_otg_hcd->flags.b.port_l1_change = 0;
2228 case UHF_C_PORT_OVER_CURRENT:
2229 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2230 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2231 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2234 retval = -DWC_E_INVALID;
2235 DWC_ERROR("DWC OTG HCD - "
2236 "ClearPortFeature request %xh "
2237 "unknown or unsupported\n", wValue);
2240 case UCR_GET_HUB_DESCRIPTOR:
2241 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2242 "GetHubDescriptor\n");
2243 hub_desc = (usb_hub_descriptor_t *) buf;
2244 hub_desc->bDescLength = 9;
2245 hub_desc->bDescriptorType = 0x29;
2246 hub_desc->bNbrPorts = 1;
2247 USETW(hub_desc->wHubCharacteristics, 0x08);
2248 hub_desc->bPwrOn2PwrGood = 1;
2249 hub_desc->bHubContrCurrent = 0;
2250 hub_desc->DeviceRemovable[0] = 0;
2251 hub_desc->DeviceRemovable[1] = 0xff;
2253 case UCR_GET_HUB_STATUS:
2254 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2256 DWC_MEMSET(buf, 0, 4);
2258 case UCR_GET_PORT_STATUS:
2259 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2260 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2261 wIndex, dwc_otg_hcd->flags.d32);
2262 if (!wIndex || wIndex > 1)
2267 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2268 port_status |= (1 << UHF_C_PORT_CONNECTION);
2270 if (dwc_otg_hcd->flags.b.port_enable_change)
2271 port_status |= (1 << UHF_C_PORT_ENABLE);
2273 if (dwc_otg_hcd->flags.b.port_suspend_change)
2274 port_status |= (1 << UHF_C_PORT_SUSPEND);
2276 if (dwc_otg_hcd->flags.b.port_l1_change)
2277 port_status |= (1 << UHF_C_PORT_L1);
2279 if (dwc_otg_hcd->flags.b.port_reset_change) {
2280 port_status |= (1 << UHF_C_PORT_RESET);
2283 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2284 DWC_WARN("Overcurrent change detected\n");
2285 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2288 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2290 * The port is disconnected, which means the core is
2291 * either in device mode or it soon will be. Just
2292 * return 0's for the remainder of the port status
2293 * since the port register can't be read if the core
2294 * is in device mode.
2296 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2300 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2301 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2303 if (hprt0.b.prtconnsts)
2304 port_status |= (1 << UHF_PORT_CONNECTION);
2307 port_status |= (1 << UHF_PORT_ENABLE);
2309 if (hprt0.b.prtsusp)
2310 port_status |= (1 << UHF_PORT_SUSPEND);
2312 if (hprt0.b.prtovrcurract)
2313 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2316 port_status |= (1 << UHF_PORT_RESET);
2319 port_status |= (1 << UHF_PORT_POWER);
2321 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2322 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2323 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2324 port_status |= (1 << UHF_PORT_LOW_SPEED);
2326 if (hprt0.b.prttstctl)
2327 port_status |= (1 << UHF_PORT_TEST);
2328 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2329 port_status |= (1 << UHF_PORT_L1);
2332 For Synopsys HW emulation of Power down wkup_control asserts the
2333 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2334 We intentionally tell the software that port is in L2Suspend state.
2337 if ((core_if->power_down == 2)
2338 && (core_if->hibernation_suspend == 1)) {
2339 port_status |= (1 << UHF_PORT_SUSPEND);
2341 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2343 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2346 case UCR_SET_HUB_FEATURE:
2347 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2349 /* No HUB features supported */
2351 case UCR_SET_PORT_FEATURE:
2352 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2355 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2357 * The port is disconnected, which means the core is
2358 * either in device mode or it soon will be. Just
2359 * return without doing anything since the port
2360 * register can't be written if the core is in device
2367 case UHF_PORT_SUSPEND:
2368 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2369 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2370 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2373 if (core_if->power_down == 2) {
2375 dwc_irqflags_t flags;
2376 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2377 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2378 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2379 #ifdef DWC_DEV_SRPCAP
2380 int32_t otg_cap_param =
2381 core_if->core_params->otg_cap;
2384 ("Preparing for complete power-off\n");
2386 /* Save registers before hibernation */
2387 dwc_otg_save_global_regs(core_if);
2388 dwc_otg_save_host_regs(core_if);
2390 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2391 hprt0.b.prtsusp = 1;
2393 DWC_WRITE_REG32(core_if->host_if->hprt0,
2395 /* Spin hprt0.b.prtsusp to became 1 */
2397 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2398 if (hprt0.b.prtsusp) {
2402 } while (--timeout);
2404 DWC_WARN("Suspend wasn't genereted\n");
2409 * We need to disable interrupts to prevent servicing of any IRQ
2410 * during going to hibernation
2412 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2413 core_if->lx_state = DWC_OTG_L2;
2414 #ifdef DWC_DEV_SRPCAP
2415 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2418 DWC_WRITE_REG32(core_if->host_if->hprt0,
2422 DWC_READ_REG32(&core_if->
2423 core_global_regs->gusbcfg);
2424 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2425 /* ULPI interface */
2426 /* Suspend the Phy Clock */
2428 pcgcctl.b.stoppclk = 1;
2429 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2432 gpwrdn.b.pmuactv = 1;
2434 (&core_if->core_global_regs->gpwrdn,
2437 /* UTMI+ Interface */
2438 gpwrdn.b.pmuactv = 1;
2440 (&core_if->core_global_regs->gpwrdn,
2443 pcgcctl.b.stoppclk = 1;
2444 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2448 #ifdef DWC_DEV_SRPCAP
2450 gpwrdn.b.dis_vbus = 1;
2451 DWC_MODIFY_REG32(&core_if->
2452 core_global_regs->gpwrdn, 0,
2456 gpwrdn.b.pmuintsel = 1;
2457 DWC_MODIFY_REG32(&core_if->
2458 core_global_regs->gpwrdn, 0,
2463 #ifdef DWC_DEV_SRPCAP
2464 gpwrdn.b.srp_det_msk = 1;
2466 gpwrdn.b.disconn_det_msk = 1;
2467 gpwrdn.b.lnstchng_msk = 1;
2468 gpwrdn.b.sts_chngint_msk = 1;
2469 DWC_MODIFY_REG32(&core_if->
2470 core_global_regs->gpwrdn, 0,
2474 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2476 gpwrdn.b.pwrdnclmp = 1;
2477 DWC_MODIFY_REG32(&core_if->
2478 core_global_regs->gpwrdn, 0,
2482 /* Switch off VDD */
2484 gpwrdn.b.pwrdnswtch = 1;
2485 DWC_MODIFY_REG32(&core_if->
2486 core_global_regs->gpwrdn, 0,
2489 #ifdef DWC_DEV_SRPCAP
2490 if (otg_cap_param ==
2491 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2492 core_if->pwron_timer_started = 1;
2493 DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2497 /* Save gpwrdn register for further usage if stschng interrupt */
2498 core_if->gr_backup->gpwrdn_local =
2499 DWC_READ_REG32(&core_if->core_global_regs->
2502 /* Set flag to indicate that we are in hibernation */
2503 core_if->hibernation_suspend = 1;
2504 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2507 DWC_PRINTF("Host hibernation completed\n");
2508 /* Exit from case statement */
2512 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2513 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2514 gotgctl_data_t gotgctl = {.d32 = 0 };
2515 gotgctl.b.hstsethnpen = 1;
2516 DWC_MODIFY_REG32(&core_if->
2517 core_global_regs->gotgctl, 0,
2519 core_if->op_state = A_SUSPEND;
2521 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2522 hprt0.b.prtsusp = 1;
2523 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2525 dwc_irqflags_t flags;
2526 /* Update lx_state */
2527 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2528 core_if->lx_state = DWC_OTG_L2;
2529 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2532 /* Suspend the Phy Clock */
2533 if (core_if->otg_ver == 0) {
2534 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2535 pcgcctl.b.stoppclk = 1;
2536 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2541 /* For HNP the bus must be suspended for at least 200ms. */
2542 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2543 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2544 pcgcctl.b.stoppclk = 1;
2545 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2550 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2552 if (core_if->adp_enable) {
2553 gotgctl_data_t gotgctl = {.d32 = 0 };
2554 gpwrdn_data_t gpwrdn;
2556 while (gotgctl.b.asesvld == 1) {
2559 (&core_if->core_global_regs->gotgctl);
2563 /* Enable Power Down Logic */
2565 gpwrdn.b.pmuactv = 1;
2566 DWC_MODIFY_REG32(&core_if->
2567 core_global_regs->gpwrdn, 0,
2570 /* Unmask SRP detected interrupt from Power Down Logic */
2572 gpwrdn.b.srp_det_msk = 1;
2573 DWC_MODIFY_REG32(&core_if->
2574 core_global_regs->gpwrdn, 0,
2577 dwc_otg_adp_probe_start(core_if);
2581 case UHF_PORT_POWER:
2582 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2583 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2584 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2586 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2588 case UHF_PORT_RESET:
2589 if ((core_if->power_down == 2)
2590 && (core_if->hibernation_suspend == 1)) {
2591 /* If we are going to exit from Hibernated
2592 * state via USB RESET.
2594 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2596 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2598 DWC_DEBUGPL(DBG_HCD,
2599 "DWC OTG HCD HUB CONTROL - "
2600 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2602 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2603 pcgcctl.b.enbl_sleep_gating = 1;
2604 pcgcctl.b.stoppclk = 1;
2605 DWC_MODIFY_REG32(core_if->pcgcctl,
2607 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2609 #ifdef CONFIG_USB_DWC_OTG_LPM
2611 glpmcfg_data_t lpmcfg;
2613 DWC_READ_REG32(&core_if->
2616 if (lpmcfg.b.prt_sleep_sts) {
2617 lpmcfg.b.en_utmi_sleep = 0;
2618 lpmcfg.b.hird_thres &=
2620 DWC_WRITE_REG32(&core_if->
2628 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2629 /* Clear suspend bit if resetting from suspended state. */
2630 hprt0.b.prtsusp = 0;
2631 /* When B-Host the Port reset bit is set in
2632 * the Start HCD Callback function, so that
2633 * the reset is started within 1ms of the HNP
2634 * success interrupt. */
2635 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2639 ("Indeed it is in host mode hprt0 = %08x\n",
2641 DWC_WRITE_REG32(core_if->host_if->hprt0,
2644 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2647 DWC_WRITE_REG32(core_if->host_if->hprt0,
2649 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2652 #ifdef DWC_HS_ELECT_TST
2656 gintmsk_data_t gintmsk;
2658 t = (wIndex >> 8); /* MSB wIndex USB */
2659 DWC_DEBUGPL(DBG_HCD,
2660 "DWC OTG HCD HUB CONTROL - "
2661 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2663 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2665 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2666 hprt0.b.prttstctl = t;
2667 DWC_WRITE_REG32(core_if->host_if->hprt0,
2670 /* Setup global vars with reg addresses (quick and
2671 * dirty hack, should be cleaned up)
2673 global_regs = core_if->core_global_regs;
2675 core_if->host_if->host_global_regs;
2677 (dwc_otg_hc_regs_t *) ((char *)
2681 (uint32_t *) ((char *)global_regs +
2684 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2685 /* Save current interrupt mask */
2688 (&global_regs->gintmsk);
2690 /* Disable all interrupts while we muck with
2691 * the hardware directly
2693 DWC_WRITE_REG32(&global_regs->
2696 /* 15 second delay per the test spec */
2699 /* Drive suspend on the root port */
2701 dwc_otg_read_hprt0(core_if);
2702 hprt0.b.prtsusp = 1;
2704 DWC_WRITE_REG32(core_if->
2708 /* 15 second delay per the test spec */
2711 /* Drive resume on the root port */
2713 dwc_otg_read_hprt0(core_if);
2714 hprt0.b.prtsusp = 0;
2716 DWC_WRITE_REG32(core_if->
2721 /* Clear the resume bit */
2723 DWC_WRITE_REG32(core_if->
2727 /* Restore interrupts */
2728 DWC_WRITE_REG32(&global_regs->
2731 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2732 /* Save current interrupt mask */
2735 (&global_regs->gintmsk);
2737 /* Disable all interrupts while we muck with
2738 * the hardware directly
2740 DWC_WRITE_REG32(&global_regs->
2743 /* 15 second delay per the test spec */
2746 /* Send the Setup packet */
2749 /* 15 second delay so nothing else happens for awhile */
2752 /* Restore interrupts */
2753 DWC_WRITE_REG32(&global_regs->
2756 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2757 /* Save current interrupt mask */
2760 (&global_regs->gintmsk);
2762 /* Disable all interrupts while we muck with
2763 * the hardware directly
2765 DWC_WRITE_REG32(&global_regs->
2768 /* Send the Setup packet */
2771 /* 15 second delay so nothing else happens for awhile */
2774 /* Send the In and Ack packets */
2777 /* 15 second delay so nothing else happens for awhile */
2780 /* Restore interrupts */
2781 DWC_WRITE_REG32(&global_regs->
2788 #endif /* DWC_HS_ELECT_TST */
2790 case UHF_PORT_INDICATOR:
2791 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2792 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2796 retval = -DWC_E_INVALID;
2797 DWC_ERROR("DWC OTG HCD - "
2798 "SetPortFeature request %xh "
2799 "unknown or unsupported\n", wValue);
2803 #ifdef CONFIG_USB_DWC_OTG_LPM
2804 case UCR_SET_AND_TEST_PORT_FEATURE:
2805 if (wValue != UHF_PORT_L1) {
2809 int portnum, hird, devaddr, remwake;
2810 glpmcfg_data_t lpmcfg;
2811 uint32_t time_usecs;
2812 gintsts_data_t gintsts;
2813 gintmsk_data_t gintmsk;
2815 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2818 if (wValue != UHF_PORT_L1 || wLength != 1) {
2821 /* Check if the port currently is in SLEEP state */
2823 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2824 if (lpmcfg.b.prt_sleep_sts) {
2825 DWC_INFO("Port is already in sleep mode\n");
2826 buf[0] = 0; /* Return success */
2830 portnum = wIndex & 0xf;
2831 hird = (wIndex >> 4) & 0xf;
2832 devaddr = (wIndex >> 8) & 0x7f;
2833 remwake = (wIndex >> 15);
2836 retval = -DWC_E_INVALID;
2838 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2844 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2845 portnum, hird, devaddr, remwake);
2846 /* Disable LPM interrupt */
2848 gintmsk.b.lpmtranrcvd = 1;
2849 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2852 if (dwc_otg_hcd_send_lpm
2853 (dwc_otg_hcd, devaddr, hird, remwake)) {
2854 retval = -DWC_E_INVALID;
2858 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2859 /* We will consider timeout if time_usecs microseconds pass,
2860 * and we don't receive LPM transaction status.
2861 * After receiving non-error responce(ACK/NYET/STALL) from device,
2862 * core will set lpmtranrcvd bit.
2866 DWC_READ_REG32(&core_if->core_global_regs->
2868 if (gintsts.b.lpmtranrcvd) {
2872 } while (--time_usecs);
2873 /* lpm_int bit will be cleared in LPM interrupt handler */
2880 if (!gintsts.b.lpmtranrcvd) {
2881 buf[0] = 0x3; /* Completion code is Timeout */
2882 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2885 DWC_READ_REG32(&core_if->core_global_regs->
2887 if (lpmcfg.b.lpm_resp == 0x3) {
2888 /* ACK responce from the device */
2889 buf[0] = 0x00; /* Success */
2890 } else if (lpmcfg.b.lpm_resp == 0x2) {
2891 /* NYET responce from the device */
2894 /* Otherwise responce with Timeout */
2898 DWC_PRINTF("Device responce to LPM trans is %x\n",
2900 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2905 #endif /* CONFIG_USB_DWC_OTG_LPM */
2908 retval = -DWC_E_INVALID;
2909 DWC_WARN("DWC OTG HCD - "
2910 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2911 typeReq, wIndex, wValue);
2918 #ifdef CONFIG_USB_DWC_OTG_LPM
2919 /** Returns index of host channel to perform LPM transaction. */
2920 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2922 dwc_otg_core_if_t *core_if = hcd->core_if;
2924 hcchar_data_t hcchar;
2925 gintmsk_data_t gintmsk = {.d32 = 0 };
2927 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2928 DWC_PRINTF("No free channel to select for LPM transaction\n");
2932 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2934 /* Mask host channel interrupts. */
2935 gintmsk.b.hcintr = 1;
2936 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2938 /* Fill fields that core needs for LPM transaction */
2939 hcchar.b.devaddr = devaddr;
2941 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2943 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2944 hcchar.b.epdir = 0; /* OUT */
2945 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2948 /* Remove the host channel from the free list. */
2949 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2951 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2956 /** Release hc after performing LPM transaction */
2957 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2960 glpmcfg_data_t lpmcfg;
2963 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2964 hc_num = lpmcfg.b.lpm_chan_index;
2966 hc = hcd->hc_ptr_array[hc_num];
2968 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2969 /* Return host channel to free list */
2970 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2973 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2974 uint8_t bRemoteWake)
2976 glpmcfg_data_t lpmcfg;
2977 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2980 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2985 pcgcctl.b.enbl_sleep_gating = 1;
2986 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2988 /* Read LPM config register */
2989 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2991 /* Program LPM transaction fields */
2992 lpmcfg.b.rem_wkup_en = bRemoteWake;
2993 lpmcfg.b.hird = hird;
2995 if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2996 lpmcfg.b.hird_thres = 0x16;
2997 lpmcfg.b.en_besl = 1;
2999 lpmcfg.b.hird_thres = 0x1c;
3002 lpmcfg.b.lpm_chan_index = channel;
3003 lpmcfg.b.en_utmi_sleep = 1;
3004 /* Program LPM config register */
3005 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3007 /* Send LPM transaction */
3008 lpmcfg.b.send_lpm = 1;
3009 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3014 #endif /* CONFIG_USB_DWC_OTG_LPM */
3016 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3021 return -DWC_E_INVALID;
3024 retval = (hcd->flags.b.port_connect_status_change ||
3025 hcd->flags.b.port_reset_change ||
3026 hcd->flags.b.port_enable_change ||
3027 hcd->flags.b.port_suspend_change ||
3028 hcd->flags.b.port_over_current_change);
3031 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3032 " Root port status changed\n");
3033 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
3034 hcd->flags.b.port_connect_status_change);
3035 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
3036 hcd->flags.b.port_reset_change);
3037 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
3038 hcd->flags.b.port_enable_change);
3039 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
3040 hcd->flags.b.port_suspend_change);
3041 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
3042 hcd->flags.b.port_over_current_change);
3048 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3052 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3053 host_global_regs->hfnum);
3056 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3059 return hfnum.b.frnum;
3062 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3063 struct dwc_otg_hcd_function_ops *fops)
3068 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3069 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3070 dwc_otg_hcd_reinit(hcd);
3072 retval = -DWC_E_NO_DEVICE;
3078 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3083 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3085 hcd->priv = priv_data;
3088 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3090 return hcd->otg_port;
3093 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3096 if (hcd->core_if->op_state == B_HOST) {
3105 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3106 int iso_desc_count, int atomic_alloc)
3108 dwc_otg_hcd_urb_t *dwc_otg_urb;
3112 sizeof(*dwc_otg_urb) +
3113 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3115 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3117 dwc_otg_urb = DWC_ALLOC(size);
3119 dwc_otg_urb->packet_count = iso_desc_count;
3124 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3125 uint8_t dev_addr, uint8_t ep_num,
3126 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3128 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3129 ep_type, ep_dir, mps);
3132 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3133 dev_addr, ep_num, ep_dir, ep_type, mps);
3137 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3138 void *urb_handle, void *buf, dwc_dma_t dma,
3139 uint32_t buflen, void *setup_packet,
3140 dwc_dma_t setup_dma, uint32_t flags,
3143 dwc_otg_urb->priv = urb_handle;
3144 dwc_otg_urb->buf = buf;
3145 dwc_otg_urb->dma = dma;
3146 dwc_otg_urb->length = buflen;
3147 dwc_otg_urb->setup_packet = setup_packet;
3148 dwc_otg_urb->setup_dma = setup_dma;
3149 dwc_otg_urb->flags = flags;
3150 dwc_otg_urb->interval = interval;
3151 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3154 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3156 return dwc_otg_urb->status;
3159 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3161 return dwc_otg_urb->actual_length;
3164 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3166 return dwc_otg_urb->error_count;
3169 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3170 int desc_num, uint32_t offset,
3173 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3174 dwc_otg_urb->iso_descs[desc_num].length = length;
3177 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3180 return dwc_otg_urb->iso_descs[desc_num].status;
3183 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3184 dwc_otg_urb, int desc_num)
3186 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3189 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3192 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3195 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3202 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3204 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3206 DWC_ASSERT(qh, "qh is not allocated\n");
3208 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3215 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3217 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3218 DWC_ASSERT(qh, "qh is not allocated\n");
3222 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3227 gnptxsts_data_t np_tx_status;
3228 hptxsts_data_t p_tx_status;
3230 num_channels = hcd->core_if->core_params->host_channels;
3233 ("************************************************************\n");
3234 DWC_PRINTF("HCD State:\n");
3235 DWC_PRINTF(" Num channels: %d\n", num_channels);
3236 for (i = 0; i < num_channels; i++) {
3237 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3238 DWC_PRINTF(" Channel %d:\n", i);
3239 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3240 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3241 DWC_PRINTF(" speed: %d\n", hc->speed);
3242 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3243 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3244 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3245 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3246 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3247 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3248 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3249 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3250 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3251 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3252 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3253 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3254 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3255 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3256 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3257 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3258 DWC_PRINTF(" requests: %d\n", hc->requests);
3259 DWC_PRINTF(" qh: %p\n", hc->qh);
3260 if (hc->xfer_started) {
3262 hcchar_data_t hcchar;
3263 hctsiz_data_t hctsiz;
3265 hcintmsk_data_t hcintmsk;
3267 DWC_READ_REG32(&hcd->core_if->host_if->
3268 host_global_regs->hfnum);
3270 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3273 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3276 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3279 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3281 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3282 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3283 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3284 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3285 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3287 if (hc->xfer_started && hc->qh) {
3289 dwc_otg_hcd_urb_t *urb;
3291 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3293 if (!qtd->in_process)
3297 DWC_PRINTF(" URB Info:\n");
3298 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd,
3301 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3302 dwc_otg_hcd_get_dev_addr
3304 dwc_otg_hcd_get_ep_num
3306 dwc_otg_hcd_is_pipe_in
3307 (&urb->pipe_info) ? "IN" :
3310 (" Max packet size: %d\n",
3314 (" transfer_buffer: %p\n",
3316 DWC_PRINTF(" transfer_dma: %p\n",
3319 (" transfer_buffer_length: %d\n",
3321 DWC_PRINTF(" actual_length: %d\n",
3322 urb->actual_length);
3327 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3328 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3329 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3331 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3332 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3333 np_tx_status.b.nptxqspcavail);
3334 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3335 np_tx_status.b.nptxfspcavail);
3337 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3338 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3339 p_tx_status.b.ptxqspcavail);
3340 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3341 dwc_otg_hcd_dump_frrem(hcd);
3342 dwc_otg_dump_global_registers(hcd->core_if);
3343 dwc_otg_dump_host_registers(hcd->core_if);
3345 ("************************************************************\n");
3351 void dwc_print_setup_data(uint8_t *setup)
3354 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3355 DWC_PRINTF("Setup Data = MSB ");
3356 for (i = 7; i >= 0; i--)
3357 DWC_PRINTF("%02x ", setup[i]);
3359 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3360 (setup[0] & 0x80) ? "Device-to-Host" :
3362 DWC_PRINTF(" bmRequestType Type = ");
3363 switch ((setup[0] & 0x60) >> 5) {
3365 DWC_PRINTF("Standard\n");
3368 DWC_PRINTF("Class\n");
3371 DWC_PRINTF("Vendor\n");
3374 DWC_PRINTF("Reserved\n");
3377 DWC_PRINTF(" bmRequestType Recipient = ");
3378 switch (setup[0] & 0x1f) {
3380 DWC_PRINTF("Device\n");
3383 DWC_PRINTF("Interface\n");
3386 DWC_PRINTF("Endpoint\n");
3389 DWC_PRINTF("Other\n");
3392 DWC_PRINTF("Reserved\n");
3395 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3396 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3397 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3398 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3403 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3406 DWC_PRINTF("Frame remaining at SOF:\n");
3407 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3408 hcd->frrem_samples, hcd->frrem_accum,
3409 (hcd->frrem_samples > 0) ?
3410 hcd->frrem_accum / hcd->frrem_samples : 0);
3413 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3414 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3415 hcd->core_if->hfnum_7_samples,
3416 hcd->core_if->hfnum_7_frrem_accum,
3417 (hcd->core_if->hfnum_7_samples >
3418 0) ? hcd->core_if->hfnum_7_frrem_accum /
3419 hcd->core_if->hfnum_7_samples : 0);
3420 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3421 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3422 hcd->core_if->hfnum_0_samples,
3423 hcd->core_if->hfnum_0_frrem_accum,
3424 (hcd->core_if->hfnum_0_samples >
3425 0) ? hcd->core_if->hfnum_0_frrem_accum /
3426 hcd->core_if->hfnum_0_samples : 0);
3427 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3428 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3429 hcd->core_if->hfnum_other_samples,
3430 hcd->core_if->hfnum_other_frrem_accum,
3431 (hcd->core_if->hfnum_other_samples >
3432 0) ? hcd->core_if->hfnum_other_frrem_accum /
3433 hcd->core_if->hfnum_other_samples : 0);
3436 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3437 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3438 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3439 (hcd->hfnum_7_samples_a > 0) ?
3440 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3441 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3442 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3443 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3444 (hcd->hfnum_0_samples_a > 0) ?
3445 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3446 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3447 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3448 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3449 (hcd->hfnum_other_samples_a > 0) ?
3450 hcd->hfnum_other_frrem_accum_a /
3451 hcd->hfnum_other_samples_a : 0);
3454 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3455 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3456 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3457 (hcd->hfnum_7_samples_b > 0) ?
3458 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3459 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3460 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3461 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3462 (hcd->hfnum_0_samples_b > 0) ?
3463 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3464 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3465 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3466 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3467 (hcd->hfnum_other_samples_b > 0) ?
3468 hcd->hfnum_other_frrem_accum_b /
3469 hcd->hfnum_other_samples_b : 0);
3473 #endif /* DWC_DEVICE_ONLY */