1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
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19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t *hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
178 if (qtd->urb != NULL) {
179 hcd->fops->complete(hcd, qtd->urb->priv,
180 qtd->urb, -DWC_E_SHUTDOWN);
181 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
189 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
190 * and periodic schedules. The QTD associated with each URB is removed from
191 * the schedule and freed. This function may be called when a disconnect is
192 * detected or when the HCD is being stopped.
194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
196 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
197 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
198 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
199 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
200 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
201 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
205 * Start the connection timer. An OTG host is required to display a
206 * message if the device does not connect within 10 seconds. The
207 * timer is deleted if a port connect interrupt occurs before the
210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
212 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
216 * HCD Callback function for disconnect of the HCD.
218 * @param p void pointer to the <code>struct usb_hcd</code>
220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
222 dwc_otg_hcd_t *dwc_otg_hcd;
223 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
225 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
230 * HCD Callback function for starting the HCD when A-Cable is
233 * @param p void pointer to the <code>struct usb_hcd</code>
235 static int32_t dwc_otg_hcd_start_cb(void *p)
237 dwc_otg_hcd_t *dwc_otg_hcd = p;
238 dwc_otg_core_if_t *core_if;
240 uint32_t timeout = 50;
242 core_if = dwc_otg_hcd->core_if;
244 if (core_if->op_state == B_HOST) {
246 * Reset the port. During a HNP mode switch the reset
247 * needs to occur within 1ms and have a duration of at
250 hprt0.d32 = dwc_otg_read_hprt0(core_if);
252 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
253 if (core_if->otg_ver) {
255 hprt0.d32 = dwc_otg_read_hprt0(core_if);
257 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
260 /**@todo vahrama: Check the timeout value for OTG 2.0 */
261 if (core_if->otg_ver)
263 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
264 hcd_start_func, dwc_otg_hcd, timeout,
271 * HCD Callback function for disconnect of the HCD.
273 * @param p void pointer to the <code>struct usb_hcd</code>
275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
278 dwc_otg_hcd_t *dwc_otg_hcd = p;
281 dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
282 dwc_otg_hcd->non_periodic_channels = 0;
283 dwc_otg_hcd->periodic_channels = 0;
284 dwc_otg_hcd->frame_number =0;
286 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
287 /* In some case, we don't disconnect a usb device, but
288 * disconnect intr was triggered, so check hprt0 here. */
289 if ((!hprt0.b.prtenchng)
290 && (!hprt0.b.prtconndet)
291 && hprt0.b.prtconnsts) {
292 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
296 * Set status flags for the hub driver.
298 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
299 dwc_otg_hcd->flags.b.port_connect_status = 0;
302 * Shutdown any transfers in process by clearing the Tx FIFO Empty
303 * interrupt mask and status bits and disabling subsequent host
304 * channel interrupts.
307 intr.b.nptxfempty = 1;
308 intr.b.ptxfempty = 1;
310 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
312 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
316 * Turn off the vbus power only if the core has transitioned to device
317 * mode. If still in host mode, need to keep power on to detect a
320 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
321 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
322 hprt0_data_t hprt0 = {.d32 = 0 };
323 DWC_PRINTF("Disconnect: PortPower off\n");
325 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
328 /** Delete timers if become device */
329 del_timers(dwc_otg_hcd);
330 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
334 /* Respond with an error status to all URBs in the schedule. */
335 kill_all_urbs(dwc_otg_hcd);
337 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
338 /* Clean up any host channels that were in use. */
342 dwc_otg_hc_regs_t *hc_regs;
343 hcchar_data_t hcchar;
345 DWC_PRINTF("Disconnect cb-Host\n");
346 if (dwc_otg_hcd->core_if->otg_ver == 1)
347 del_xfer_timers(dwc_otg_hcd);
349 del_timers(dwc_otg_hcd);
351 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
353 if (!dwc_otg_hcd->core_if->dma_enable) {
354 /* Flush out any channel requests in slave mode. */
355 for (i = 0; i < num_channels; i++) {
356 channel = dwc_otg_hcd->hc_ptr_array[i];
357 if (DWC_CIRCLEQ_EMPTY_ENTRY
358 (channel, hc_list_entry)) {
360 dwc_otg_hcd->core_if->host_if->
363 DWC_READ_REG32(&hc_regs->hcchar);
376 for (i = 0; i < num_channels; i++) {
377 channel = dwc_otg_hcd->hc_ptr_array[i];
378 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
380 dwc_otg_hcd->core_if->host_if->hc_regs[i];
381 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
383 /* Halt the channel. */
385 DWC_WRITE_REG32(&hc_regs->hcchar,
389 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
391 DWC_CIRCLEQ_INSERT_TAIL
392 (&dwc_otg_hcd->free_hc_list, channel,
395 * Added for Descriptor DMA to prevent channel double cleanup
396 * in release_channel_ddma(). Which called from ep_disable
397 * when device disconnect.
405 if (dwc_otg_hcd->fops->disconnect) {
406 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
413 * HCD Callback function for stopping the HCD.
415 * @param p void pointer to the <code>struct usb_hcd</code>
417 static int32_t dwc_otg_hcd_stop_cb(void *p)
419 dwc_otg_hcd_t *dwc_otg_hcd = p;
421 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
422 dwc_otg_hcd_stop(dwc_otg_hcd);
426 #ifdef CONFIG_USB_DWC_OTG_LPM
428 * HCD Callback function for sleep of HCD.
430 * @param p void pointer to the <code>struct usb_hcd</code>
432 static int dwc_otg_hcd_sleep_cb(void *p)
434 dwc_otg_hcd_t *hcd = p;
436 dwc_otg_hcd_free_hc_from_lpm(hcd);
443 * HCD Callback function for Remote Wakeup.
445 * @param p void pointer to the <code>struct usb_hcd</code>
447 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
449 dwc_otg_hcd_t *dwc_otg_hcd = p;
450 struct usb_hcd *hcd = dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
452 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
453 dwc_otg_hcd->flags.b.port_suspend_change = 1;
454 usb_hcd_resume_root_hub(hcd);
456 #ifdef CONFIG_USB_DWC_OTG_LPM
458 dwc_otg_hcd->flags.b.port_l1_change = 1;
465 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
468 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
470 hprt0_data_t hprt0 = {.d32 = 0 };
471 struct dwc_otg_platform_data *pldata;
472 pldata = hcd->core_if->otg_dev->pldata;
474 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
477 * The root hub should be disconnected before this function is called.
478 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
479 * and the QH lists (via ..._hcd_endpoint_disable).
482 /* Turn off all host-specific interrupts. */
483 dwc_otg_disable_host_interrupts(hcd->core_if);
485 /* Turn off the vbus power */
486 DWC_PRINTF("PortPower off\n");
488 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
490 if (pldata->power_enable)
491 pldata->power_enable(0);
496 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
497 dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
500 dwc_irqflags_t flags;
503 gintmsk_data_t intr_mask = {.d32 = 0 };
505 if (!hcd->flags.b.port_connect_status) {
506 /* No longer connected. */
507 DWC_DEBUG("Not connected\n");
508 return -DWC_E_NO_DEVICE;
511 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
513 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
514 return -DWC_E_NO_MEMORY;
516 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
518 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
521 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
522 "Error status %d\n", retval);
523 dwc_otg_hcd_qtd_free(qtd);
526 DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
527 if (!intr_mask.b.sofintr && retval == 0) {
528 dwc_otg_transaction_type_e tr_type;
529 if ((qtd->qh->ep_type == UE_BULK)
530 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
531 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
535 tr_type = dwc_otg_hcd_select_transactions(hcd);
536 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
537 dwc_otg_hcd_queue_transactions(hcd, tr_type);
541 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
545 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
546 dwc_otg_hcd_urb_t *dwc_otg_urb)
549 dwc_otg_qtd_t *urb_qtd;
551 urb_qtd = dwc_otg_urb->qtd;
552 if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
553 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
554 __func__, urb_qtd, dwc_otg_urb);
559 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
560 if (urb_qtd->in_process) {
561 dump_channel_info(hcd, qh);
565 if (urb_qtd->in_process && qh->channel) {
566 /* The QTD is in process (it has been assigned to a channel). */
567 if (hcd->flags.b.port_connect_status) {
569 * If still connected (i.e. in host mode), halt the
570 * channel so it can be used for other transfers. If
571 * no longer connected, the host registers can't be
572 * written to halt the channel since the core is in
575 dwc_otg_hc_halt(hcd->core_if, qh->channel,
576 DWC_OTG_HC_XFER_URB_DEQUEUE);
581 * Free the QTD and clean up the associated QH. Leave the QH in the
582 * schedule if it has any remaining QTDs.
585 if (!hcd->core_if->dma_desc_enable) {
586 uint8_t b = urb_qtd->in_process;
587 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
589 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
591 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
592 dwc_otg_hcd_qh_remove(hcd, qh);
595 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
600 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
603 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
605 dwc_irqflags_t flags;
608 retval = -DWC_E_INVALID;
613 retval = -DWC_E_INVALID;
617 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
619 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
620 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
623 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
626 dwc_otg_hcd_qh_remove(hcd, qh);
628 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
630 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
631 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
632 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
633 * and dwc_otg_hcd_frame_list_alloc().
635 dwc_otg_hcd_qh_free(hcd, qh);
641 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
642 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
645 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
647 return -DWC_E_INVALID;
649 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
655 * HCD Callback structure for handling mode switching.
657 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
658 .start = dwc_otg_hcd_start_cb,
659 .stop = dwc_otg_hcd_stop_cb,
660 .disconnect = dwc_otg_hcd_disconnect_cb,
661 .session_start = dwc_otg_hcd_session_start_cb,
662 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
663 #ifdef CONFIG_USB_DWC_OTG_LPM
664 .sleep = dwc_otg_hcd_sleep_cb,
670 * Reset tasklet function
672 static void reset_tasklet_func(void *data)
674 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
675 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
678 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
680 hprt0.d32 = dwc_otg_read_hprt0(core_if);
682 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
686 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
687 dwc_otg_hcd->flags.b.port_reset_change = 1;
690 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
692 dwc_list_link_t *item;
694 dwc_irqflags_t flags;
696 if (!qh_list->next) {
697 /* The list hasn't been initialized yet. */
701 * Hold spinlock here. Not needed in that case if bellow
702 * function is being called from ISR
704 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
705 /* Ensure there are no QTDs or URBs left. */
706 kill_urbs_in_qh_list(hcd, qh_list);
707 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
709 DWC_LIST_FOREACH(item, qh_list) {
710 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
711 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
716 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
717 * Device during SRP time by host power up.
719 void dwc_otg_hcd_power_up(void *ptr)
721 gpwrdn_data_t gpwrdn = {.d32 = 0 };
722 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
724 DWC_PRINTF("%s called\n", __FUNCTION__);
726 if (!core_if->hibernation_suspend) {
727 DWC_PRINTF("Already exited from Hibernation\n");
731 /* Switch on the voltage to the core */
732 gpwrdn.b.pwrdnswtch = 1;
733 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
738 gpwrdn.b.pwrdnrstn = 1;
739 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
742 /* Disable power clamps */
744 gpwrdn.b.pwrdnclmp = 1;
745 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
747 /* Remove reset the core signal */
749 gpwrdn.b.pwrdnrstn = 1;
750 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
753 /* Disable PMU interrupt */
755 gpwrdn.b.pmuintsel = 1;
756 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
758 core_if->hibernation_suspend = 0;
762 gpwrdn.b.pmuactv = 1;
763 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
768 gpwrdn.b.dis_vbus = 1;
769 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
771 core_if->op_state = A_HOST;
772 dwc_otg_core_init(core_if);
773 dwc_otg_enable_global_interrupts(core_if);
774 cil_hcd_start(core_if);
778 * Frees secondary storage associated with the dwc_otg_hcd structure contained
779 * in the struct usb_hcd field.
781 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
785 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
787 del_timers(dwc_otg_hcd);
789 /* Free memory for QH/QTD lists */
790 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
791 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
792 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
793 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
794 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
795 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
797 /* Free memory for the host channels. */
798 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
799 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
802 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
803 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
807 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
813 if (dwc_otg_hcd->core_if->dma_enable) {
814 if (dwc_otg_hcd->status_buf_dma) {
815 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
816 dwc_otg_hcd->status_buf,
817 dwc_otg_hcd->status_buf_dma);
819 } else if (dwc_otg_hcd->status_buf != NULL) {
820 DWC_FREE(dwc_otg_hcd->status_buf);
822 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
823 /* Set core_if's lock pointer to NULL */
824 dwc_otg_hcd->core_if->lock = NULL;
826 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
827 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
829 #ifdef DWC_DEV_SRPCAP
830 if (dwc_otg_hcd->core_if->power_down == 2 &&
831 dwc_otg_hcd->core_if->pwron_timer) {
832 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
835 DWC_FREE(dwc_otg_hcd);
838 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
845 hcd->lock = DWC_SPINLOCK_ALLOC();
847 DWC_ERROR("Could not allocate lock for pcd");
849 retval = -DWC_E_NO_MEMORY;
852 hcd->core_if = core_if;
854 /* Register the HCD CIL Callbacks */
855 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
856 &hcd_cil_callbacks, hcd);
858 /* Initialize the non-periodic schedule. */
859 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
860 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
862 /* Initialize the periodic schedule. */
863 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
864 DWC_LIST_INIT(&hcd->periodic_sched_ready);
865 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
866 DWC_LIST_INIT(&hcd->periodic_sched_queued);
869 * Create a host channel descriptor for each host channel implemented
870 * in the controller. Initialize the channel descriptor array.
872 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
873 num_channels = hcd->core_if->core_params->host_channels;
874 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
875 for (i = 0; i < num_channels; i++) {
876 channel = DWC_ALLOC(sizeof(dwc_hc_t));
877 if (channel == NULL) {
878 retval = -DWC_E_NO_MEMORY;
879 DWC_ERROR("%s: host channel allocation failed\n",
881 dwc_otg_hcd_free(hcd);
885 hcd->hc_ptr_array[i] = channel;
887 hcd->core_if->hc_xfer_timer[i] =
888 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
889 &hcd->core_if->hc_xfer_info[i]);
891 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
895 /* Initialize the Connection timeout timer. */
896 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
897 dwc_otg_hcd_connect_timeout, hcd);
899 /* Initialize reset tasklet. */
901 DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
902 #ifdef DWC_DEV_SRPCAP
903 if (hcd->core_if->power_down == 2) {
904 /* Initialize Power on timer for Host power up in case hibernation */
905 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
906 dwc_otg_hcd_power_up,
912 * Allocate space for storing data on status transactions. Normally no
913 * data is sent, but this space acts as a bit bucket. This must be
914 * done after usb_add_hcd since that function allocates the DMA buffer
917 if (hcd->core_if->dma_enable) {
919 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
920 &hcd->status_buf_dma);
922 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
924 if (!hcd->status_buf) {
925 retval = -DWC_E_NO_MEMORY;
926 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
927 dwc_otg_hcd_free(hcd);
932 hcd->frame_list = NULL;
933 hcd->frame_list_dma = 0;
934 hcd->periodic_qh_count = 0;
939 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
941 /* Turn off all host-specific interrupts. */
942 dwc_otg_disable_host_interrupts(hcd->core_if);
944 dwc_otg_hcd_free(hcd);
948 * Initializes dynamic portions of the DWC_otg HCD state.
950 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
955 dwc_hc_t *channel_tmp;
959 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
960 hcd->non_periodic_channels = 0;
961 hcd->periodic_channels = 0;
964 * Put all channels in the free channel list and clean up channel
967 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
968 &hcd->free_hc_list, hc_list_entry) {
969 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
972 num_channels = hcd->core_if->core_params->host_channels;
973 for (i = 0; i < num_channels; i++) {
974 channel = hcd->hc_ptr_array[i];
975 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
977 dwc_otg_hc_cleanup(hcd->core_if, channel);
980 /* Initialize the DWC core for host mode operation. */
981 dwc_otg_core_host_init(hcd->core_if);
983 /* Set core_if's lock pointer to the hcd->lock */
984 hcd->core_if->lock = hcd->lock;
988 * Assigns transactions from a QTD to a free host channel and initializes the
989 * host channel to perform the transactions. The host channel is removed from
992 * @param hcd The HCD state structure.
993 * @param qh Transactions from the first QTD for this QH are selected and
994 * assigned to a free host channel.
996 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1000 dwc_otg_hcd_urb_t *urb;
1004 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1006 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1008 /* Remove the host channel from the free list. */
1009 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1011 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1015 printk("%s : urb is NULL\n", __func__);
1022 qtd->in_process = 1;
1025 * Use usb_pipedevice to determine device address. This address is
1026 * 0 before the SET_ADDRESS command and the correct address afterward.
1028 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1029 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1030 hc->speed = qh->dev_speed;
1031 hc->max_packet = dwc_max_packet(qh->maxp);
1033 hc->xfer_started = 0;
1034 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1035 hc->error_state = (qtd->error_count > 0);
1036 hc->halt_on_queue = 0;
1037 hc->halt_pending = 0;
1041 * The following values may be modified in the transfer type section
1042 * below. The xfer_len value may be reduced when the transfer is
1043 * started to accommodate the max widths of the XferSize and PktCnt
1044 * fields in the HCTSIZn register.
1047 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1051 hc->do_ping = qh->ping_state;
1053 hc->data_pid_start = qh->data_toggle;
1054 hc->multi_count = 1;
1056 if (hcd->core_if->dma_enable) {
1057 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1059 /* For non-dword aligned case */
1060 if (((unsigned long)hc->xfer_buff & 0x3)
1061 && !hcd->core_if->dma_desc_enable) {
1062 ptr = (uint8_t *) urb->buf + urb->actual_length;
1065 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1067 hc->xfer_len = urb->length - urb->actual_length;
1071 * Set the split attributes
1076 uint32_t hub_addr, port_addr;
1078 hc->xact_pos = qtd->isoc_split_pos;
1079 hc->complete_split = qtd->complete_split;
1080 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1081 hc->hub_addr = (uint8_t) hub_addr;
1082 hc->port_addr = (uint8_t) port_addr;
1085 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1087 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1088 switch (qtd->control_phase) {
1089 case DWC_OTG_CONTROL_SETUP:
1090 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1093 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1094 if (hcd->core_if->dma_enable)
1095 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1097 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1102 case DWC_OTG_CONTROL_DATA:
1103 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1104 hc->data_pid_start = qtd->data_toggle;
1106 case DWC_OTG_CONTROL_STATUS:
1108 * Direction is opposite of data direction or IN if no
1111 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1112 if (urb->length == 0) {
1116 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1121 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1124 if (hcd->core_if->dma_enable)
1125 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1127 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1134 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1137 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1139 case UE_ISOCHRONOUS:
1141 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1143 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1145 if (hcd->core_if->dma_desc_enable)
1148 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1150 frame_desc->status = 0;
1152 if (hcd->core_if->dma_enable) {
1153 hc->xfer_buff = (uint8_t *) urb->dma;
1155 hc->xfer_buff = (uint8_t *) urb->buf;
1158 frame_desc->offset + qtd->isoc_split_offset;
1160 frame_desc->length - qtd->isoc_split_offset;
1162 /* For non-dword aligned buffers */
1163 if (((unsigned long)hc->xfer_buff & 0x3)
1164 && hcd->core_if->dma_enable) {
1166 (uint8_t *) urb->buf + frame_desc->offset +
1167 qtd->isoc_split_offset;
1171 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1172 if (hc->xfer_len <= 188) {
1173 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1176 DWC_HCSPLIT_XACTPOS_BEGIN;
1182 /* non DWORD-aligned buffer case */
1185 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1186 buf_size = hcd->core_if->core_params->max_transfer_size;
1190 if (!qh->dw_align_buf) {
1191 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1194 if (!qh->dw_align_buf) {
1196 ("%s: Failed to allocate memory to handle "
1197 "non-dword aligned buffer case\n",
1202 if (!hc->ep_is_in) {
1203 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1205 hc->align_buff = qh->dw_align_buf_dma;
1210 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1211 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1213 * This value may be modified when the transfer is started to
1214 * reflect the actual transfer length.
1216 hc->multi_count = dwc_hb_mult(qh->maxp);
1219 if (hcd->core_if->dma_desc_enable)
1220 hc->desc_list_addr = qh->desc_list_dma;
1222 dwc_otg_hc_init(hcd->core_if, hc);
1228 * This function selects transactions from the HCD transfer schedule and
1229 * assigns them to available host channels. It is called from HCD interrupt
1230 * handler functions.
1232 * @param hcd The HCD state structure.
1234 * @return The types of new transactions that were assigned to host channels.
1236 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1238 dwc_list_link_t *qh_ptr;
1241 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1245 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1248 /* Process entries in the periodic ready list. */
1249 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1251 while (qh_ptr != &hcd->periodic_sched_ready &&
1252 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1254 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1255 assign_and_init_hc(hcd, qh);
1258 * Move the QH from the periodic ready schedule to the
1259 * periodic assigned schedule.
1261 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1262 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1263 &qh->qh_list_entry);
1265 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1269 * Process entries in the inactive portion of the non-periodic
1270 * schedule. Some free host channels may not be used if they are
1271 * reserved for periodic transfers.
1273 qh_ptr = hcd->non_periodic_sched_inactive.next;
1274 num_channels = hcd->core_if->core_params->host_channels;
1275 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1276 (hcd->non_periodic_channels <
1277 num_channels - hcd->periodic_channels) &&
1278 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1280 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1282 err = assign_and_init_hc(hcd, qh);
1285 * Move the QH from the non-periodic inactive schedule to the
1286 * non-periodic active schedule.
1288 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1291 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1292 &qh->qh_list_entry);
1294 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1295 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1297 ret_val = DWC_OTG_TRANSACTION_ALL;
1300 hcd->non_periodic_channels++;
1307 * Attempts to queue a single transaction request for a host channel
1308 * associated with either a periodic or non-periodic transfer. This function
1309 * assumes that there is space available in the appropriate request queue. For
1310 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1311 * is available in the appropriate Tx FIFO.
1313 * @param hcd The HCD state structure.
1314 * @param hc Host channel descriptor associated with either a periodic or
1315 * non-periodic transfer.
1316 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1317 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1320 * @return 1 if a request is queued and more requests may be needed to
1321 * complete the transfer, 0 if no more requests are required for this
1322 * transfer, -1 if there is insufficient space in the Tx FIFO.
1324 static int queue_transaction(dwc_otg_hcd_t *hcd,
1325 dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1329 if (hcd->core_if->dma_enable) {
1330 if (hcd->core_if->dma_desc_enable) {
1331 if (!hc->xfer_started
1332 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1333 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1334 hc->qh->ping_state = 0;
1336 } else if (!hc->xfer_started) {
1337 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1338 hc->qh->ping_state = 0;
1341 } else if (hc->halt_pending) {
1342 /* Don't queue a request if the channel has been halted. */
1344 } else if (hc->halt_on_queue) {
1345 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1347 } else if (hc->do_ping) {
1348 if (!hc->xfer_started) {
1349 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1352 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1353 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1354 if (!hc->xfer_started) {
1355 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1359 dwc_otg_hc_continue_transfer(hcd->core_if,
1366 if (!hc->xfer_started) {
1367 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1370 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1378 * Processes periodic channels for the next frame and queues transactions for
1379 * these channels to the DWC_otg controller. After queueing transactions, the
1380 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1381 * to queue as Periodic Tx FIFO or request queue space becomes available.
1382 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1384 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1386 hptxsts_data_t tx_status;
1387 dwc_list_link_t *qh_ptr;
1390 int no_queue_space = 0;
1391 int no_fifo_space = 0;
1393 dwc_otg_host_global_regs_t *host_regs;
1394 host_regs = hcd->core_if->host_if->host_global_regs;
1396 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1398 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1399 DWC_DEBUGPL(DBG_HCDV,
1400 " P Tx Req Queue Space Avail (before queue): %d\n",
1401 tx_status.b.ptxqspcavail);
1402 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1403 tx_status.b.ptxfspcavail);
1406 qh_ptr = hcd->periodic_sched_assigned.next;
1407 while (qh_ptr != &hcd->periodic_sched_assigned) {
1408 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1409 if (tx_status.b.ptxqspcavail == 0) {
1414 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1417 * Set a flag if we're queuing high-bandwidth in slave mode.
1418 * The flag prevents any halts to get into the request queue in
1419 * the middle of multiple high-bandwidth packets getting queued.
1421 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1422 hcd->core_if->queuing_high_bandwidth = 1;
1425 queue_transaction(hcd, qh->channel,
1426 tx_status.b.ptxfspcavail);
1433 * In Slave mode, stay on the current transfer until there is
1434 * nothing more to do or the high-bandwidth request count is
1435 * reached. In DMA mode, only need to queue one request. The
1436 * controller automatically handles multiple packets for
1437 * high-bandwidth transfers.
1439 if (hcd->core_if->dma_enable || status == 0 ||
1440 qh->channel->requests == qh->channel->multi_count) {
1441 qh_ptr = qh_ptr->next;
1443 * Move the QH from the periodic assigned schedule to
1444 * the periodic queued schedule.
1446 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1447 &qh->qh_list_entry);
1449 /* done queuing high bandwidth */
1450 hcd->core_if->queuing_high_bandwidth = 0;
1454 if (!hcd->core_if->dma_enable) {
1455 dwc_otg_core_global_regs_t *global_regs;
1456 gintmsk_data_t intr_mask = {.d32 = 0 };
1458 global_regs = hcd->core_if->core_global_regs;
1459 intr_mask.b.ptxfempty = 1;
1461 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1462 DWC_DEBUGPL(DBG_HCDV,
1463 " P Tx Req Queue Space Avail (after queue): %d\n",
1464 tx_status.b.ptxqspcavail);
1465 DWC_DEBUGPL(DBG_HCDV,
1466 " P Tx FIFO Space Avail (after queue): %d\n",
1467 tx_status.b.ptxfspcavail);
1469 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1470 no_queue_space || no_fifo_space) {
1472 * May need to queue more transactions as the request
1473 * queue or Tx FIFO empties. Enable the periodic Tx
1474 * FIFO empty interrupt. (Always use the half-empty
1475 * level to ensure that new requests are loaded as
1476 * soon as possible.)
1478 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1482 * Disable the Tx FIFO empty interrupt since there are
1483 * no more transactions that need to be queued right
1484 * now. This function is called from interrupt
1485 * handlers to queue more transactions as transfer
1488 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1495 * Processes active non-periodic channels and queues transactions for these
1496 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1497 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1498 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1499 * FIFO Empty interrupt is disabled.
1501 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1503 gnptxsts_data_t tx_status;
1504 dwc_list_link_t *orig_qh_ptr;
1507 int no_queue_space = 0;
1508 int no_fifo_space = 0;
1511 dwc_otg_core_global_regs_t *global_regs =
1512 hcd->core_if->core_global_regs;
1514 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1516 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1517 DWC_DEBUGPL(DBG_HCDV,
1518 " NP Tx Req Queue Space Avail (before queue): %d\n",
1519 tx_status.b.nptxqspcavail);
1520 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1521 tx_status.b.nptxfspcavail);
1524 * Keep track of the starting point. Skip over the start-of-list
1527 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1528 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1530 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1533 * Process once through the active list or until no more space is
1534 * available in the request queue or the Tx FIFO.
1537 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1538 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1543 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1546 queue_transaction(hcd, qh->channel,
1547 tx_status.b.nptxfspcavail);
1551 } else if (status < 0) {
1556 /* Advance to next QH, skipping start-of-list entry. */
1557 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1558 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1559 hcd->non_periodic_qh_ptr =
1560 hcd->non_periodic_qh_ptr->next;
1563 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1565 if (!hcd->core_if->dma_enable) {
1566 gintmsk_data_t intr_mask = {.d32 = 0 };
1567 intr_mask.b.nptxfempty = 1;
1570 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1571 DWC_DEBUGPL(DBG_HCDV,
1572 " NP Tx Req Queue Space Avail (after queue): %d\n",
1573 tx_status.b.nptxqspcavail);
1574 DWC_DEBUGPL(DBG_HCDV,
1575 " NP Tx FIFO Space Avail (after queue): %d\n",
1576 tx_status.b.nptxfspcavail);
1578 if (more_to_do || no_queue_space || no_fifo_space) {
1580 * May need to queue more transactions as the request
1581 * queue or Tx FIFO empties. Enable the non-periodic
1582 * Tx FIFO empty interrupt. (Always use the half-empty
1583 * level to ensure that new requests are loaded as
1584 * soon as possible.)
1586 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1590 * Disable the Tx FIFO empty interrupt since there are
1591 * no more transactions that need to be queued right
1592 * now. This function is called from interrupt
1593 * handlers to queue more transactions as transfer
1596 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1603 * This function processes the currently active host channels and queues
1604 * transactions for these channels to the DWC_otg controller. It is called
1605 * from HCD interrupt handler functions.
1607 * @param hcd The HCD state structure.
1608 * @param tr_type The type(s) of transactions to queue (non-periodic,
1609 * periodic, or both).
1611 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1612 dwc_otg_transaction_type_e tr_type)
1615 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1617 /* Process host channels associated with periodic transfers. */
1618 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1619 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1620 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1622 process_periodic_channels(hcd);
1625 /* Process host channels associated with non-periodic transfers. */
1626 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1627 tr_type == DWC_OTG_TRANSACTION_ALL) {
1628 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1629 process_non_periodic_channels(hcd);
1632 * Ensure NP Tx FIFO empty interrupt is disabled when
1633 * there are no non-periodic transfers to process.
1635 gintmsk_data_t gintmsk = {.d32 = 0 };
1636 gintmsk.b.nptxfempty = 1;
1637 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1638 gintmsk, gintmsk.d32, 0);
1643 #ifdef DWC_HS_ELECT_TST
1645 * Quick and dirty hack to implement the HS Electrical Test
1646 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1648 * This code was copied from our userspace app "hset". It sends a
1649 * Get Device Descriptor control sequence in two parts, first the
1650 * Setup packet by itself, followed some time later by the In and
1651 * Ack packets. Rather than trying to figure out how to add this
1652 * functionality to the normal driver code, we just hijack the
1653 * hardware, using these two function to drive the hardware
1657 static dwc_otg_core_global_regs_t *global_regs;
1658 static dwc_otg_host_global_regs_t *hc_global_regs;
1659 static dwc_otg_hc_regs_t *hc_regs;
1660 static uint32_t *data_fifo;
1662 static void do_setup(void)
1664 gintsts_data_t gintsts;
1665 hctsiz_data_t hctsiz;
1666 hcchar_data_t hcchar;
1671 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1674 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1677 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1680 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1683 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1686 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1689 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1692 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1695 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1698 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1701 * Send Setup packet (Get Device Descriptor)
1704 /* Make sure channel is disabled */
1705 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1706 if (hcchar.b.chen) {
1708 /* hcchar.b.chen = 1; */
1709 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1714 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1717 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1720 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1723 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1726 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1729 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1732 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1734 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1739 hctsiz.b.xfersize = 8;
1740 hctsiz.b.pktcnt = 1;
1741 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1742 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1745 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1746 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1751 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1753 /* Fill FIFO with Setup data for Get Device Descriptor */
1754 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1755 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1756 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1758 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1760 /* Wait for host channel interrupt */
1762 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1763 } while (gintsts.b.hcintr == 0);
1765 /* Disable HCINTs */
1766 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1768 /* Disable HAINTs */
1769 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1772 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1775 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1778 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1781 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1784 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1787 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1790 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1793 static void do_in_ack(void)
1795 gintsts_data_t gintsts;
1796 hctsiz_data_t hctsiz;
1797 hcchar_data_t hcchar;
1800 host_grxsts_data_t grxsts;
1803 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1806 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1809 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1812 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1815 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1818 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1821 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1824 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1827 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1830 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1833 * Receive Control In packet
1836 /* Make sure channel is disabled */
1837 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1838 if (hcchar.b.chen) {
1841 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1846 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1849 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1852 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1855 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1858 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1861 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1864 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1866 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1871 hctsiz.b.xfersize = 8;
1872 hctsiz.b.pktcnt = 1;
1873 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1874 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1877 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1878 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1883 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1885 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1887 /* Wait for receive status queue interrupt */
1889 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1890 } while (gintsts.b.rxstsqlvl == 0);
1893 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1895 /* Clear RXSTSQLVL in GINTSTS */
1897 gintsts.b.rxstsqlvl = 1;
1898 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1900 switch (grxsts.b.pktsts) {
1901 case DWC_GRXSTS_PKTSTS_IN:
1902 /* Read the data into the host buffer */
1903 if (grxsts.b.bcnt > 0) {
1905 int word_count = (grxsts.b.bcnt + 3) / 4;
1907 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1909 for (i = 0; i < word_count; i++) {
1910 (void)DWC_READ_REG32(data_fifo++);
1919 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1921 /* Wait for receive status queue interrupt */
1923 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1924 } while (gintsts.b.rxstsqlvl == 0);
1927 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1929 /* Clear RXSTSQLVL in GINTSTS */
1931 gintsts.b.rxstsqlvl = 1;
1932 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1934 switch (grxsts.b.pktsts) {
1935 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1942 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1944 /* Wait for host channel interrupt */
1946 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1947 } while (gintsts.b.hcintr == 0);
1950 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1953 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1956 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1959 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1962 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1965 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1968 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1970 /* usleep(100000); */
1975 * Send handshake packet
1979 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1982 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1985 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1988 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1991 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1994 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1997 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1999 /* Make sure channel is disabled */
2000 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2001 if (hcchar.b.chen) {
2004 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2009 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2012 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2015 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2018 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2021 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2024 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2027 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2029 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2034 hctsiz.b.xfersize = 0;
2035 hctsiz.b.pktcnt = 1;
2036 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2037 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2040 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2041 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2046 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2048 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2050 /* Wait for host channel interrupt */
2052 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2053 } while (gintsts.b.hcintr == 0);
2055 /* Disable HCINTs */
2056 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2058 /* Disable HAINTs */
2059 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2062 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2065 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2068 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2071 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2074 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2077 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2080 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2084 /** Handles hub class-specific requests. */
2085 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2088 uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2092 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2093 usb_hub_descriptor_t *hub_desc;
2094 hprt0_data_t hprt0 = {.d32 = 0 };
2096 uint32_t port_status;
2099 case UCR_CLEAR_HUB_FEATURE:
2100 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2101 "ClearHubFeature 0x%x\n", wValue);
2103 case UHF_C_HUB_LOCAL_POWER:
2104 case UHF_C_HUB_OVER_CURRENT:
2105 /* Nothing required here */
2108 retval = -DWC_E_INVALID;
2109 DWC_ERROR("DWC OTG HCD - "
2110 "ClearHubFeature request %xh unknown\n",
2114 case UCR_CLEAR_PORT_FEATURE:
2115 #ifdef CONFIG_USB_DWC_OTG_LPM
2116 if (wValue != UHF_PORT_L1)
2118 if (!wIndex || wIndex > 1)
2122 case UHF_PORT_ENABLE:
2123 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2124 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2125 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2127 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2129 case UHF_PORT_SUSPEND:
2130 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2131 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2133 if (core_if->power_down == 2) {
2134 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2136 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2139 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2141 DWC_WRITE_REG32(core_if->host_if->hprt0,
2143 hprt0.b.prtsusp = 0;
2144 /* Clear Resume bit */
2147 DWC_WRITE_REG32(core_if->host_if->hprt0,
2151 #ifdef CONFIG_USB_DWC_OTG_LPM
2154 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2155 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2158 DWC_READ_REG32(&core_if->core_global_regs->
2160 lpmcfg.b.en_utmi_sleep = 0;
2161 lpmcfg.b.hird_thres &= (~(1 << 4));
2162 lpmcfg.b.prt_sleep_sts = 1;
2163 DWC_WRITE_REG32(&core_if->core_global_regs->
2164 glpmcfg, lpmcfg.d32);
2166 /* Clear Enbl_L1Gating bit. */
2167 pcgcctl.b.enbl_sleep_gating = 1;
2168 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2173 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2175 DWC_WRITE_REG32(core_if->host_if->hprt0,
2177 /* This bit will be cleared in wakeup interrupt handle */
2181 case UHF_PORT_POWER:
2182 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2183 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2184 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2186 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2188 case UHF_PORT_INDICATOR:
2189 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2190 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2191 /* Port inidicator not supported */
2193 case UHF_C_PORT_CONNECTION:
2194 /* Clears drivers internal connect status change
2196 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2197 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2198 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2200 case UHF_C_PORT_RESET:
2201 /* Clears the driver's internal Port Reset Change
2203 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2204 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2205 dwc_otg_hcd->flags.b.port_reset_change = 0;
2207 case UHF_C_PORT_ENABLE:
2208 /* Clears the driver's internal Port
2209 * Enable/Disable Change flag */
2210 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2211 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2212 dwc_otg_hcd->flags.b.port_enable_change = 0;
2214 case UHF_C_PORT_SUSPEND:
2215 /* Clears the driver's internal Port Suspend
2216 * Change flag, which is set when resume signaling on
2217 * the host port is complete */
2218 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2219 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2220 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2222 #ifdef CONFIG_USB_DWC_OTG_LPM
2224 dwc_otg_hcd->flags.b.port_l1_change = 0;
2227 case UHF_C_PORT_OVER_CURRENT:
2228 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2229 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2230 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2233 retval = -DWC_E_INVALID;
2234 DWC_ERROR("DWC OTG HCD - "
2235 "ClearPortFeature request %xh "
2236 "unknown or unsupported\n", wValue);
2239 case UCR_GET_HUB_DESCRIPTOR:
2240 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2241 "GetHubDescriptor\n");
2242 hub_desc = (usb_hub_descriptor_t *) buf;
2243 hub_desc->bDescLength = 9;
2244 hub_desc->bDescriptorType = 0x29;
2245 hub_desc->bNbrPorts = 1;
2246 USETW(hub_desc->wHubCharacteristics, 0x08);
2247 hub_desc->bPwrOn2PwrGood = 1;
2248 hub_desc->bHubContrCurrent = 0;
2249 hub_desc->DeviceRemovable[0] = 0;
2250 hub_desc->DeviceRemovable[1] = 0xff;
2252 case UCR_GET_HUB_STATUS:
2253 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2255 DWC_MEMSET(buf, 0, 4);
2257 case UCR_GET_PORT_STATUS:
2258 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2259 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2260 wIndex, dwc_otg_hcd->flags.d32);
2261 if (!wIndex || wIndex > 1)
2266 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2267 port_status |= (1 << UHF_C_PORT_CONNECTION);
2269 if (dwc_otg_hcd->flags.b.port_enable_change)
2270 port_status |= (1 << UHF_C_PORT_ENABLE);
2272 if (dwc_otg_hcd->flags.b.port_suspend_change)
2273 port_status |= (1 << UHF_C_PORT_SUSPEND);
2275 if (dwc_otg_hcd->flags.b.port_l1_change)
2276 port_status |= (1 << UHF_C_PORT_L1);
2278 if (dwc_otg_hcd->flags.b.port_reset_change) {
2279 port_status |= (1 << UHF_C_PORT_RESET);
2282 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2283 DWC_WARN("Overcurrent change detected\n");
2284 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2287 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2289 * The port is disconnected, which means the core is
2290 * either in device mode or it soon will be. Just
2291 * return 0's for the remainder of the port status
2292 * since the port register can't be read if the core
2293 * is in device mode.
2295 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2299 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2300 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2302 if (hprt0.b.prtconnsts)
2303 port_status |= (1 << UHF_PORT_CONNECTION);
2306 port_status |= (1 << UHF_PORT_ENABLE);
2308 if (hprt0.b.prtsusp)
2309 port_status |= (1 << UHF_PORT_SUSPEND);
2311 if (hprt0.b.prtovrcurract)
2312 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2315 port_status |= (1 << UHF_PORT_RESET);
2318 port_status |= (1 << UHF_PORT_POWER);
2320 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2321 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2322 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2323 port_status |= (1 << UHF_PORT_LOW_SPEED);
2325 if (hprt0.b.prttstctl)
2326 port_status |= (1 << UHF_PORT_TEST);
2327 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2328 port_status |= (1 << UHF_PORT_L1);
2331 For Synopsys HW emulation of Power down wkup_control asserts the
2332 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2333 We intentionally tell the software that port is in L2Suspend state.
2336 if ((core_if->power_down == 2)
2337 && (core_if->hibernation_suspend == 1)) {
2338 port_status |= (1 << UHF_PORT_SUSPEND);
2340 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2342 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2345 case UCR_SET_HUB_FEATURE:
2346 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2348 /* No HUB features supported */
2350 case UCR_SET_PORT_FEATURE:
2351 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2354 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2356 * The port is disconnected, which means the core is
2357 * either in device mode or it soon will be. Just
2358 * return without doing anything since the port
2359 * register can't be written if the core is in device
2366 case UHF_PORT_SUSPEND:
2367 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2368 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2369 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2372 if (core_if->power_down == 2) {
2374 dwc_irqflags_t flags;
2375 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2376 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2377 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2378 #ifdef DWC_DEV_SRPCAP
2379 int32_t otg_cap_param =
2380 core_if->core_params->otg_cap;
2383 ("Preparing for complete power-off\n");
2385 /* Save registers before hibernation */
2386 dwc_otg_save_global_regs(core_if);
2387 dwc_otg_save_host_regs(core_if);
2389 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2390 hprt0.b.prtsusp = 1;
2392 DWC_WRITE_REG32(core_if->host_if->hprt0,
2394 /* Spin hprt0.b.prtsusp to became 1 */
2396 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2397 if (hprt0.b.prtsusp) {
2401 } while (--timeout);
2403 DWC_WARN("Suspend wasn't genereted\n");
2408 * We need to disable interrupts to prevent servicing of any IRQ
2409 * during going to hibernation
2411 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2412 core_if->lx_state = DWC_OTG_L2;
2413 #ifdef DWC_DEV_SRPCAP
2414 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2417 DWC_WRITE_REG32(core_if->host_if->hprt0,
2421 DWC_READ_REG32(&core_if->
2422 core_global_regs->gusbcfg);
2423 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2424 /* ULPI interface */
2425 /* Suspend the Phy Clock */
2427 pcgcctl.b.stoppclk = 1;
2428 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2431 gpwrdn.b.pmuactv = 1;
2433 (&core_if->core_global_regs->gpwrdn,
2436 /* UTMI+ Interface */
2437 gpwrdn.b.pmuactv = 1;
2439 (&core_if->core_global_regs->gpwrdn,
2442 pcgcctl.b.stoppclk = 1;
2443 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2447 #ifdef DWC_DEV_SRPCAP
2449 gpwrdn.b.dis_vbus = 1;
2450 DWC_MODIFY_REG32(&core_if->
2451 core_global_regs->gpwrdn, 0,
2455 gpwrdn.b.pmuintsel = 1;
2456 DWC_MODIFY_REG32(&core_if->
2457 core_global_regs->gpwrdn, 0,
2462 #ifdef DWC_DEV_SRPCAP
2463 gpwrdn.b.srp_det_msk = 1;
2465 gpwrdn.b.disconn_det_msk = 1;
2466 gpwrdn.b.lnstchng_msk = 1;
2467 gpwrdn.b.sts_chngint_msk = 1;
2468 DWC_MODIFY_REG32(&core_if->
2469 core_global_regs->gpwrdn, 0,
2473 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2475 gpwrdn.b.pwrdnclmp = 1;
2476 DWC_MODIFY_REG32(&core_if->
2477 core_global_regs->gpwrdn, 0,
2481 /* Switch off VDD */
2483 gpwrdn.b.pwrdnswtch = 1;
2484 DWC_MODIFY_REG32(&core_if->
2485 core_global_regs->gpwrdn, 0,
2488 #ifdef DWC_DEV_SRPCAP
2489 if (otg_cap_param ==
2490 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2491 core_if->pwron_timer_started = 1;
2492 DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2496 /* Save gpwrdn register for further usage if stschng interrupt */
2497 core_if->gr_backup->gpwrdn_local =
2498 DWC_READ_REG32(&core_if->core_global_regs->
2501 /* Set flag to indicate that we are in hibernation */
2502 core_if->hibernation_suspend = 1;
2503 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2506 DWC_PRINTF("Host hibernation completed\n");
2507 /* Exit from case statement */
2511 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2512 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2513 gotgctl_data_t gotgctl = {.d32 = 0 };
2514 gotgctl.b.hstsethnpen = 1;
2515 DWC_MODIFY_REG32(&core_if->
2516 core_global_regs->gotgctl, 0,
2518 core_if->op_state = A_SUSPEND;
2520 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2521 hprt0.b.prtsusp = 1;
2522 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2524 dwc_irqflags_t flags;
2525 /* Update lx_state */
2526 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2527 core_if->lx_state = DWC_OTG_L2;
2528 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2531 /* Suspend the Phy Clock */
2532 if (core_if->otg_ver == 0) {
2533 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2534 pcgcctl.b.stoppclk = 1;
2535 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2540 /* For HNP the bus must be suspended for at least 200ms. */
2541 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2542 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2543 pcgcctl.b.stoppclk = 1;
2544 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2549 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2551 if (core_if->adp_enable) {
2552 gotgctl_data_t gotgctl = {.d32 = 0 };
2553 gpwrdn_data_t gpwrdn;
2555 while (gotgctl.b.asesvld == 1) {
2558 (&core_if->core_global_regs->gotgctl);
2562 /* Enable Power Down Logic */
2564 gpwrdn.b.pmuactv = 1;
2565 DWC_MODIFY_REG32(&core_if->
2566 core_global_regs->gpwrdn, 0,
2569 /* Unmask SRP detected interrupt from Power Down Logic */
2571 gpwrdn.b.srp_det_msk = 1;
2572 DWC_MODIFY_REG32(&core_if->
2573 core_global_regs->gpwrdn, 0,
2576 dwc_otg_adp_probe_start(core_if);
2580 case UHF_PORT_POWER:
2581 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2582 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2583 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2585 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2587 case UHF_PORT_RESET:
2588 if ((core_if->power_down == 2)
2589 && (core_if->hibernation_suspend == 1)) {
2590 /* If we are going to exit from Hibernated
2591 * state via USB RESET.
2593 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2595 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2597 DWC_DEBUGPL(DBG_HCD,
2598 "DWC OTG HCD HUB CONTROL - "
2599 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2601 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2602 pcgcctl.b.enbl_sleep_gating = 1;
2603 pcgcctl.b.stoppclk = 1;
2604 DWC_MODIFY_REG32(core_if->pcgcctl,
2606 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2608 #ifdef CONFIG_USB_DWC_OTG_LPM
2610 glpmcfg_data_t lpmcfg;
2612 DWC_READ_REG32(&core_if->
2615 if (lpmcfg.b.prt_sleep_sts) {
2616 lpmcfg.b.en_utmi_sleep = 0;
2617 lpmcfg.b.hird_thres &=
2619 DWC_WRITE_REG32(&core_if->
2627 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2628 /* Clear suspend bit if resetting from suspended state. */
2629 hprt0.b.prtsusp = 0;
2630 /* When B-Host the Port reset bit is set in
2631 * the Start HCD Callback function, so that
2632 * the reset is started within 1ms of the HNP
2633 * success interrupt. */
2634 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2638 ("Indeed it is in host mode hprt0 = %08x\n",
2640 DWC_WRITE_REG32(core_if->host_if->hprt0,
2643 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2646 DWC_WRITE_REG32(core_if->host_if->hprt0,
2648 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2651 #ifdef DWC_HS_ELECT_TST
2655 gintmsk_data_t gintmsk;
2657 t = (wIndex >> 8); /* MSB wIndex USB */
2658 DWC_DEBUGPL(DBG_HCD,
2659 "DWC OTG HCD HUB CONTROL - "
2660 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2662 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2664 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2665 hprt0.b.prttstctl = t;
2666 DWC_WRITE_REG32(core_if->host_if->hprt0,
2669 /* Setup global vars with reg addresses (quick and
2670 * dirty hack, should be cleaned up)
2672 global_regs = core_if->core_global_regs;
2674 core_if->host_if->host_global_regs;
2676 (dwc_otg_hc_regs_t *) ((char *)
2680 (uint32_t *) ((char *)global_regs +
2683 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2684 /* Save current interrupt mask */
2687 (&global_regs->gintmsk);
2689 /* Disable all interrupts while we muck with
2690 * the hardware directly
2692 DWC_WRITE_REG32(&global_regs->
2695 /* 15 second delay per the test spec */
2698 /* Drive suspend on the root port */
2700 dwc_otg_read_hprt0(core_if);
2701 hprt0.b.prtsusp = 1;
2703 DWC_WRITE_REG32(core_if->
2707 /* 15 second delay per the test spec */
2710 /* Drive resume on the root port */
2712 dwc_otg_read_hprt0(core_if);
2713 hprt0.b.prtsusp = 0;
2715 DWC_WRITE_REG32(core_if->
2720 /* Clear the resume bit */
2722 DWC_WRITE_REG32(core_if->
2726 /* Restore interrupts */
2727 DWC_WRITE_REG32(&global_regs->
2730 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2731 /* Save current interrupt mask */
2734 (&global_regs->gintmsk);
2736 /* Disable all interrupts while we muck with
2737 * the hardware directly
2739 DWC_WRITE_REG32(&global_regs->
2742 /* 15 second delay per the test spec */
2745 /* Send the Setup packet */
2748 /* 15 second delay so nothing else happens for awhile */
2751 /* Restore interrupts */
2752 DWC_WRITE_REG32(&global_regs->
2755 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2756 /* Save current interrupt mask */
2759 (&global_regs->gintmsk);
2761 /* Disable all interrupts while we muck with
2762 * the hardware directly
2764 DWC_WRITE_REG32(&global_regs->
2767 /* Send the Setup packet */
2770 /* 15 second delay so nothing else happens for awhile */
2773 /* Send the In and Ack packets */
2776 /* 15 second delay so nothing else happens for awhile */
2779 /* Restore interrupts */
2780 DWC_WRITE_REG32(&global_regs->
2787 #endif /* DWC_HS_ELECT_TST */
2789 case UHF_PORT_INDICATOR:
2790 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2791 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2795 retval = -DWC_E_INVALID;
2796 DWC_ERROR("DWC OTG HCD - "
2797 "SetPortFeature request %xh "
2798 "unknown or unsupported\n", wValue);
2802 #ifdef CONFIG_USB_DWC_OTG_LPM
2803 case UCR_SET_AND_TEST_PORT_FEATURE:
2804 if (wValue != UHF_PORT_L1) {
2808 int portnum, hird, devaddr, remwake;
2809 glpmcfg_data_t lpmcfg;
2810 uint32_t time_usecs;
2811 gintsts_data_t gintsts;
2812 gintmsk_data_t gintmsk;
2814 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2817 if (wValue != UHF_PORT_L1 || wLength != 1) {
2820 /* Check if the port currently is in SLEEP state */
2822 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2823 if (lpmcfg.b.prt_sleep_sts) {
2824 DWC_INFO("Port is already in sleep mode\n");
2825 buf[0] = 0; /* Return success */
2829 portnum = wIndex & 0xf;
2830 hird = (wIndex >> 4) & 0xf;
2831 devaddr = (wIndex >> 8) & 0x7f;
2832 remwake = (wIndex >> 15);
2835 retval = -DWC_E_INVALID;
2837 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2843 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2844 portnum, hird, devaddr, remwake);
2845 /* Disable LPM interrupt */
2847 gintmsk.b.lpmtranrcvd = 1;
2848 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2851 if (dwc_otg_hcd_send_lpm
2852 (dwc_otg_hcd, devaddr, hird, remwake)) {
2853 retval = -DWC_E_INVALID;
2857 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2858 /* We will consider timeout if time_usecs microseconds pass,
2859 * and we don't receive LPM transaction status.
2860 * After receiving non-error responce(ACK/NYET/STALL) from device,
2861 * core will set lpmtranrcvd bit.
2865 DWC_READ_REG32(&core_if->core_global_regs->
2867 if (gintsts.b.lpmtranrcvd) {
2871 } while (--time_usecs);
2872 /* lpm_int bit will be cleared in LPM interrupt handler */
2879 if (!gintsts.b.lpmtranrcvd) {
2880 buf[0] = 0x3; /* Completion code is Timeout */
2881 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2884 DWC_READ_REG32(&core_if->core_global_regs->
2886 if (lpmcfg.b.lpm_resp == 0x3) {
2887 /* ACK responce from the device */
2888 buf[0] = 0x00; /* Success */
2889 } else if (lpmcfg.b.lpm_resp == 0x2) {
2890 /* NYET responce from the device */
2893 /* Otherwise responce with Timeout */
2897 DWC_PRINTF("Device responce to LPM trans is %x\n",
2899 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2904 #endif /* CONFIG_USB_DWC_OTG_LPM */
2907 retval = -DWC_E_INVALID;
2908 DWC_WARN("DWC OTG HCD - "
2909 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2910 typeReq, wIndex, wValue);
2917 #ifdef CONFIG_USB_DWC_OTG_LPM
2918 /** Returns index of host channel to perform LPM transaction. */
2919 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2921 dwc_otg_core_if_t *core_if = hcd->core_if;
2923 hcchar_data_t hcchar;
2924 gintmsk_data_t gintmsk = {.d32 = 0 };
2926 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2927 DWC_PRINTF("No free channel to select for LPM transaction\n");
2931 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2933 /* Mask host channel interrupts. */
2934 gintmsk.b.hcintr = 1;
2935 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2937 /* Fill fields that core needs for LPM transaction */
2938 hcchar.b.devaddr = devaddr;
2940 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2942 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2943 hcchar.b.epdir = 0; /* OUT */
2944 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2947 /* Remove the host channel from the free list. */
2948 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2950 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2955 /** Release hc after performing LPM transaction */
2956 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2959 glpmcfg_data_t lpmcfg;
2962 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2963 hc_num = lpmcfg.b.lpm_chan_index;
2965 hc = hcd->hc_ptr_array[hc_num];
2967 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2968 /* Return host channel to free list */
2969 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2972 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2973 uint8_t bRemoteWake)
2975 glpmcfg_data_t lpmcfg;
2976 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2979 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2984 pcgcctl.b.enbl_sleep_gating = 1;
2985 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2987 /* Read LPM config register */
2988 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2990 /* Program LPM transaction fields */
2991 lpmcfg.b.rem_wkup_en = bRemoteWake;
2992 lpmcfg.b.hird = hird;
2994 if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2995 lpmcfg.b.hird_thres = 0x16;
2996 lpmcfg.b.en_besl = 1;
2998 lpmcfg.b.hird_thres = 0x1c;
3001 lpmcfg.b.lpm_chan_index = channel;
3002 lpmcfg.b.en_utmi_sleep = 1;
3003 /* Program LPM config register */
3004 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3006 /* Send LPM transaction */
3007 lpmcfg.b.send_lpm = 1;
3008 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3013 #endif /* CONFIG_USB_DWC_OTG_LPM */
3015 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3020 return -DWC_E_INVALID;
3023 retval = (hcd->flags.b.port_connect_status_change ||
3024 hcd->flags.b.port_reset_change ||
3025 hcd->flags.b.port_enable_change ||
3026 hcd->flags.b.port_suspend_change ||
3027 hcd->flags.b.port_over_current_change);
3030 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3031 " Root port status changed\n");
3032 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
3033 hcd->flags.b.port_connect_status_change);
3034 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
3035 hcd->flags.b.port_reset_change);
3036 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
3037 hcd->flags.b.port_enable_change);
3038 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
3039 hcd->flags.b.port_suspend_change);
3040 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
3041 hcd->flags.b.port_over_current_change);
3047 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3051 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3052 host_global_regs->hfnum);
3055 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3058 return hfnum.b.frnum;
3061 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3062 struct dwc_otg_hcd_function_ops *fops)
3067 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3068 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3069 dwc_otg_hcd_reinit(hcd);
3071 retval = -DWC_E_NO_DEVICE;
3077 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3082 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3084 hcd->priv = priv_data;
3087 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3089 return hcd->otg_port;
3092 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3095 if (hcd->core_if->op_state == B_HOST) {
3104 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3105 int iso_desc_count, int atomic_alloc)
3107 dwc_otg_hcd_urb_t *dwc_otg_urb;
3111 sizeof(*dwc_otg_urb) +
3112 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3114 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3116 dwc_otg_urb = DWC_ALLOC(size);
3118 dwc_otg_urb->packet_count = iso_desc_count;
3123 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3124 uint8_t dev_addr, uint8_t ep_num,
3125 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3127 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3128 ep_type, ep_dir, mps);
3131 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3132 dev_addr, ep_num, ep_dir, ep_type, mps);
3136 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3137 void *urb_handle, void *buf, dwc_dma_t dma,
3138 uint32_t buflen, void *setup_packet,
3139 dwc_dma_t setup_dma, uint32_t flags,
3142 dwc_otg_urb->priv = urb_handle;
3143 dwc_otg_urb->buf = buf;
3144 dwc_otg_urb->dma = dma;
3145 dwc_otg_urb->length = buflen;
3146 dwc_otg_urb->setup_packet = setup_packet;
3147 dwc_otg_urb->setup_dma = setup_dma;
3148 dwc_otg_urb->flags = flags;
3149 dwc_otg_urb->interval = interval;
3150 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3153 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3155 return dwc_otg_urb->status;
3158 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3160 return dwc_otg_urb->actual_length;
3163 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3165 return dwc_otg_urb->error_count;
3168 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3169 int desc_num, uint32_t offset,
3172 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3173 dwc_otg_urb->iso_descs[desc_num].length = length;
3176 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3179 return dwc_otg_urb->iso_descs[desc_num].status;
3182 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3183 dwc_otg_urb, int desc_num)
3185 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3188 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3191 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3194 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3201 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3203 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3205 DWC_ASSERT(qh, "qh is not allocated\n");
3207 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3214 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3216 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3217 DWC_ASSERT(qh, "qh is not allocated\n");
3221 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3226 gnptxsts_data_t np_tx_status;
3227 hptxsts_data_t p_tx_status;
3229 num_channels = hcd->core_if->core_params->host_channels;
3232 ("************************************************************\n");
3233 DWC_PRINTF("HCD State:\n");
3234 DWC_PRINTF(" Num channels: %d\n", num_channels);
3235 for (i = 0; i < num_channels; i++) {
3236 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3237 DWC_PRINTF(" Channel %d:\n", i);
3238 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3239 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3240 DWC_PRINTF(" speed: %d\n", hc->speed);
3241 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3242 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3243 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3244 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3245 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3246 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3247 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3248 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3249 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3250 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3251 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3252 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3253 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3254 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3255 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3256 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3257 DWC_PRINTF(" requests: %d\n", hc->requests);
3258 DWC_PRINTF(" qh: %p\n", hc->qh);
3259 if (hc->xfer_started) {
3261 hcchar_data_t hcchar;
3262 hctsiz_data_t hctsiz;
3264 hcintmsk_data_t hcintmsk;
3266 DWC_READ_REG32(&hcd->core_if->host_if->
3267 host_global_regs->hfnum);
3269 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3272 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3275 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3278 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3280 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3281 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3282 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3283 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3284 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3286 if (hc->xfer_started && hc->qh) {
3288 dwc_otg_hcd_urb_t *urb;
3290 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3292 if (!qtd->in_process)
3296 DWC_PRINTF(" URB Info:\n");
3297 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd,
3300 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3301 dwc_otg_hcd_get_dev_addr
3303 dwc_otg_hcd_get_ep_num
3305 dwc_otg_hcd_is_pipe_in
3306 (&urb->pipe_info) ? "IN" :
3309 (" Max packet size: %d\n",
3313 (" transfer_buffer: %p\n",
3315 DWC_PRINTF(" transfer_dma: %p\n",
3318 (" transfer_buffer_length: %d\n",
3320 DWC_PRINTF(" actual_length: %d\n",
3321 urb->actual_length);
3326 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3327 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3328 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3330 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3331 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3332 np_tx_status.b.nptxqspcavail);
3333 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3334 np_tx_status.b.nptxfspcavail);
3336 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3337 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3338 p_tx_status.b.ptxqspcavail);
3339 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3340 dwc_otg_hcd_dump_frrem(hcd);
3341 dwc_otg_dump_global_registers(hcd->core_if);
3342 dwc_otg_dump_host_registers(hcd->core_if);
3344 ("************************************************************\n");
3350 void dwc_print_setup_data(uint8_t *setup)
3353 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3354 DWC_PRINTF("Setup Data = MSB ");
3355 for (i = 7; i >= 0; i--)
3356 DWC_PRINTF("%02x ", setup[i]);
3358 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3359 (setup[0] & 0x80) ? "Device-to-Host" :
3361 DWC_PRINTF(" bmRequestType Type = ");
3362 switch ((setup[0] & 0x60) >> 5) {
3364 DWC_PRINTF("Standard\n");
3367 DWC_PRINTF("Class\n");
3370 DWC_PRINTF("Vendor\n");
3373 DWC_PRINTF("Reserved\n");
3376 DWC_PRINTF(" bmRequestType Recipient = ");
3377 switch (setup[0] & 0x1f) {
3379 DWC_PRINTF("Device\n");
3382 DWC_PRINTF("Interface\n");
3385 DWC_PRINTF("Endpoint\n");
3388 DWC_PRINTF("Other\n");
3391 DWC_PRINTF("Reserved\n");
3394 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3395 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3396 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3397 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3402 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3405 DWC_PRINTF("Frame remaining at SOF:\n");
3406 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3407 hcd->frrem_samples, hcd->frrem_accum,
3408 (hcd->frrem_samples > 0) ?
3409 hcd->frrem_accum / hcd->frrem_samples : 0);
3412 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3413 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3414 hcd->core_if->hfnum_7_samples,
3415 hcd->core_if->hfnum_7_frrem_accum,
3416 (hcd->core_if->hfnum_7_samples >
3417 0) ? hcd->core_if->hfnum_7_frrem_accum /
3418 hcd->core_if->hfnum_7_samples : 0);
3419 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3420 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3421 hcd->core_if->hfnum_0_samples,
3422 hcd->core_if->hfnum_0_frrem_accum,
3423 (hcd->core_if->hfnum_0_samples >
3424 0) ? hcd->core_if->hfnum_0_frrem_accum /
3425 hcd->core_if->hfnum_0_samples : 0);
3426 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3427 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3428 hcd->core_if->hfnum_other_samples,
3429 hcd->core_if->hfnum_other_frrem_accum,
3430 (hcd->core_if->hfnum_other_samples >
3431 0) ? hcd->core_if->hfnum_other_frrem_accum /
3432 hcd->core_if->hfnum_other_samples : 0);
3435 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3436 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3437 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3438 (hcd->hfnum_7_samples_a > 0) ?
3439 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3440 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3441 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3442 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3443 (hcd->hfnum_0_samples_a > 0) ?
3444 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3445 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3446 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3447 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3448 (hcd->hfnum_other_samples_a > 0) ?
3449 hcd->hfnum_other_frrem_accum_a /
3450 hcd->hfnum_other_samples_a : 0);
3453 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3454 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3455 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3456 (hcd->hfnum_7_samples_b > 0) ?
3457 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3458 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3459 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3460 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3461 (hcd->hfnum_0_samples_b > 0) ?
3462 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3463 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3464 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3465 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3466 (hcd->hfnum_other_samples_b > 0) ?
3467 hcd->hfnum_other_frrem_accum_b /
3468 hcd->hfnum_other_samples_b : 0);
3472 #endif /* DWC_DEVICE_ONLY */