1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
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18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t * hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
178 if (qtd->urb != NULL) {
179 hcd->fops->complete(hcd, qtd->urb->priv,
180 qtd->urb, -DWC_E_TIMEOUT);
181 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
189 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
190 * and periodic schedules. The QTD associated with each URB is removed from
191 * the schedule and freed. This function may be called when a disconnect is
192 * detected or when the HCD is being stopped.
194 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
196 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
197 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
198 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
199 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
200 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
201 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
205 * Start the connection timer. An OTG host is required to display a
206 * message if the device does not connect within 10 seconds. The
207 * timer is deleted if a port connect interrupt occurs before the
210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
212 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
216 * HCD Callback function for disconnect of the HCD.
218 * @param p void pointer to the <code>struct usb_hcd</code>
220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
222 dwc_otg_hcd_t *dwc_otg_hcd;
223 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
225 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
230 * HCD Callback function for starting the HCD when A-Cable is
233 * @param p void pointer to the <code>struct usb_hcd</code>
235 static int32_t dwc_otg_hcd_start_cb(void *p)
237 dwc_otg_hcd_t *dwc_otg_hcd = p;
238 dwc_otg_core_if_t *core_if;
240 uint32_t timeout = 50;
242 core_if = dwc_otg_hcd->core_if;
244 if (core_if->op_state == B_HOST) {
246 * Reset the port. During a HNP mode switch the reset
247 * needs to occur within 1ms and have a duration of at
250 hprt0.d32 = dwc_otg_read_hprt0(core_if);
252 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
253 if (core_if->otg_ver) {
255 hprt0.d32 = dwc_otg_read_hprt0(core_if);
257 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
260 /**@todo vahrama: Check the timeout value for OTG 2.0 */
261 if (core_if->otg_ver)
263 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
264 hcd_start_func, dwc_otg_hcd, timeout,
271 * HCD Callback function for disconnect of the HCD.
273 * @param p void pointer to the <code>struct usb_hcd</code>
275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
278 dwc_otg_hcd_t *dwc_otg_hcd = p;
281 * Set status flags for the hub driver.
283 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
284 dwc_otg_hcd->flags.b.port_connect_status = 0;
287 * Shutdown any transfers in process by clearing the Tx FIFO Empty
288 * interrupt mask and status bits and disabling subsequent host
289 * channel interrupts.
292 intr.b.nptxfempty = 1;
293 intr.b.ptxfempty = 1;
295 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
297 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
301 * Turn off the vbus power only if the core has transitioned to device
302 * mode. If still in host mode, need to keep power on to detect a
305 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
306 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
307 hprt0_data_t hprt0 = {.d32 = 0 };
308 DWC_PRINTF("Disconnect: PortPower off\n");
310 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
313 /** Delete timers if become device */
314 del_timers(dwc_otg_hcd);
315 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
318 /* Respond with an error status to all URBs in the schedule. */
319 kill_all_urbs(dwc_otg_hcd);
321 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
322 /* Clean up any host channels that were in use. */
326 dwc_otg_hc_regs_t *hc_regs;
327 hcchar_data_t hcchar;
329 DWC_PRINTF("Disconnect cb-Host\n");
330 if (dwc_otg_hcd->core_if->otg_ver == 1)
331 del_xfer_timers(dwc_otg_hcd);
333 del_timers(dwc_otg_hcd);
335 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
337 if (!dwc_otg_hcd->core_if->dma_enable) {
338 /* Flush out any channel requests in slave mode. */
339 for (i = 0; i < num_channels; i++) {
340 channel = dwc_otg_hcd->hc_ptr_array[i];
341 if (DWC_CIRCLEQ_EMPTY_ENTRY
342 (channel, hc_list_entry)) {
344 dwc_otg_hcd->core_if->
347 DWC_READ_REG32(&hc_regs->hcchar);
360 for (i = 0; i < num_channels; i++) {
361 channel = dwc_otg_hcd->hc_ptr_array[i];
362 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
364 dwc_otg_hcd->core_if->host_if->hc_regs[i];
365 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
367 /* Halt the channel. */
369 DWC_WRITE_REG32(&hc_regs->hcchar,
373 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
375 DWC_CIRCLEQ_INSERT_TAIL
376 (&dwc_otg_hcd->free_hc_list, channel,
379 * Added for Descriptor DMA to prevent channel double cleanup
380 * in release_channel_ddma(). Which called from ep_disable
381 * when device disconnect.
388 if (dwc_otg_hcd->fops->disconnect) {
389 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
396 * HCD Callback function for stopping the HCD.
398 * @param p void pointer to the <code>struct usb_hcd</code>
400 static int32_t dwc_otg_hcd_stop_cb(void *p)
402 dwc_otg_hcd_t *dwc_otg_hcd = p;
404 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
405 dwc_otg_hcd_stop(dwc_otg_hcd);
409 #ifdef CONFIG_USB_DWC_OTG_LPM
411 * HCD Callback function for sleep of HCD.
413 * @param p void pointer to the <code>struct usb_hcd</code>
415 static int dwc_otg_hcd_sleep_cb(void *p)
417 dwc_otg_hcd_t *hcd = p;
419 dwc_otg_hcd_free_hc_from_lpm(hcd);
426 * HCD Callback function for Remote Wakeup.
428 * @param p void pointer to the <code>struct usb_hcd</code>
430 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd);
431 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
433 dwc_otg_hcd_t *dwc_otg_hcd = p;
434 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
436 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
437 dwc_otg_hcd->flags.b.port_suspend_change = 1;
438 usb_hcd_resume_root_hub(hcd);
440 #ifdef CONFIG_USB_DWC_OTG_LPM
442 dwc_otg_hcd->flags.b.port_l1_change = 1;
449 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
452 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
454 hprt0_data_t hprt0 = {.d32 = 0 };
455 struct dwc_otg_platform_data *pldata;
456 pldata = hcd->core_if->otg_dev->pldata;
458 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
461 * The root hub should be disconnected before this function is called.
462 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
463 * and the QH lists (via ..._hcd_endpoint_disable).
466 /* Turn off all host-specific interrupts. */
467 dwc_otg_disable_host_interrupts(hcd->core_if);
469 /* Turn off the vbus power */
470 DWC_PRINTF("PortPower off\n");
472 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
474 if(pldata->power_enable)
475 pldata->power_enable(0);
481 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
482 dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
485 dwc_irqflags_t flags;
488 gintmsk_data_t intr_mask = {.d32 = 0 };
490 if (!hcd->flags.b.port_connect_status) {
491 /* No longer connected. */
492 DWC_ERROR("Not connected\n");
493 return -DWC_E_NO_DEVICE;
496 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
498 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
499 return -DWC_E_NO_MEMORY;
503 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
505 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
507 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
508 "Error status %d\n", retval);
509 dwc_otg_hcd_qtd_free(qtd);
511 intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
512 if (!intr_mask.b.sofintr && retval == 0) {
513 dwc_otg_transaction_type_e tr_type;
514 if ((qtd->qh->ep_type == UE_BULK)
515 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
516 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
520 tr_type = dwc_otg_hcd_select_transactions(hcd);
521 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
522 dwc_otg_hcd_queue_transactions(hcd, tr_type);
526 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
530 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
531 dwc_otg_hcd_urb_t * dwc_otg_urb)
534 dwc_otg_qtd_t *urb_qtd;
536 urb_qtd = dwc_otg_urb->qtd;
537 if(((uint32_t)urb_qtd&0xf0000000) == 0){
538 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
539 __func__, urb_qtd, dwc_otg_urb);
544 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
545 if (urb_qtd->in_process) {
546 dump_channel_info(hcd, qh);
550 if (urb_qtd->in_process && qh->channel) {
551 /* The QTD is in process (it has been assigned to a channel). */
552 if (hcd->flags.b.port_connect_status) {
554 * If still connected (i.e. in host mode), halt the
555 * channel so it can be used for other transfers. If
556 * no longer connected, the host registers can't be
557 * written to halt the channel since the core is in
560 dwc_otg_hc_halt(hcd->core_if, qh->channel,
561 DWC_OTG_HC_XFER_URB_DEQUEUE);
566 * Free the QTD and clean up the associated QH. Leave the QH in the
567 * schedule if it has any remaining QTDs.
570 if (!hcd->core_if->dma_desc_enable) {
571 uint8_t b = urb_qtd->in_process;
572 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
574 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
576 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
577 dwc_otg_hcd_qh_remove(hcd, qh);
580 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
585 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
588 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
590 dwc_irqflags_t flags;
593 retval = -DWC_E_INVALID;
598 retval = -DWC_E_INVALID;
602 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
604 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
605 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
608 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
611 dwc_otg_hcd_qh_remove(hcd, qh);
613 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
615 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
616 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
617 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
618 * and dwc_otg_hcd_frame_list_alloc().
620 dwc_otg_hcd_qh_free(hcd, qh);
626 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
627 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
630 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
632 return -DWC_E_INVALID;
634 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
640 * HCD Callback structure for handling mode switching.
642 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
643 .start = dwc_otg_hcd_start_cb,
644 .stop = dwc_otg_hcd_stop_cb,
645 .disconnect = dwc_otg_hcd_disconnect_cb,
646 .session_start = dwc_otg_hcd_session_start_cb,
647 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
648 #ifdef CONFIG_USB_DWC_OTG_LPM
649 .sleep = dwc_otg_hcd_sleep_cb,
655 * Reset tasklet function
657 static void reset_tasklet_func(void *data)
659 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
660 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
663 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
665 hprt0.d32 = dwc_otg_read_hprt0(core_if);
667 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
671 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
672 dwc_otg_hcd->flags.b.port_reset_change = 1;
675 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
677 dwc_list_link_t *item;
679 dwc_irqflags_t flags;
681 if (!qh_list->next) {
682 /* The list hasn't been initialized yet. */
686 * Hold spinlock here. Not needed in that case if bellow
687 * function is being called from ISR
689 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
690 /* Ensure there are no QTDs or URBs left. */
691 kill_urbs_in_qh_list(hcd, qh_list);
692 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
694 DWC_LIST_FOREACH(item, qh_list) {
695 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
696 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
701 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
702 * Device during SRP time by host power up.
704 void dwc_otg_hcd_power_up(void *ptr)
706 gpwrdn_data_t gpwrdn = {.d32 = 0 };
707 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
709 DWC_PRINTF("%s called\n", __FUNCTION__);
711 if (!core_if->hibernation_suspend) {
712 DWC_PRINTF("Already exited from Hibernation\n");
716 /* Switch on the voltage to the core */
717 gpwrdn.b.pwrdnswtch = 1;
718 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
723 gpwrdn.b.pwrdnrstn = 1;
724 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
727 /* Disable power clamps */
729 gpwrdn.b.pwrdnclmp = 1;
730 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
732 /* Remove reset the core signal */
734 gpwrdn.b.pwrdnrstn = 1;
735 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
738 /* Disable PMU interrupt */
740 gpwrdn.b.pmuintsel = 1;
741 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
743 core_if->hibernation_suspend = 0;
747 gpwrdn.b.pmuactv = 1;
748 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
753 gpwrdn.b.dis_vbus = 1;
754 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
756 core_if->op_state = A_HOST;
757 dwc_otg_core_init(core_if);
758 dwc_otg_enable_global_interrupts(core_if);
759 cil_hcd_start(core_if);
763 * Frees secondary storage associated with the dwc_otg_hcd structure contained
764 * in the struct usb_hcd field.
766 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
770 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
772 del_timers(dwc_otg_hcd);
774 /* Free memory for QH/QTD lists */
775 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
776 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
777 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
778 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
779 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
780 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
782 /* Free memory for the host channels. */
783 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
784 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
787 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
788 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
792 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
798 if (dwc_otg_hcd->core_if->dma_enable) {
799 if (dwc_otg_hcd->status_buf_dma) {
800 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
801 dwc_otg_hcd->status_buf,
802 dwc_otg_hcd->status_buf_dma);
804 } else if (dwc_otg_hcd->status_buf != NULL) {
805 DWC_FREE(dwc_otg_hcd->status_buf);
807 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
808 /* Set core_if's lock pointer to NULL */
809 dwc_otg_hcd->core_if->lock = NULL;
811 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
812 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
814 #ifdef DWC_DEV_SRPCAP
815 if (dwc_otg_hcd->core_if->power_down == 2 &&
816 dwc_otg_hcd->core_if->pwron_timer) {
817 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
820 DWC_FREE(dwc_otg_hcd);
823 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
830 hcd->lock = DWC_SPINLOCK_ALLOC();
832 DWC_ERROR("Could not allocate lock for pcd");
834 retval = -DWC_E_NO_MEMORY;
837 hcd->core_if = core_if;
839 /* Register the HCD CIL Callbacks */
840 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
841 &hcd_cil_callbacks, hcd);
843 /* Initialize the non-periodic schedule. */
844 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
845 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
847 /* Initialize the periodic schedule. */
848 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
849 DWC_LIST_INIT(&hcd->periodic_sched_ready);
850 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
851 DWC_LIST_INIT(&hcd->periodic_sched_queued);
854 * Create a host channel descriptor for each host channel implemented
855 * in the controller. Initialize the channel descriptor array.
857 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
858 num_channels = hcd->core_if->core_params->host_channels;
859 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
860 for (i = 0; i < num_channels; i++) {
861 channel = DWC_ALLOC(sizeof(dwc_hc_t));
862 if (channel == NULL) {
863 retval = -DWC_E_NO_MEMORY;
864 DWC_ERROR("%s: host channel allocation failed\n",
866 dwc_otg_hcd_free(hcd);
870 hcd->hc_ptr_array[i] = channel;
872 hcd->core_if->hc_xfer_timer[i] =
873 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
874 &hcd->core_if->hc_xfer_info[i]);
876 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
880 /* Initialize the Connection timeout timer. */
881 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
882 dwc_otg_hcd_connect_timeout, hcd);
884 /* Initialize reset tasklet. */
885 hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
886 #ifdef DWC_DEV_SRPCAP
887 if (hcd->core_if->power_down == 2) {
888 /* Initialize Power on timer for Host power up in case hibernation */
889 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
890 dwc_otg_hcd_power_up, core_if);
895 * Allocate space for storing data on status transactions. Normally no
896 * data is sent, but this space acts as a bit bucket. This must be
897 * done after usb_add_hcd since that function allocates the DMA buffer
900 if (hcd->core_if->dma_enable) {
902 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
903 &hcd->status_buf_dma);
905 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
907 if (!hcd->status_buf) {
908 retval = -DWC_E_NO_MEMORY;
909 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
910 dwc_otg_hcd_free(hcd);
915 hcd->frame_list = NULL;
916 hcd->frame_list_dma = 0;
917 hcd->periodic_qh_count = 0;
922 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
924 /* Turn off all host-specific interrupts. */
925 dwc_otg_disable_host_interrupts(hcd->core_if);
927 dwc_otg_hcd_free(hcd);
931 * Initializes dynamic portions of the DWC_otg HCD state.
933 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
938 dwc_hc_t *channel_tmp;
942 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
943 hcd->non_periodic_channels = 0;
944 hcd->periodic_channels = 0;
947 * Put all channels in the free channel list and clean up channel
950 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
951 &hcd->free_hc_list, hc_list_entry) {
952 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
955 num_channels = hcd->core_if->core_params->host_channels;
956 for (i = 0; i < num_channels; i++) {
957 channel = hcd->hc_ptr_array[i];
958 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
960 dwc_otg_hc_cleanup(hcd->core_if, channel);
963 /* Initialize the DWC core for host mode operation. */
964 dwc_otg_core_host_init(hcd->core_if);
966 /* Set core_if's lock pointer to the hcd->lock */
967 hcd->core_if->lock = hcd->lock;
971 * Assigns transactions from a QTD to a free host channel and initializes the
972 * host channel to perform the transactions. The host channel is removed from
975 * @param hcd The HCD state structure.
976 * @param qh Transactions from the first QTD for this QH are selected and
977 * assigned to a free host channel.
979 static int assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
983 dwc_otg_hcd_urb_t *urb;
987 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
989 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
991 /* Remove the host channel from the free list. */
992 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
994 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
998 printk("%s : urb is NULL\n", __func__);
1005 qtd->in_process = 1;
1008 * Use usb_pipedevice to determine device address. This address is
1009 * 0 before the SET_ADDRESS command and the correct address afterward.
1011 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1012 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1013 hc->speed = qh->dev_speed;
1014 hc->max_packet = dwc_max_packet(qh->maxp);
1016 hc->xfer_started = 0;
1017 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1018 hc->error_state = (qtd->error_count > 0);
1019 hc->halt_on_queue = 0;
1020 hc->halt_pending = 0;
1024 * The following values may be modified in the transfer type section
1025 * below. The xfer_len value may be reduced when the transfer is
1026 * started to accommodate the max widths of the XferSize and PktCnt
1027 * fields in the HCTSIZn register.
1030 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1034 hc->do_ping = qh->ping_state;
1037 hc->data_pid_start = qh->data_toggle;
1038 hc->multi_count = 1;
1040 if (hcd->core_if->dma_enable) {
1041 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1043 /* For non-dword aligned case */
1044 if (((unsigned long)hc->xfer_buff & 0x3)
1045 && !hcd->core_if->dma_desc_enable) {
1046 ptr = (uint8_t *) urb->buf + urb->actual_length;
1049 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1051 hc->xfer_len = urb->length - urb->actual_length;
1055 * Set the split attributes
1059 uint32_t hub_addr, port_addr;
1061 hc->xact_pos = qtd->isoc_split_pos;
1062 hc->complete_split = qtd->complete_split;
1063 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1064 hc->hub_addr = (uint8_t) hub_addr;
1065 hc->port_addr = (uint8_t) port_addr;
1068 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1070 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1071 switch (qtd->control_phase) {
1072 case DWC_OTG_CONTROL_SETUP:
1073 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1076 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1077 if (hcd->core_if->dma_enable) {
1078 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1080 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1085 case DWC_OTG_CONTROL_DATA:
1086 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1087 hc->data_pid_start = qtd->data_toggle;
1089 case DWC_OTG_CONTROL_STATUS:
1091 * Direction is opposite of data direction or IN if no
1094 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1095 if (urb->length == 0) {
1099 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1105 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1108 if (hcd->core_if->dma_enable) {
1109 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1111 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1118 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1121 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1123 case UE_ISOCHRONOUS:
1125 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1127 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1129 if (hcd->core_if->dma_desc_enable)
1132 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1134 frame_desc->status = 0;
1136 if (hcd->core_if->dma_enable) {
1137 hc->xfer_buff = (uint8_t *) urb->dma;
1139 hc->xfer_buff = (uint8_t *) urb->buf;
1142 frame_desc->offset + qtd->isoc_split_offset;
1144 frame_desc->length - qtd->isoc_split_offset;
1146 /* For non-dword aligned buffers */
1147 if (((unsigned long)hc->xfer_buff & 0x3)
1148 && hcd->core_if->dma_enable) {
1150 (uint8_t *) urb->buf + frame_desc->offset +
1151 qtd->isoc_split_offset;
1155 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1156 if (hc->xfer_len <= 188) {
1157 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1160 DWC_HCSPLIT_XACTPOS_BEGIN;
1166 /* non DWORD-aligned buffer case */
1169 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1170 buf_size = hcd->core_if->core_params->max_transfer_size;
1174 if (!qh->dw_align_buf) {
1175 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1176 &qh->dw_align_buf_dma);
1177 if (!qh->dw_align_buf) {
1179 ("%s: Failed to allocate memory to handle "
1180 "non-dword aligned buffer case\n",
1185 if (!hc->ep_is_in) {
1186 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1188 hc->align_buff = qh->dw_align_buf_dma;
1193 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1194 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1196 * This value may be modified when the transfer is started to
1197 * reflect the actual transfer length.
1199 hc->multi_count = dwc_hb_mult(qh->maxp);
1202 if (hcd->core_if->dma_desc_enable)
1203 hc->desc_list_addr = qh->desc_list_dma;
1205 dwc_otg_hc_init(hcd->core_if, hc);
1211 * This function selects transactions from the HCD transfer schedule and
1212 * assigns them to available host channels. It is called from HCD interrupt
1213 * handler functions.
1215 * @param hcd The HCD state structure.
1217 * @return The types of new transactions that were assigned to host channels.
1219 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
1221 dwc_list_link_t *qh_ptr;
1224 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1228 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1231 /* Process entries in the periodic ready list. */
1232 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1234 while (qh_ptr != &hcd->periodic_sched_ready &&
1235 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1237 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1238 assign_and_init_hc(hcd, qh);
1241 * Move the QH from the periodic ready schedule to the
1242 * periodic assigned schedule.
1244 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1245 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1246 &qh->qh_list_entry);
1248 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1252 * Process entries in the inactive portion of the non-periodic
1253 * schedule. Some free host channels may not be used if they are
1254 * reserved for periodic transfers.
1256 qh_ptr = hcd->non_periodic_sched_inactive.next;
1257 num_channels = hcd->core_if->core_params->host_channels;
1258 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1259 (hcd->non_periodic_channels <
1260 num_channels - hcd->periodic_channels) &&
1261 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1263 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1265 err = assign_and_init_hc(hcd, qh);
1268 * Move the QH from the non-periodic inactive schedule to the
1269 * non-periodic active schedule.
1271 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1274 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1275 &qh->qh_list_entry);
1277 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1278 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1280 ret_val = DWC_OTG_TRANSACTION_ALL;
1283 hcd->non_periodic_channels++;
1290 * Attempts to queue a single transaction request for a host channel
1291 * associated with either a periodic or non-periodic transfer. This function
1292 * assumes that there is space available in the appropriate request queue. For
1293 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1294 * is available in the appropriate Tx FIFO.
1296 * @param hcd The HCD state structure.
1297 * @param hc Host channel descriptor associated with either a periodic or
1298 * non-periodic transfer.
1299 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1300 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1303 * @return 1 if a request is queued and more requests may be needed to
1304 * complete the transfer, 0 if no more requests are required for this
1305 * transfer, -1 if there is insufficient space in the Tx FIFO.
1307 static int queue_transaction(dwc_otg_hcd_t * hcd,
1308 dwc_hc_t * hc, uint16_t fifo_dwords_avail)
1312 if (hcd->core_if->dma_enable) {
1313 if (hcd->core_if->dma_desc_enable) {
1314 if (!hc->xfer_started
1315 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1316 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1317 hc->qh->ping_state = 0;
1319 } else if (!hc->xfer_started) {
1320 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1321 hc->qh->ping_state = 0;
1324 } else if (hc->halt_pending) {
1325 /* Don't queue a request if the channel has been halted. */
1327 } else if (hc->halt_on_queue) {
1328 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1330 } else if (hc->do_ping) {
1331 if (!hc->xfer_started) {
1332 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1335 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1336 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1337 if (!hc->xfer_started) {
1338 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1342 dwc_otg_hc_continue_transfer(hcd->core_if,
1349 if (!hc->xfer_started) {
1350 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1353 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1361 * Processes periodic channels for the next frame and queues transactions for
1362 * these channels to the DWC_otg controller. After queueing transactions, the
1363 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1364 * to queue as Periodic Tx FIFO or request queue space becomes available.
1365 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1367 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
1369 hptxsts_data_t tx_status;
1370 dwc_list_link_t *qh_ptr;
1373 int no_queue_space = 0;
1374 int no_fifo_space = 0;
1376 dwc_otg_host_global_regs_t *host_regs;
1377 host_regs = hcd->core_if->host_if->host_global_regs;
1379 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1381 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1382 DWC_DEBUGPL(DBG_HCDV,
1383 " P Tx Req Queue Space Avail (before queue): %d\n",
1384 tx_status.b.ptxqspcavail);
1385 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1386 tx_status.b.ptxfspcavail);
1389 qh_ptr = hcd->periodic_sched_assigned.next;
1390 while (qh_ptr != &hcd->periodic_sched_assigned) {
1391 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1392 if (tx_status.b.ptxqspcavail == 0) {
1397 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1400 * Set a flag if we're queuing high-bandwidth in slave mode.
1401 * The flag prevents any halts to get into the request queue in
1402 * the middle of multiple high-bandwidth packets getting queued.
1404 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1405 hcd->core_if->queuing_high_bandwidth = 1;
1408 queue_transaction(hcd, qh->channel,
1409 tx_status.b.ptxfspcavail);
1416 * In Slave mode, stay on the current transfer until there is
1417 * nothing more to do or the high-bandwidth request count is
1418 * reached. In DMA mode, only need to queue one request. The
1419 * controller automatically handles multiple packets for
1420 * high-bandwidth transfers.
1422 if (hcd->core_if->dma_enable || status == 0 ||
1423 qh->channel->requests == qh->channel->multi_count) {
1424 qh_ptr = qh_ptr->next;
1426 * Move the QH from the periodic assigned schedule to
1427 * the periodic queued schedule.
1429 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1430 &qh->qh_list_entry);
1432 /* done queuing high bandwidth */
1433 hcd->core_if->queuing_high_bandwidth = 0;
1437 if (!hcd->core_if->dma_enable) {
1438 dwc_otg_core_global_regs_t *global_regs;
1439 gintmsk_data_t intr_mask = {.d32 = 0 };
1441 global_regs = hcd->core_if->core_global_regs;
1442 intr_mask.b.ptxfempty = 1;
1444 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1445 DWC_DEBUGPL(DBG_HCDV,
1446 " P Tx Req Queue Space Avail (after queue): %d\n",
1447 tx_status.b.ptxqspcavail);
1448 DWC_DEBUGPL(DBG_HCDV,
1449 " P Tx FIFO Space Avail (after queue): %d\n",
1450 tx_status.b.ptxfspcavail);
1452 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1453 no_queue_space || no_fifo_space) {
1455 * May need to queue more transactions as the request
1456 * queue or Tx FIFO empties. Enable the periodic Tx
1457 * FIFO empty interrupt. (Always use the half-empty
1458 * level to ensure that new requests are loaded as
1459 * soon as possible.)
1461 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1465 * Disable the Tx FIFO empty interrupt since there are
1466 * no more transactions that need to be queued right
1467 * now. This function is called from interrupt
1468 * handlers to queue more transactions as transfer
1471 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1478 * Processes active non-periodic channels and queues transactions for these
1479 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1480 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1481 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1482 * FIFO Empty interrupt is disabled.
1484 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
1486 gnptxsts_data_t tx_status;
1487 dwc_list_link_t *orig_qh_ptr;
1490 int no_queue_space = 0;
1491 int no_fifo_space = 0;
1494 dwc_otg_core_global_regs_t *global_regs =
1495 hcd->core_if->core_global_regs;
1497 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1499 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1500 DWC_DEBUGPL(DBG_HCDV,
1501 " NP Tx Req Queue Space Avail (before queue): %d\n",
1502 tx_status.b.nptxqspcavail);
1503 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1504 tx_status.b.nptxfspcavail);
1507 * Keep track of the starting point. Skip over the start-of-list
1510 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1511 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1513 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1516 * Process once through the active list or until no more space is
1517 * available in the request queue or the Tx FIFO.
1520 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1521 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1526 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1529 queue_transaction(hcd, qh->channel,
1530 tx_status.b.nptxfspcavail);
1534 } else if (status < 0) {
1539 /* Advance to next QH, skipping start-of-list entry. */
1540 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1541 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1542 hcd->non_periodic_qh_ptr =
1543 hcd->non_periodic_qh_ptr->next;
1546 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1548 if (!hcd->core_if->dma_enable) {
1549 gintmsk_data_t intr_mask = {.d32 = 0 };
1550 intr_mask.b.nptxfempty = 1;
1553 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1554 DWC_DEBUGPL(DBG_HCDV,
1555 " NP Tx Req Queue Space Avail (after queue): %d\n",
1556 tx_status.b.nptxqspcavail);
1557 DWC_DEBUGPL(DBG_HCDV,
1558 " NP Tx FIFO Space Avail (after queue): %d\n",
1559 tx_status.b.nptxfspcavail);
1561 if (more_to_do || no_queue_space || no_fifo_space) {
1563 * May need to queue more transactions as the request
1564 * queue or Tx FIFO empties. Enable the non-periodic
1565 * Tx FIFO empty interrupt. (Always use the half-empty
1566 * level to ensure that new requests are loaded as
1567 * soon as possible.)
1569 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1573 * Disable the Tx FIFO empty interrupt since there are
1574 * no more transactions that need to be queued right
1575 * now. This function is called from interrupt
1576 * handlers to queue more transactions as transfer
1579 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1586 * This function processes the currently active host channels and queues
1587 * transactions for these channels to the DWC_otg controller. It is called
1588 * from HCD interrupt handler functions.
1590 * @param hcd The HCD state structure.
1591 * @param tr_type The type(s) of transactions to queue (non-periodic,
1592 * periodic, or both).
1594 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
1595 dwc_otg_transaction_type_e tr_type)
1598 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1600 /* Process host channels associated with periodic transfers. */
1601 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1602 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1603 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1605 process_periodic_channels(hcd);
1608 /* Process host channels associated with non-periodic transfers. */
1609 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1610 tr_type == DWC_OTG_TRANSACTION_ALL) {
1611 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1612 process_non_periodic_channels(hcd);
1615 * Ensure NP Tx FIFO empty interrupt is disabled when
1616 * there are no non-periodic transfers to process.
1618 gintmsk_data_t gintmsk = {.d32 = 0 };
1619 gintmsk.b.nptxfempty = 1;
1620 DWC_MODIFY_REG32(&hcd->core_if->
1621 core_global_regs->gintmsk, gintmsk.d32,
1627 #ifdef DWC_HS_ELECT_TST
1629 * Quick and dirty hack to implement the HS Electrical Test
1630 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1632 * This code was copied from our userspace app "hset". It sends a
1633 * Get Device Descriptor control sequence in two parts, first the
1634 * Setup packet by itself, followed some time later by the In and
1635 * Ack packets. Rather than trying to figure out how to add this
1636 * functionality to the normal driver code, we just hijack the
1637 * hardware, using these two function to drive the hardware
1641 static dwc_otg_core_global_regs_t *global_regs;
1642 static dwc_otg_host_global_regs_t *hc_global_regs;
1643 static dwc_otg_hc_regs_t *hc_regs;
1644 static uint32_t *data_fifo;
1646 static void do_setup(void)
1648 gintsts_data_t gintsts;
1649 hctsiz_data_t hctsiz;
1650 hcchar_data_t hcchar;
1655 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1658 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1661 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1664 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1667 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1670 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1673 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1676 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1679 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1682 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1685 * Send Setup packet (Get Device Descriptor)
1688 /* Make sure channel is disabled */
1689 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1690 if (hcchar.b.chen) {
1692 // hcchar.b.chen = 1;
1693 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1698 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1701 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1704 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1707 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1710 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1713 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1716 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1718 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1723 hctsiz.b.xfersize = 8;
1724 hctsiz.b.pktcnt = 1;
1725 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1726 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1729 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1730 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1735 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1737 /* Fill FIFO with Setup data for Get Device Descriptor */
1738 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1739 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1740 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1742 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1744 /* Wait for host channel interrupt */
1746 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1747 } while (gintsts.b.hcintr == 0);
1749 /* Disable HCINTs */
1750 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1752 /* Disable HAINTs */
1753 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1756 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1759 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1762 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1765 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1768 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1771 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1774 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1777 static void do_in_ack(void)
1779 gintsts_data_t gintsts;
1780 hctsiz_data_t hctsiz;
1781 hcchar_data_t hcchar;
1784 host_grxsts_data_t grxsts;
1787 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1790 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1793 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1796 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1799 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1802 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1805 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1808 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1811 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1814 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1817 * Receive Control In packet
1820 /* Make sure channel is disabled */
1821 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1822 if (hcchar.b.chen) {
1825 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1830 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1833 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1836 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1839 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1842 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1845 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1848 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1850 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1855 hctsiz.b.xfersize = 8;
1856 hctsiz.b.pktcnt = 1;
1857 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1858 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1861 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1862 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1867 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1869 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1871 /* Wait for receive status queue interrupt */
1873 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1874 } while (gintsts.b.rxstsqlvl == 0);
1877 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1879 /* Clear RXSTSQLVL in GINTSTS */
1881 gintsts.b.rxstsqlvl = 1;
1882 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1884 switch (grxsts.b.pktsts) {
1885 case DWC_GRXSTS_PKTSTS_IN:
1886 /* Read the data into the host buffer */
1887 if (grxsts.b.bcnt > 0) {
1889 int word_count = (grxsts.b.bcnt + 3) / 4;
1891 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1893 for (i = 0; i < word_count; i++) {
1894 (void)DWC_READ_REG32(data_fifo++);
1903 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1905 /* Wait for receive status queue interrupt */
1907 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1908 } while (gintsts.b.rxstsqlvl == 0);
1911 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1913 /* Clear RXSTSQLVL in GINTSTS */
1915 gintsts.b.rxstsqlvl = 1;
1916 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1918 switch (grxsts.b.pktsts) {
1919 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1926 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1928 /* Wait for host channel interrupt */
1930 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1931 } while (gintsts.b.hcintr == 0);
1934 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1937 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1940 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1943 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1946 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1949 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1952 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1959 * Send handshake packet
1963 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1966 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1969 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1972 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1975 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1978 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1981 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1983 /* Make sure channel is disabled */
1984 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1985 if (hcchar.b.chen) {
1988 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1993 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1996 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1999 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2002 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2005 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2008 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2011 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2013 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2018 hctsiz.b.xfersize = 0;
2019 hctsiz.b.pktcnt = 1;
2020 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2021 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2024 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2025 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2030 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2032 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2034 /* Wait for host channel interrupt */
2036 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2037 } while (gintsts.b.hcintr == 0);
2039 /* Disable HCINTs */
2040 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2042 /* Disable HAINTs */
2043 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2046 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2049 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2052 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2055 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2058 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2061 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2064 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2068 /** Handles hub class-specific requests. */
2069 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
2072 uint16_t wIndex, uint8_t * buf, uint16_t wLength)
2076 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2077 usb_hub_descriptor_t *hub_desc;
2078 hprt0_data_t hprt0 = {.d32 = 0 };
2080 uint32_t port_status;
2083 case UCR_CLEAR_HUB_FEATURE:
2084 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2085 "ClearHubFeature 0x%x\n", wValue);
2087 case UHF_C_HUB_LOCAL_POWER:
2088 case UHF_C_HUB_OVER_CURRENT:
2089 /* Nothing required here */
2092 retval = -DWC_E_INVALID;
2093 DWC_ERROR("DWC OTG HCD - "
2094 "ClearHubFeature request %xh unknown\n",
2098 case UCR_CLEAR_PORT_FEATURE:
2099 #ifdef CONFIG_USB_DWC_OTG_LPM
2100 if (wValue != UHF_PORT_L1)
2102 if (!wIndex || wIndex > 1)
2106 case UHF_PORT_ENABLE:
2107 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2108 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2109 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2111 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2113 case UHF_PORT_SUSPEND:
2114 #if 0//def CONFIG_PM_RUNTIME
2117 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2118 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2120 if (core_if->power_down == 2) {
2121 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2123 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2126 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2128 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2129 hprt0.b.prtsusp = 0;
2130 /* Clear Resume bit */
2133 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2136 #ifdef CONFIG_USB_DWC_OTG_LPM
2139 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2140 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2143 DWC_READ_REG32(&core_if->
2144 core_global_regs->glpmcfg);
2145 lpmcfg.b.en_utmi_sleep = 0;
2146 lpmcfg.b.hird_thres &= (~(1 << 4));
2147 lpmcfg.b.prt_sleep_sts = 1;
2148 DWC_WRITE_REG32(&core_if->
2149 core_global_regs->glpmcfg,
2152 /* Clear Enbl_L1Gating bit. */
2153 pcgcctl.b.enbl_sleep_gating = 1;
2154 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2159 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2161 DWC_WRITE_REG32(core_if->host_if->hprt0,
2163 /* This bit will be cleared in wakeup interrupt handle */
2167 case UHF_PORT_POWER:
2168 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2169 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2170 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2172 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2174 case UHF_PORT_INDICATOR:
2175 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2176 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2177 /* Port inidicator not supported */
2179 case UHF_C_PORT_CONNECTION:
2180 /* Clears drivers internal connect status change
2182 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2183 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2184 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2186 case UHF_C_PORT_RESET:
2187 /* Clears the driver's internal Port Reset Change
2189 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2190 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2191 dwc_otg_hcd->flags.b.port_reset_change = 0;
2193 case UHF_C_PORT_ENABLE:
2194 /* Clears the driver's internal Port
2195 * Enable/Disable Change flag */
2196 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2197 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2198 dwc_otg_hcd->flags.b.port_enable_change = 0;
2200 case UHF_C_PORT_SUSPEND:
2201 /* Clears the driver's internal Port Suspend
2202 * Change flag, which is set when resume signaling on
2203 * the host port is complete */
2204 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2205 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2206 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2208 #ifdef CONFIG_USB_DWC_OTG_LPM
2210 dwc_otg_hcd->flags.b.port_l1_change = 0;
2213 case UHF_C_PORT_OVER_CURRENT:
2214 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2215 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2216 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2219 retval = -DWC_E_INVALID;
2220 DWC_ERROR("DWC OTG HCD - "
2221 "ClearPortFeature request %xh "
2222 "unknown or unsupported\n", wValue);
2225 case UCR_GET_HUB_DESCRIPTOR:
2226 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2227 "GetHubDescriptor\n");
2228 hub_desc = (usb_hub_descriptor_t *) buf;
2229 hub_desc->bDescLength = 9;
2230 hub_desc->bDescriptorType = 0x29;
2231 hub_desc->bNbrPorts = 1;
2232 USETW(hub_desc->wHubCharacteristics, 0x08);
2233 hub_desc->bPwrOn2PwrGood = 1;
2234 hub_desc->bHubContrCurrent = 0;
2235 hub_desc->DeviceRemovable[0] = 0;
2236 hub_desc->DeviceRemovable[1] = 0xff;
2238 case UCR_GET_HUB_STATUS:
2239 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2241 DWC_MEMSET(buf, 0, 4);
2243 case UCR_GET_PORT_STATUS:
2244 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2245 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2246 wIndex, dwc_otg_hcd->flags.d32);
2247 if (!wIndex || wIndex > 1)
2252 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2253 port_status |= (1 << UHF_C_PORT_CONNECTION);
2255 if (dwc_otg_hcd->flags.b.port_enable_change)
2256 port_status |= (1 << UHF_C_PORT_ENABLE);
2258 if (dwc_otg_hcd->flags.b.port_suspend_change)
2259 port_status |= (1 << UHF_C_PORT_SUSPEND);
2261 if (dwc_otg_hcd->flags.b.port_l1_change)
2262 port_status |= (1 << UHF_C_PORT_L1);
2264 if (dwc_otg_hcd->flags.b.port_reset_change) {
2265 port_status |= (1 << UHF_C_PORT_RESET);
2268 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2269 DWC_WARN("Overcurrent change detected\n");
2270 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2273 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2275 * The port is disconnected, which means the core is
2276 * either in device mode or it soon will be. Just
2277 * return 0's for the remainder of the port status
2278 * since the port register can't be read if the core
2279 * is in device mode.
2281 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2285 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2286 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2288 if (hprt0.b.prtconnsts)
2289 port_status |= (1 << UHF_PORT_CONNECTION);
2292 port_status |= (1 << UHF_PORT_ENABLE);
2294 if (hprt0.b.prtsusp)
2295 port_status |= (1 << UHF_PORT_SUSPEND);
2297 if (hprt0.b.prtovrcurract)
2298 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2301 port_status |= (1 << UHF_PORT_RESET);
2304 port_status |= (1 << UHF_PORT_POWER);
2306 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2307 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2308 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2309 port_status |= (1 << UHF_PORT_LOW_SPEED);
2311 if (hprt0.b.prttstctl)
2312 port_status |= (1 << UHF_PORT_TEST);
2313 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2314 port_status |= (1 << UHF_PORT_L1);
2317 For Synopsys HW emulation of Power down wkup_control asserts the
2318 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2319 We intentionally tell the software that port is in L2Suspend state.
2322 if ((core_if->power_down == 2)
2323 && (core_if->hibernation_suspend == 1)) {
2324 port_status |= (1 << UHF_PORT_SUSPEND);
2326 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2328 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2331 case UCR_SET_HUB_FEATURE:
2332 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2334 /* No HUB features supported */
2336 case UCR_SET_PORT_FEATURE:
2337 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2340 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2342 * The port is disconnected, which means the core is
2343 * either in device mode or it soon will be. Just
2344 * return without doing anything since the port
2345 * register can't be written if the core is in device
2352 case UHF_PORT_SUSPEND:
2353 #if 0//def CONFIG_PM_RUNTIME
2356 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2357 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2358 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2361 if (core_if->power_down == 2) {
2363 dwc_irqflags_t flags;
2364 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2365 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2366 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2367 #ifdef DWC_DEV_SRPCAP
2368 int32_t otg_cap_param = core_if->core_params->otg_cap;
2370 DWC_PRINTF("Preparing for complete power-off\n");
2372 /* Save registers before hibernation */
2373 dwc_otg_save_global_regs(core_if);
2374 dwc_otg_save_host_regs(core_if);
2376 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2377 hprt0.b.prtsusp = 1;
2379 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2380 /* Spin hprt0.b.prtsusp to became 1 */
2382 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2383 if (hprt0.b.prtsusp) {
2387 } while (--timeout);
2389 DWC_WARN("Suspend wasn't genereted\n");
2394 * We need to disable interrupts to prevent servicing of any IRQ
2395 * during going to hibernation
2397 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2398 core_if->lx_state = DWC_OTG_L2;
2399 #ifdef DWC_DEV_SRPCAP
2400 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2403 DWC_WRITE_REG32(core_if->host_if->hprt0,
2407 DWC_READ_REG32(&core_if->core_global_regs->
2409 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2410 /* ULPI interface */
2411 /* Suspend the Phy Clock */
2413 pcgcctl.b.stoppclk = 1;
2414 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2417 gpwrdn.b.pmuactv = 1;
2418 DWC_MODIFY_REG32(&core_if->
2420 gpwrdn, 0, gpwrdn.d32);
2422 /* UTMI+ Interface */
2423 gpwrdn.b.pmuactv = 1;
2424 DWC_MODIFY_REG32(&core_if->
2426 gpwrdn, 0, gpwrdn.d32);
2428 pcgcctl.b.stoppclk = 1;
2429 DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
2432 #ifdef DWC_DEV_SRPCAP
2434 gpwrdn.b.dis_vbus = 1;
2435 DWC_MODIFY_REG32(&core_if->core_global_regs->
2436 gpwrdn, 0, gpwrdn.d32);
2439 gpwrdn.b.pmuintsel = 1;
2440 DWC_MODIFY_REG32(&core_if->core_global_regs->
2441 gpwrdn, 0, gpwrdn.d32);
2445 #ifdef DWC_DEV_SRPCAP
2446 gpwrdn.b.srp_det_msk = 1;
2448 gpwrdn.b.disconn_det_msk = 1;
2449 gpwrdn.b.lnstchng_msk = 1;
2450 gpwrdn.b.sts_chngint_msk = 1;
2451 DWC_MODIFY_REG32(&core_if->core_global_regs->
2452 gpwrdn, 0, gpwrdn.d32);
2455 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2457 gpwrdn.b.pwrdnclmp = 1;
2458 DWC_MODIFY_REG32(&core_if->core_global_regs->
2459 gpwrdn, 0, gpwrdn.d32);
2462 /* Switch off VDD */
2464 gpwrdn.b.pwrdnswtch = 1;
2465 DWC_MODIFY_REG32(&core_if->core_global_regs->
2466 gpwrdn, 0, gpwrdn.d32);
2468 #ifdef DWC_DEV_SRPCAP
2469 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
2471 core_if->pwron_timer_started = 1;
2472 DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
2475 /* Save gpwrdn register for further usage if stschng interrupt */
2476 core_if->gr_backup->gpwrdn_local =
2477 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
2479 /* Set flag to indicate that we are in hibernation */
2480 core_if->hibernation_suspend = 1;
2481 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
2483 DWC_PRINTF("Host hibernation completed\n");
2484 // Exit from case statement
2488 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2489 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2490 gotgctl_data_t gotgctl = {.d32 = 0 };
2491 gotgctl.b.hstsethnpen = 1;
2492 DWC_MODIFY_REG32(&core_if->core_global_regs->
2493 gotgctl, 0, gotgctl.d32);
2494 core_if->op_state = A_SUSPEND;
2496 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2497 hprt0.b.prtsusp = 1;
2498 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2500 dwc_irqflags_t flags;
2501 /* Update lx_state */
2502 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2503 core_if->lx_state = DWC_OTG_L2;
2504 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
2506 /* Suspend the Phy Clock */
2507 if (core_if->otg_ver == 0) {
2508 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2509 pcgcctl.b.stoppclk = 1;
2510 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2515 /* For HNP the bus must be suspended for at least 200ms. */
2516 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2517 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2518 pcgcctl.b.stoppclk = 1;
2519 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2523 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2524 #if 0 //vahrama !!!!!!!!!!!!!!!!!!
2525 if (core_if->adp_enable) {
2526 gotgctl_data_t gotgctl = {.d32 = 0 };
2527 gpwrdn_data_t gpwrdn;
2529 while (gotgctl.b.asesvld == 1) {
2531 DWC_READ_REG32(&core_if->
2537 /* Enable Power Down Logic */
2539 gpwrdn.b.pmuactv = 1;
2540 DWC_MODIFY_REG32(&core_if->core_global_regs->
2541 gpwrdn, 0, gpwrdn.d32);
2543 /* Unmask SRP detected interrupt from Power Down Logic */
2545 gpwrdn.b.srp_det_msk = 1;
2546 DWC_MODIFY_REG32(&core_if->core_global_regs->
2547 gpwrdn, 0, gpwrdn.d32);
2549 dwc_otg_adp_probe_start(core_if);
2553 case UHF_PORT_POWER:
2554 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2555 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2556 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2558 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2560 case UHF_PORT_RESET:
2561 if ((core_if->power_down == 2)
2562 && (core_if->hibernation_suspend == 1)) {
2563 /* If we are going to exit from Hibernated
2564 * state via USB RESET.
2566 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2568 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2570 DWC_DEBUGPL(DBG_HCD,
2571 "DWC OTG HCD HUB CONTROL - "
2572 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2574 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2575 pcgcctl.b.enbl_sleep_gating = 1;
2576 pcgcctl.b.stoppclk = 1;
2577 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2578 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2580 #ifdef CONFIG_USB_DWC_OTG_LPM
2582 glpmcfg_data_t lpmcfg;
2584 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2585 if (lpmcfg.b.prt_sleep_sts) {
2586 lpmcfg.b.en_utmi_sleep = 0;
2587 lpmcfg.b.hird_thres &= (~(1 << 4));
2589 (&core_if->core_global_regs->glpmcfg,
2595 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2596 /* Clear suspend bit if resetting from suspended state. */
2597 hprt0.b.prtsusp = 0;
2598 /* When B-Host the Port reset bit is set in
2599 * the Start HCD Callback function, so that
2600 * the reset is started within 1ms of the HNP
2601 * success interrupt. */
2602 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2605 DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
2606 DWC_WRITE_REG32(core_if->host_if->hprt0,
2609 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2612 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2613 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2616 #ifdef DWC_HS_ELECT_TST
2620 gintmsk_data_t gintmsk;
2622 t = (wIndex >> 8); /* MSB wIndex USB */
2623 DWC_DEBUGPL(DBG_HCD,
2624 "DWC OTG HCD HUB CONTROL - "
2625 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2627 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2629 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2630 hprt0.b.prttstctl = t;
2631 DWC_WRITE_REG32(core_if->host_if->hprt0,
2634 /* Setup global vars with reg addresses (quick and
2635 * dirty hack, should be cleaned up)
2637 global_regs = core_if->core_global_regs;
2639 core_if->host_if->host_global_regs;
2641 (dwc_otg_hc_regs_t *) ((char *)
2645 (uint32_t *) ((char *)global_regs +
2648 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2649 /* Save current interrupt mask */
2652 (&global_regs->gintmsk);
2654 /* Disable all interrupts while we muck with
2655 * the hardware directly
2657 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2659 /* 15 second delay per the test spec */
2662 /* Drive suspend on the root port */
2664 dwc_otg_read_hprt0(core_if);
2665 hprt0.b.prtsusp = 1;
2667 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2669 /* 15 second delay per the test spec */
2672 /* Drive resume on the root port */
2674 dwc_otg_read_hprt0(core_if);
2675 hprt0.b.prtsusp = 0;
2677 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2680 /* Clear the resume bit */
2682 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2684 /* Restore interrupts */
2685 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2686 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2687 /* Save current interrupt mask */
2690 (&global_regs->gintmsk);
2692 /* Disable all interrupts while we muck with
2693 * the hardware directly
2695 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2697 /* 15 second delay per the test spec */
2700 /* Send the Setup packet */
2703 /* 15 second delay so nothing else happens for awhile */
2706 /* Restore interrupts */
2707 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2708 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2709 /* Save current interrupt mask */
2712 (&global_regs->gintmsk);
2714 /* Disable all interrupts while we muck with
2715 * the hardware directly
2717 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2719 /* Send the Setup packet */
2722 /* 15 second delay so nothing else happens for awhile */
2725 /* Send the In and Ack packets */
2728 /* 15 second delay so nothing else happens for awhile */
2731 /* Restore interrupts */
2732 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
2737 #endif /* DWC_HS_ELECT_TST */
2739 case UHF_PORT_INDICATOR:
2740 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2741 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2745 retval = -DWC_E_INVALID;
2746 DWC_ERROR("DWC OTG HCD - "
2747 "SetPortFeature request %xh "
2748 "unknown or unsupported\n", wValue);
2752 #ifdef CONFIG_USB_DWC_OTG_LPM
2753 case UCR_SET_AND_TEST_PORT_FEATURE:
2754 if (wValue != UHF_PORT_L1) {
2758 int portnum, hird, devaddr, remwake;
2759 glpmcfg_data_t lpmcfg;
2760 uint32_t time_usecs;
2761 gintsts_data_t gintsts;
2762 gintmsk_data_t gintmsk;
2764 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2767 if (wValue != UHF_PORT_L1 || wLength != 1) {
2770 /* Check if the port currently is in SLEEP state */
2772 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2773 if (lpmcfg.b.prt_sleep_sts) {
2774 DWC_INFO("Port is already in sleep mode\n");
2775 buf[0] = 0; /* Return success */
2779 portnum = wIndex & 0xf;
2780 hird = (wIndex >> 4) & 0xf;
2781 devaddr = (wIndex >> 8) & 0x7f;
2782 remwake = (wIndex >> 15);
2785 retval = -DWC_E_INVALID;
2787 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2793 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2794 portnum, hird, devaddr, remwake);
2795 /* Disable LPM interrupt */
2797 gintmsk.b.lpmtranrcvd = 1;
2798 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2801 if (dwc_otg_hcd_send_lpm
2802 (dwc_otg_hcd, devaddr, hird, remwake)) {
2803 retval = -DWC_E_INVALID;
2807 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2808 /* We will consider timeout if time_usecs microseconds pass,
2809 * and we don't receive LPM transaction status.
2810 * After receiving non-error responce(ACK/NYET/STALL) from device,
2811 * core will set lpmtranrcvd bit.
2815 DWC_READ_REG32(&core_if->core_global_regs->gintsts);
2816 if (gintsts.b.lpmtranrcvd) {
2820 } while (--time_usecs);
2821 /* lpm_int bit will be cleared in LPM interrupt handler */
2828 if (!gintsts.b.lpmtranrcvd) {
2829 buf[0] = 0x3; /* Completion code is Timeout */
2830 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2833 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2834 if (lpmcfg.b.lpm_resp == 0x3) {
2835 /* ACK responce from the device */
2836 buf[0] = 0x00; /* Success */
2837 } else if (lpmcfg.b.lpm_resp == 0x2) {
2838 /* NYET responce from the device */
2841 /* Otherwise responce with Timeout */
2845 DWC_PRINTF("Device responce to LPM trans is %x\n",
2847 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2852 #endif /* CONFIG_USB_DWC_OTG_LPM */
2855 retval = -DWC_E_INVALID;
2856 DWC_WARN("DWC OTG HCD - "
2857 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2858 typeReq, wIndex, wValue);
2865 #ifdef CONFIG_USB_DWC_OTG_LPM
2866 /** Returns index of host channel to perform LPM transaction. */
2867 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
2869 dwc_otg_core_if_t *core_if = hcd->core_if;
2871 hcchar_data_t hcchar;
2872 gintmsk_data_t gintmsk = {.d32 = 0 };
2874 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2875 DWC_PRINTF("No free channel to select for LPM transaction\n");
2879 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2881 /* Mask host channel interrupts. */
2882 gintmsk.b.hcintr = 1;
2883 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2885 /* Fill fields that core needs for LPM transaction */
2886 hcchar.b.devaddr = devaddr;
2888 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2890 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2891 hcchar.b.epdir = 0; /* OUT */
2892 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2895 /* Remove the host channel from the free list. */
2896 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2898 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2903 /** Release hc after performing LPM transaction */
2904 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
2907 glpmcfg_data_t lpmcfg;
2910 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2911 hc_num = lpmcfg.b.lpm_chan_index;
2913 hc = hcd->hc_ptr_array[hc_num];
2915 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2916 /* Return host channel to free list */
2917 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2920 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
2921 uint8_t bRemoteWake)
2923 glpmcfg_data_t lpmcfg;
2924 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2927 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2932 pcgcctl.b.enbl_sleep_gating = 1;
2933 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2935 /* Read LPM config register */
2936 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2938 /* Program LPM transaction fields */
2939 lpmcfg.b.rem_wkup_en = bRemoteWake;
2940 lpmcfg.b.hird = hird;
2942 if(dwc_otg_get_param_besl_enable(hcd->core_if)) {
2943 lpmcfg.b.hird_thres = 0x16;
2944 lpmcfg.b.en_besl = 1;
2946 lpmcfg.b.hird_thres = 0x1c;
2949 lpmcfg.b.lpm_chan_index = channel;
2950 lpmcfg.b.en_utmi_sleep = 1;
2951 /* Program LPM config register */
2952 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2954 /* Send LPM transaction */
2955 lpmcfg.b.send_lpm = 1;
2956 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
2961 #endif /* CONFIG_USB_DWC_OTG_LPM */
2963 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
2968 return -DWC_E_INVALID;
2971 retval = (hcd->flags.b.port_connect_status_change ||
2972 hcd->flags.b.port_reset_change ||
2973 hcd->flags.b.port_enable_change ||
2974 hcd->flags.b.port_suspend_change ||
2975 hcd->flags.b.port_over_current_change);
2978 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
2979 " Root port status changed\n");
2980 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
2981 hcd->flags.b.port_connect_status_change);
2982 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
2983 hcd->flags.b.port_reset_change);
2984 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
2985 hcd->flags.b.port_enable_change);
2986 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
2987 hcd->flags.b.port_suspend_change);
2988 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
2989 hcd->flags.b.port_over_current_change);
2995 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
2999 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
3003 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3006 return hfnum.b.frnum;
3009 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
3010 struct dwc_otg_hcd_function_ops *fops)
3015 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3016 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3017 dwc_otg_hcd_reinit(hcd);
3019 retval = -DWC_E_NO_DEVICE;
3025 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
3030 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
3032 hcd->priv = priv_data;
3035 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
3037 return hcd->otg_port;
3040 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
3043 if (hcd->core_if->op_state == B_HOST) {
3052 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
3053 int iso_desc_count, int atomic_alloc)
3055 dwc_otg_hcd_urb_t *dwc_otg_urb;
3059 sizeof(*dwc_otg_urb) +
3060 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3062 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3064 dwc_otg_urb = DWC_ALLOC(size);
3066 dwc_otg_urb->packet_count = iso_desc_count;
3071 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
3072 uint8_t dev_addr, uint8_t ep_num,
3073 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3075 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3076 ep_type, ep_dir, mps);
3079 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3080 dev_addr, ep_num, ep_dir, ep_type, mps);
3084 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
3085 void *urb_handle, void *buf, dwc_dma_t dma,
3086 uint32_t buflen, void *setup_packet,
3087 dwc_dma_t setup_dma, uint32_t flags,
3090 dwc_otg_urb->priv = urb_handle;
3091 dwc_otg_urb->buf = buf;
3092 dwc_otg_urb->dma = dma;
3093 dwc_otg_urb->length = buflen;
3094 dwc_otg_urb->setup_packet = setup_packet;
3095 dwc_otg_urb->setup_dma = setup_dma;
3096 dwc_otg_urb->flags = flags;
3097 dwc_otg_urb->interval = interval;
3098 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3101 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
3103 return dwc_otg_urb->status;
3106 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
3108 return dwc_otg_urb->actual_length;
3111 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
3113 return dwc_otg_urb->error_count;
3116 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
3117 int desc_num, uint32_t offset,
3120 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3121 dwc_otg_urb->iso_descs[desc_num].length = length;
3124 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
3127 return dwc_otg_urb->iso_descs[desc_num].status;
3130 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3131 dwc_otg_urb, int desc_num)
3133 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3136 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
3139 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3142 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3149 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
3151 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3153 DWC_ASSERT(qh, "qh is not allocated\n");
3155 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3162 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
3164 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3165 DWC_ASSERT(qh, "qh is not allocated\n");
3169 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
3174 gnptxsts_data_t np_tx_status;
3175 hptxsts_data_t p_tx_status;
3177 num_channels = hcd->core_if->core_params->host_channels;
3180 ("************************************************************\n");
3181 DWC_PRINTF("HCD State:\n");
3182 DWC_PRINTF(" Num channels: %d\n", num_channels);
3183 for (i = 0; i < num_channels; i++) {
3184 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3185 DWC_PRINTF(" Channel %d:\n", i);
3186 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3187 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3188 DWC_PRINTF(" speed: %d\n", hc->speed);
3189 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3190 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3191 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3192 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3193 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3194 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3195 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3196 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3197 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3198 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3199 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3200 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3201 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3202 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3203 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3204 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3205 DWC_PRINTF(" requests: %d\n", hc->requests);
3206 DWC_PRINTF(" qh: %p\n", hc->qh);
3207 if (hc->xfer_started) {
3209 hcchar_data_t hcchar;
3210 hctsiz_data_t hctsiz;
3212 hcintmsk_data_t hcintmsk;
3214 DWC_READ_REG32(&hcd->core_if->
3215 host_if->host_global_regs->hfnum);
3217 DWC_READ_REG32(&hcd->core_if->host_if->
3218 hc_regs[i]->hcchar);
3220 DWC_READ_REG32(&hcd->core_if->host_if->
3221 hc_regs[i]->hctsiz);
3223 DWC_READ_REG32(&hcd->core_if->host_if->
3226 DWC_READ_REG32(&hcd->core_if->host_if->
3227 hc_regs[i]->hcintmsk);
3228 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3229 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3230 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3231 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3232 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3234 if (hc->xfer_started && hc->qh) {
3236 dwc_otg_hcd_urb_t *urb;
3238 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
3239 if (!qtd->in_process)
3243 DWC_PRINTF(" URB Info:\n");
3244 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
3246 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3247 dwc_otg_hcd_get_dev_addr(&urb->
3249 dwc_otg_hcd_get_ep_num(&urb->
3251 dwc_otg_hcd_is_pipe_in(&urb->
3254 DWC_PRINTF(" Max packet size: %d\n",
3255 dwc_otg_hcd_get_mps(&urb->
3257 DWC_PRINTF(" transfer_buffer: %p\n",
3259 DWC_PRINTF(" transfer_dma: %p\n",
3261 DWC_PRINTF(" transfer_buffer_length: %d\n",
3263 DWC_PRINTF(" actual_length: %d\n",
3264 urb->actual_length);
3269 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3270 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3271 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3273 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3274 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3275 np_tx_status.b.nptxqspcavail);
3276 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3277 np_tx_status.b.nptxfspcavail);
3279 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3280 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3281 p_tx_status.b.ptxqspcavail);
3282 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3283 dwc_otg_hcd_dump_frrem(hcd);
3284 dwc_otg_dump_global_registers(hcd->core_if);
3285 dwc_otg_dump_host_registers(hcd->core_if);
3287 ("************************************************************\n");
3293 void dwc_print_setup_data(uint8_t * setup)
3296 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3297 DWC_PRINTF("Setup Data = MSB ");
3298 for (i = 7; i >= 0; i--)
3299 DWC_PRINTF("%02x ", setup[i]);
3301 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3302 (setup[0] & 0x80) ? "Device-to-Host" :
3304 DWC_PRINTF(" bmRequestType Type = ");
3305 switch ((setup[0] & 0x60) >> 5) {
3307 DWC_PRINTF("Standard\n");
3310 DWC_PRINTF("Class\n");
3313 DWC_PRINTF("Vendor\n");
3316 DWC_PRINTF("Reserved\n");
3319 DWC_PRINTF(" bmRequestType Recipient = ");
3320 switch (setup[0] & 0x1f) {
3322 DWC_PRINTF("Device\n");
3325 DWC_PRINTF("Interface\n");
3328 DWC_PRINTF("Endpoint\n");
3331 DWC_PRINTF("Other\n");
3334 DWC_PRINTF("Reserved\n");
3337 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3338 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
3339 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
3340 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
3345 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
3348 DWC_PRINTF("Frame remaining at SOF:\n");
3349 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3350 hcd->frrem_samples, hcd->frrem_accum,
3351 (hcd->frrem_samples > 0) ?
3352 hcd->frrem_accum / hcd->frrem_samples : 0);
3355 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3356 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3357 hcd->core_if->hfnum_7_samples,
3358 hcd->core_if->hfnum_7_frrem_accum,
3359 (hcd->core_if->hfnum_7_samples >
3360 0) ? hcd->core_if->hfnum_7_frrem_accum /
3361 hcd->core_if->hfnum_7_samples : 0);
3362 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3363 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3364 hcd->core_if->hfnum_0_samples,
3365 hcd->core_if->hfnum_0_frrem_accum,
3366 (hcd->core_if->hfnum_0_samples >
3367 0) ? hcd->core_if->hfnum_0_frrem_accum /
3368 hcd->core_if->hfnum_0_samples : 0);
3369 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3370 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3371 hcd->core_if->hfnum_other_samples,
3372 hcd->core_if->hfnum_other_frrem_accum,
3373 (hcd->core_if->hfnum_other_samples >
3374 0) ? hcd->core_if->hfnum_other_frrem_accum /
3375 hcd->core_if->hfnum_other_samples : 0);
3378 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3379 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3380 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3381 (hcd->hfnum_7_samples_a > 0) ?
3382 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3383 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3384 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3385 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3386 (hcd->hfnum_0_samples_a > 0) ?
3387 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3388 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3389 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3390 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3391 (hcd->hfnum_other_samples_a > 0) ?
3392 hcd->hfnum_other_frrem_accum_a /
3393 hcd->hfnum_other_samples_a : 0);
3396 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3397 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3398 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3399 (hcd->hfnum_7_samples_b > 0) ?
3400 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3401 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3402 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3403 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3404 (hcd->hfnum_0_samples_b > 0) ?
3405 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3406 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3407 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3408 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3409 (hcd->hfnum_other_samples_b > 0) ?
3410 hcd->hfnum_other_frrem_accum_b /
3411 hcd->hfnum_other_samples_b : 0);
3415 #endif /* DWC_DEVICE_ONLY */